Driving control circuit for light emission driving circuit, and display driving circuit and display apparatus

Abstract

A driving control circuit for a light emission driving circuit, and a display driving circuit and a display apparatus. The driving control circuit comprises at least two groups of first driving circuits (01X), wherein the at least two groups of first driving circuits (01X) are respectively connected to at least two groups of input control ends (INX) and at least two groups of driving power supply ends (VRGX) that correspond to each other on a one-to-one basis; and each group of first driving circuits (01X) can control, in response to input control signals provided by a corresponding group of input control ends (INX) connected thereto, the connection / disconnection between a corresponding group of driving power supply ends (VRGX) and an output end (Vgout) connected to the light emission driving circuit. Thus, by flexibly setting input control signals provided by each group of input control ends (INX), a driving control circuit can flexibly provide driving power supply signals having different levels to a light emission driving circuit, thereby improving the flexibility of driving the light emission driving circuit.

Description

Driving control circuit of light emitting driving circuit, display driving circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving control circuit of a light-emitting driving circuit, a display driving circuit, and a display device. Background Art

[0002] A display driver circuit is one of the essential circuits of a display device. Typically, the display driver circuit is connected to pixels in the display device to drive the pixels to emit light.

[0003] In related art, a display driver circuit generally includes a drive control circuit and a light-emitting driver circuit. The drive control circuit is connected to a drive power supply terminal and the light-emitting driver circuit, respectively. The light-emitting driver circuit is also connected to the pixels. The drive control circuit is used to drive the light-emitting driver circuit based on a drive power signal provided by the drive power supply terminal. Specifically, the drive control circuit drives the light-emitting driver circuit to transmit a drive signal to the pixel to drive the pixel to emit light.

[0004] However, due to the limitation of the selection of the driving power signal, the flexibility of the driving control circuit in driving the light-emitting driving circuit in the related art is relatively poor.

[0005] Summary of the Invention

[0006] Provided are a drive control circuit for a light-emitting drive circuit, a display drive circuit, and a display device. The technical solution is as follows:

[0007] In one aspect, a drive control circuit for a light-emitting drive circuit is provided, the drive control circuit comprising:

[0008] At least two groups of first drive circuits are respectively connected to at least two groups of input control terminals, at least two groups of drive power terminals, and an output terminal, wherein the output terminal is used to be connected to the light-emitting drive circuit; wherein the drive power terminals of each group provide drive power signals at different levels, the at least two groups of input control terminals correspond one-to-one with the at least two groups of first drive circuits, the at least two groups of drive power terminals correspond one-to-one with the at least two groups of first drive circuits, and the at least two groups of input control terminals correspond one-to-one with the at least two groups of drive power terminals;

[0009] Each group of the first driving circuits is used to control the connection and disconnection between a corresponding group of driving power supply terminals and the output terminals in response to an input control signal provided by a corresponding group of input control terminals.

[0010] Optionally, each group of the input control terminals includes: a first input control terminal and a second input control terminal; each group of the driving power supply terminals includes: a first driving power supply terminal corresponding to the first input control terminal, and a second driving power supply terminal corresponding to the second input control terminal; and a level of a driving power supply signal provided by the first driving power supply terminal is greater than a level of a driving power supply signal provided by the second driving power supply terminal;

[0011] Each group of the first driving circuits is used to: control the on / off connection between the first driving power supply terminal and the output terminal in response to the input control signal provided by the first input control terminal; and control the on / off connection between the second driving power supply terminal and the output terminal in response to the input control signal provided by the second input control terminal.

[0012] Optionally, each group of the first driving circuits includes: a first transistor and a second transistor;

[0013] The gate of the first transistor is connected to the first input control terminal, the first electrode of the first transistor is connected to the first driving power supply terminal, and the second electrode of the first transistor is connected to the output terminal;

[0014] The gate of the second transistor is connected to the second input control terminal, the first electrode of the second transistor is connected to the second driving power supply terminal, and the second electrode of the second transistor is connected to the output terminal.

[0015] Optionally, among the first transistor and the second transistor, one transistor is a P-type transistor and the other transistor is an N-type transistor.

[0016] Optionally, the drive control circuit further includes:

[0017] The first signal control circuit is connected to the at least two groups of input control terminals and is used to transmit an input control signal to each group of the input control terminals.

[0018] Optionally, the drive control circuit further includes:

[0019] The second driving circuit is connected to the enable control terminal, the pull-down power supply terminal and the output terminal respectively, and is used to control the on / off of the pull-down power supply terminal and the output terminal in response to the enable control signal provided by the enable control terminal.

[0020] Optionally, the second driving circuit includes: a third transistor;

[0021] The gate of the third transistor is connected to the enable control terminal, the first electrode of the third transistor is connected to the pull-down power supply terminal, and the second electrode of the third transistor is connected to the output terminal.

[0022] Optionally, the drive control circuit further includes:

[0023] The second signal control circuit is connected to the enable control terminal and is used to transmit an enable control signal to the enable control terminal.

[0024] Optionally, the drive control circuit further includes:

[0025] The power supply circuit is connected to the at least two groups of driving power terminals and is used to transmit driving power signals of different levels to each group of the driving power terminals.

[0026] Optionally, the power supply circuit includes:

[0027] a level conversion sub-circuit, connected to the input power terminal and the output pin respectively, and used to perform level conversion on the input power signal provided by the input power terminal and transmit the result to the output pin;

[0028] The voltage stabilization processing sub-circuit is connected to the output pin and the at least two groups of driving power terminals respectively, and is used to transmit driving power signals of different levels to each group of the driving power terminals based on the received input power signal.

[0029] Optionally, the drive control circuit further includes: a display driver chip DDIC; and the level conversion sub-circuit includes:

[0030] a charge pump integrated in the DDIC;

[0031] and / or, a charge pump independent of the DDIC.

[0032] Optionally, the level conversion sub-circuit includes: a charge pump integrated in the DDIC, and a charge pump independent of the DDIC; the power supply circuit further includes:

[0033] a switch selection subcircuit, connected to the switch control terminal, the charge pump in the DDIC, and the output pin, respectively, and configured to control the on / off switching of the charge pump in the DDIC and the output pin in response to a switch control signal provided by the switch control terminal;

[0034] The switch control subcircuit is connected to the switch control terminal and is used to transmit the switch control signal to the switch control terminal.

[0035] Optionally, the switch selection subcircuit includes: a single-pole single-throw switch;

[0036] The control end of the single-pole single-throw switch is connected to the switch control end, the first end of the single-pole single-throw switch is connected to the charge pump in the DDIC, and the second end of the single-pole single-throw switch is connected to the output pin.

[0037] Optionally, the single-pole single-throw switch is a high-impedance switch; and the switch control subcircuit includes: a register.

[0038] Optionally, the switch control subcircuit and the voltage stabilization processing subcircuit are both integrated into the DDIC.

[0039] Optionally, the drive control circuit further includes: a power management chip PMIC;

[0040] Furthermore, the level conversion sub-circuit includes: a charge pump that is independent of the DDIC; the charge pump is integrated into the PMIC, or the charge pump and the PMIC are independent of each other.

[0041] Optionally, the drive control circuit further includes:

[0042] At least two groups of amplifiers are connected to the at least two groups of input control terminals and the at least two groups of first drive circuits in a one-to-one correspondence, and are used to amplify the input control signals provided by each group of input control terminals and transmit them to the corresponding group of first drive circuits.

[0043] On the other hand, a display driving circuit is provided, which is applied to a display panel; the display driving circuit comprises: a light-emitting driving circuit, and the driving control circuit as described in the above aspect;

[0044] The drive control circuit is connected to the light emitting drive circuit, and the light emitting drive circuit is used to connect to the pixels in the display panel;

[0045] The driving control circuit is used to control the light-emitting driving circuit to drive the pixel to emit light.

[0046] Optionally, the light emitting drive circuit includes: a gate drive circuit;

[0047] The drive control circuit is used to control the gate drive circuit to transmit a gate drive signal to the pixel to drive the pixel to emit light.

[0048] In another aspect, a display device is provided, comprising: a display panel, and the display driving circuit as described in the above another aspect;

[0049] The display panel includes a plurality of pixels; the display driving circuit is connected to the plurality of pixels, and the display driving circuit is used to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0051] FIG1 is a schematic structural diagram of a drive control circuit provided by an embodiment of the present disclosure;

[0052] FIG2 is a schematic structural diagram of another drive control circuit provided by an embodiment of the present disclosure;

[0053] FIG3 is a schematic structural diagram of another drive control circuit provided by an embodiment of the present disclosure;

[0054] FIG4 is a schematic structural diagram of another drive control circuit provided by an embodiment of the present disclosure;

[0055] FIG5 is a schematic structural diagram of another drive control circuit provided by an embodiment of the present disclosure;

[0056] FIG6 is a schematic diagram of a circuit structure of a drive control circuit provided in an embodiment of the present disclosure;

[0057] FIG7 is a schematic diagram of the circuit structure of another drive control circuit provided in an embodiment of the present disclosure;

[0058] FIG8 is a schematic diagram of the circuit structure of another drive control circuit provided in an embodiment of the present disclosure;

[0059] FIG9 is a working equivalent circuit diagram of a drive control circuit shown on the basis of FIG6;

[0060] FIG10 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG6;

[0061] FIG11 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG6;

[0062] FIG12 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG6;

[0063] FIG13 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG6;

[0064] FIG14 is a working equivalent circuit diagram of a drive control circuit shown in FIG7;

[0065] FIG15 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG7;

[0066] FIG16 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG7;

[0067] FIG17 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG7;

[0068] FIG18 is a working equivalent circuit diagram of another drive control circuit shown on the basis of FIG7;

[0069] FIG19 is a schematic structural diagram of a power supply circuit provided by an embodiment of the present disclosure;

[0070] FIG20 is a schematic structural diagram of another power supply circuit provided in an embodiment of the present disclosure;

[0071] FIG21 is a schematic diagram of a circuit structure of a power supply circuit provided in an embodiment of the present disclosure;

[0072] FIG22 is a schematic diagram of a circuit structure of a charge pump provided by an embodiment of the present disclosure;

[0073] FIG23 is a schematic structural diagram of a display driving circuit provided by an embodiment of the present disclosure;

[0074] FIG24 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0076] The transistors used in all embodiments of the present disclosure can be thin-film transistors, metal-oxide-semiconductor (MOS) field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of a switching transistor are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode and the drain is referred to as the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control electrode, which can also be referred to as the gate, the signal input end is the source electrode, and the signal output end is the drain electrode. In addition, the switching transistors used in the embodiments of the present disclosure can include either a P-type transistor or an N-type transistor, wherein a P-type transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, and an N-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Multiple signals in each embodiment of the present disclosure correspond to a first level and a second level. The first level and the second level only represent that the level of the signal has two state variables and do not mean that the first level or the second level has a specific value throughout the text.

[0077] With the development of display technology, display products such as mobile terminals are gradually becoming lightweight and convenient. This requires display products to be smaller in size, lighter in weight and at the same time able to achieve a larger display area. Accordingly, the capacity of the power supply for the display product is limited, and the low power consumption requirements for the display product are more stringent. At present, the two parts with higher power consumption in display products include: light-emitting display devices and display driver integrated circuits (DDICs). The light-emitting display device is, for example, an electroluminescent (EL) pixel, and the pixel includes a pixel circuit and an EL light-emitting element. The pixel circuit is connected to the display driver circuit and the light-emitting element respectively to drive the light-emitting element to emit light under the drive of the display driver circuit. The light-emitting drive circuit in the display driver circuit is mostly arranged on the display panel using array substrate row drive (gate driver on array, GOA) technology to facilitate narrow frame design. Accordingly, the light-emitting drive circuit can also be called a GOA circuit. For example, the common gate drive GOA circuit.

[0078] Among them, traditional EL pixels are mostly driven by low-temperature polysilicon (LTPS). That is, the pixel circuit mostly includes P-type transistors (such as PMOS tubes) made of LTPS. However, tests have found that in the scenario of using low-frequency refresh to save power consumption, the leakage of P-type transistors is relatively serious, resulting in poor pixel luminescence stability, causing the display products to have flickering display abnormalities and cannot be used. Therefore, the use of LTPS+oxide (Oxide) LTPO drive is considered. That is, the pixel circuit is set to include a P-type transistor made of LTPS and an N-type transistor (such as NMOS tube) made of Oxide. In this way, the advantage of the relatively small leakage of N-type transistors can be used to ensure that display abnormalities such as flickering screens do not occur when the display is refreshed at a low frequency.

[0079] First, for the pixel circuits of the LTPO architecture, a group of GOA circuits are currently used to transmit driving signals to the pixel circuits of the LTPO architecture to control the pixel circuits to drive the light-emitting elements to emit light, which cannot flexibly meet the driving voltage requirements for driving PMOS and NMOS tubes.

[0080] Secondly, most current GOA circuits operate based on the driving power signal provided by the DDIC, resulting in the consumption of most of the DDIC's power. Furthermore, because the DDIC contains a large number of other structures, the DDIC's response time and power supply efficiency are both low, and its load capacity is poor, which is not conducive to timely and reliable driving of the GOA circuit. Furthermore, because the driving power signal required by the GOA circuit is generally high (e.g., 8 volts V / -8V), while the power supply voltage input to the DDIC is relatively low, a boost module is generally required in the DDIC. The boost module requires a large area of ​​the DDIC and causes the DDIC to consume a large amount of power.

[0081] Based on this, the disclosed embodiments provide a new drive control circuit including a DDIC, which not only flexibly meets the drive voltage requirements of the LTPO architecture but also improves response time and operating efficiency, saving power. Figure 1 is a schematic diagram of the structure of a drive control circuit for a light-emitting drive circuit provided by an embodiment of the disclosed embodiments. As shown in Figure 1, the drive control circuit includes at least two sets of first drive circuits O1X.

[0082] At least two first drive circuits O1X are respectively connected to at least two input control terminals INX, at least two drive power supply terminals VRGX, and an output terminal Vgout. The output terminal Vgout is used to connect to a light-emitting drive circuit (not shown). Optionally, the light-emitting drive circuit can be, for example, a gate drive GOA circuit.

[0083] The at least two groups of driving power supply terminals VRGX each provide a driving power signal at a different level. The at least two groups of input control terminals INX each correspond one-to-one with the at least two groups of first driving circuits O1X. The at least two groups of driving power supply terminals VRGX each correspond one-to-one with the at least two groups of first driving circuits O1X. Furthermore, the at least two groups of input control terminals INX each correspond one-to-one with the at least two groups of driving power supply terminals VRGX. It should be understood that the one-to-one correspondence between the at least two groups A and the at least two groups B means that each group A corresponds to a group B, and each group A corresponds to a different group B.

[0084] Optionally, each group of input control terminals INX may include one or more input control terminals. Accordingly, each group of driving power supply terminals VRGX corresponding to each group of input control terminals INX may include the same number of one or more driving power supply terminals VRGX. For example, each group of input control terminals INX may include two input control terminals. Accordingly, each group of driving power supply terminals VRGX may include two driving power supply terminals.

[0085] Furthermore, each group of first driving circuits 01X is configured to control the connection and disconnection of a corresponding group of driving power supply terminals VRGX and the output terminal Vgout in response to an input control signal provided by a corresponding group of input control terminals INX.

[0086] For example, taking each group of input control terminals INX including two input control terminals and each group of driving power supply terminals VRGX including two driving power supply terminals as an example, each group of first driving circuits O1X can, when the level of the input control signal provided by one input control terminal in the corresponding group of input control terminals INX is a first level, control the driving power supply terminal corresponding to the one input control terminal to be conductive with the output terminal Vgout, so that the one driving power supply terminal transmits the driving power supply signal to the output terminal Vgout; and can, when the level of the input control signal provided by the one input control terminal is a second level, control the driving power supply terminal corresponding to the one input control terminal to be decoupled from the output terminal Vgout. Each group of first driving circuits 01X can control another driving power supply terminal corresponding to another input control terminal to be connected to the output terminal Vgout when the level of the input control signal provided by another input control terminal in a corresponding group of input control terminals INX is a first level, so that the other driving power supply terminal transmits the driving power supply signal to the output terminal Vgout; and can control another driving power supply terminal corresponding to the other input control terminal to be disconnected from the output terminal Vgout when the level of the input control signal provided by the other input control terminal is a second level.

[0087] Because the levels of the driving power signals provided by different driving power terminals are different, the input control signals can be flexibly provided to each input control terminal, so that the driving control circuit can flexibly provide driving power signals of different levels to the GOA circuit, thereby meeting the driving voltage requirements of the LTPO architecture.

[0088] Optionally, the first level may be a high level relative to the second level; that is, the first level is a high level and the second level is a low level; or the first level may be a low level relative to the second level; that is, the first level is a low level and the second level is a high level. The first levels of the input control signals provided by the respective input control terminals in each group of input control terminals INX may be different, and the second levels may also be different.

[0089] In summary, embodiments of the present disclosure provide a drive control circuit for a light-emitting driver circuit. The drive control circuit includes at least two groups of first driver circuits, each of which is connected to at least two groups of input control terminals and at least two groups of driving power supply terminals in a one-to-one correspondence. Each group of first driver circuits is capable of controlling the connection and disconnection between the corresponding group of driving power supply terminals and the output terminal connected to the light-emitting driver circuit in response to an input control signal provided by the corresponding group of input control terminals. By flexibly configuring the input control signals provided by each group of input control terminals, the drive control circuit can flexibly provide driving power supply signals of varying levels to the light-emitting driver circuit, thereby increasing the flexibility of driving the light-emitting driver circuit.

[0090] Optionally, Figure 2 is a schematic diagram of the structure of another drive control circuit provided by an embodiment of the present disclosure. As shown in Figure 2 , the drive control circuit described in the embodiment of the present disclosure may further include: a second drive circuit 02 .

[0091] The second driver circuit 02 can be connected to the enable control terminal EN, the pull-down power supply terminal AVSS, and the output terminal Vgout, respectively. The second driver circuit 02 can be used to control the connection and disconnection between the pull-down power supply terminal AVSS and the output terminal Vgout in response to an enable control signal provided by the enable control terminal EN. Optionally, the pull-down power supply terminal AVSS can be the ground terminal GND.

[0092] For example, the second driving circuit 02 can control the pull-down power supply terminal AVSS and the output terminal Vgout to be turned on when the level of the enable control signal provided by the enable control terminal EN is a first level, so that the pull-down power supply signal provided by the pull-down power supply terminal AVSS is transmitted to the output terminal Vgout, that is, the output terminal Vgout is grounded; and can control the pull-down power supply terminal AVSS to be decoupled from the output terminal Vgout when the level of the enable control signal is a second level.

[0093] Optionally, Figure 3 is a schematic diagram of the structure of another drive control circuit provided by an embodiment of the present disclosure. As shown in Figure 3, the drive control circuit recorded in the embodiment of the present disclosure may further include: a first signal control circuit 03, a second signal control circuit 04 and a power supply circuit 05.

[0094] The first signal control circuit 03 may be connected to at least two groups of input control terminals INX. The first signal control circuit 03 may be configured to transmit an input control signal to each group of input control terminals INX.

[0095] The second signal control circuit 04 may be connected to the enable control terminal EN and may be configured to transmit an enable control signal to the enable control terminal EN.

[0096] The power supply circuit 05 can be connected to at least two groups of driving power terminals VRGX and can be used to transmit driving power signals of different levels to each group of driving power terminals VRGX.

[0097] Alternatively, the first signal control circuit 03 and the second signal control circuit 04 may be integrated, that is, they may be an integral structure, belonging to two parts of the same signal control circuit. Alternatively, the first signal control circuit 03 and the second signal control circuit 04 may be independent of each other.

[0098] Optionally, Figure 4 is a schematic diagram of the structure of another drive control circuit provided by an embodiment of the present disclosure. As shown in Figure 4, each set of input control terminals INX may include: a first input control terminal IN1 and a second input control terminal IN2. That is, each set of input control terminals INX may include two input control terminals. Each set of drive power supply terminals VRGX may include: a first drive power supply terminal VRGH corresponding to the first input control terminal IN1, and a second drive power supply terminal VRGL corresponding to the second input control terminal IN2. That is, each set of drive power supply terminals VRGX may include two drive power supply terminals.

[0099] Furthermore, the level of the driving power signal provided by the first driving power terminal VRGH may be greater than the level of the driving power signal provided by the second driving power terminal VRGL. For example, the level of the driving power signal provided by the first driving power terminal VRGH may be 8V, and the level of the driving power signal provided by the second driving power terminal VRGL may be -8V.

[0100] Each group of first driving circuits 01X can be used to: control the on / off connection between the first driving power supply terminal VRGH and the output terminal Vgout in response to the input control signal provided by the first input control terminal IN1; and control the on / off connection between the second driving power supply terminal VRGL and the output terminal Vgout in response to the input control signal provided by the second input control terminal IN2.

[0101] For example, each group of first driving circuits 01X can control the first driving power supply terminal VRGH to be conductively connected to the output terminal Vgout when the level of the input control signal provided at the first input control terminal IN1 is a first level (e.g., a high level); and can control the first driving power supply terminal VRGH to be decoupled from the output terminal Vgout when the level of the input control signal provided at the first input control terminal IN1 is a second level (e.g., a low level). Each group of first driving circuits 01X can control the second driving power supply terminal VRGL to be conductively connected to the output terminal Vgout when the level of the input control signal provided at the second input control terminal IN2 is a first level (e.g., a low level); and can control the second driving power supply terminal VRGL to be decoupled from the output terminal Vgout when the level of the input control signal provided at the second input control terminal IN2 is a second level (e.g., a high level).

[0102] Alternatively, referring to FIG4 , it can be seen that the drive control circuit described in the embodiment of the present disclosure may include two sets of first drive circuits 011 and 012. Alternatively, referring to FIG5 , which shows a schematic diagram of another drive control circuit structure, it can be seen that the drive control circuit may include three sets of first drive circuits 011, 012, and 013. Of course, more sets of first drive circuits may be included, and this is not limited in the embodiment of the present disclosure.

[0103] Furthermore, for the sake of distinction, referring to FIG4 , for the two groups of first drive circuits 011 and 012, the first input control terminal IN1 and the second input control terminal IN2 corresponding to the first group of first drive circuits 011 are labeled IN1_1 and IN2_1, respectively. The first drive power supply terminal VRGH and the second drive power supply terminal VRGL corresponding to the first group of first drive circuits 011 are labeled VRGH1 and VRGL1, respectively. The first input control terminal IN1 and the second input control terminal IN2 corresponding to the second group of first drive circuits 012 are labeled IN1_2 and IN2_2, respectively. The first drive power supply terminal VRGH and the second drive power supply terminal VRGL corresponding to the second group of first drive circuits 012 are labeled VRGH2 and VRGL2, respectively. Furthermore, referring to FIG5 , for the three groups of first drive circuits 011, 012, and 013, the first input control terminal IN1 and the second input control terminal IN2 corresponding to the third group of first drive circuits 013 included in FIG4 are labeled as IN1_3 and IN2_3, respectively. Furthermore, the first drive power supply terminal VRGH and the second drive power supply terminal VRGL corresponding to the third group of first drive circuits 013 are labeled as VRGH3 and VRGL3, respectively. The labeling in the following figures is similar and will not be repeated here.

[0104] Optionally, it can be seen from FIG. 4 and FIG. 5 that the driving control circuit described in the embodiment of the present disclosure may further include: at least two groups of amplifiers (AMPs).

[0105] At least two amplifiers AMP can be connected to the at least two sets of input control terminals INX and the at least two sets of first drive circuits 01X in a one-to-one correspondence. The at least two amplifiers AMP can be used to amplify the input control signals provided by each set of input control terminals INX and transmit them to the corresponding set of first drive circuits 01X. This improves the output reliability of the input control signals, allowing the first drive circuits 01X to reliably control the on / off connection between the drive power supply terminal VRGX and the output terminal.

[0106] Alternatively, taking Figure 4 as an example, Figures 6 and 7 respectively illustrate schematic circuit structures of two drive control circuits. Taking Figure 5 as an example, Figure 8 illustrates a schematic circuit structure of yet another drive control circuit. As shown in Figures 6 to 8 , each set of first drive circuits 01X described in the embodiments of the present disclosure may include: a first transistor T1 and a second transistor T2.

[0107] A gate of the first transistor T1 may be connected to the first input control terminal IN1 , a first electrode of the first transistor T1 may be connected to the first driving power terminal VRGH, and a second electrode of the first transistor T1 may be connected to the output terminal Vgout.

[0108] A gate of the second transistor T2 may be connected to the second input control terminal IN2 , a first electrode of the second transistor T2 may be connected to the second driving power terminal VRGL, and a second electrode of the second transistor T2 may be connected to the output terminal Vgout.

[0109] Optionally, among the first transistor T1 and the second transistor T2 , one transistor may be a P-type transistor, and the other transistor may be an N-type transistor.

[0110] For example, referring to Figures 6 and 8, the first transistor T1 shown therein is a P-type transistor (e.g., a PMOS transistor), and the second transistor T2 is an N-type transistor (e.g., an NMOS transistor). Accordingly, it can be seen that for each group of first drive circuits 01X shown in Figures 6 and 8, when the level of the input control signal provided by the first input control terminal IN1 is low, the first transistor T1 can be turned on, so that the first drive power supply terminal VRGH is conductively connected to the output terminal Vgout, and a high-level drive power supply signal is transmitted to the output terminal Vgout. When the level of the input control signal provided by the first input control terminal IN1 is high, the first transistor T1 can be turned off, so that the first drive power supply terminal VRGH is disconnected from the output terminal Vgout. When the level of the input control signal provided by the second input control terminal IN2 is high, the second transistor T2 can be turned on, so that the second drive power supply terminal VRGL is conductively connected to the output terminal Vgout, and a low-level drive power supply signal is transmitted to the output terminal Vgout. When the level of the input control signal provided by the second input control terminal IN2 is low, the second transistor T2 may be turned off, so that the second driving power terminal VRGL is disconnected from the output terminal Vgout.

[0111] Alternatively, referring to FIG7 , the first transistor T1 shown therein is an N-type transistor (e.g., an NMOS transistor), and the second transistor T2 is a P-type transistor (e.g., a PMOS transistor). Accordingly, it can be seen that for each group of first drive circuits 01X shown in FIG7 , when the level of the input control signal provided by the first input control terminal IN1 is high, the first transistor T1 can be turned on, so that the first drive power supply terminal VRGH is conductively connected to the output terminal Vgout, and a high-level drive power supply signal is transmitted to the output terminal Vgout. When the level of the input control signal provided by the first input control terminal IN1 is low, the first transistor T1 can be turned off, so that the first drive power supply terminal VRGH is decoupled from the output terminal Vgout. When the level of the input control signal provided by the second input control terminal IN2 is low, the second transistor T2 can be turned on, so that the second drive power supply terminal VRGL is conductively connected to the output terminal Vgout, and a low-level drive power supply signal is transmitted to the output terminal Vgout. When the level of the input control signal provided by the second input control terminal IN2 is high, the second transistor T2 may be turned off, so that the second driving power terminal VRGL is disconnected from the output terminal Vgout.

[0112] For the purpose of distinction, in FIG6 and FIG8 , the first input control terminal IN1_1 connected to the P-type first transistor T1 in the first group of first driving circuits 011 is identified as IN1_P1, and the second input control terminal IN2_1 connected to the N-type second transistor T2 is identified as IN2_N1; at the same time, the first input control terminal IN1_2 connected to the P-type first transistor T1 in the second group of first driving circuits 012 is identified as IN1_P2, and the second input control terminal IN2_2 connected to the N-type second transistor T2 is identified as IN2_N2. In FIG7 , the first input control terminal IN1_1 connected to the N-type first transistor T1 in the first group of first drive circuits 011 is labeled IN1_N1, and the second input control terminal IN2_1 connected to the P-type second transistor T2 is labeled IN2_P1. Simultaneously, the first input control terminal IN1_2 connected to the N-type first transistor T1 in the second group of first drive circuits 012 is labeled IN1_N2, and the second input control terminal IN2_2 connected to the P-type second transistor T2 is labeled IN2_P2. In FIG8 , the first input control terminal IN1_3 connected to the P-type first transistor T1 in the third group of first drive circuits 013 is labeled IN1_P3, and the second input control terminal IN2_3 connected to the N-type second transistor T2 is labeled IN2_N3.

[0113] Optionally, it can be seen from FIG. 6 to FIG. 8 that the second driving circuit 02 may include: a third transistor T3 .

[0114] A gate of the third transistor T3 may be connected to the enable control terminal EN, a first electrode of the third transistor T3 may be connected to the pull-down power supply terminal AVSS, and a second electrode of the third transistor T3 may be connected to the output terminal Vgout.

[0115] Optionally, the third transistor T3 may be an N-type transistor (eg, an NMOS transistor) as shown in Figures 6 to 8. Alternatively, in some other embodiments, the third transistor T3 may also be a P-type transistor (eg, a PMOS transistor).

[0116] Optionally, FIG. 6 to FIG. 8 also schematically illustrate an amplifier AMP connected between the input control terminal and the gates of the transistors (including the first transistor T1 and the second transistor T2 ).

[0117] Taking the circuit shown in FIG6 as an example, the following embodiment describes how at least two groups of first driving circuits in the driving control circuit select and output driving power signals of different levels:

[0118] (1) When the level of the input control signal provided by the first input control terminal IN1_P1 is a low level, and the level of the input control signal provided by the first input control terminal IN1_P2 is a high level, and at the same time, the levels of the input control signals provided by the second input control terminals IN2_N1 and IN2_N2 are both low levels, the first transistor T1 connected to the first input control terminal IN1_P1 can be turned on, and the first transistor T1 connected to the first input control terminal IN1_P2, the second transistor T2 connected to the second input control terminal IN2_N1, and the second transistor T2 connected to the second input control terminal IN2_N2 can all be turned off. Accordingly, the first driving power supply terminal VRGH1 can be connected to the output terminal Vgout, and the first driving power supply terminal VRGH2, the second driving power supply terminal VRGL1, and the second driving power supply terminal VRGL2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the first driving power supply terminal VRGH1 can be transmitted to the output terminal Vgout. That is, the first group of first driving circuits 011 can selectively output the driving power signal provided by the first driving power supply terminal VRGH1 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the first driving power supply terminal VRGH1. For example, FIG9 shows a corresponding equivalent circuit diagram.

[0119] (2) When the level of the input control signal provided by the second input control terminal IN2_N1 is high, and the level of the input control signal provided by the second input control terminal IN2_N2 is low, and at the same time, the levels of the input control signals provided by the first input control terminals IN1_P1 and IN1_P2 are both high, the second transistor T2 connected to the second input control terminal IN2_N1 can be turned on, and the second transistor T2 connected to the second input control terminal IN2_N2, the first transistor T1 connected to the first input control terminal IN1_P1, and the first transistor T1 connected to the first input control terminal IN1_P2 can all be turned off. Accordingly, the second driving power supply terminal VRGL1 can be connected to the output terminal Vgout, and the second driving power supply terminal VRGL2, the first driving power supply terminal VRGH1, and the first driving power supply terminal VRGH2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the second driving power supply terminal VRGL1 can be transmitted to the output terminal Vgout. That is, the first group of first driving circuits 011 can selectively output the driving power signal provided by the second driving power terminal VRGL1 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the second driving power terminal VRGL1. For example, FIG10 shows a corresponding equivalent circuit diagram.

[0120] (3) When the level of the input control signal provided by the first input control terminal IN1_P2 is low, and the level of the input control signal provided by the first input control terminal IN1_P1 is high, and at the same time, the levels of the input control signals provided by the second input control terminals IN2_N1 and IN2_N2 are both low, the first transistor T1 connected to the first input control terminal IN1_P2 can be turned on, and the first transistor T1 connected to the first input control terminal IN1_P1, the second transistor T2 connected to the second input control terminal IN2_N1, and the second transistor T2 connected to the second input control terminal IN2_N2 can all be turned off. Accordingly, the first driving power supply terminal VRGH2 can be connected to the output terminal Vgout, and the first driving power supply terminal VRGH1, the second driving power supply terminal VRGL1, and the second driving power supply terminal VRGL2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the first driving power supply terminal VRGH2 can be transmitted to the output terminal Vgout. That is, the second group of first driving circuits 012 can selectively output the driving power signal provided by the first driving power supply terminal VRGH2 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the first driving power supply terminal VRGH2. For example, FIG11 shows a corresponding equivalent circuit diagram.

[0121] (4) When the level of the input control signal provided by the second input control terminal IN2_N2 is high, and the level of the input control signal provided by the second input control terminal IN2_N1 is low, and at the same time, the levels of the input control signals provided by the first input control terminals IN1_P1 and IN1_P2 are both high, the second transistor T2 connected to the second input control terminal IN2_N2 can be turned on, and the second transistor T2 connected to the second input control terminal IN2_N1, the first transistor T1 connected to the first input control terminal IN1_P1, and the first transistor T1 connected to the first input control terminal IN1_P2 can all be turned off. Accordingly, the second driving power supply terminal VRGL2 can be connected to the output terminal Vgout, and the second driving power supply terminal VRGL1, the first driving power supply terminal VRGH1, and the first driving power supply terminal VRGH2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the second driving power supply terminal VRGL2 can be transmitted to the output terminal Vgout. That is, the second group of first driving circuits 012 can selectively output the driving power signal provided by the second driving power supply terminal VRGL2 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the second driving power supply terminal VRGL2. For example, FIG12 shows a corresponding equivalent circuit diagram.

[0122] Furthermore, with respect to FIG. 6 , when the enable control signal provided by the enable control terminal EN is at a high level, the input control signals provided by the first input control terminals IN1_P1 and IN1_P2 are both at a high level, and the input control signals provided by the second input control terminals IN2_N1 and IN2_N2 are both at a low level, the third transistor T3 can be turned on, while each of the first transistors T1 and each of the second transistors T2 can be turned off. Accordingly, the pull-down power supply terminal AVSS can be conductively connected to the output terminal Vgout, while the first drive power supply terminals VRGH1 and VRGH2, as well as the second drive power supply terminals VRGL1 and VRGL2, can be decoupled from the output terminal Vgout. That is, the level of the output terminal Vgout at this time can be the level of the pull-down power signal provided by the pull-down power supply terminal AVSS. Alternatively, the pull-down power supply terminal AVSS can be the ground terminal GND. Accordingly, it can be seen that the output terminal Vgout can be grounded at this time. For example, FIG. 13 shows the corresponding equivalent circuit diagram. On the other hand, when the level of the enable control signal provided by the enable control terminal EN is low, and at the same time the levels of the input control signals provided by the first input control terminals IN1_P1 and IN1_P2 are both high, and the levels of the input control signals provided by the second input control terminals IN2_N1 and IN2_N2 are both low, each of the first transistors T1, each of the second transistors T2, and the third transistor T3 can be turned off. At this time, the output terminal Vgout can be in a floating state.

[0123] In summary, for the circuit structure shown in Figure 6, its electrical levels can be organized as shown in Table 1 below:

[0124] Table 1

[0125] Taking the circuit shown in FIG7 as an example, the following embodiment describes how at least two groups of first driving circuits in the driving control circuit select and output driving power signals of different levels:

[0126] (1) When the level of the input control signal provided by the first input control terminal IN1_N1 is high, and the level of the input control signal provided by the first input control terminal IN1_N2 is low, and at the same time, the levels of the input control signals provided by the second input control terminals IN2_P1 and IN2_P2 are both low, the first transistor T1 connected to the first input control terminal IN1_N1 can be turned on, and the first transistor T1 connected to the first input control terminal IN1_N2, the second transistor T2 connected to the second input control terminal IN2_P1, and the second transistor T2 connected to the second input control terminal IN2_P2 can all be turned off. Accordingly, the first driving power supply terminal VRGH1 can be connected to the output terminal Vgout, and the first driving power supply terminal VRGH2, the second driving power supply terminal VRGL1, and the second driving power supply terminal VRGL2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the first driving power supply terminal VRGH1 can be transmitted to the output terminal Vgout. That is, the first group of first driving circuits 011 can selectively output the driving power signal provided by the first driving power supply terminal VRGH1 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the first driving power supply terminal VRGH1. For example, FIG14 shows a corresponding equivalent circuit diagram.

[0127] (2) When the level of the input control signal provided by the second input control terminal IN2_P1 is low, and the level of the input control signal provided by the second input control terminal IN2_P2 is high, and at the same time, the levels of the input control signals provided by the first input control terminals IN1_N1 and IN1_N2 are both low, the second transistor T2 connected to the second input control terminal IN2_P1 can be turned on, and the second transistor T2 connected to the second input control terminal IN2_P2, the first transistor T1 connected to the first input control terminal IN1_N1, and the first transistor T1 connected to the first input control terminal IN1_N2 can all be turned off. Accordingly, the second driving power supply terminal VRGL1 can be connected to the output terminal Vgout, and the second driving power supply terminal VRGL2, the first driving power supply terminal VRGH1, and the first driving power supply terminal VRGH2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the second driving power supply terminal VRGL1 can be transmitted to the output terminal Vgout. That is, the first group of first driving circuits 011 can selectively output the driving power signal provided by the second driving power terminal VRGL1 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the second driving power terminal VRGL1. For example, FIG15 shows a corresponding equivalent circuit diagram.

[0128] (3) When the level of the input control signal provided by the first input control terminal IN1_N2 is high, and the level of the input control signal provided by the first input control terminal IN1_N1 is low, and at the same time, the levels of the input control signals provided by the second input control terminals IN2_P1 and IN2_P2 are both high, the first transistor T1 connected to the first input control terminal IN1_N2 can be turned on, and the first transistor T1 connected to the first input control terminal IN1_N1, the second transistor T2 connected to the second input control terminal IN2_P1, and the second transistor T2 connected to the second input control terminal IN2_P2 can all be turned off. Accordingly, the first driving power supply terminal VRGH2 can be connected to the output terminal Vgout, and the first driving power supply terminal VRGH1, the second driving power supply terminal VRGL1, and the second driving power supply terminal VRGL2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the first driving power supply terminal VRGH2 can be transmitted to the output terminal Vgout. That is, the second group of first driving circuits 012 can selectively output the driving power signal provided by the first driving power supply terminal VRGH2 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the first driving power supply terminal VRGH2. For example, FIG16 shows a corresponding equivalent circuit diagram.

[0129] (4) When the level of the input control signal provided by the second input control terminal IN2_P2 is low, and the level of the input control signal provided by the second input control terminal IN2_P1 is high, and at the same time, the levels of the input control signals provided by the first input control terminals IN1_N1 and IN1_N2 are both low, the second transistor T2 connected to the second input control terminal IN2_P2 can be turned on, and the second transistor T2 connected to the second input control terminal IN2_P1, the first transistor T1 connected to the first input control terminal IN1_N1, and the first transistor T1 connected to the first input control terminal IN1_N2 can all be turned off. Accordingly, the second driving power supply terminal VRGL2 can be connected to the output terminal Vgout, and the second driving power supply terminal VRGL1, the first driving power supply terminal VRGH1, and the first driving power supply terminal VRGH2 can all be disconnected from the output terminal Vgout. Furthermore, the driving power signal provided by the second driving power supply terminal VRGL2 can be transmitted to the output terminal Vgout. That is, the second group of first driving circuits 012 can selectively output the driving power signal provided by the second driving power supply terminal VRGL2 to the output terminal Vgout. In other words, the voltage level of the output terminal Vgout can be the voltage level of the driving power signal provided by the second driving power supply terminal VRGL2. For example, FIG17 shows a corresponding equivalent circuit diagram.

[0130] Furthermore, with respect to FIG. 7 , when the enable control signal provided by the enable control terminal EN is at a high level, while the input control signals provided by the first input control terminals IN1_N1 and IN1_N2 are both at a low level, and simultaneously, the input control signals provided by the second input control terminals IN2_P1 and IN2_P2 are both at a high level, the third transistor T3 can be turned on, while each of the first transistors T1 and each of the second transistors T2 can be turned off. Accordingly, the pull-down power supply terminal AVSS can be conductively connected to the output terminal Vgout, while the first drive power supply terminals VRGH1 and VRGH2, as well as the second drive power supply terminals VRGL1 and VRGL2, can be decoupled from the output terminal Vgout. That is, the level of the output terminal Vgout at this time can be the level of the pull-down power signal provided by the pull-down power supply terminal AVSS. Alternatively, the pull-down power supply terminal AVSS can be the ground terminal GND, and accordingly, the output terminal Vgout can be grounded. For example, FIG. 18 shows a corresponding equivalent circuit diagram. On the other hand, when the level of the enable control signal provided by the enable control terminal EN is low, and at the same time the levels of the input control signals provided by the first input control terminals IN1_N1 and IN1_N2 are both low, and the levels of the input control signals provided by the second input control terminals IN2_P1 and IN2_P2 are both high, each of the first transistors T1, each of the second transistors T2, and the third transistor T3 can be turned off. At this time, the output terminal Vgout can be in a floating state.

[0131] In summary, for the circuit structure shown in FIG7 , its electrical levels can be organized as shown in the following Table 2:

[0132] Table 2

[0133] In combination with the above-mentioned embodiment, based on the control principle that the gate of the P-type transistor is turned on when it receives a low-level signal and is turned off when it receives a high-level signal; the gate of the N-type transistor is turned on when it receives a high-level signal and is turned off when it receives a low-level signal, the levels of the circuit structure shown in Figure 8 are similarly sorted as shown in Table 3 below, and the specific control methods are not repeated one by one.

[0134] Table 3

[0135] It can be seen from the above embodiments that by flexibly providing a high level or a low level input control signal to the input control terminal, driving power signals of different levels can be selectively output to the output terminal Vgout.

[0136] Of course, for any structure shown in Figures 6 to 8, multiple level selections can also be satisfied at the same time. For example, in combination with Table 1 corresponding to Figure 6 and the embodiment, (1) and (2) can be satisfied at the same time, that is, the first transistor T1 and the second transistor T2 in the first group of first drive circuits 011 can both be turned on, while the first transistor T1 and the second transistor T2 in the second group of first drive circuits 012 can both be turned off. The first group of first drive circuits 011 can choose to provide the driving power signal of the first driving power supply terminal VRGH1 and the second driving power supply terminal VRGL1 connected to the output terminal Vgout. Alternatively, the above (3) and (4) can be satisfied at the same time, that is, the first transistor T1 and the second transistor T2 in the first group of first drive circuits 011 can both be turned off, while the first transistor T1 and the second transistor T2 in the second group of first drive circuits 012 can both be turned on. The second group of first drive circuits 012 can choose to provide the driving power signal of the first driving power supply terminal VRGH2 and the second driving power supply terminal VRGL2 connected to the output terminal Vgout.

[0137] Optionally, a schematic structural diagram of a power supply circuit is shown in FIG19 . As shown in FIG19 , the power supply circuit 05 may include: a level conversion sub-circuit 051 and a voltage stabilization processing sub-circuit 052 .

[0138] The level conversion sub-circuit 051 can be connected to the input power terminal Vin and the output pin PAD respectively. The level conversion sub-circuit 051 can be used to convert the input power signal provided by the input power terminal Vin and transmit it to the output pin PAD.

[0139] The voltage stabilization processing sub-circuit 052 can be connected to the output pin PAD and at least two groups of driving power terminals VRGX respectively. The voltage stabilization processing sub-circuit 052 can be used to transmit driving power signals of different levels to each group of driving power terminals VRGX based on the received input power signal.

[0140] It is understood that the signal transmitted to the output pin PAD by the level conversion sub-circuit 051 may include a set of driving power signals (e.g., VGH / VGL). Subsequently, after processing by the next-stage voltage regulation sub-circuit 052, the set of driving power signals may be converted into at least two sets of driving power signals of different required levels, and provided to at least two sets of driving power terminals VRGX, respectively.

[0141] Optionally, both the level conversion sub-circuit 051 and the voltage stabilization processing sub-circuit 052 may include analog circuits.

[0142] Optionally, as mentioned above, the drive control circuit may further include a display driver chip DDIC. The level conversion sub-circuit 051 may include a charge pump integrated in the DDIC and / or a charge pump independent of the DDIC.

[0143] That is, in the embodiment of the present disclosure, the charge pump can be integrated into the DDIC / set independently from the DDIC. The charge pump can be used to boost the voltage level. Transmitting the driving power signal through the charge pump integrated in the DDIC can be considered as internal power supply; transmitting the driving power signal through a charge pump independent of the DDIC can be considered as external power supply. Among them, compared with the internal power supply, the external power supply is not limited to other structures inside the DDIC, has higher power supply efficiency and faster response time, and can also save the internal power consumption of the DDIC. In addition, on the basis of external power supply, you can also choose to remove the charge pump in the DDIC, thereby reducing the size of the DDIC, and also facilitate module binding (Bonding) in the display product.

[0144] Taking the example of a level conversion sub-circuit 051 comprising a charge pump integrated into the DDIC and a charge pump independent of the DDIC, that is, a charge pump provided not only within the DDIC but also externally, as shown in FIG20 , the power supply circuit 05 described in the embodiment of the present disclosure may further include a switch selection sub-circuit 053 and a switch control sub-circuit 054.

[0145] The switch selection subcircuit 053 can be connected to a switch control terminal (not shown), a charge pump in the DDIC, and an output pin PAD. The switch selection subcircuit 053 can be used to control the on / off state of the charge pump in the DDIC and the output pin PAD in response to a switch control signal provided by the switch control terminal.

[0146] The switch control subcircuit 054 may be connected to the switch control terminal and may be used to transmit a switch control signal to the switch control terminal.

[0147] That is, the switch selection subcircuit 053 can be used to control the connection between the DDIC and the output pin PAD, allowing for flexible selection of whether to use the charge pump integrated into the DDIC or a charge pump independent of the DDIC. For an external charge pump, external power can be stopped while the charge pump in the DDIC is providing internal power.

[0148] Optionally, based on Figure 20, Figure 21 shows a schematic diagram of a circuit structure of a power supply circuit. As shown in Figure 21, the switch selection sub-circuit 053 may include: a single-pole single-throw switch S1.

[0149] The control end of the SPST switch S1 can be connected to the switch control end (not shown), the first end of the SPST switch S1 can be connected to the charge pump in the DDIC, and the second end of the SPST switch S1 can be connected to the output pin PAD.

[0150] Optionally, the single-pole, single-throw switch S1 may be a high-impedance Hi-Z switch. Based on this, the switch control subcircuit 054 may include a register. Specifically, the register may be used to configure the Hi-Z switch to control the connection between the charge pump and the output pin PAD in the DDIC. Of course, in other embodiments, the single-pole, single-throw switch S1 may be replaced with a switching transistor. This is not limited in the presently disclosed embodiments.

[0151] Optionally, in some embodiments, the switch control subcircuit 054 (e.g., a register) and the voltage regulation processing subcircuit 052 can both be integrated into a DDIC. Of course, the first drive circuit, the second drive circuit, the first signal control circuit, the second signal control circuit, and the like can also be integrated into a DDIC to facilitate circuit integration and module bonding.

[0152] Optionally, in some embodiments, the drive control circuit may further include: a power management integrated circuit (PMIC).

[0153] In scenarios where the charge pump is independently provided in the DDIC, i.e., externally powered, the charge pump can be integrated into the PMIC, or the charge pump can be independent of the PMIC. That is, the charge pump can be provided in the PMIC for external power supply, or a separate external charge pump can be provided for external power supply.

[0154] Optionally, as shown in FIG21 , one end of the charge pump in the DDIC can be connected to the input power supply terminal Vin via an input resistor Rin, and the other end can be connected to the output pin PAD via an output resistor Rout. Furthermore, the circuit structure shown in FIG21 also includes a filter capacitor C1 connected between the output pin PAD and ground. The resistor and capacitor configuration ensures reliable signal transmission.

[0155] Optionally, Figure 22 shows a schematic diagram of the circuit structure of a charge pump. As shown in Figure 22, the charge pump may include: a clock control (CC) unit and four switches S01, S02, S03 and S04. The four switches S01 to S04 can be connected between the input power supply terminal Vin and the output terminal Vout, and can also be connected to the external capacitor Cfly and the ground terminal GND respectively. The clock control unit CC can be connected to the clock terminal CLK and the four switches S01 to S04 respectively. In addition, an input capacitor Cin is also connected between the input power supply terminal Vin and the ground terminal GND; an output capacitor Cout is also connected between the output terminal Vout and the ground terminal GND. In conjunction with Figure 21, the output terminal Vout can be connected to the output pin PAD through a single-pole single-throw switch S1.

[0156] The charge pump circuit shown in Figure 22 can take advantage of the characteristic that the voltage difference across the capacitor does not jump, and charge and discharge the external capacitor Cfly through four switches S01 to S04 to achieve the purpose of boosting the voltage. For example, during charging, the clock control unit CC can control the switches S02 and S03 to conduct based on the clock signal provided by the clock terminal CLK to charge the external capacitor Cfly. At this time, the voltage at the upper end C+ of the external capacitor Cfly can be the voltage V of the input power signal provided by the input power terminal Vin. Vin , the lower end C- can be grounded. During discharge, the clock control unit CC can control switches S01 and S04 to turn on based on the clock signal provided by the clock terminal CLK to discharge the external capacitor Cfly. At this time, the voltage at the lower end C- of the external capacitor can be the voltage of the input power signal V Vin , under the characteristic that the voltage across the capacitor does not jump, the voltage at the output terminal Vout can be made 2V Vin .

[0157] Of course, in some other embodiments, the charge pump may also be replaced by other circuits with a voltage boosting function, such as a boost circuit.

[0158] Based on the above-mentioned embodiment records, it can be known that, on the one hand, the embodiment of the present disclosure can provide at least two groups of first driving circuits to flexibly output driving power signals of different levels to the GOA circuit to meet the driving voltage requirements of the LTPO architecture. On the other hand, the power supply efficiency and circuit response time can be improved by combining external power supply with internal power supply of the DDIC, thereby saving the working power consumption of the circuit. Furthermore, in the scenario of external power supply, it is also possible to choose to remove the charge pump inside the DDIC to reduce the size of the DDIC and reduce the power consumption of the DDIC.

[0159] It is understood that the GOA circuit may include multiple cascaded GOA units, each of which may be connected to a signal terminal such as a start terminal STV, a clock signal terminal CK, and a reset signal terminal RST, respectively, to transmit a drive signal to the pixel circuit under the control of the connected signal terminals, thereby enabling the pixel circuit to reliably drive the light-emitting element to emit light. The output terminal Vgout of the drive control circuit described in the embodiments of the present disclosure may be connected to any signal terminal connected to each GOA unit to provide it with the required drive power signal.

[0160] In summary, embodiments of the present disclosure provide a drive control circuit for a light-emitting driver circuit. The drive control circuit includes at least two groups of first driver circuits, each of which is connected to at least two groups of input control terminals and at least two groups of driving power supply terminals in a one-to-one correspondence. Each group of first driver circuits is capable of controlling the connection and disconnection between the corresponding group of driving power supply terminals and the output terminal connected to the light-emitting driver circuit in response to an input control signal provided by the corresponding group of input control terminals. By flexibly configuring the input control signals provided by each group of input control terminals, the drive control circuit can flexibly provide driving power supply signals of varying levels to the light-emitting driver circuit, thereby increasing the flexibility of driving the light-emitting driver circuit.

[0161] FIG23 is a schematic diagram of the structure of a display driver circuit provided in an embodiment of the present disclosure. The display driver circuit is applied to a display panel. As shown in FIG23 , the display driver circuit includes: a light-emitting driver circuit 10 and a drive control circuit 00 provided in an embodiment of the present disclosure as described in the above embodiment.

[0162] The driving control circuit 00 is connected to the light-emitting driving circuit 10, which is used to connect to the pixels in the display panel. The driving control circuit 00 is used to control the light-emitting driving circuit 10 to drive the pixels to emit light.

[0163] For example, the light-emitting driver circuit 10 may include a gate driver circuit. The driver control circuit 00 may be used to control the gate driver circuit to transmit a gate driver signal to the pixel to drive the pixel to emit light. For example, the driver control circuit 00 may transmit a required driving power supply signal to the gate driver circuit so that the gate driver circuit transmits the gate driver signal to the pixel circuit in the pixel, thereby driving the pixel circuit to reliably control the light-emitting element to emit light.

[0164] Of course, in some other embodiments, the pixel circuit also needs to receive a light-emitting control signal and a reset control signal to drive the light-emitting element to emit light. In this scenario, the light-emitting drive circuit 10 can also be a reset control drive circuit that transmits a reset control signal to the pixel; or a light-emitting control drive circuit that transmits a light-emitting control signal to the pixel.

[0165] Optionally, as mentioned above, the light-emitting driving circuit 10 may be provided on the display panel using the GOA technology, that is, the light-emitting driving circuit 10 may be a GOA circuit, so as to facilitate the narrow-frame design of the display product.

[0166] FIG24 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG24 , the display device includes: a display panel 100 and a display driving circuit 000 as shown in FIG23 .

[0167] The display panel 100 includes a plurality of pixels (not shown). A display driving circuit 000 is connected to the plurality of pixels and is configured to drive the plurality of pixels to emit light.

[0168] Optionally, the display device may be any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, or a navigation device.

[0169] It should be understood that the terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0170] For example, the words “first”, “second” or “third” and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as “a” or “an” do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as “include” or “comprise” mean that the elements or objects appearing before “include” or “comprise” include the elements or objects listed after “include” or “comprise” and their equivalents, and do not exclude other elements or objects. “Up”, “down”, “left” or “right” are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. “Connected” means electrically connected. “And / or” means that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character “ / ” generally indicates that the objects related to each other are in an “or” relationship.

[0171] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A drive control circuit for a light-emitting drive circuit, the drive control circuit comprising: At least two groups of first drive circuits are respectively connected to at least two groups of input control terminals, at least two groups of drive power terminals, and an output terminal, wherein the output terminal is used to be connected to the light-emitting drive circuit; wherein the drive power terminals of each group provide drive power signals at different levels, the at least two groups of input control terminals correspond one-to-one with the at least two groups of first drive circuits, the at least two groups of drive power terminals correspond one-to-one with the at least two groups of first drive circuits, and the at least two groups of input control terminals correspond one-to-one with the at least two groups of drive power terminals; Each group of the first driving circuits is used to control the connection and disconnection between a corresponding group of driving power supply terminals and the output terminals in response to an input control signal provided by a corresponding group of input control terminals.

2. The drive control circuit according to claim 1, wherein: Each group of the input control terminals includes: a first input control terminal and a second input control terminal; each group of the driving power terminals includes: a first driving power terminal corresponding to the first input control terminal, and a second driving power terminal corresponding to the second input control terminal; and the level of the driving power signal provided by the first driving power terminal is greater than the level of the driving power signal provided by the second driving power terminal; Each group of the first driving circuits is used to: control the on / off connection between the first driving power supply terminal and the output terminal in response to the input control signal provided by the first input control terminal; and control the on / off connection between the second driving power supply terminal and the output terminal in response to the input control signal provided by the second input control terminal.

3. The drive control circuit according to claim 2, wherein: Each group of the first driving circuits includes: a first transistor and a second transistor; The gate of the first transistor is connected to the first input control terminal, the first electrode of the first transistor is connected to the first driving power supply terminal, and the second electrode of the first transistor is connected to the output terminal; The gate of the second transistor is connected to the second input control terminal, the first electrode of the second transistor is connected to the second driving power supply terminal, and the second electrode of the second transistor is connected to the output terminal.

4. The drive control circuit according to claim 3, wherein: Of the first transistor and the second transistor, one is a P-type transistor and the other is an N-type transistor.

5. The drive control circuit according to any one of claims 1 to 4, wherein: The drive control circuit further includes: The first signal control circuit is connected to the at least two groups of input control terminals and is used to transmit an input control signal to each group of the input control terminals.

6. The drive control circuit according to any one of claims 1 to 5, wherein: The drive control circuit further includes: The second driving circuit is connected to the enable control terminal, the pull-down power supply terminal and the output terminal respectively, and is used to control the on / off of the pull-down power supply terminal and the output terminal in response to the enable control signal provided by the enable control terminal.

7. The drive control circuit according to claim 6, wherein: The second driving circuit includes: a third transistor; The gate of the third transistor is connected to the enable control terminal, the first electrode of the third transistor is connected to the pull-down power supply terminal, and the second electrode of the third transistor is connected to the output terminal.

8. The drive control circuit according to claim 6 or 7, wherein: The drive control circuit further includes: The second signal control circuit is connected to the enable control terminal and is used to transmit an enable control signal to the enable control terminal.

9. The drive control circuit according to any one of claims 1 to 8, wherein: The drive control circuit further includes: The power supply circuit is connected to the at least two groups of driving power terminals and is used to transmit driving power signals of different levels to each group of the driving power terminals.

10. The drive control circuit according to claim 9, wherein: The power supply circuit includes: a level conversion sub-circuit, connected to the input power terminal and the output pin respectively, and used to perform level conversion on the input power signal provided by the input power terminal and transmit the result to the output pin; The voltage stabilization processing sub-circuit is connected to the output pin and the at least two groups of driving power terminals respectively, and is used to transmit driving power signals of different levels to each group of the driving power terminals based on the received input power signal.

11. The drive control circuit according to claim 10, wherein: The drive control circuit further includes: a display driver chip DDIC; the level conversion sub-circuit includes: a charge pump integrated in the DDIC; and / or, a charge pump independent of the DDIC.

12. The drive control circuit according to claim 11, wherein: The level conversion sub-circuit includes: a charge pump integrated in the DDIC, and a charge pump independent of the DDIC; the power supply circuit also includes: a switch selection subcircuit, connected to the switch control terminal, the charge pump in the DDIC, and the output pin, respectively, and configured to control the on / off switching of the charge pump in the DDIC and the output pin in response to a switch control signal provided by the switch control terminal; The switch control subcircuit is connected to the switch control terminal and is used to transmit the switch control signal to the switch control terminal.

13. The drive control circuit according to claim 12, wherein: The switch selection subcircuit includes: a single-pole single-throw switch; The control end of the single-pole single-throw switch is connected to the switch control end, the first end of the single-pole single-throw switch is connected to the charge pump in the DDIC, and the second end of the single-pole single-throw switch is connected to the output pin.

14. The drive control circuit according to claim 13, wherein: The single-pole single-throw switch is a high-impedance switch; the switch control subcircuit includes: a register.

15. The drive control circuit according to any one of claims 12 to 14, wherein: The switch control subcircuit and the voltage stabilization processing subcircuit are both integrated into the DDIC.

16. The drive control circuit according to any one of claims 11 to 15, wherein: The drive control circuit further includes: a power management chip PMIC; Furthermore, the level conversion sub-circuit includes: a charge pump that is independent of the DDIC; the charge pump is integrated into the PMIC, or the charge pump and the PMIC are independent of each other.

17. The drive control circuit according to any one of claims 1 to 16, wherein: The drive control circuit further includes: At least two groups of amplifiers are connected to the at least two groups of input control terminals and the at least two groups of first drive circuits in a one-to-one correspondence, and are used to amplify the input control signals provided by each group of input control terminals and transmit them to the corresponding group of first drive circuits.

18. A display driving circuit, used in a display panel; The display driving circuit includes: A light-emitting drive circuit, and a drive control circuit according to any one of claims 1 to 17; The drive control circuit is connected to the light emitting drive circuit, and the light emitting drive circuit is used to connect to the pixels in the display panel; The driving control circuit is used to control the light-emitting driving circuit to drive the pixel to emit light.

19. The display driving circuit according to claim 18, wherein: The light-emitting drive circuit includes: a gate drive circuit; The drive control circuit is used to control the gate drive circuit to transmit a gate drive signal to the pixel to drive the pixel to emit light.

20. A display device, comprising: A display panel, and a display driving circuit as claimed in claim 18 or 19; The display panel includes a plurality of pixels; The display driving circuit is connected to the plurality of pixels, and is used to drive the plurality of pixels to emit light.

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