Array substrate, display panel, and display device

Abstract

An array substrate, comprising multiple pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit among the multiple pixel driving circuits comprises multiple transistors, wherein the multiple transistors at least include a sensing transistor. The array substrate comprises a base substrate, a transistor distribution layer, and a first source-drain metal layer. The transistor distribution layer is arranged on one side of the base substrate; the transistor distribution layer is provided with an active layer pattern of the sensing transistor and a gate pattern of the sensing transistor; and the active layer pattern of the sensing transistor is further away from the base substrate than the gate pattern of the sensing transistor. The first source-drain metal layer is arranged on the side of the transistor distribution layer away from the base substrate; the first source-drain metal layer comprises a first anode connection pattern; and the first anode connection pattern is connected to the active layer pattern of the sensing transistor.

Description

Array substrate, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate includes a plurality of pixel drive circuits arranged in multiple rows and columns, each of the plurality of pixel drive circuits including a plurality of transistors, the plurality of transistors including at least a sensing transistor. The array substrate includes a base substrate, a transistor distribution layer, and a first source-drain metal layer. The transistor distribution layer is disposed on one side of the base substrate, the transistor distribution layer being provided with an active layer pattern of a sensing transistor and a gate pattern of the sensing transistor, the active layer pattern of the sensing transistor being further away from the base substrate than the gate pattern of the sensing transistor; the first source-drain metal layer is disposed on a side of the transistor distribution layer away from the base substrate, the first source-drain metal layer including a first anode transfer pattern, the first anode transfer pattern being connected to the active layer pattern of the sensing transistor.

[0005] In some embodiments, the active layer pattern of the sensing transistor is connected to a sensing line transition pattern, and the sensing line transition pattern is located in the first source-drain metal layer. The array substrate also includes a second source-drain metal layer. The second source-drain metal layer includes a sensing line, and the active layer pattern of the sensing transistor is connected to the sensing line via the sensing line transition pattern.

[0006] In some embodiments, the transistor distribution layer includes multiple sub-transistor distribution layers, each sub-transistor distribution layer includes an active film layer and a gate film layer arranged in a stacked manner, the active film layer including an active layer pattern of the transistor, and the gate film layer including a gate pattern of the transistor. The active film layers of the multiple sub-transistor distribution layers are stacked. The active film layer of at least one sub-transistor distribution layer is a polysilicon active film layer, and the active film layer of at least one sub-transistor distribution layer is an oxide active film layer. The multiple transistors also include a write transistor and a drive transistor, and at least one active layer pattern of the active layer patterns of the sensing transistor, the write transistor, and the drive transistor is located in the polysilicon active film layer, and at least one active layer pattern is located in the oxide active film layer.

[0007] In some embodiments, the plurality of sub-transistor distribution layers include a first sub-transistor distribution layer and a second sub-transistor distribution layer, wherein the active film layer of the first sub-transistor distribution layer is closer to the substrate than the active film layer of the second sub-transistor distribution layer. The gate film layer of the first sub-transistor distribution layer and the gate film layer of the second sub-transistor distribution layer are located between the active film layer of the first sub-transistor distribution layer and the active film layer of the second sub-transistor distribution layer. The gate film layer of the first sub-transistor distribution layer and the gate film layer of the second sub-transistor distribution layer are the same layer. The write transistor and the drive transistor are located in the first sub-transistor distribution layer, and the sense transistor is located in the second sub-transistor distribution layer.

[0008] In some embodiments, the array substrate further includes a third source / drain metal layer. The third source / drain metal layer includes a data signal line, and the active layer pattern of the write transistor is connected to the data signal line via a data signal transfer pattern, and the data signal transfer pattern is located in the first transfer gate film layer. The first transfer gate film layer is located between the active film layers of adjacent sub-transistor distribution layers, or the first transfer gate film layer and the first source / drain metal layer are the same layer. One of the second source / drain metal layer and the third source / drain metal layer is disposed on a side of the transistor distribution layer close to the base substrate, and the other is disposed on a side of the first source / drain metal layer away from the base substrate.

[0009] In some embodiments, when the second source / drain metal layer is disposed on a side of the first source / drain metal layer away from the base substrate, the sensing line covers a channel region of the active layer pattern of the sensing transistor in an orthographic projection onto the base substrate.

[0010] In some embodiments, the active layer pattern of the write transistor is connected to the gate pattern of the drive transistor through a first switching pattern, and the first switching pattern is located in the first source-drain metal layer.

[0011] In some embodiments, the active layer pattern of the driving transistor is connected to the first voltage signal line through a via hole, and the first voltage signal line is located in the first source-drain metal layer.

[0012] In some embodiments, the array substrate further includes a light shielding layer. The light shielding layer is disposed on a side of the transistor distribution layer closest to the base substrate. At least one of the plurality of transistors is a dual-gate transistor, disposed in the sub-transistor distribution layer closest to the base substrate. The gate film layer of the sub-transistor distribution layer closest to the base substrate includes a top gate pattern of the dual-gate transistor, and the light shielding layer includes a bottom gate pattern of the dual-gate transistor.

[0013] In some embodiments, the light shielding layer and the second source / drain metal layer are the same layer.

[0014] In some embodiments, the array substrate includes a plurality of sub-pixel regions arranged in multiple rows and columns, and the patterns of at least two film layers of every two adjacent sub-pixel regions arranged along the column direction are symmetrically arranged.

[0015] In some embodiments, the array substrate includes a plurality of sub-pixel regions arranged in multiple rows and columns, and the patterns of at least two film layers of every two adjacent sub-pixel regions arranged along the column direction are symmetrically arranged.

[0016] In some embodiments, a size of the sub-pixel region along a column direction is greater than a size of the sub-pixel region along a row direction.

[0017] In some embodiments, the ratio of the size of the sub-pixel region along the column direction to the size of the sub-pixel region along the row direction is 1:3 or 1:2.

[0018] In some embodiments, the array substrate further comprises a planar layer, which is disposed on a side of the first source / drain metal layer away from the base substrate, and the first anode transfer pattern is connected to the anode through a via hole penetrating the planar layer.

[0019] In some embodiments, the array substrate further includes a planarization layer and a fifth source / drain metal layer. The planarization layer is disposed on a side of the first source / drain metal layer away from the base substrate. The fifth source / drain metal layer is disposed between the first source / drain metal layer and the planarization layer. The fifth source / drain metal layer includes a second anode transfer pattern, and the first anode transfer pattern is connected to the anode via the second anode transfer pattern.

[0020] In another aspect, a display panel is provided. The display panel comprises: an array substrate as described in any of the above embodiments and an anode layer. The anode layer is disposed on one side of the array substrate. The anode layer includes a plurality of anodes, and the anodes are connected to the array substrate.

[0021] In another aspect, a display device is provided, comprising the display panel according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0023] FIG1 is a structural diagram of a display device provided by some embodiments of the present disclosure;

[0024] FIG2 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

[0025] FIG3 is an equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure;

[0026] FIG4 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0027] FIG5 is a structural diagram of a display panel according to some embodiments;

[0028] FIG6 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

[0029] FIG7 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0030] FIG8 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0031] FIG9 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0032] FIG10 is a structural diagram of another display panel provided by some embodiments of the present disclosure;

[0033] FIG11A is a diagram illustrating a film layer stacking arrangement structure of multiple sub-pixel regions of an array substrate provided by some embodiments of the present disclosure;

[0034] FIG11B is an enlarged view of point E in FIG11A ;

[0035] FIG11C is an enlarged view of point F in FIG11B ;

[0036] 12A to 12O are structural diagrams of various film layers provided in some embodiments of the present disclosure;

[0037] FIG13A is a diagram illustrating a film layer stacking arrangement structure of multiple sub-pixel regions of an array substrate provided by some embodiments of the present disclosure;

[0038] FIG13B is an enlarged view of point M in FIG13A;

[0039] FIG13C is an enlarged view of point N in FIG13B ;

[0040] 14A to 14O are structural diagrams of various film layers provided in some embodiments of the present disclosure;

[0041] FIG15 is a structural diagram of a sub-pixel region provided by some embodiments of the present disclosure;

[0042] FIG16 is a structural diagram of another sub-pixel region provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0046] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] Some embodiments of the present disclosure provide a display device. The display device is an electronic device having an image (including: static image or dynamic image, wherein the dynamic image can be a video) display function. For example, the display device can be any one of a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a large-area wall, a home appliance, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, an electronic painting screen, a virtual reality (VR) display device, an augmented reality (AR) display device, and a vehicle-mounted display, but is not limited thereto.

[0051] For example, the display device may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0052] FIG1 is a structural diagram of a display device provided by some embodiments of the present disclosure.

[0053] As shown in FIG1 , the embodiment of the present disclosure is exemplified by using a mobile phone as the display device. The display device 1000 includes a display panel 100. The display panel 100 can be any of an OLED display panel, a QLED display panel, or a micro-light emitting diode (Mini LED or Micro LED) display panel.

[0054] The embodiment of the present disclosure is exemplified by taking the display panel 100 as an OLED display panel, but the embodiments of the present disclosure include but are not limited to this.

[0055] FIG2 is a structural diagram of a display panel provided by some embodiments of the present disclosure.

[0056] To facilitate the following description, an XYZ coordinate system is established. The first direction X and the second direction Y are both parallel to the plane on which the display side of the display panel 100 is located, and the two directions intersect. For example, the first direction X and the second direction Y are perpendicular to each other. The third direction Z is perpendicular to the plane on which the display surface of the display panel 100 is located.

[0057] As shown in FIG2 , the display panel 100 includes a display area AA and a peripheral area BB. The display area AA corresponds to the area of ​​the display panel 100 used for displaying images, and the peripheral area BB corresponds to the area of ​​the display panel 100 other than the display area AA. The peripheral area BB may be located on at least one side (e.g., one side or multiple sides) of the display area AA. For example, the peripheral area BB may be disposed around the display area AA.

[0058] The display area AA includes a plurality of pixels P and a plurality of signal lines. The pixels P are arranged in an array within the display area AA. The first direction X may be the row direction of the pixels P, and the second direction Y may be the column direction of the pixels P. Each pixel P includes a plurality of sub-pixels SP, each of which can display a single color. For example, a pixel P includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, each displaying red, green, or blue, respectively.

[0059] A subpixel SP is the smallest unit for displaying images within the display panel 100. Each subpixel SP includes a light-emitting device and a pixel driver circuit 200 that controls the light-emitting device. In other words, each subpixel SP corresponds to a pixel driver circuit 200. The pixel driver circuit 200 can be configured to write a data signal in response to a received scan signal and drive the light-emitting device to emit light using this signal. The brightness of the light-emitting device can be positively correlated with the voltage value of the data signal line. By adjusting the brightness of different subpixels SP, color superposition can achieve the display of multiple colors.

[0060] Multiple sub-pixels SP are arranged in the display area AA according to a specified rule. For example, the sub-pixels SP are arranged in multiple rows and columns. Since each sub-pixel SP corresponds to a pixel driving circuit 200, the pixel driving circuits 200 are also arranged in multiple rows and columns.

[0061] The pixel driving circuit 200 includes multiple transistors and capacitors. The pixel driving circuit can be a 3T1C, 7T1C, 8T1C, or 9T1C circuit, where T represents a transistor and the number before T represents the number of transistors. C represents a capacitor and the number before C represents the number of capacitors. For example, 3T1C represents three transistors and one capacitor, and 7T1C represents seven transistors and one capacitor.

[0062] FIG3 is an equivalent circuit diagram of a pixel driving circuit provided by some embodiments of the present disclosure. A 3T1C mode pixel driving circuit 200 is used as an example for description.

[0063] As shown in FIG3 , the pixel driving circuit 200 includes three transistors and one storage capacitor C, wherein the three transistors are a sensing transistor T1 , a writing transistor T2 , and a driving transistor T3 .

[0064] Exemplarily, the sensing transistor T1, the writing transistor T2, and the driving transistor T3 may be P-type transistors or N-type transistors. For example, the sensing transistor T1, the writing transistor T2, and the driving transistor T3 may include both P-type transistors and N-type transistors. For another example, the driving transistor T3, the writing transistor T2, and the sensing transistor T1 may all be N-type transistors or all be P-type transistors. Using the same type of transistors in the pixel driving circuit 200 can simplify the process flow, reduce the difficulty of manufacturing the array substrate 10, and improve the product yield.

[0065] The connection relationship among the sensing transistor T1 , the writing transistor T2 , the driving transistor T3 , the storage capacitor C, and the signal lines in the pixel driving circuit shown in FIG. 3 is schematically described below.

[0066] 3 , the signal lines electrically connected to the pixel driving circuit 200 include a sensing line Sense, a data signal line Data, a reset signal line Ref, a first scan line SCAN1 , a second scan line SCAN2 , a first voltage signal line VDD, and a second voltage signal line VSS.

[0067] The gate of the sensing transistor T1 is electrically connected to the first scan line SCAN1. The first electrode of the sensing transistor T1 is electrically connected to the reset signal line Ref via the first node N1. The first electrode of the sensing transistor T1 is also electrically connected to the sensing line Sense via the first node N1. The second electrode of the sensing transistor T1 is connected to the first plate of the storage capacitor C via the second node N2. The second electrode of the sensing transistor T1 is also electrically connected to the anode of the light-emitting device OLED via the second node N2. The second electrode of the sensing transistor T1 is also electrically connected to the second electrode of the driving transistor T3 via the second node N2, for resetting the initial potential of the second electrode of the driving transistor T3 to detect the threshold voltage of the driving transistor T3 in real time, thereby maintaining a stable initial potential of the second electrode of the driving transistor T3. After detecting the threshold voltage of the driving transistor T3, the threshold voltage of the driving transistor T3 can be compensated, so that the brightness of the light-emitting device OLED is not affected by the threshold voltage of the driving transistor T3, thereby maintaining a stable brightness of the light-emitting device OLED.

[0068] The gate of the write transistor T2 is electrically connected to the second scan line SCAN2. The first electrode of the write transistor T2 is electrically connected to the data signal line Data via a third node N3. The data signal line Data is used to transmit a data signal. The second electrode of the write transistor T2 is connected to the second plate of the storage capacitor C via a fourth node N4. The second electrode of the write transistor T2 is also connected to the gate of the drive transistor T3 via the fourth node N4. The write transistor T2 writes the data voltage Vdata to the gate of the drive transistor T3. The written data voltage Vdata is stored by the storage capacitor C, thereby keeping the drive transistor T3 on when the light-emitting device OLED emits light.

[0069] A first electrode of the driving transistor T3 is electrically connected to a first voltage signal line VDD, a second electrode of the driving transistor T3 is electrically connected to an anode of the light-emitting device OLED, and a cathode of the light-emitting device OLED is electrically connected to a second voltage signal line VSS. The first voltage signal line VDD is used to transmit a first voltage signal, such as a high-voltage DC signal, and the second voltage signal line VSS is used to transmit a second voltage signal, such as a low-voltage DC signal.

[0070] The first scan line SCAN1 is used to control the switching of the sensing transistor T1. When detecting the threshold voltage of the driving transistor T3, the writing transistor T2 is turned off and the sensing transistor T1 is turned on, so that the gate point of the driving transistor T3 is in a floating state. When the driving transistor T3 is turned on and the potential of the first electrode of the driving transistor T3 is pulled up by the power input terminal VDD, the potential difference across the storage capacitor C can be kept stable due to the coupling effect of the storage capacitor C. Therefore, the potential of the gate of the driving transistor T3 can change with the change of the potential of the second electrode of the driving transistor T3. In this way, the potential difference Vgs between the gate and the second electrode of the driving transistor T3 can be kept stable, thereby stabilizing the luminance of the light-emitting device OLED and accurately detecting the mobility of the driving transistor T3.

[0071] It should be noted that the first electrode of the transistor disclosed herein is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0072] In the circuit provided by the embodiments of the present disclosure, nodes do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0073] FIG4 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0074] As shown in FIG. 4 , the display panel 100 includes an array substrate 10 , a light emitting device layer 20 , and an encapsulation layer (not shown) stacked in sequence.

[0075] The light-emitting device layer 20 is arranged on one side of the array substrate 10. The light-emitting device layer 20 includes an anode layer 21, a pixel defining layer 22, a light-emitting layer 23 and a cathode layer 24. Among them, the anode layer 21 is arranged on one side of the array substrate 10, and the anode layer 21 includes a plurality of anodes 211. The anode 211 is connected to the array substrate 10. The specific connection method is described in detail below. The light-emitting layer 23 includes a plurality of light-emitting parts, each of which overlaps with an anode 211. A plurality of pixel openings 221 are formed in the pixel defining layer 22, and each pixel opening 221 exposes a portion of an anode 211. The light-emitting parts in the light-emitting layer 23 are arranged in a one-to-one correspondence within the pixel openings, so that the edge of the light-emitting part can coincide with the edge of the pixel opening. The cathode layer 24 is located on the side of the pixel defining layer 22 and the light-emitting layer 23 away from the array substrate 10.

[0076] The encapsulation layer is located on the side of the cathode layer 24 away from the array substrate 10. For example, the encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer. The encapsulation layer is used to encapsulate and protect the light-emitting device layer 20.

[0077] The structure of the array substrate 10 is described in detail below.

[0078] The pixel driving circuit 200 is disposed in the film layer structure of the array substrate 10 . The following describes the film layer structures included in the array substrate 10 and the arrangement of the transistors in the pixel driving circuit 200 .

[0079] Continuing with FIG4 , the array substrate 10 includes a base substrate 101 and a pixel circuit stack 102. The pixel circuit stack 102 includes a plurality of functional layers sequentially stacked on the base substrate 101, and an insulating layer located between adjacent functional layers. The insulating layer is used to prevent connection between adjacent functional layers. The insulating layer can be made of one or two inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). The functional layer may include an active film layer, a gate film layer, and a source / drain metal layer. The active film layer, the gate film layer, and the source / drain metal layer are used to form multiple pixel driving circuits in the display panel 100. The multiple pixel driving circuits are formed in the display area AA of the display panel 100.

[0080] In which, the active layer patterns of multiple transistors of the pixel driving circuit are located in the active film layer, and the active layer pattern of each transistor includes a first pole region, a second pole region and a channel region for connecting the first pole region and the second pole region, wherein the first pole region of the active layer pattern of the transistor corresponds to the first pole of the transistor mentioned above, and the second pole region of the active layer pattern of the transistor corresponds to the second pole of the transistor mentioned above. For example, the active layer pattern T11 of the sensing transistor T1 includes a first electrode region T11a of the sensing transistor T1, a second electrode region T11c of the sensing transistor T1, and a channel region T11b of the sensing transistor T1 located between the first electrode region T11a of the sensing transistor T1 and the second electrode region T11c of the sensing transistor T1; the active layer pattern T21 of the writing transistor T2 includes a first electrode region T21a of the writing transistor T2, a second electrode region T12c of the writing transistor T2, and a channel region T21b of the writing transistor T2 located between the first electrode region T21a of the writing transistor T2 and the second electrode region T21c of the writing transistor T2; the active layer pattern T31 of the driving transistor T3 includes a first electrode region T31a of the driving transistor T3, a second electrode region T31c of the driving transistor T3, and a channel region T31b of the driving transistor T3 located between the first electrode region T31a of the driving transistor T3 and the second electrode region T31c of the driving transistor T3.

[0081] The gate patterns of multiple transistors in the pixel driving circuit are located in the gate film layer, wherein the gate film layer includes, for example, multiple signal lines. The portion of a signal line that passes through the active layer pattern of a certain transistor can serve as the gate of the transistor. Here, "passing through" refers to the portion where the signal line and the active layer pattern overlap in their orthographic projections on the base substrate 101. When manufacturing a transistor, an active film layer can be first formed on the base substrate 101 to obtain the active layer pattern of the transistor, and then a gate film layer can be formed on the side of the active film layer away from the base substrate 101; or, a gate film layer can be first formed on the base substrate 101 to obtain the gate pattern of the transistor, and then an active film layer can be formed on the side of the gate film layer away from the base substrate 101. The position where the gate film layer overlaps the active film layer is the position where the gate film layer "passes through" the active layer pattern. For example, the gate pattern of the transistor is arranged to overlap with the channel region of the transistor. For example, the gate pattern T12 of the sensing transistor T1 overlaps the channel region T11b of the sensing transistor T1, the gate pattern T22 of the writing transistor T2 overlaps the channel region T22b of the writing transistor T2, and the gate pattern T32 of the driving transistor T3 overlaps the channel region T32b of the driving transistor T3.

[0082] The pixel driving circuit is primarily composed of transistors. Therefore, the size of the space occupied by the transistors can determine the size of the space occupied by the pixel driving circuit. For example, the space occupied by the transistors includes the lateral area parallel to the plane of the substrate 101 and the longitudinal area perpendicular to the plane of the substrate 101. The lateral area is the area of ​​the orthographic projection of the transistor on the substrate 101, while the longitudinal area is mainly related to the number of film layers included in the array substrate 10. The area of ​​the active layer pattern of the transistor included in the pixel driving circuit can affect the area of ​​the pixel driving circuit in the XY plane, and the connection method of the film layers in the array substrate can affect the number of film layers in the array substrate.

[0083] FIG5 is a structural diagram of a display panel according to some embodiments.

[0084] As shown in Figure 5, in some embodiments, the array substrate 10' includes a base substrate 101' and a pixel circuit stack 102', and the pixel circuit stack 102' is arranged on the base substrate 101'. The pixel circuit stack 102' includes a second active film layer 16', a second gate film layer 17' and a first source-drain metal layer 181'. A second insulating layer 122' is provided between the second active film layer 16' and the second gate film layer 17', and a first insulating layer 121' is provided between the second gate film layer 17' and the first source-drain metal layer 181'. Among them, the second active film layer 16' includes an active layer pattern T11' of the sensing transistor T1', the second gate film layer 17' includes a gate pattern T12' of the sensing transistor T1', and the first source-drain metal layer 181' includes a first anode transfer pattern 1811'.

[0085] The first insulating layer 121' is provided with a first via hole VIA1 extending through the first insulating layer 121', and the second insulating layer 122' is provided with a second via hole VIA2 extending through the second insulating layer 122'. Metal material is deposited in the first via hole VIA1 to form a first connection pattern, and metal material is deposited in the second via hole VIA2 to form a second connection pattern. The first anode transfer pattern 1811' is electrically connected to the active layer pattern T11' of the sensing transistor T1' via the first and second connection patterns. The first and second via holes VIA1 and VIA2 occupy a certain area on the XY plane, increasing the area of ​​the pixel driving circuit on the XY plane. Furthermore, space is required for the active layer pattern T11' of the sensing transistor T1' to connect with the second connection pattern, increasing the area of ​​the transistor's active layer pattern. Consequently, for an array substrate 10' of the same size, the space occupied by the transistor in the lateral area increases, reducing the number of pixel driving circuits provided within the array substrate 10', which is detrimental to achieving a high pixel density (PPI) for the display panel 100.

[0086] The second gate film layer 17' is located on the side of the second active film layer 16' away from the base substrate 101'. The active layer pattern T11' of the sensing transistor T1' cannot be directly connected to the first anode transfer pattern 1811', but must be connected to the first anode transfer pattern 1811' through a via hole penetrating the first insulating layer 121' and the second insulating layer 122'. As a result, the film layer of the array substrate 10' is increased by at least one layer. As a result, the size of the array substrate 10' in the third direction Z increases, which is not conducive to the development of thin and lightweight array substrates.

[0087] In order to solve the above problems, an embodiment of the present disclosure provides an array substrate 10 .

[0088] FIG6 is a structural diagram of a display panel provided by some embodiments of the present disclosure.

[0089] As shown in FIG. 6 , the array substrate 10 includes a base substrate 101 and a pixel circuit stack 102 . The pixel circuit stack 102 is disposed on the base substrate 101 .

[0090] The base substrate 101 is used to support the pixel circuit stack 102. For example, the base substrate 101 can be a hard substrate made of a light-conducting and non-metallic material with a certain degree of durability, such as glass, quartz, or common resin, or a flexible substrate made of a flexible material such as polyimide (PI).

[0091] The pixel circuit stack 102 includes a transistor distribution layer and a first source / drain metal layer 181 . The transistor distribution layer is disposed on one side of the base substrate 101 , and the first source / drain metal layer 181 is disposed on a side of the transistor distribution layer away from the base substrate 101 .

[0092] A sensing transistor T1 is disposed within the transistor distribution layer. Specifically, the transistor distribution layer includes an active layer pattern T11 of the sensing transistor T1 and a gate pattern T12 of the sensing transistor T1. The active layer pattern T11 of the sensing transistor T1 is further away from the substrate 101 than the gate pattern T12 of the sensing transistor T1. In this case, the sensing transistor T1 is a bottom-gate transistor. It is understood that the active layer pattern T11 of the sensing transistor T1 is closer to the first source-drain metal layer 181 than the gate pattern T12 of the sensing transistor T1. The active layer pattern T11 of the sensing transistor T1 is located in the second active film layer 16, and the gate pattern T12 of the sensing transistor T1 is located in the second gate film layer 17. A first insulating layer 121 is disposed between the second active film layer 16 and the second gate film layer 17.

[0093] The first source / drain metal layer 181 includes a first anode transfer pattern 1811 and a sensing line transfer pattern 1812. For example, the first source / drain metal layer 181 can be formed by depositing metal materials such as molybdenum (MO) / titanium (Ti) / aluminum (Al) / copper (Cu) using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0094] The sensing line transfer pattern 1812 is used to connect the sensing line S. Specifically, the sensing line S is connected to the first electrode region T11a of the sensing transistor T1 through the sensing line transfer pattern 1812. The sensing line S is located in the second source-drain metal layer 182. The location of the second source-drain metal layer 182 will be described in detail later.

[0095] The first anode transfer pattern 1811 is connected to the active layer pattern T11 of the sensing transistor T1. Specifically, the first anode transfer pattern 1811 is connected to the second electrode region T11c of the sensing transistor T1. "Connected" here means that the first anode transfer pattern 1811 is directly overlapped with the active layer pattern T11 of the sensing transistor T1. In other words, no additional insulating layer is provided between the first source-drain metal layer 181 and the active layer pattern T11 of the sensing transistor T1. In this case, there is no other insulating layer between the first source-drain metal layer 181 where the first anode transfer pattern 1811 is located and the active film layer of the transistor distribution layer where the active layer pattern T11 of the sensing transistor T1 is located.

[0096] The first anode switching pattern 1811 and the active layer pattern T11 of the sensing transistor T1 do not need to be directly overlapped through vias. A certain area needs to be reserved on the active layer pattern for the via to connect the switching pattern in the via to the active layer pattern. When the second pole region T11c of the sensing transistor T1 is directly overlapped with the first anode switching pattern 1811, the second pole region T11c of the sensing transistor T1 is in contact with the first anode switching pattern 1811. Compared with the via, the area of ​​the active layer pattern occupied by the direct overlap is smaller, so that the area occupied by the active layer pattern T11 of the sensing transistor T1 on the XY plane is reduced, thereby reducing the area of ​​the pixel driving circuit on the XY plane. For an array substrate 10 of the same size, the space occupied by the transistor on the XY plane is reduced, and the number of pixel driving circuits that can be set in the array substrate 10 is reduced, which is beneficial for the display panel 100 to achieve high PPI.

[0097] On the other hand, the second insulating layer 122 is not provided between the first source-drain metal layer 181 and the second active film layer 16 where the active layer pattern T11 of the sensing transistor T1 is located, so that the film layers of the array substrate 10 are reduced and the size of the array substrate 10 in the third direction Z is reduced, which is conducive to the lightweight and thin development of the display panel 100.

[0098] In some embodiments, referring to FIG6 , the active layer pattern T11 of the sensing transistor T1 is connected to the sensing line transfer pattern 1812, which is located in the first source-drain metal layer 181. Specifically, the sensing line transfer pattern 1812 is connected to the first electrode region T11a of the sensing transistor T1. Since the sensing line transfer pattern 1812 is located in the first source-drain metal layer 181, the sensing line transfer pattern 1812 can be in direct contact with the first electrode region T11a of the sensing transistor T1. Compared with vias, the area of ​​the active layer pattern occupied by direct contact is smaller, which reduces the area occupied by the active layer pattern T11 of the sensing transistor T1 in the XY plane, thereby reducing the area of ​​the pixel driving circuit in the XY plane. For an array substrate 10 of the same size, the space occupied by the transistor in the XY plane is reduced, and the number of pixel driving circuits that can be set in the array substrate 10 is reduced, which is beneficial for the display panel 100 to achieve a high PPI.

[0099] In some other embodiments, the pixel driving circuit utilizes a 7T1C or 8T1C internal compensation circuit, which utilizes a low-temperature polycrystalline oxide (LTPO) process or a low-temperature polysilicon (LTPS) process. However, this internal compensation circuit utilizes a large number of transistors, which increases the lateral space occupied by the transistors. This results in a larger area occupied by the pixel driving circuit, limiting the PPI of the display panel 100 to 600 PPI, hindering the display panel 100 from achieving a high PPI.

[0100] The pixel drive circuit uses a 3T1C external compensation circuit, which uses an oxide process. The smaller the oxide transistor device, the worse the device stability. Therefore, in order to improve device stability, the oxide transistor device must maintain a certain size and cannot be made smaller. In addition, the electron mobility of the oxide transistor is low, and the transistor compensation time is long. As a result, oxide transistors can only be used in large-size, low-PPI products (such as TVs).

[0101] In order to solve the above problems, in some embodiments, the transistor distribution layer includes multiple (for example, two, or more) sub-transistor distribution layers. Each sub-transistor distribution layer includes an active film layer and a gate film layer arranged in a stacked manner. The active film layer includes an active layer pattern of the transistor, and the gate film layer includes a gate pattern of the transistor. The active film layers of the multiple sub-transistor distribution layers are stacked. For example, referring to Figure 6, the multiple transistor distribution layers include a first sub-transistor distribution layer and a second sub-transistor distribution layer. The first sub-transistor distribution layer includes an active film layer of a first sub-transistor (hereinafter referred to as the first active film layer) 11 and a gate film layer of the first sub-transistor (hereinafter referred to as the first gate film layer) 13 arranged in a stacked manner, and the second sub-transistor distribution layer includes an active film layer of a second sub-transistor (hereinafter referred to as the second active film layer) 16 and a gate film layer of the second sub-transistor (hereinafter referred to as the second gate film layer) 17 arranged in a stacked manner. The first active film layer 11 and the second active film layer 16 are stacked, for example, the first active film layer 11 is closer to the base substrate 101 than the second active film layer 16.

[0102] The active film layer of at least one sub-transistor distribution layer is a polysilicon active film layer, and the active film layer of at least one sub-transistor distribution layer is an oxide (Oxide) active film layer. The material of the polysilicon active film layer may be low-temperature polysilicon (LTPS), and the material of the oxide active film layer may be indium gallium zinc oxide (IGZO), wherein IGZO is a high-mobility active layer material. For example, the first active film layer 11 is a polysilicon active film layer, and the second active film layer 16 is an oxide active film layer. For another example, the first active film layer 11 is an oxide active film layer, and the second active film layer 11 is a polysilicon active film layer. The material of the active layer pattern located in the oxide active film layer is oxide, and the material of the active layer pattern located in the polysilicon active film layer is polysilicon.

[0103] Specifically, the active layer patterns of the sensing transistor T1, writing transistor T2, and driving transistor T3 in the pixel driving circuit are located in the active film layers of at least two sub-transistor distribution layers. That is, the active layer pattern T11 and gate pattern T12 of the sensing transistor T1 are located in the active film layer and gate film layer of one sub-transistor distribution layer, respectively; the active layer pattern T21 and gate pattern T22 of the writing transistor T2 are located in the active film layer and gate film layer of one sub-transistor distribution layer, respectively; and the active layer pattern T31 and gate pattern T32 of the driving transistor T3 are located in the active film layer and gate film layer of one sub-transistor distribution layer, respectively.

[0104] At least one of the active layer pattern T11 of the sensing transistor T1 , the active layer pattern T21 of the writing transistor T2 , and the active layer pattern T31 of the driving transistor T3 is made of polysilicon, and at least one is made of oxide.

[0105] For example, the active layer patterns of the sensing transistor T1, the writing transistor T2, and the driving transistor T3 may be made of LTPS and oxide. That is, at least one of the sensing transistor T1, the writing transistor T2, and the driving transistor T3 is a low-temperature polysilicon transistor, and at least one is an oxide transistor. LTPS has high electron mobility, which can reduce transistor compensation time and improve the yield and stability of the pixel driving circuit.

[0106] In some examples, the active layer pattern T11 of the sensing transistor T1 and the active layer pattern T21 of the writing transistor T2 have different materials.

[0107] For example, the material of the active layer pattern T11 of the sensing transistor T1 can be an oxide. That is, the sensing transistor T1 can be an oxide transistor. For example, the active layer pattern T11 of the sensing transistor T1 can be IGZO. The active layer pattern T11 of the sensing transistor T1 is connected to the anode 211 via the first anode transfer pattern 1811. The off-state current (loff) of IGZO is low, thereby reducing the leakage current of the sensing transistor T1 and ensuring the anode potential. The material of the active layer pattern T21 of the write transistor T2 and the active layer pattern T31 of the drive transistor T3 can be LTPS. That is, the write transistor T2 and the drive transistor T3 can be low-temperature polysilicon transistors.

[0108] For another example, the material of the active layer pattern T11 of the sensing transistor T1 can be LTPS, and the material of the active layer pattern T31 of the writing transistor T2 and the driving transistor T3 can be IGZO. In other words, the sensing transistor T1 is a low-temperature polysilicon transistor, and the writing transistor T2 and the driving transistor T3 are oxide transistors.

[0109] In some examples, the active layer pattern T11 of the sensing transistor T1 and the active layer pattern T21 of the writing transistor T2 are made of the same material.

[0110] For example, the sensing transistor T1 and the writing transistor T2 are the same type of transistors, such as a low-temperature polysilicon transistor, and the driving transistor T3 is another type of transistor, such as an oxide transistor.

[0111] Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Low-temperature polysilicon transistors and oxide transistors are integrated on an array substrate 10 to form a low-temperature polycrystalline oxide (LTPO) array substrate. By utilizing the advantages of both, the refresh frequency of the array substrate 10 can be switched to achieve low-frequency driving, which is beneficial to reducing power consumption and improving display quality.

[0112] It should be noted that the above-mentioned “transistor distribution layer includes multiple sub-transistor distribution layers” means that the number of sub-transistor distribution layers in the transistor distribution layer is greater than or equal to two. For example, the number of sub-transistor distribution layers in the transistor distribution layer can be two, or three, four, five or six, etc., which can be set according to actual needs, and the embodiments of the present disclosure do not specifically limit this.

[0113] Continuing with Figure 6 , the transistor distribution layer further includes a first transfer layer 14. The second plate C2 of the storage capacitor C in the pixel driving circuit is disposed on the first transfer layer 14 and is connected to the first anode transfer pattern 1811 via a via. The gate pattern T32 of the driving transistor T3 also serves as the first plate C1 of the storage capacitor C. The active layer pattern T31 of the driving transistor T3 is connected to the first transfer layer 14 via a via.

[0114] In some embodiments, referring again to FIG6 , the first gate film layer 13 and the second gate film layer 17 are located between the first active film layer 11 and the second active film layer 16. The first active film layer 11 and the second active film layer 16 are stacked so that multiple transistors (including low-temperature polysilicon transistors and oxide transistors) are located in different sub-transistor distribution layers in the third direction Z. This reduces the area occupied by the multiple transistors in the XY plane, thereby increasing the number of pixel driving circuits in the array substrate 10 and improving the PPI of the display panel 100.

[0115] The write transistor T2 and the drive transistor T3 are located in the first sub-transistor distribution layer. It can be understood that the active layer pattern T21 of the write transistor T2 and the active layer pattern T31 of the drive transistor T3 are both located in the first active film layer 11, and the gate pattern T22 of the write transistor T2 and the gate pattern T32 of the drive transistor T3 are both located in the first gate film layer 13.

[0116] The sensing transistor T1 is located in the second sub-transistor distribution layer. It is understood that the active layer pattern T11 of the sensing transistor T1 is located in the second active film layer 16 , and the gate pattern T12 of the sensing transistor T1 is located in the second gate film layer 17 .

[0117] In some examples, referring again to FIG6 , the first gate film layer 13 and the second gate film layer 17 are different layers. In this case, the gate pattern T12 of the sensing transistor T1 and the gate pattern T22 of the write transistor T2 are located in different film layers. The first gate film layer 13 and the second gate film layer 17 are sequentially stacked and disposed between the first active film layer 11 and the second active film layer 16. For example, the first active film layer 11, the first gate film layer 13, the second gate film layer 17, and the second active film layer 16 are sequentially stacked and disposed on the base substrate 101. The first transfer layer 14 can be located between the first sub-transistor distribution layer and the second sub-transistor distribution layer, for example, the first transfer layer 14 is located between the first gate film layer 13 and the second gate film layer 17.

[0118] Among them, a first insulating layer 121 is arranged between the second active film layer 16 and the second gate film layer 17, and the first insulating layer 121 covers the second gate film layer 17; a third insulating layer 123 is arranged between the second gate film layer 17 and the first transfer layer 14, and the third insulating layer 123 covers the first transfer layer 14; a fourth insulating layer 124 is arranged between the first transfer layer 14 and the first gate film layer 13, and the fourth insulating layer 124 covers the first gate film layer 13; a fifth insulating layer 125 is arranged between the first gate film layer 13 and the first active film layer 11, and the fifth insulating layer 125 covers the first active film layer 11.

[0119] FIG7 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0120] In some other examples, as shown in FIG7 , the first gate film layer 13 and the second gate film layer 17 are the same layer. In this case, the gate pattern T12 of the sensing transistor T1, the gate pattern T22 of the write transistor T2, and the gate pattern T32 of the drive transistor T3 are located in the same film layer (hereinafter referred to as the third gate film layer G1). Furthermore, since at least one active layer pattern of the active layer patterns of the sensing transistor T1, the write transistor T2, and the drive transistor T3 is located in the polysilicon active film layer, and at least one active layer pattern is located in the oxide active film layer, the gate pattern of the low-temperature polysilicon transistor and the gate pattern of the oxide transistor share the third gate film layer G1.

[0121] The first transfer layer 14 is located between the first active film layer 11 and the second active film layer 16 . For example, the first transfer layer is located between the third gate film layer G1 and the second active film layer 16 .

[0122] Of course, insulating layers are provided between the first active film layer 11, the third gate film layer G1, the first transfer layer 14, and the second active film layer 16. Specifically, a third insulating layer 123 is provided between the second active film layer 16 and the first transfer layer 14, covering the first transfer layer 14; a fourth insulating layer 124 is provided between the first transfer layer 14 and the third gate film layer G1, covering the third gate film layer G1; and a fifth insulating layer 125 is provided between the third gate film layer G1 and the first active film layer 11, covering the first active film layer 11. This eliminates the need for the first insulating layer 121, which was originally provided between the second active film layer 16 and the second gate film layer 17, thereby reducing the number of film layers in the array substrate 10 and the size of the array substrate 10 in the third direction Z, which facilitates a lightweight and thin design for the display panel 100.

[0123] In some embodiments, referring again to FIG. 7 , the array substrate 10 further includes a second source / drain metal layer 182 and a third source / drain metal layer 183. The second source / drain metal layer 182 includes a sensing line S, and the third source / drain metal layer 183 includes a data signal line D. The active layer pattern T11 of the sensing transistor T1 is connected to the sensing line S via a sensing line transfer pattern 1812. The active layer pattern T21 of the write transistor T2 is connected to the data signal line D via a data signal transfer pattern Dt. The data signal transfer pattern Dt is located in a first transfer gate film layer, wherein the first transfer gate film layer is located between active film layers of adjacent sub-transistor distribution layers, or the first transfer gate film layer and the first source / drain metal layer 181 are the same layer.

[0124] In some embodiments, referring again to FIG. 5 , the sensing line S' and the data signal line D' are located on the same side of the transistor distribution layer away from the base substrate 101'. The sensing line transfer pattern 1812' needs to be connected to the sensing line S' through a via disposed on the side of the sensing line transfer pattern 1812' away from the base substrate 101'. The data signal transfer pattern Dt' needs to be connected to the data signal line D' through a via disposed on the side of the data line transfer pattern Dt' away from the base substrate 101'. In this way, multiple vias are arranged on the same side of the transistor distribution layer away from the base substrate 101', resulting in a large number of vias (hereinafter referred to as same-direction vias) located on the side of the transistor distribution layer away from the base substrate 101' in the array substrate 10. The orthographic projections of each same-direction via on the base substrate 101' cannot overlap, so it is necessary to reserve space for multiple same-direction vias in the XY plane, resulting in a large space occupied by the pixel driving circuit in the XY plane; moreover, the sensing line S' and the data signal line D' are both located in the same source and drain metal layer, and the orthographic projections of the sensing line S' and the data signal line D' on the base substrate 101' cannot overlap, which further reduces the number of pixel driving circuits that can be set in the array substrate 10', which is not conducive to achieving a high PPI for the display panel 100.

[0125] To address the above technical issues, in some embodiments, one of the sensing line S and the data signal line D is located on a side of the transistor distribution layer close to the base substrate 101, and the other is located on a side of the first source / drain metal layer 181 away from the base substrate 101. In other words, the second source / drain metal layer 182 and the third source / drain metal layer 183 are located on either side of the transistor distribution layer, respectively.

[0126] For example, referring again to FIG7 , the second source / drain metal layer 182 is located on the side of the first source / drain metal layer away from the substrate 101 (hereinafter referred to as the "side away from the substrate 101"). The third source / drain metal layer 183 is located on the side of the transistor distribution layer closer to the substrate 101 (hereinafter referred to as the "side closer to the substrate 101"). For process stability considerations, the material of the second source / drain metal layer 182 can be molybdenum (Mo).

[0127] When the first gate transition film layer 201 is located between the second active film layer 16 and the first active film layer 11, for example, between the first active film layer 16 and the third gate film layer G1, the sensing line transition pattern 1812 and the data signal transition pattern Dt are located in different film layers. The sensing line transition pattern 1812 is located on the side of the data signal transition pattern Dt away from the base substrate 101. In some examples, the first gate transition film layer 201 and the first transition layer 14 are the same layer. When forming the first transition layer 14, the second electrode C2 and the data signal transition pattern Dt can be formed simultaneously, reducing process steps and improving product production efficiency.

[0128] A sixth insulating layer 126 is provided between the second source-drain metal layer 182 and the first source-drain metal layer 181, and the sensing line S is connected to the sensing line transfer pattern 1812 through a via penetrating the sixth insulating layer 126. These vias are located on the upper side of the sensing line transfer pattern 1812. A seventh insulating layer 127 is provided between the third source-drain metal layer 183 and the first active film layer 11, and the data signal transfer pattern Dt is connected to the data signal line D through a via penetrating the fourth insulating layer 124, the fifth insulating layer 125 and the seventh insulating layer 127. These vias are located on the lower side of the data signal transfer pattern Dt. The vias penetrating the sensing line transfer pattern 1812 for connecting the sensing line S are located on the upper side, and the vias penetrating the data signal transfer pattern Dt for connecting the data line D are located on the lower side, that is, they are not unidirectional vias.

[0129] When the first gate transfer film layer 201 and the sensing line transfer pattern 1812 are located in the same film layer (both located in the first source-drain metal layer 181), the sensing line transfer pattern 1812 is located on the upper side for connecting the vias through which the sensing line S passes, while the data signal transfer pattern Dt is located on the lower side for connecting the vias through which the data line D passes, i.e., they are not co-directional vias. When forming the first source-drain metal layer 181, the first anode transfer pattern 1811, the sensing line transfer pattern 1812, and the data signal transfer pattern Dt can be formed simultaneously, reducing process steps and improving product production efficiency.

[0130] In this way, when the vias through which the sensing line transfer pattern 1812 connects the sensing line S and the vias through which the data signal transfer pattern Dt connects the data line D are not unidirectional vias, the number of unidirectional vias in the array substrate 10 can be reduced, and the orthographic projections of the vias on both sides on the base substrate 101 can overlap, and the non-unidirectional vias occupy a smaller space in the XY plane, thereby reducing the area occupied by the pixel driving circuit in the XY plane. Moreover, the sensing line S and the data signal line D are located in different source and drain metal layers, and the orthographic projections of the sensing line S and the data signal line D on the base substrate 101 can overlap, thereby reducing the area occupied by the pixel driving circuit in the XY plane; this is beneficial to increase the number of pixel driving circuits that can be set in the array substrate 10 and further improve the PPI of the display panel 100.

[0131] FIG8 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0132] 8 , the second source / drain metal layer 182 is located on the upper side of the transistor distribution layer, and the third source / drain metal layer 183 is located on the lower side of the first source / drain metal layer 181. The material of the second source / drain metal layer 182 can be a metal conductive material such as titanium (Ti), aluminum (Al), copper (Cu), or molybdenum (Mo). There are many types of materials available for the second source / drain metal layer 182.

[0133] When the first gate transfer film layer 201 and the sensing line transfer pattern 1812 are located in the same film layer (both located in the first source-drain metal layer 181): an eighth insulating layer 128 is provided between the sensing line S and the first active film layer 11. The sensing line S is connected to the sensing line transfer pattern 1812 through vias penetrating the eighth insulating layer 128, the fifth insulating layer 125, the fourth insulating layer 124, and the third insulating layer 123. These vias are located on the bottom side of the sensing line transfer pattern 1812. The data signal D is connected to the data signal transfer pattern Dt through vias penetrating the sixth insulating layer 126. These vias are located on the top side of the data signal transfer pattern Dt. The vias through which the sensing line transfer pattern 1812 connects to the sensing line S are located on the bottom side of the sensing line transfer pattern 1812, and the vias through which the data signal transfer pattern Dt connects to the data signal line D are located on the top side of the data signal transfer pattern Dt, i.e., they are not unidirectional vias. The number of same-direction vias in the array substrate 10 can be reduced, the orthographic projections of the vias on both sides on the base substrate 101 can overlap, the non-same-direction vias occupy a smaller space in the XY plane, thereby reducing the area occupied by the pixel driving circuit in the XY plane. In addition, the sensing line S and the data signal line D are located in different source and drain metal layers, and the orthographic projections of the sensing line S and the data signal line D on the base substrate 101 can overlap, thereby reducing the area occupied by the pixel driving circuit in the XY plane; this is conducive to increasing the number of pixel driving circuits that can be set in the array substrate 10 and further improving the PPI of the display panel 100.

[0134] FIG9 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0135] In some embodiments, as shown in FIG9 , when the second source / drain metal layer 182 is disposed on the upper side of the first source / drain metal layer 181, the sensing line S covers the channel region T11b of the active layer pattern of the sensing transistor T1 in an orthographic projection onto the substrate 101. The sensing line S acts as a light-blocking layer for the active layer pattern T11 of the sensing transistor T1, shielding light from the side of the first source / drain metal layer 181 away from the substrate 101 and entering the sensing transistor T1, thereby improving the stability of the sensing transistor T1.

[0136] In some embodiments, referring again to FIG. 6 , the active layer pattern T21 of the write transistor T2 is connected to the gate pattern T32 of the drive transistor T3 via a first transfer pattern Se. Specifically, the second electrode region T12c of the write transistor T2 is connected to the gate pattern T32 of the drive transistor T3 via the first transfer pattern Se. The first transfer pattern Se is located in the first source-drain metal layer 181. Exemplarily, the first transfer pattern Se is connected to the active layer pattern T21 of the write transistor T2 via a via extending through the third insulating layer 123, the fourth insulating layer 124, and the fifth insulating layer 125. The first transfer pattern Se is connected to the gate pattern T32 of the drive transistor T3 via a via extending through the third insulating layer 123 and the fourth insulating layer 124. When forming the first source-drain metal layer 181, the first anode transfer pattern 1811, the sense line transfer pattern 1812, and the first transfer pattern Se can be formed simultaneously, reducing process steps and improving product production efficiency.

[0137] In some embodiments, referring again to FIG. 6 , the active layer pattern T31 of the driving transistor T3 is connected to the first voltage signal line VDD through a via. The active layer pattern T31 of the driving transistor T3 is also connected to the first anode transfer pattern 1811 through a via. Specifically, the first electrode region T31a of the driving transistor T3 is connected to the first voltage signal line VDD through a via, and the second electrode region T31c of the driving transistor T3 is connected to the first anode transfer pattern 1811 through a via. The first voltage signal line VDD is located on the first source / drain metal layer 181.

[0138] That is to say, the first anode transfer pattern 1811, the sensing line transfer pattern 1812 and the first voltage signal line VDD are all located in the first source-drain metal layer 181. In this way, when the first source-drain metal layer 181 is formed, the first anode transfer pattern 1811, the sensing line transfer pattern 1812 and the first voltage signal line VDD can be formed at the same time, reducing the process steps and improving product production efficiency.

[0139] In some implementations, the first anode transfer pattern 1811, the sensing line transfer pattern 1812, the first transfer pattern Se, the data signal transfer pattern Dt, and the first voltage signal line VDD are all located on the same layer. This allows the first anode transfer pattern 1811, the sensing line transfer pattern 1812, the first transfer pattern Se, the data signal transfer pattern Dt, and the first voltage signal line VDD to be formed simultaneously when the first source / drain metal layer 181 is formed, thereby reducing process steps and improving product production efficiency. Furthermore, the film layers containing the first anode transfer pattern 1811, the sensing line transfer pattern 1812, the first transfer pattern Se, the data signal transfer pattern Dt, and the first voltage signal line VDD are all functional layers. When these functional layers are the same layer, there is no need to provide an insulating layer between adjacent functional layers, thereby reducing the number of film layers in the array substrate 10 and, in turn, reducing the size of the array substrate 10 in the third direction Z, which is conducive to the development of a thinner and lighter display panel 100.

[0140] In some embodiments, referring to FIG7 , the array substrate 10 further includes a light shielding layer 30. The light shielding layer 30 is disposed on the lower side of the transistor distribution layer. The light shielding layer 30 can block light from the side of the base substrate 101 away from the light shielding layer 30 and directed into the array substrate 10. Exemplarily, the material of the light shielding layer 30 can be one or more materials such as Ti, aluminum Al, copper Cu, molybdenum Mo, etc. At least one (for example, one, or more) transistor among the multiple transistors is a dual-gate transistor. The dual-gate transistor is disposed in the sub-transistor distribution layer closest to the base substrate 101. The gate film layer of the sub-transistor distribution layer closest to the base substrate includes a top gate pattern of the dual-gate transistor, and the light shielding layer 30 includes a bottom gate pattern of the dual-gate transistor.

[0141] Here, the “sub-transistor distribution layer closest to the base substrate 101 ” refers to the sub-transistor distribution layer where the active film layer closest to the base substrate 101 is located among the stacked active film layers of the plurality of sub-transistors.

[0142] Exemplarily, referring to FIG. 7 , the active film layer closest to the base substrate 101 is the first active film layer 11 , and thus the sub-transistor distribution layer closest to the base substrate 101 is the first sub-transistor distribution layer.

[0143] In some examples, the driving transistor T3 may be a dual-gate transistor. The driving transistor T3 includes an active layer pattern T31 of the driving transistor T3, a gate pattern T32 (top gate pattern) of the driving transistor T3, and a bottom gate pattern T33 of the driving transistor T3. The active layer pattern T31 of the driving transistor T3 is disposed on the first active film layer 11, the gate pattern T32 (top gate pattern) of the driving transistor is disposed on the first gate film layer 13, and the bottom gate pattern T33 of the driving transistor T3 is disposed on the light shielding layer 30. The bottom gate pattern T33 overlaps with the active layer pattern T31 of the driving transistor T3. Specifically, the bottom gate pattern T33 overlaps with the channel region T31b of the active layer pattern T31 of the driving transistor T3, thereby shielding light from the driving transistor T3 and preventing the characteristics of the driving transistor T3 from being affected by light.

[0144] In some other examples, the write transistor T2 may be a dual-gate transistor, comprising an active layer pattern T21 of the write transistor T2, a gate pattern T22 (top gate pattern) of the write transistor T2, and a bottom gate pattern T23 of the write transistor T2 (not shown). The active layer pattern T21 of the write transistor T2 is disposed on the first active film layer 11, the gate pattern T22 (top gate pattern) of the write transistor T2 is disposed on the first gate film layer 13, and the bottom gate pattern T33 of the write transistor T2 is disposed on the light shielding layer 30. The bottom gate pattern T33 of the write transistor T2 overlaps with the channel region T21b of the active layer pattern T21 of the write transistor T2, thereby shielding light from entering the write transistor T2 and preventing the characteristics of the write transistor T2 from being altered by light.

[0145] In some other examples, the driving transistor T3 and the writing transistor T2 are both dual-gate transistors, and the bottom gate pattern T33 of the driving transistor T3 and the bottom gate pattern T23 of the writing transistor T2 are both located on the light shielding layer 30 .

[0146] Driving the active layer pattern through the top-gate pattern and the bottom-gate pattern makes it easier to control the threshold voltage and improve carrier mobility. In other words, compared with top-gate transistors and bottom-gate transistors, dual-gate transistors have higher stability.

[0147] In some embodiments, referring again to FIG8 , the light shielding layer 30 and the second source / drain metal layer 182 are coextensive. In other words, the second source / drain metal layer 182 is also located below the transistor distribution layer. The light shielding layer 30 can be formed simultaneously with the second source / drain metal layer 182 to reduce process steps and improve production efficiency.

[0148] In some embodiments, referring again to FIG7 , the array substrate 10 further includes a fifth source / drain metal layer 185. The fifth source / drain metal layer 185 is disposed on an upper side of the first source / drain metal layer 181. The fifth source / drain metal layer 185 includes a second anode transfer pattern 1851, which is connected to the first anode transfer pattern 1811 via a via penetrating the sixth insulating layer 126.

[0149] The array substrate 10 also includes a planarization layer 19, which is primarily used to block water, oxygen, and alkaline ions. Planarization layer 19 is disposed on top of the first source / drain metal layer 181. Specifically, planarization layer 19 is located between the anode layer 21 and the fifth source / drain metal layer 185, and covers the fifth source / drain metal layer 185. Planarization layer 19 can be formed by applying PI (polyimide) using a spin coating process, or by depositing silicon nitride, silicon oxide, or silicon oxynitride using a thin film substrate process.

[0150] The first anode switching pattern 1811 is connected to the anode 211 of the anode layer 21 through the second anode switching pattern 1851 .

[0151] In some examples, the second source / drain metal layer 182 and the fifth source / drain metal layer 185 are the same layer. It is understood that the sensing line S and the second anode transfer pattern 1851 are located on the same layer, and the planarization layer 19 covers the fifth source / drain metal layer 185 and the sensing line S. When forming the second source / drain metal layer 182, the sensing line S and the second anode transfer pattern 1851 can be formed simultaneously, reducing process steps and improving product production efficiency.

[0152] In some other examples, the second source-drain metal layer 182 and the fifth source-drain metal layer 185 may not be the same layer. The fifth source-drain metal layer 185 is disposed on the upper side of the second source-drain metal layer 182 .

[0153] FIG10 is a structural diagram of another display panel provided by some embodiments of the present disclosure.

[0154] In some embodiments, as shown in FIG10 , the array substrate 10 further includes a planarization layer 19 . The planarization layer 19 is disposed on top of the first source / drain metal layer 181 and covers the sensing line S. The pixel circuit stack 102 does not include a fifth source / drain metal layer. The first anode transfer pattern 1811 is connected to the anode 211 via a via extending through the planarization layer 19 . During the fabrication process, the planarization layer 19 is formed directly after the second source / drain metal layer 182 is formed, reducing the fabrication process.

[0155] The area corresponding to each sub-pixel SP on the array substrate 10 is a sub-pixel region, and the sub-pixel regions are also arranged in multiple rows and columns. Taking the 2*2 pixel design of a display panel as an example, the 2*2 pixel includes a first pixel, a second pixel, a third pixel, and a fourth pixel. The area corresponding to the first pixel on the array substrate 10 is the first pixel region P1, the area corresponding to the second pixel on the array substrate 10 is the second pixel region P2, the area corresponding to the third pixel on the array substrate 10 is the third pixel region P3, and the area corresponding to the fourth pixel on the array substrate 10 is the fourth pixel region P4. The first pixel region P1 is arranged in the same row as the second pixel region P2, and the third pixel region P3 is arranged in the same row as the fourth pixel region P4. The first pixel region P1 and the fourth pixel region P4 are arranged in the same column, and the second pixel region P2 and the third pixel region P3 are arranged in the same column.

[0156] Each pixel region includes three sub-pixel regions arranged along the first direction X.

[0157] Figure 11A is a diagram illustrating a film layer stacking arrangement structure of multiple sub-pixel regions of an array substrate provided by some embodiments of the present disclosure. Figure 11B is an enlarged view of point E in Figure 11A. Figure 11C is an enlarged view of point F in Figure 11B.

[0158] Exemplarily, as shown in FIG. 11A and FIG. 11B , the first pixel region P1 includes a first sub-pixel region SP11 , a second sub-pixel region SP12 , and a third sub-pixel region SP13 .

[0159] 12A to 12O are structural diagrams of various film layers provided in some embodiments of the present disclosure.

[0160] Specifically, Figures 12A to 12O are structural diagrams of the various film layers in Figure 7. Taking the first pixel region P1 as an example, the steps for forming the film layer pattern of the first pixel region P1 are:

[0161] S1. An initial light shielding layer is formed on the base substrate 101 by deposition, and a light shielding layer 30 is formed through a patterning process. The light shielding layer 30 of the first sub-pixel region SP11, the second sub-pixel region SP12, and the third sub-pixel region SP13 are formed simultaneously. The film structure of the light shielding layer 30 is shown in FIG12A. The light shielding layer 30 may include a bottom gate pattern T33 of the driving transistor T3. The material of the light shielding layer 30 may be a metallic conductive material such as titanium (Ti), aluminum (Al), copper (Cu), or molybdenum (Mo). The structure of the light shielding layer 30 is described above and will not be repeated here.

[0162] S2. Form a ninth insulating layer 129 on the base substrate 101. The ninth insulating layer 129 covers the light shielding layer 30. The material of the ninth insulating layer 129 can refer to the above description of the inorganic insulating material, which will not be repeated here.

[0163] S3. An initial third source / drain metal layer is formed, and a patterning process is performed to form a third source / drain metal layer 183. The film structure of the third source / drain metal layer 183 is shown in FIG12B. The third source / drain metal layer 183 includes data signal lines D for connecting to the subsequently formed data signal transfer pattern Dt. The materials for the third source / drain metal layer 183 can be found in the materials for the light shielding layer 30 and are not described in detail here. The structure of the third source / drain metal layer 183 is described above and is not described in detail here.

[0164] S4 , forming a seventh insulating layer 127 . The seventh insulating layer 127 covers the third source / drain metal layer 183 .

[0165] S5. An initial first active film layer is formed, and a single patterning process is performed to form the first active film layer 11. The first active film layer 11 includes an active layer pattern T31 for the drive transistor T3 and an active layer pattern T21 for the write transistor T2. The film structure of the first active film layer 11 is shown in FIG12C . The materials for the first active film layer 11 can be found in the materials for the light shielding layer 30 and are not further described here. The structure of the first active film layer 11 is described above and is not further described here.

[0166] In some implementations, an active film layer including an active layer pattern T31 of the driving transistor T3 and an active film layer including an active layer pattern T21 of the writing transistor T2 may be formed separately, and the two active film layers are separated by an insulating layer.

[0167] S6 , forming a fifth insulating layer 125 , wherein the fifth insulating layer 125 covers the first active film layer 11 .

[0168] S7. An initial third gate film layer is formed, and a third gate film layer G3 is formed through a single patterning process. The third gate film layer G3 includes a gate pattern T32 of the drive transistor T3, a gate pattern T12 of the sensing transistor T1, and a gate pattern T22 of the write transistor T2. The film structure of the third gate film layer G3 is shown in FIG12D , where the gate pattern T32 of the drive transistor T3 and the gate pattern T22 of the write transistor T2 are interconnected. The material of the third gate film layer G3 can be found in the material of the light shielding layer 30 and will not be described in detail here. The structure of the third gate film layer G3 is described above and will not be described in detail here.

[0169] In some implementations, a gate film layer including a gate pattern T32 of the driving transistor T3, a gate film layer including a gate pattern T12 of the sensing transistor T1, and a gate film layer including a gate pattern T22 of the writing transistor T2 may be formed separately, with adjacent gate film layers separated by an insulating layer.

[0170] In some implementations, a lightly doped drain (LDD) structure can be provided in the channel region of the transistor near the drain. The LDD film structure is shown in FIG12E . The LDD structure provides a low-doped drain region in the channel of the transistor near the drain, allowing the low-doped drain region to also withstand a portion of the voltage. This structure can prevent hot electron degradation effects.

[0171] S8. Form a fourth insulating layer 124. The fourth insulating layer 124 covers the third gate film layer G3. The film structure of the fourth insulating layer 124 is shown in FIG12F. The fourth insulating layer 124 is provided with through holes for connecting between functional layers.

[0172] S9. An initial first transfer layer is formed, and a single patterning process is performed to form the first transfer layer 14. The first transfer layer 14 includes the second electrode C2 of the storage capacitor C. The film structure of the first transfer layer 14 is shown in FIG12G . The materials for the first transfer layer 14 can be found in the materials for the light shielding layer 30 and are not described in detail here. The structure of the first transfer layer 14 is described above and is not described in detail here.

[0173] S10: Form a third insulating layer 123, which covers the first transfer layer 14. The film structure of the third insulating layer 123 is shown in Figure 12H. The third insulating layer 123 is provided with through holes for connecting between functional layers.

[0174] S11: An initial second active film layer is formed, followed by a single patterning process to form a second active film layer 16. The second active film layer 16 includes an active layer pattern T11 for the sensing transistor T1. The film structure of the second active film layer 16 is shown in FIG12I . The materials for the second active film layer 16 can be found in the materials for the light shielding layer 30 and are not further described here. The structure of the second active film layer 16 is described above and is not further described here.

[0175] S12. An initial first source-drain metal layer is formed, and a first source-drain metal layer 181 is formed through a patterning process. The film structure of the first source-drain metal layer 181 is shown in FIG12J. The first source-drain metal layer 181 includes a first anode transfer pattern 1811, and may also include a first voltage signal line VDD, a sensing line transfer pattern 1812, and a first transfer pattern Se. The material of the first source-drain metal layer 181 can refer to the material of the light-shielding layer 30, and will not be repeated here. The first anode transfer pattern 1811 of the first source-drain metal layer 181 is directly overlapped with the active layer pattern T11 of the sensing transistor T1. The structure of the first source-drain metal layer 181 is described above and will not be repeated here.

[0176] S13 , forming a sixth insulating layer 126 , which covers the first source / drain metal layer 181 . The film structure of the sixth insulating layer 126 is shown in FIG12K . The sixth insulating layer 126 is provided with a through hole for connecting to the anode layer 21 .

[0177] S14. An initial second source / drain metal layer is formed, and a second source / drain metal layer 182 is formed through a single patterning process. The film structure of the second source / drain metal layer 182 is shown in FIG12L . The materials of the second source / drain metal layer 182 can be referred to as the materials of the light shielding layer 30 and are not described in detail here. The second source / drain metal layer 182 includes a sensing line S and a second anode transfer pattern 1851. The structure of the second source / drain metal layer 182 is described above and is not described in detail here.

[0178] In some implementations, a second source / drain metal layer 182 including the sensing line S and a fifth source / drain metal layer 185 including the second anode transfer pattern 1851 may be formed separately. Adjacent source / drain metal layers are separated by an insulating layer.

[0179] S15: forming a planar layer 19, which covers the second source / drain metal layer 182. The film structure of the planar layer 19 is shown in FIG12M. The planar layer 19 is provided with a through hole for connecting to the anode layer 21.

[0180] S16: forming an initial anode layer, and performing a patterning process to form the anode layer 21. The film structure of the anode layer 21 is shown in FIG12N.

[0181] S17: forming a pixel defining layer 22. The structure of the pixel defining layer 22 can be found in the above description and will not be repeated here. The film structure of the pixel defining layer 22 is shown in FIG12O.

[0182] In some embodiments, the patterns of at least two (eg, two, or more) film layers in two adjacent sub-pixel regions arranged along the second direction Y are symmetrically arranged, and the axis of symmetry is a straight line parallel to the first direction X.

[0183] For example, as shown in Figures 11A and 11B, the first pixel region P1 includes a first sub-pixel region SP11, a second sub-pixel region SP12, and a third sub-pixel region SP13. The fourth pixel region P4 includes a first sub-pixel region SP41, a second sub-pixel region SP42, and a third sub-pixel region SP43. Along the second direction Y, the first sub-pixel region SP11 of the first pixel region P1 is adjacent to the first sub-pixel region SP41 of the fourth pixel region P4, the second sub-pixel region SP12 of the first pixel region P1 is adjacent to the second sub-pixel region SP42 of the fourth pixel region P4, and the third sub-pixel region SP13 of the first pixel region P1 is adjacent to the third sub-pixel region SP43 of the fourth pixel region P4.

[0184] In this way, the film layer patterns of the first sub-pixel region SP11 of the first pixel region P1 and the first sub-pixel region SP41 of the fourth pixel region P4 are symmetrical along a line parallel to the first direction X. The second sub-pixel region SP12 of the first pixel region P1 and the second sub-pixel region SP42 of the fourth pixel region P4 are symmetrical along a line parallel to the first direction X. The third sub-pixel region SP13 of the first pixel region P1 and the third sub-pixel region SP43 of the fourth pixel region P4 are symmetrical along a line parallel to the first direction X. The symmetric arrangement along the second direction Y can reduce the total area of ​​the multiple sub-pixel regions, further reducing the space occupied by the multiple sub-pixels, which is beneficial for improving the PPI of the display panel while simplifying the pattern design of each film layer.

[0185] The film layer structures located between adjacent sub-pixel regions in the second direction Y may overlap. For example, the first voltage signal line VDD may be shared by the first pixel region P1 and the fourth pixel region P4, the data signal transfer pattern may be shared by the first pixel region P1 and the fourth pixel region P4, and the sensing line may be shared by the first pixel region P1 and the fourth pixel region P4.

[0186] Figure 13A is a diagram illustrating a film layer stacking arrangement structure of multiple sub-pixel regions of an array substrate provided by some embodiments of the present disclosure. Figure 13B is an enlarged view of point M in Figure 13A. Figure 13C is an enlarged view of point N in Figure 13B.

[0187] As another example, as shown in FIG13A , the first pixel region P1 includes a first sub-pixel region SP11 , a second sub-pixel region SP12 , and a third sub-pixel region SP13 .

[0188] For example, as shown in FIG14A to FIG14C , taking four adjacent sub-pixel regions along the first direction X as an example, the four sub-pixel regions include a first sub-pixel region SP11, a second sub-pixel region SP12, a third sub-pixel region SP13, and a fourth sub-pixel region SP14. Along the first direction X, the first sub-pixel region SP11 is adjacent to the second sub-pixel region SP12, the second sub-pixel region SP12 is adjacent to the third sub-pixel region SP13, and the third sub-pixel region SP13 is adjacent to the fourth sub-pixel region SP14.

[0189] 14A to 14O are structural diagrams of various film layers provided in some embodiments of the present disclosure.

[0190] Specifically, Figures 14A to 14O are another structural diagram of each film layer in Figure 7. Taking the first sub-pixel region SP11 and the second sub-pixel region SP12 as an example, the steps of forming the film layer pattern are:

[0191] S1. An initial light shielding layer is formed on the base substrate 101 by deposition, and then a light shielding layer 30 is formed through a single patterning process. The light shielding layer 30 is formed simultaneously in the first sub-pixel region SP11 and the second sub-pixel region SP12. The film structure of the light shielding layer 30 is shown in FIG14A . The light shielding layers 30 in the first sub-pixel region SP11 and the second sub-pixel region SP12 can be symmetrically arranged along the first direction X. The light shielding layer 30 may include a bottom gate pattern T33 of the driving transistor T3. The materials and structure of the light shielding layer 30 are described above and are not further elaborated here.

[0192] S2. Form a ninth insulating layer 129 on the base substrate 101. The ninth insulating layer 129 covers the light shielding layer 30. The material of the ninth insulating layer 129 can refer to the above description of the inorganic insulating material, which will not be repeated here.

[0193] S3. An initial third source / drain metal layer is formed, and a single patterning process is performed to form a third source / drain metal layer 183. The film structure of the third source / drain metal layer 183 is shown in FIG14B . The third source / drain metal layer 183 includes data signal lines D. The data signal lines D in the first sub-pixel region SP11 and the second sub-pixel region SP12 can be symmetrically arranged along the first direction X. The materials and structure of the third source / drain metal layer 183 are described above and are not further elaborated here.

[0194] S4 , forming a seventh insulating layer 127 . The seventh insulating layer 127 covers the third source / drain metal layer 183 .

[0195] S5. An initial first active film layer is formed, and a single patterning process is performed to form the first active film layer 11. The first active film layer 11 includes an active layer pattern T31 for the drive transistor T3 and an active layer pattern T21 for the write transistor T2. The film structure of the first active film layer 11 is shown in FIG14C . The active layer pattern T21 for the write transistor T2 in the first sub-pixel region SP11 and the second sub-pixel region SP12 are connected via a first transfer pattern 111. The materials and structure of the first active film layer 11 are described above and are not further elaborated here.

[0196] S6 , forming a fifth insulating layer 125 , wherein the fifth insulating layer 125 covers the first active film layer 11 .

[0197] S7: An initial third gate film layer is formed, and a single patterning process is performed to form a third gate film layer G3. The third gate film layer G3 includes a gate pattern T32 for the drive transistor T3, a gate pattern T12 for the sensing transistor T1, and a gate pattern T22 for the write transistor T2. The film structure of the third gate film layer G3 is shown in FIG14D . The materials and structure of the third gate film layer G3 are described above and are not further described here.

[0198] A lightly doped drain (LDD) structure can also be provided in the transistor channel region near the drain. The LDD film structure is shown in Figure 14E. The LDD structure provides a low-doped drain region in the transistor channel near the drain, allowing the low-doped drain region to also bear a portion of the voltage. This structure can prevent the hot electron degradation effect.

[0199] S8. Form a fourth insulating layer 124. The fourth insulating layer 124 covers the third gate film layer G3. The film structure of the fourth insulating layer 124 is shown in FIG14F. ​​The fourth insulating layer 124 is provided with through holes for connecting between functional layers.

[0200] S9. An initial first transfer layer is formed, followed by a single patterning process to form the first transfer layer 14. The first transfer layer 14 includes the second electrode C2 of the storage capacitor C. The film structure of the first transfer layer 14 is shown in Figure 14G. The materials and structure of the first transfer layer 14 are described above and are not repeated here. The patterns of the first transfer layer 14 in the first sub-pixel region SP11 and the second sub-pixel region SP12 can be symmetrically arranged along the first direction X.

[0201] S10: Form a third insulating layer 123, which covers the first transfer layer 14. The film structure of the third insulating layer 123 is shown in Figure 14H. The third insulating layer 123 is provided with through holes for connecting between functional layers.

[0202] S11: An initial second active film layer is formed, followed by a single patterning process to form a second active film layer 16. The second active film layer 16 includes an active layer pattern T11 for the sensing transistor T1. The film structure of the second active film layer 16 is shown in FIG14I . The materials and structure of the second active film layer 16 are described above and will not be repeated here.

[0203] S12. An initial first source-drain metal layer is formed, and a first source-drain metal layer 181 is formed through a patterning process. The film structure of the first source-drain metal layer 181 is shown in FIG12J. The first source-drain metal layer 181 includes a first anode transfer pattern 1811, and may also include a first voltage signal line VDD, a sensing line transfer pattern 1812, and a first transfer pattern Se. Among them, the first voltage signal line VDD of the first sub-pixel area SP11 and the second sub-pixel area SP12 are connected through the second transfer pattern 1816. The material and structure of the first source-drain metal layer 181 are described above and will not be repeated here. The first anode transfer pattern 1811, the first voltage signal line VDD, the sensing line transfer pattern 1812, and the first transfer pattern Se of the first sub-pixel area SP11 and the second sub-pixel area SP12 can be symmetrically arranged along the first direction X.

[0204] S13 , forming a sixth insulating layer 126 , which covers the first source / drain metal layer 181 . The film structure of the sixth insulating layer 126 is shown in FIG14K . The sixth insulating layer 126 is provided with a through hole for connecting to the anode layer 21 .

[0205] S14: An initial second source / drain metal layer is formed, and a patterning process is performed to form a second source / drain metal layer 182. The film structure of the second source / drain metal layer 182 is shown in FIG14L . The second source / drain metal layer 182 includes a sensing line S and a second anode transfer pattern 1851. The materials and structure of the second source / drain metal layer 182 are described above and are not repeated here.

[0206] S15: forming a planar layer 19, which covers the second source / drain metal layer 182. The film structure of the planar layer 19 is shown in FIG14M. The planar layer 19 is provided with a through hole for connecting to the anode layer 21.

[0207] S16: Form an initial anode layer, and then perform a patterning process to form the anode layer 21. The film structure of the anode layer 21 is shown in FIG14N. The anode layers 21 of the first sub-pixel region SP11 and the second sub-pixel region SP12 can be symmetrically arranged along the first direction X.

[0208] S17: forming a pixel defining layer 22. The structure of the pixel defining layer 22 can be found in the above description and will not be repeated here. The film structure of the pixel defining layer 22 is shown in FIG14O.

[0209] In some embodiments, at least two (e.g., two, or more) film layer patterns of each of two adjacent sub-pixel regions arranged along the first direction X are symmetrically arranged, with the axis of symmetry being a straight line parallel to the second direction Y. For example, the film layer patterns in the first sub-pixel region SP11 and the second sub-pixel region SP12 are symmetrical along the first direction X. The film layer structures of the light shielding layer 30, the third source / drain metal layer 183, the first active film layer 11, the third gate film layer G1, the first transfer layer 14, the first active film layer 16, and the first source / drain metal layer 181 in the first sub-pixel region SP11 and the second sub-pixel region SP12 are symmetrical along a straight line parallel to the second direction Y. The vias in the fourth insulating layer 124, the third insulating layer 123, and the sixth insulating layer 126 are also symmetrical along a straight line parallel to the second direction Y.

[0210] In another exemplary embodiment, the film layer patterns in the second sub-pixel region SP12 and the third sub-pixel region SP13 are symmetrical along a line parallel to the second direction Y. In another exemplary embodiment, the film layer patterns in the third sub-pixel region SP13 and the fourth sub-pixel region SP14 are symmetrical along a line parallel to the second direction Y.

[0211] The symmetrical arrangement of the film layer structures of adjacent sub-pixel regions along the first direction X can reduce the total area of ​​multiple sub-pixel regions, further reducing the space occupied by multiple sub-pixels, which is beneficial for improving the PPI of the display panel and simplifying the pattern design of each film layer.

[0212] Figure 15 is a structural diagram of a sub-pixel region provided by some embodiments of the present disclosure. Figure 16 is a structural diagram of yet another sub-pixel region provided by some embodiments of the present disclosure.

[0213] In some embodiments, the size H2 of the sub-pixel region along the second direction Y is larger than the size H1 of the sub-pixel region along the first direction X, thereby reducing the size in the first direction X and further reducing the area of ​​the pixel driving circuit in the first direction X.

[0214] For example, as shown in FIG15 , the ratio of the dimension H2a of the sub-pixel region along the second direction Y to the dimension H1a of the sub-pixel region along the second direction Y is 1:3. Three sub-pixel regions are arranged in a row to form a pixel region, and the dimension H2a of the three sub-pixel regions along the second direction Y is the same as the dimension H1a of the sub-pixel region along the first direction X, so that the pixel region has the same dimensions in the first direction X and the second direction Y.

[0215] As another example, as shown in FIG16 , the ratio of dimension H2b of the sub-pixel region along the second direction Y to dimension H1b of the sub-pixel region along the second direction Y is 1:2. Two sub-pixel regions are arranged in a row, and two sub-pixel regions are arranged in a column. As a result, the four sub-pixel regions have the same dimensions in the first direction X and the second direction Y. This makes the film pattern design of each pixel region more compact, thereby increasing the number of pixel driving circuits and improving the PPI of the display panel 100.

[0216] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising: a plurality of pixel driving circuits arranged in a plurality of rows and columns, each of the plurality of pixel driving circuits comprising a plurality of transistors; The plurality of transistors includes at least a sensing transistor; The array substrate includes: substrate; a transistor distribution layer disposed on one side of the base substrate, wherein the transistor distribution layer is provided with an active layer pattern of the sensing transistor and a gate pattern of the sensing transistor, and the active layer pattern of the sensing transistor is farther away from the base substrate than the gate pattern of the sensing transistor; A first source-drain metal layer is provided on a side of the transistor distribution layer away from the base substrate. The first source-drain metal layer includes a first anode transfer pattern connected to the active layer pattern of the sensing transistor.

2. The array substrate according to claim 1, wherein: The active layer pattern of the sensing transistor is connected to a sensing line transfer pattern, and the sensing line transfer pattern is located in the first source-drain metal layer; The array substrate further includes: The second source-drain metal layer includes a sensing line, and the active layer pattern of the sensing transistor is connected to the sensing line through the sensing line transfer pattern.

3. The array substrate according to claim 1 or 2, wherein: The transistor distribution layer includes a plurality of sub-transistor distribution layers, each of which includes an active film layer and a gate film layer that are stacked, the active film layer including an active layer pattern of the transistor, and the gate film layer including a gate pattern of the transistor; the active film layers of the plurality of sub-transistor distribution layers are stacked, the active film layer of at least one sub-transistor distribution layer is a polysilicon active film layer, and the active film layer of at least one sub-transistor distribution layer is an oxide active film layer; The multiple transistors further include a write transistor and a drive transistor. Among the active layer patterns of the sensing transistor, the write transistor and the drive transistor, at least one active layer pattern is located in the polysilicon active film layer, and at least one active layer pattern is located in the oxide active film layer.

4. The array substrate according to claim 3, wherein: The multiple sub-transistor distribution layers include a first sub-transistor distribution layer and a second sub-transistor distribution layer, the active film layer of the first sub-transistor distribution layer is closer to the substrate than the active film layer of the second sub-transistor distribution layer, the gate film layer of the first sub-transistor distribution layer and the gate film layer of the second sub-transistor distribution layer are located between the active film layer of the first sub-transistor distribution layer and the active film layer of the second sub-transistor distribution layer; the gate film layer of the first sub-transistor distribution layer and the gate film layer of the second sub-transistor distribution layer are the same layer; The write transistor and the drive transistor are located in a first sub-transistor distribution layer, and the sense transistor is located in a second sub-transistor distribution layer.

5. The array substrate according to any one of claims 2 to 4, wherein: Also includes: a third source-drain metal layer, the third source-drain metal layer including a data signal line, the active layer pattern of the write transistor being connected to the data signal line via a data signal transfer pattern, the data signal transfer pattern being located in a first transfer gate film layer; the first transfer gate film layer being located between active film layers of adjacent sub-transistor distribution layers, or the first transfer gate film layer being the same layer as the first source-drain metal layer; One of the second source-drain metal layer and the third source-drain metal layer is disposed on a side of the transistor distribution layer close to the base substrate, and the other is disposed on a side of the first source-drain metal layer away from the base substrate.

6. The array substrate according to claim 5, wherein: When the second source / drain metal layer is disposed on a side of the first source / drain metal layer away from the base substrate, the sensing line covers a channel region of the active layer pattern of the sensing transistor in an orthographic projection onto the base substrate.

7. The array substrate according to any one of claims 3 to 6, wherein: The active layer pattern of the write transistor is connected to the gate pattern of the drive transistor through a first switching pattern; the first switching pattern is located in the first source-drain metal layer.

8. The array substrate according to any one of claims 3 to 7, wherein: The active layer pattern of the driving transistor is connected to the first voltage signal line through a via hole; the first voltage signal line is located in the first source-drain metal layer.

9. The array substrate according to any one of claims 3 to 8, wherein: Also includes: a light shielding layer provided on a side of the transistor distribution layer close to the base substrate; At least one transistor of the plurality of transistors is a dual-gate transistor, the dual-gate transistor being disposed in a sub-transistor distribution layer closest to the substrate, and the gate film layer of the sub-transistor distribution layer closest to the substrate comprising a top gate pattern of the dual-gate transistor; The light shielding layer includes a bottom gate pattern of the dual-gate transistor.

10. The array substrate according to claim 9, wherein: The light shielding layer and the second source / drain metal layer are the same layer.

11. The array substrate according to any one of claims 1 to 10, wherein: The array substrate includes a plurality of sub-pixel regions arranged in multiple rows and columns, and patterns of at least two film layers of every two adjacent sub-pixel regions arranged along the column direction are symmetrically arranged.

12. The array substrate according to any one of claims 1 to 11, wherein: The array substrate includes a plurality of sub-pixel regions arranged in multiple rows and columns, and patterns of at least two film layers of every two adjacent sub-pixel regions arranged along the row direction are symmetrically arranged.

13. The array substrate according to claim 11 or 12, wherein: The size of the sub-pixel region along the column direction is greater than the size of the sub-pixel region along the row direction.

14. The array substrate according to claim 13, wherein: The ratio of the size of the sub-pixel region along the column direction to the size of the sub-pixel region along the row direction is 1:3 or 1:

2.

15. The array substrate according to any one of claims 1 to 14, wherein: Also includes: The first anode transfer pattern is connected to the anode through a via hole penetrating the flat layer.

16. The array substrate according to any one of claims 1 to 14, wherein: Also includes: a planar layer provided on a side of the first source / drain metal layer away from the base substrate; a fifth source-drain metal layer disposed between the first source-drain metal layer and the planar layer, wherein the fifth source-drain metal layer includes a second anode transfer pattern; The first anode switching pattern is connected to the anode through the second anode switching pattern.

17. A display panel comprising: The array substrate according to any one of claims 1 to 16; An anode layer is provided on one side of the array substrate, and the anode layer includes a plurality of anodes, and the plurality of anodes are connected to the array substrate.

18. A display device comprising: The display panel as claimed in claim 17.

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