Digital low dropout linear regulator based on improved successive approximation logic

Abstract

The invention discloses a digital low dropout linear regulator based on improved successive approximation logic, which comprises a comparator, an MOS (Metal Oxide Semiconductor) transistor array, an improved successive approximation logic control module, a sampling-holding dynamic comparator, an analog-to-digital converter and a transient detector, a PMOS (P-channel Metal Oxide Semiconductor) transistor array is arranged in the analog-to-digital converter and has a comparison state and a PMOS transistor array state; the improved successive approximation logic control module is used for controlling the state switching of the analog-to-digital converter, whether the sampling-maintaining dynamic comparator works or not and the internal on-off state of the MOS tube array; the improved successive approximation logic control module has an estimation binary search mode, a reverse binary search mode, a bidirectional search mode and a freezing mode; the circuit has the advantages that the precision of output voltage is high, the circuit can be used for a high-precision on-chip power supply, the transient response speed is not limited by the scale of the MOS tube array, the transient response speed is high under any scale of the MOS tube array, obvious overshoot and undershoot phenomena cannot be caused, and the stability of the output voltage is high.

Description

TECHNICAL FIELD

[0001] The present application relates to a digital low-dropout linear regulator, in particular to a digital low-dropout linear regulator based on improved successive approximation logic. BACKGROUND

[0002] In the era of increasingly innovative power technology, after the revolution from chip-level to system-level of power management, the logic storage systems and high-performance computing scenarios that need to process massive data in real time, such as Internet of Things nodes, edge computing systems driven by artificial intelligence, and medical electronic devices, have put forward more stringent requirements for power management integrated circuits in terms of energy efficiency, precision, and dynamic adaptability.

[0003] A digital low-dropout linear regulator (DLDO) restructures the voltage stabilizing mechanism through full-digital control, breaking through the limitations of traditional analog architecture and exhibiting excellent performance in the low-voltage domain.

[0004] Traditional DLDOs usually include a comparator, a bidirectional shift register, and an MOS array. The MOS array is composed of 2 m MOS transistors, m is usually an integer greater than or equal to 7, and the sources of the 2 m MOS transistors are connected to the power supply voltage, and the drains are connected together to output the output voltage of the DLDO. The gates of each MOS transistor are used to input control signals to control its on-off state. The bidirectional shift register outputs 2 m control signals to the 2 m MOS transistors. When the traditional DLDO is working, the comparator compares the output voltage with the preset reference voltage to obtain a comparison signal indicating the size relationship between the output voltage and the reference voltage, which is output to the bidirectional shift register. The bidirectional shift register adjusts the 2 m control signals it currently outputs and outputs them one by one to the gates of the 2 m MOS transistors, controlling the on-off state of the 2 m MOS transistors to stabilize the output voltage. Since the bidirectional shift register in the traditional DLDO adjusts one control signal at a time, its transient response is relatively slow, and it adjusts when the output voltage is close to the preset reference voltage, which will cause the output voltage to have ripple, resulting in insufficient output voltage precision.

[0005] In recent years, DLDOs based on successive approximation logic have emerged. A DLDO based on successive approximation logic usually includes a comparator, a successive approximation type shift register, and an MOS array. The MOS array is composed of 2 n MOS transistors, n is usually an integer greater than or equal to 7, and the sources of the 2 nThe source of each MOS tube is connected to the power supply voltage, and the drain is connected together to output the output voltage of the DLDO. The gate of each MOS tube is used to connect the control signal that controls its on and off. The successive approximation shift register is used to output 2 n control signals to 2 n When the DLDO based on successive approximation logic works, the comparator compares its output voltage with the preset reference voltage, obtains a comparison signal indicating the relationship between the output voltage and the reference voltage, and outputs it to the successive approximation shift register. The successive approximation shift register uses a binary search strategy to find the current output of the 2 n After adjusting the control signals, they are output to 2 n The gate of the MOS tube controls 2 n The MOS tube is turned on or off to stabilize the output voltage.

[0006] In the aforementioned DLDO based on successive approximation logic, the successive approximation shift register uses a binary search strategy to adjust multiple control signals at a time. This results in large fluctuations in the output voltage during the adjustment process, manifesting as significant overshoot or undershoot, which adversely affects output voltage stability. Due to the binary search strategy, the transient response speed is fixed at n clock cycles. Although faster than traditional DLDO, its transient response speed is limited by the size of n (the size of the MOS transistor array) and is negatively correlated with the n value. Furthermore, the system operates when the output voltage reaches near the preset reference voltage, which causes output voltage ripple and leads to insufficient output voltage accuracy. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a digital low-dropout linear regulator based on improved successive approximation logic, which has high output voltage accuracy and can be used for a high-precision on-chip power supply. The transient response speed is not limited by the size of the MOS tube array. The transient response speed is fast under any MOS tube array size, and significant overshoot and undershoot phenomena will not be caused. The output voltage stability is high.

[0008] The technical solution adopted by the present invention to solve the above technical problems is: a digital low-voltage dropout linear regulator based on improved successive approximation logic, including a comparator and a MOS tube array, wherein the comparator is used to adjust the output voltage V OUT With the preset reference voltage V REF Comparison shows the output voltage V OUT With reference voltage V REFThe digital low-dropout linear regulator also includes an improved successive approximation logic control module, a sample-and-hold dynamic comparator, an analog-to-digital converter, and a transient detector. The analog-to-digital converter is internally provided with a PMOS tube array, which has a comparison state and a PMOS tube array state. When it is in the comparison state, it is used to compare the output voltage V OUT Compare with the preset reference voltage to get the output voltage V OUT With reference voltage V REF The comparison signal of the magnitude relationship is output to the improved successive approximation logic control module, and the output voltage V OUT The voltage output by the MOS transistor array is used to superimpose the output voltage with the voltage output by the MOS transistor array when it is in the PMOS transistor array state. At this time, the output voltage V OUT The improved successive approximation logic control module is used to control the state switching of the analog-to-digital converter, whether the sample-and-hold dynamic comparator works or not, and the internal on-off state of the MOS tube array. The improved successive approximation logic control module has an estimated binary search mode, a reverse binary search mode, a bidirectional search mode, and a freeze mode. When the improved successive approximation logic control module is in the estimated binary search mode, it determines whether to switch from the estimated binary search mode to the reverse binary search mode based on the comparison signal output by the analog-to-digital converter. If not, it determines the initial search bit number of the binary search strategy based on the comparison signal output by the analog-to-digital converter, and then adopts the binary search strategy to iterate based on the comparison signal CMP output by the comparator to control the internal on-off state of the MOS tube array. When the improved successive approximation logic control module is in the estimated binary search mode, it determines whether to switch from the estimated binary search mode to the reverse binary search mode based on the comparison signal output by the analog-to-digital converter. If not, it determines the initial search bit number of the binary search strategy based on the comparison signal output by the analog-to-digital converter, and then adopts the binary search strategy to iterate based on the comparison signal CMP output by the comparator to control the internal on-off state of the MOS tube array. When the logic control module is in the reverse binary search mode, the binary search strategy is used to control the internal on-off state of the MOS transistor array according to the comparison signal output by the analog-to-digital converter in a low-to-high order search sequence; when the improved successive approximation logic control module is in the bidirectional search mode, the bidirectional search strategy is used to control the internal on-off state of the MOS transistor array and the on-off state of the PMOS transistor array inside the analog-to-digital converter according to the comparison signal output by the analog-to-digital converter; when the improved successive approximation logic control module enters the freeze mode, the current state of the MOS transistor array and the analog-to-digital converter is kept unchanged, and the sample-and-hold dynamic comparator is controlled to start working; when the improved successive approximation logic control module is in the non-freeze mode, the sample-and-hold dynamic comparator is controlled not to work; the transient detector is used to detect the output voltage V OUTThe transient change is detected, and the detection result is sent to the improved successive approximation logic control module to control the improved successive approximation logic control module to enter an estimated dichotomy search mode or keep the current mode unchanged; the sample-hold dynamic comparator is used to detect whether the output voltage V OUT changes in working time, and the detection result is output to the improved successive approximation logic control module to control the improved successive approximation logic control module to keep the frozen mode or enter the bidirectional search mode.

[0009] Compared with the prior art, the improved successive approximation logic control module, the sample-hold dynamic comparator, the analog-to-digital converter and the transient detector are arranged, the transient detector detects the output voltage V OUT The transient change detection is an asynchronous detection mechanism and does not depend on a clock signal, can monitor and output a signal to the improved successive approximation logic control module in real time, and the improved successive approximation logic control module adopts the estimated dichotomy search mode in the search process, determines the initial search bit number of the dichotomy search strategy and performs dichotomy search, instead of fixed highest bit to lowest bit traversal search, so that the search time is shortened, the transient response speed is not limited by the MOS transistor array size, the transient response speed is fast under any MOS transistor array size, and significant overshoot and undershoot phenomena are not caused; the output voltage V OUT is adjusted by the output voltage of the PMOS transistor array in the analog-to-digital converter, the size of the PMOS transistor array is further improved, and the output voltage V OUT is further improved in accuracy; the frozen mode is adopted to keep the current state of the MOS transistor array and the analog-to-digital converter unchanged, and the ripple caused by the MOS transistor array switch is not generated; the sample-hold dynamic comparator can detect whether the output voltage V OUT changes in the frozen mode, if the change occurs, the bidirectional search mode is adopted to adjust the small-size PMOS array and the PMOS transistor array in the analog-to-digital converter to be set to be on or off, so that the output voltage V OUT is returned to the reference voltage V REF nearby, the load change resistance is good, and the stability of the digital low-dropout linear regulator is improved; therefore, the output voltage accuracy of the present application is high, the present application can be used for high-precision on-chip power supply, the transient response speed is not limited by the MOS transistor array size, the transient response speed is fast under any MOS transistor array size, significant overshoot and undershoot phenomena are not caused, and the output voltage stability is high.

[0010] The detection result output by the transient detector includes an undershoot signal Droop indicating whether the output voltage V OUT undershoots and an overshoot signal Overshoot indicating whether the output voltage V OUTThe improved successive approximation logic control module enters the estimated binary search mode when either the downstroke signal Droop or the upstroke signal Up is a pulse signal; the improved successive approximation logic control module maintains its current mode when both the downstroke signal Droop and the upstroke signal Up are low-level signals; the MOS transistor array includes a small-size PMOS transistor array and a large-size PMOS transistor array; the small-size PMOS transistor array consists of 2 8 PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 100n / 30n; the large-size PMOS tube array consists of 2 8 PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 800n / 30n; the 2 8 PMOS tubes and 2 of the large-size PMOS tube array 8 The sources of the PMOS tubes are connected to the power supply voltage VDD, the gates are connected to the improved successive approximation logic control module, and the drains are connected together to output voltage; the improved successive approximation logic control module outputs a control signal C<255:0> to control the 2 in the large-size PMOS tube array 8 The output control signal S<255:0> controls the on / off of the PMOS tubes in the small-size PMOS tube array. 8 The control signals C<255:0> and S<255:0> are both 256-bit binary data, and the 256-bit data of the control signal C<255:0> are output to the large-size PMOS tube array in a one-to-one correspondence. 8 The gates of the PMOS tubes are controlled to output the 256-bit data of the signal S<255:0> to the small-size PMOS tube array in a one-to-one correspondence. 8 The gate of a PMOS tube; when the gate of a PMOS tube in the MOS tube array is connected to 1, the PMOS tube is turned off, and when it is connected to 0, the PMOS tube is turned on; the comparison signal output by the analog-to-digital converter is recorded as CMP<5:0>, and the reference voltage connected to the analog-to-digital converter is recorded as V REF<5:0> , V REF<5:0> Including 6 reference voltage V REF<0> To V REF<5>The PMOS transistor array provided inside the analog-to-digital converter is composed of 12 PMOS transistors, and the width-to-length ratio of the 12 PMOS transistors is 100n / 30n; the sources of the 12 PMOS transistors in the PMOS transistor array provided inside the analog-to-digital converter are all connected to the power supply voltage VDD, the gates are respectively connected to the improved successive approximation logic control module, and the drains are connected together to output a voltage that is superimposed on the voltage output by the MOS transistor array to adjust the output voltage V OUT The improved successive approximation logic control module outputs a control signal Code<5:0> to control the on / off switching of the 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter. The control signal Code<5:0> is 6-bit binary data, and each bit of binary data controls the on / off switching of two PMOS transistors. The 6-bit data of the control signal Code<5:0> is output to the gates of the 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter in a one-to-one correspondence.

[0011] Furthermore, the detection result output by the sample-hold dynamic comparator is called a disturbance signal RD. The improved successive approximation logic control module outputs a control signal St to control whether the sample-hold dynamic comparator works. When the control signal St is at a low level, the sample-hold dynamic comparator starts working and the output represents the output voltage V OUT A disturbance signal RD indicating whether there has been a change is sent to the improved successive approximation logic control module. When the control signal St is at a high level, the sample-and-hold dynamic comparator does not work. The improved successive approximation logic control module outputs a control signal Ct to control the state of the analog-to-digital converter. When the improved successive approximation logic control module is in an estimated binary search mode, the output control signal Ct is at a low level, at which time the analog-to-digital converter is controlled to enter a comparison state. When the improved successive approximation logic control module is in a reverse binary search mode, a bidirectional search mode, or a freeze mode, the output control signal Ct is at a high level, at which time the analog-to-digital converter is controlled to enter a PMOS transistor array state.

[0012] Furthermore, when the improved successive approximation logic control module is in the estimated binary search mode, the current control signal S<255:0> and the current control signal Code<5:0> are kept unchanged. At the same time, if CMP<5:0> is 6'b000111, the improved successive approximation logic control module switches from the estimated binary search mode to the reverse binary search mode. If CMP<5:0> is 6'b111111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 7th bit, performs code-raising iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thereby achieves the output voltage V OUT If CMP<5:0> is 6'b000000 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 6th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT If CMP<5:0> is 6'b011111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT If CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, and changes the on-off state of the large-size PMOS array, thereby achieving the output voltage V OUT If CMP<5:0> is 6'b001111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUTIf CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs downscaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, and changes the on-off state of the large-size PMOS array, thereby achieving the output voltage V OUT When the improved successive approximation logic control module is in the reverse binary search mode, the current control signal C<255:0> and the current control signal Code<5:0> are kept unchanged, and a binary search strategy from low to high is adopted. According to the current value of the comparison signal CMP, it is iterated (if the current value of the comparison signal CMP is 1, the code is iterated upward, and if the current value of the comparison signal CMP is 0, the code is iterated downward), the control signal S<255:0> is updated, and the on-off state of the small-size PMOS array is changed, thereby achieving the output voltage V OUT When the improved successive approximation logic control module is in the bidirectional search mode, the current control signal C<255:0> is kept unchanged. If the disturbance signal RD is high, the current control signal Code<5:0> is kept unchanged, and the bidirectional search strategy is used to update the control signal S<255:0> to change the on-off state of the small-size PMOS array, thereby achieving the output voltage V OUT If the disturbance signal RD is low, the current control signal S<255:0> is kept unchanged, and the control signal Code<5:0> is updated using a bidirectional search strategy to change the on-off state of the PMOS array of the analog-to-digital converter to achieve the output voltage V OUT Adjustment;

[0013] Furthermore, the digital low-dropout linear regulator based on improved successive approximation logic further includes a bias voltage generating circuit, which is used to generate two bias voltages V bias_D and V bias_U , where V bias_D Output to the analog-to-digital converter V bias_D and V bias_U output to the transient detector.

[0014] Furthermore, the analog-to-digital converter has four input terminals, one output terminal and one input-output terminal, and the four input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal and the fourth input terminal. The first input terminal of the analog-to-digital converter is used to connect to the reference voltage V REF<5:0> The second input terminal is used to access the bias voltage V bias_DThe third input terminal is used to access the control signal Ct, the fourth input terminal is used to access the control signal Code<5:0>, and the input and output terminals are used to access the output voltage V when the analog-to-digital converter is in the comparison state. OUT Or when the analog-to-digital converter is in a PMOS transistor array state, the output voltage is superimposed on the voltage output by the MOS transistor array, and the output end is used to output a comparison signal CMP<5:0>; the analog-to-digital converter includes six analog-to-digital conversion units, each of which has four input ends, one output end, and one input-output end. The four input ends are respectively referred to as the first input end, the second input end, the third input end, and the fourth input end. The first input ends of the six analog-to-digital conversion units constitute the first input end of the analog-to-digital converter; the second input ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the second input end of the analog-to-digital converter; the third input ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the third input end of the analog-to-digital converter; the fourth input ends of the six analog-to-digital conversion units constitute the fourth input end of the analog-to-digital converter; the input and output ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the input and output end of the analog-to-digital converter; and the output ends of the six analog-to-digital conversion units constitute the output end of the analog-to-digital converter.

[0015] Furthermore, each analog-to-digital conversion unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, seven inverters, and four two-input NOR gates, wherein the first MO The S transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the sixth MOS transistor, the eighth MOS transistor, the tenth MOS transistor, the twelfth MOS transistor, the fourteenth MOS transistor, the sixteenth MOS transistor, the eighteenth MOS transistor, the twentieth MOS transistor, the twenty-fifth MOS transistor and the twenty-seventh MOS transistor are all PMOS transistors, and the fifth MOS transistor, the seventh MOS transistor, the ninth MOS transistor, the eleventh MOS transistor, the thirteenth MOS transistor, the fifteenth MOS transistor, the seventeenth MOS transistor, the nineteenth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, the twenty-third MOS transistor, the second The fourteenth MOS transistor and the twenty-sixth MOS transistor are both NMOS transistors. Each inverter has an input terminal, an output terminal, a power terminal, and a ground terminal. The power terminals of the seven inverters are all connected to the power supply voltage VDD, and the ground terminals are all grounded. The six inverters are respectively referred to as the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter. Each two-input NOR gate has a first input terminal, a second input terminal, and an output terminal. The four two-input NOR gates are respectively referred to as the first NOR gate, the second NOR gate, the third NOR gate, and the fourth NOR gate. The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the twenty-sixth MOS transistor, and the twenty-seventh MOS transistor are connected to the power supply voltage VDD. The sources of the second MOS transistor and the fourth MOS transistor are connected to the drains of the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor; the gate of the third MOS transistor is connected to the drains of the first MOS transistor, the second MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor, and the source of the twenty-second MOS transistor; the gate of the first MOS transistor is connected to the drains of the third MOS transistor, the fourth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, and the source of the twenty-first MOS transistor;The gates of the twenty-fifth and twenty-sixth MOS transistors are connected to the input end of the seventh inverter, and the connection ends thereof are the fourth input end of the analog-to-digital conversion unit. The output end of the seventh inverter is connected to the gates of the twenty-fourth and twenty-seventh MOS transistors. The sources of the fifteenth and sixteenth MOS transistors are grounded. The sources of the twenty-fourth and twenty-fifth MOS transistors are connected, and the connection ends thereof are the second input end of the analog-to-digital conversion unit. The drains of the twenty-fourth, twenty-fifth, twenty-sixth, and twenty-seventh MOS transistors are connected to the sources of the seventh and eighth MOS transistors. The gates of the fifth and eighth MOS transistors are connected to the output end of the first inverter. The sources of the ninth and tenth MOS transistors are connected to the input end of the fifth inverter. The gates of the ninth and twelfth MOS transistors are connected to the output end of the second inverter. The sources of the seventeenth and eighteenth MOS transistors are connected to the input end of the sixth inverter. The gates of the seventeenth and twentieth MOS transistors are connected to the output end of the third inverter. The gate of the twenty-first MOS tube is connected to the first input terminal of the analog-to-digital conversion unit; the drains of the twenty-first and twenty-second MOS tubes are connected to the source of the twenty-third MOS tube; the gate of the twenty-third MOS tube is connected to the drains of the thirteenth, fourteenth, fifteenth and sixteenth MOS tubes; the drain of the twenty-third MOS tube is grounded; the sixth, seventh, tenth, eleventh, fourteenth, fifteenth and sixteenth MOS tubes are connected to the drains of the 13th, 14th, 15th and 16 .... The gates of the eighteenth MOS transistor and the nineteenth MOS transistor are connected to the input ends of the first inverter, the second inverter, the third inverter, and the fourth inverter, and their connection ends serve as the third input end of the analog-to-digital conversion unit; the sources of the eleventh MOS transistor, the twelfth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor, and the gate of the twenty-second MOS transistor are connected, and their connection ends serve as the input and output ends of the analog-to-digital conversion unit; the sources of the fifth MOS transistor, the sixth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are all connected to the clock signal CLK;The gates of the thirteenth and sixteenth MOS transistors are connected to the output of the fourth inverter. The first input of the first NOR gate is connected to the output of the sixth inverter, the second input is respectively connected to the output of the second NOR gate and the second input of the fourth NOR gate, and the output is respectively connected to the first input of the second NOR gate and the first input of the third NOR gate. The second input of the second NOR gate is connected to the output of the fifth inverter, the second input of the third NOR gate is connected to the output of the fourth NOR gate, the output of the third NOR gate is connected to the first input of the fourth NOR gate, and the connection end thereof is the output of the analog-to-digital conversion unit.

[0016] Furthermore, the sample-and-hold dynamic comparator includes a twenty-eighth MOS transistor, a twenty-ninth MOS transistor, a thirtieth MOS transistor, a thirty-first MOS transistor, a thirty-second MOS transistor, a thirty-third MOS transistor, a thirty-fourth MOS transistor, a thirty-fifth MOS transistor, a thirty-sixth MOS transistor, a thirty-seventh MOS transistor, a thirty-eighth MOS transistor, two capacitors, five inverters, two two-input AND gates, four two-input NOR gates, and two electronic switches. The twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirtieth MOS transistor, the thirty-first MOS transistor, and the thirty-third MOS transistor are all NMOS transistors, the thirty-second MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, and the thirty-eighth MOS transistor are all PMOS transistors, the input terminals of the five inverters are all connected to the power supply voltage VDD, and the ground terminals are all grounded. The five inverters are respectively referred to as an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, and a twelfth inverter. Each two-input AND gate is The device has a first input terminal, a second input terminal, and an output terminal. The two two-input AND gates are respectively referred to as a first AND gate and a second AND gate. The four two-input NOR gates are respectively referred to as a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, and an eighth NOR gate. Each electronic switch has two connection terminals and a control terminal. The control terminal is used to receive a control signal that controls the two connection terminals to be turned on or off. The two electronic switches are respectively referred to as a first switch and a second switch. The two capacitors are respectively referred to as a first capacitor and a second capacitor. The control terminal of the first switch is connected to the output terminal of the first AND gate. The first connection terminal of the first switch is connected to one terminal of the first capacitor and the gate of the twenty-ninth MOS transistor. The control terminal of the second switch is connected to the drains of the thirty-first MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, and the thirty-fourth MOS transistor. The first connection terminal of the second switch is connected to one terminal of the second capacitor and the gate of the twenty-eighth MOS transistor. The second connection terminals of the first switch and the second switch are connected, and their connection terminals are used to receive an output voltage VOUT ; the source of the thirty-fifth MOS, the thirty-sixth MOS, the thirty-seventh MOS, the thirty-eighth MOS are connected to the power voltage VDD; the input of the twelfth inverter is connected to the drain of the thirty-seventh MOS, the thirty-eighth MOS, the gate of the thirty-sixth MOS, the source of the twenty-ninth MOS; the input of the eighth inverter is connected to the drain of the thirty-fifth MOS, the thirty-sixth MOS, the gate of the thirty-seventh MOS, the source of the twenty-eighth MOS; the source of the thirty-first MOS, the thirty-second MOS is connected to the output of the second AND gate; the output of the ninth inverter is connected to the gate of the thirty-first MOS, the thirty-fourth MOS; the first input of the fifth NOR gate is connected to the output of the eighth inverter, the second input is connected to the output of the sixth NOR gate and the second input of the eighth NOR gate respectively, and the output is connected to the first input of the seventh NOR gate and the first input of the sixth NOR gate respectively; the second input of the sixth NOR gate is connected to the output of the twelfth inverter, and the second input of the seventh NOR gate is connected to the output of the eighth NOR gate; the output of the seventh NOR gate is connected to the first input of the eighth NOR gate, and the connection end is used to output the disturbance signal RD; the gate of the thirty-second MOS, the thirty-third MOS and the input of the ninth inverter are connected, and the connection end is used to input the control signal St, the input of the tenth inverter and the first input of the second AND gate input the clock signal CLK, and the output of the tenth inverter and the first input of the first AND gate are connected; the input of the eleventh inverter, the second input of the first AND gate, the second input of the second AND gate are connected to the clock signal CLK2, wherein the period of the clock signal CLK2 is twice that of the clock signal CLK, and the amplitude and phase are consistent with the clock signal CLK respectively; the output of the eleventh inverter, the gate of the thirty-fifth MOS, the thirty-eighth MOS, the thirty MOS are connected; the other end of the first capacitor, the other end of the second capacitor, the drain of the thirty MOS, the source of the thirty-third MOS, the thirty-fourth MOS are grounded; the drain of the twenty-ninth MOS, the drain of the twenty-eighth MOS and the source of the thirty MOS are connected.

[0017] Furthermore, the transient detector includes three inverters, five buffers, and two capacitors. The power supply terminals of the three inverters are all connected to the power supply voltage VDD. The three inverters are respectively referred to as the thirteenth inverter, the fourteenth inverter, and the fifteenth inverter. The five buffers are respectively referred to as the first buffer, the second buffer, the third buffer, the fourth buffer, and the fifth buffer. The two capacitors are respectively referred to as the third capacitor and the fourth capacitor. The input terminals of the first buffer and the third buffer, and one end of the third capacitor and the fourth capacitor are connected, and their connection terminals are connected to the output voltage V OUT The output terminal of the first buffer is connected to the input terminal of the fifteenth inverter; the ground terminal of the fifteenth inverter is connected to the bias voltage V bias_D The output end of the fifteenth inverter is connected to the input end of the thirteenth inverter and the other end of the third capacitor; the output end of the thirteenth inverter is connected to the input end of the second buffer; the output end of the second buffer is used to output the undershoot signal Droop, and the output end of the third buffer is connected to the input end of the fourteenth inverter; the ground end of the fourteenth inverter is connected to the bias voltage V bias_U ; The output end of the fourteenth inverter is connected to the input end of the fourth buffer and the other end of the fourth capacitor; the output end of the fourth buffer is connected to the input end of the fifth buffer; the output end of the fifth buffer is used to output an upstroke signal Up, and the ground ends of the thirteenth inverter and the fourteenth inverter are both grounded.

[0018] Furthermore, the inverter includes a 39th MOS transistor and a 40th MOS transistor; the 39th MOS transistor is a PMOS transistor, the 40th MOS transistor is an NMOS transistor, the source of the 39th MOS transistor serves as the power supply terminal of the inverter; the drain of the 39th MOS transistor is connected to the source of the 40th MOS transistor as the output terminal of the inverter; the gates of the 39th MOS transistor and the 40th MOS transistor are connected as the input terminal of the inverter; and the drain of the 40th MOS transistor serves as the ground terminal of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A structural block diagram of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0020] Figure 2 A structural block diagram of an analog-to-digital converter of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0021] Figure 3 A circuit diagram of an analog-to-digital conversion unit of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0022] Figure 4 A circuit diagram of a sample-and-hold dynamic comparator of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0023] Figure 5 A circuit diagram of a transient detector of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0024] Figure 6 A circuit diagram of an inverter of a digital low-dropout linear regulator based on improved successive approximation logic according to the present invention;

[0025] Figure 7 When the digital low voltage difference linear regulator based on improved successive approximation logic of the present invention is used to supply power to the load, the load current I LOAD Changes with output voltage V OUT The transient response diagram of

[0026] Figure 8 When the digital low voltage difference linear regulator based on improved successive approximation logic of the present invention is used to supply power to the load, the load current small disturbance change and the output voltage V OUT Transient response diagram of . DETAILED DESCRIPTION

[0027] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0028] Example 1: Figure 1 As shown, a digital low-voltage dropout linear regulator based on improved successive approximation logic includes a comparator and a MOS tube array. The comparator is used to adjust the output voltage V OUT With the preset reference voltage V REF Comparison shows the output voltage V OUT With reference voltage V REF The comparison signal CMP of the size relationship is output. The digital low-dropout linear regulator also includes an improved successive approximation logic control module, a sample-and-hold dynamic comparator, an analog-to-digital converter and a transient detector. The analog-to-digital converter is internally provided with a PMOS tube array, which has a comparison state and a PMOS tube array state. When it is in the comparison state, it is used to adjust the output voltage V OUT Compare with the preset reference voltage to get the output voltage V OUT With reference voltage V REF The comparison signal of the size relationship is output to the improved successive approximation logic control module, and the output voltage V OUT It is the voltage output by the MOS tube array. When it is in the PMOS tube array state, it is used to superimpose the output voltage with the voltage output by the MOS tube array. At this time, the output voltage V OUTThe improved successive approximation logic control module is used to control the state switching of the analog-to-digital converter, whether the sample-and-hold dynamic comparator works or not, and the internal on-off state of the MOS tube array. The improved successive approximation logic control module has an estimated binary search mode, a reverse binary search mode, a bidirectional search mode, and a freeze mode. When the improved successive approximation logic control module is in the estimated binary search mode, it determines whether to switch from the estimated binary search mode to the reverse binary search mode according to the comparison signal output by the analog-to-digital converter. If not, the binary search strategy is used to determine the initial search bit number according to the comparison signal output by the analog-to-digital converter, and then adopts the binary search strategy to iterate according to the comparison signal CMP output by the comparator to control the internal on-off state of the MOS tube array. When the improved successive approximation logic control module is in the estimated binary search mode, it determines whether to switch from the estimated binary search mode to the reverse binary search mode according to the comparison signal output by the analog-to-digital converter. If not, the binary search strategy is used to determine the initial search bit number according to the comparison signal output by the analog-to-digital converter, and then iterates according to the comparison signal CMP output by the comparator to control the internal on-off state of the MOS tube array. When the logic control module is in the reverse binary search mode, the binary search strategy is used to control the internal on-off state of the MOS tube array according to the comparison signal output by the analog-to-digital converter in a low-to-high search order; when the improved successive approximation logic control module is in the bidirectional search mode, the bidirectional search strategy is used to control the internal on-off state of the MOS tube array and the on-off state of the PMOS tube array inside the analog-to-digital converter according to the comparison signal output by the analog-to-digital converter; when the improved successive approximation logic control module enters the freeze mode, the current state of the MOS tube array and the analog-to-digital converter is kept unchanged, and the sample-hold dynamic comparator is controlled to start working; when the improved successive approximation logic control module is in the non-freeze mode, the sample-hold dynamic comparator is controlled not to work; the transient detector is used to detect the output voltage V OUT The transient change is detected and the detection result is sent to the improved successive approximation logic control module to control the improved successive approximation logic control module to enter the estimated binary search mode or maintain its current mode unchanged; the sample-hold dynamic comparator is used to detect the output voltage V OUT Whether a change occurs, and the detection result is output to the improved successive approximation logic control module, which controls the improved successive approximation logic control module to maintain the freeze mode or enter the bidirectional search mode.

[0029] In this embodiment, the detection result output by the transient detector includes the output voltage V OUT The undershoot signal Droop indicates whether the undershoot occurs and the output voltage V OUT Whether the uprush signal Up is uprush, when any one of the downrush signal Droop and the uprush signal Up is a pulse signal, the improved successive approximation logic control module enters the estimated binary search mode, and when the downrush signal Droop and the uprush signal Up are both low-level signals, the improved successive approximation logic control module maintains its current mode unchanged; the MOS tube array includes a small-size PMOS tube array and a large-size PMOS tube array; the small-size PMOS tube array consists of 2 8PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 100n / 30n; the large-size PMOS tube array consists of 2 8 PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 800n / 30n; the 2 8 2 PMOS tubes and large-size PMOS tube arrays 8 The source of each PMOS tube is connected to the power supply voltage VDD, the gate is connected to the improved successive approximation logic control module, and the drain is connected together to output voltage; the improved successive approximation logic control module outputs the control signal C<255:0> to control the 2 in the large size PMOS tube array 8 The output control signal S<255:0> controls the on / off of the 2 PMOS tubes in the small size PMOS tube array. 8 The control signals C<255:0> and S<255:0> are both 256-bit binary data. The 256-bit data of the control signal C<255:0> is output to the large-size PMOS tube array in a one-to-one correspondence. 8 The gates of the PMOS tubes are connected to the 256-bit data of the control signal S<255:0> and output to the small-size PMOS tube array in a one-to-one correspondence. 8 The gate of a PMOS tube; when the gate of a PMOS tube in the MOS tube array is connected to 1, the PMOS tube is turned off, and when it is connected to 0, the PMOS tube is turned on; the comparison signal output by the analog-to-digital converter is recorded as CMP<5:0>, and the reference voltage connected to the analog-to-digital converter is recorded as V REF<5:0> , V REF<5:0> Including 6 reference voltage V REF<0> To V REF<5> The PMOS transistor array provided inside the analog-to-digital converter is composed of 12 PMOS transistors, and the width-to-length ratio of the 12 PMOS transistors is 100n / 30n. The sources of the 12 PMOS transistors in the PMOS transistor array provided inside the analog-to-digital converter are all connected to the power supply voltage VDD, and the gates are respectively connected to the improved successive approximation logic control module, and the drains are connected together to output a voltage that is superimposed on the voltage output by the MOS transistor array to adjust the output voltage V OUT The improved successive approximation logic control module outputs a control signal Code<5:0> to control the on / off switching of 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter. The control signal Code<5:0> is 6-bit binary data, and each bit of binary data controls the on / off switching of two PMOS transistors. The 6-bit data of the control signal Code<5:0> is output one-to-one to the gates of the 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter.

[0030] In this embodiment, the PMOS tubes in the large-size PMOS tube array have a larger width-to-length ratio and can output a larger voltage. Although the resolution is low, the output voltage V can be increased by adjusting its on-off OUT Returns the preset reference voltage V REF Faster, small size PMOS tube array, PMOS tube width to length ratio is small, can output smaller voltage, higher resolution, during the adjustment process output voltage V OUT The change range is small, which can make the output voltage V OUT With the preset reference voltage V REF Therefore, the MOS tube array is composed of a small-size PMOS tube array and a large-size PMOS tube array, which can take into account both adjustment speed and adjustment accuracy.

[0031] In this embodiment, the detection result output by the sample-hold dynamic comparator is called the disturbance signal RD. The improved successive approximation logic control module outputs a control signal St to control whether the sample-hold dynamic comparator works. When the control signal St is at a low level, the sample-hold dynamic comparator starts working and the output represents the output voltage V OUT A disturbance signal RD indicating whether a change has occurred is sent to the improved successive approximation logic control module. When the control signal St is at a high level, the sample-and-hold dynamic comparator does not work. The improved successive approximation logic control module outputs a control signal Ct to control the state of the analog-to-digital converter. When the improved successive approximation logic control module is in an estimated binary search mode, the output control signal Ct is at a low level, at which point the analog-to-digital converter is controlled to enter a comparison state. When the improved successive approximation logic control module is in a reverse binary search mode, a bidirectional search mode, or a freeze mode, the output control signal Ct is at a high level, at which point the analog-to-digital converter is controlled to enter a PMOS tube array state.

[0032] In this embodiment, when the improved successive approximation logic control module is in the estimated binary search mode, the current control signal S<255:0> and the current control signal Code<5:0> are kept unchanged. At the same time, if CMP<5:0> is 6'b000111, the improved successive approximation logic control module switches from the estimated binary search mode to the reverse binary search mode. If CMP<5:0> is 6'b111111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 7th bit, performs code-raising iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thereby achieves the output voltage V OUTAdjustment; If CMP<5:0> is 6'b000000 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 6th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT Adjustment; If CMP<5:0> is 6'b011111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT Adjustment; If CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT Adjustment; If CMP<5:0> is 6'b001111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT Adjustment; If CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT When the improved successive approximation logic control module is in the reverse binary search mode, the current control signal C<255:0> and the current control signal Code<5:0> are kept unchanged, and a binary search strategy from low to high is adopted. According to the current value of the comparison signal CMP, it is iterated (if the current value of the comparison signal CMP is 1, the code is increased and iterated; if the current value of the comparison signal CMP is 0, the code is decreased and iterated), the control signal S<255:0> is updated, and the on-off state of the small-size PMOS array is changed, thereby achieving the output voltage V OUTWhen the improved successive approximation logic control module is in the bidirectional search mode, the current control signal C<255:0> is kept unchanged. If the disturbance signal RD is high, the current control signal Code<5:0> is kept unchanged, and the bidirectional search strategy is used to update the control signal S<255:0> to change the on-off state of the small-size PMOS array, thereby achieving the output voltage V OUT If the disturbance signal RD is low, the current control signal S<255:0> is kept unchanged, and the control signal Code<5:0> is updated using a bidirectional search strategy to change the on-off state of the PMOS array of the analog-to-digital converter to achieve the output voltage V OUT Adjustment;

[0033] Embodiment 2: This embodiment is basically the same as the embodiment 1, except that: in this embodiment, the digital low-dropout linear regulator based on improved successive approximation logic further includes a bias voltage generating circuit, which is used to generate two bias voltages V bias_D and V bias_U , where V bias_D Output to analog-to-digital converter V bias_D and V bias_U Output to the transient detector.

[0034] In this embodiment, two bias voltages V are generated by the bias voltage generating circuit. bias_D and V bias_U , the analog-to-digital converter is connected to V bias_D The digital code controlled by the control signal Code<5:0> is V bias_D / power supply voltage VDD instead of ground level GND / power supply voltage VDD, so that the PMOS tube array set inside the analog-to-digital converter has higher resolution and improves the voltage accuracy output by the analog-to-digital converter in the PMOS array state; V bias_D and V bias_U The internal node voltage of the transient detector is raised to improve its detection accuracy.

[0035] Example 3: This example is basically the same as Example 2, except that: Figure 2 As shown, in this embodiment, the analog-to-digital converter has four input terminals, one output terminal and one input-output terminal. The four input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal and the fourth input terminal. The first input terminal of the analog-to-digital converter is used to connect to the reference voltage V REF<5:0> The second input terminal is used to access the bias voltage V bias_D The third input terminal is used to access the control signal Ct, the fourth input terminal is used to access the control signal Code<5:0>, and the input and output terminals are used to access the output voltage V when the analog-to-digital converter is in the comparison state. OUTOr when the analog-to-digital converter is in the PMOS transistor array state, the output voltage is superimposed on the voltage output by the MOS transistor array, and the output terminal is used to output the comparison signal CMP<5:0>; the analog-to-digital converter includes six analog-to-digital conversion units, each of which has four input terminals, one output terminal, and one input-output terminal. The four input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal. The first input terminals of the six analog-to-digital conversion units constitute the first input terminal of the analog-to-digital converter; the second input terminals of the six analog-to-digital conversion units are connected, and the connection terminal thereof serves as the second input terminal of the analog-to-digital converter; the third input terminals of the six analog-to-digital conversion units are connected, and the connection terminal thereof serves as the third input terminal of the analog-to-digital converter; the fourth input terminals of the six analog-to-digital conversion units constitute the fourth input terminal of the analog-to-digital converter; the input and output terminals of the six analog-to-digital conversion units are connected, and the connection terminal thereof serves as the input and output terminals of the analog-to-digital converter; and the output terminals of the six analog-to-digital conversion units constitute the output terminal of the analog-to-digital converter.

[0036] like Figure 3As shown, in this embodiment, each analog-to-digital conversion unit includes a first MOS transistor MM1, a second MOS transistor MM2, a third MOS transistor MM3, a fourth MOS transistor MM4, a fifth MOS transistor MM5, a sixth MOS transistor MM6, a seventh MOS transistor MM7, an eighth MOS transistor MM8, a ninth MOS transistor MM9, a tenth MOS transistor MM10, an eleventh MOS transistor MM11, a twelfth MOS transistor MM12, a thirteenth MOS transistor MM13, a fourteenth MOS transistor MM14, a fifteenth MOS transistor MM15, a sixteenth MOS transistor MM16, a seventeenth MOS transistor MM17, an eighteenth MOS transistor MM18, a nineteenth MOS transistor MM19, and a twentieth MOS transistor MM2. 0, the twenty-first MOS tube MM21, the twenty-second MOS tube MM22, the twenty-third MOS tube MM23, the twenty-fourth MOS tube MM24, the twenty-fifth MOS tube MM25, the twenty-sixth MOS tube MM26, the twenty-seventh MOS tube MM27, seven inverters and four two-input NOR gates, the first MOS tube MM1, the second MOS tube MM2, the third MOS tube MM3, the fourth MOS tube MM4, the sixth MOS tube MM6, the eighth MOS tube MM8, the tenth MOS tube MM10, the twelfth MOS tube MM12, the fourteenth MOS tube MM14, the sixteenth MOS tube MM16, the eighteenth MOS tube MM18, the twentieth MOS tube MM20, the The twenty-fifth MOS tube MM25 and the twenty-seventh MOS tube MM27 are both PMOS tubes. The fifth MOS tube MM5, the seventh MOS tube MM7, the ninth MOS tube MM9, the eleventh MOS tube MM11, the thirteenth MOS tube MM13, the fifteenth MOS tube MM15, the seventeenth MOS tube MM17, the nineteenth MOS tube MM19, the twenty-first MOS tube MM21, the twenty-second MOS tube MM22, the twenty-third MOS tube MM23, the twenty-fourth MOS tube MM24 and the twenty-sixth MOS tube MM26 are all NMOS tubes. Each inverter has an input terminal, an output terminal, a power supply terminal and a ground terminal. The power supply terminal of the seven inverters is connected to the power supply voltage VDD, and the ground terminal is connected. The first and second terminals of the first MOS transistor MM1, the second MOS transistor MM2, the third MOS transistor MM3, the fourth MOS transistor MM4, the twenty-sixth MOS transistor MM26 and the twenty-seventh MOS transistor MM27 are connected to the power supply voltage VDD.The gate of the second MOS MM2 and the fourth MOS MM4 is connected with the drain of the fifth MOS MM5, the sixth MOS MM6, the seventh MOS MM7 and the eighth MOS MM8; the gate of the third MOS MM3 is connected with the drain of the first MOS MM1, the second MOS MM2, the seventeenth MOS MM17, the eighteenth MOS MM18, the nineteenth MOS MM19 and the twentieth MOS MM20, and the source of the twenty-second MOS MM22; the gate of the first MOS MM1 is connected with the drain of the third MOS MM3, the fourth MOS MM4, the ninth MOS MM9, the tenth MOS MM10, the eleventh MOS MM11 and the twelfth MOS MM12, and the source of the twenty-first MOS MM21; the gate of the twenty-fifth MOS MM25 and the twenty-sixth MOS MM26 is connected with the input of the seventh inverter INV7, and the connection end is the fourth input of the analog-digital conversion unit; the output of the seventh inverter INV7 is connected with the gate of the twenty-fourth MOS MM24 and the twenty-seventh MOS MM27; the source of the fifteenth MOS MM15 and the sixteenth MOS MM16 is grounded; the source of the twenty-fourth MOS MM24 and the twenty-fifth MOS MM25 is connected, and the connection end is the second input of the analog-digital conversion unit; the drain of the twenty-fourth MOS MM24, the twenty-fifth MOS MM25, the twenty-sixth MOS MM26 and the twenty-seventh MOS MM27 is connected with the source of the seventh MOS MM7 and the eighth MOS MM8; the gate of the fifth MOS MM5 and the eighth MOS MM8 is connected with the output of the first inverter INV1; the source of the ninth MOS MM9 and the tenth MOS MM10 is connected with the input of the fifth inverter INV5; the gate of the ninth MOS MM9 and the twelfth MOS MM12 is connected with the output of the second inverter INV2; the source of the seventeenth MOS MM17 and the eighteenth MOS MM18 is connected with the input of the sixth inverter INV6; the gate of the seventeenth MOS MM17 and the twentieth MOS MM20 is connected with the output of the third inverter INV3; the gate of the twenty-first MOS MM21 is the first input of the analog-digital conversion unit; the drain of the twenty-first MOS MM21 and the twenty-second MOS MM22 is connected with the source of the twenty-third MOS MM23; the gate of the twenty-third MOS MM23 is connected with the drain of the thirteenth MOS MM13, the fourteenth MOS MM14, the fifteenth MOS MM15 and the sixteenth MOS MM16; the drain of the twenty-third MOS MM23 is grounded.The gate of the sixth MOS MM6, the seventh MOS MM7, the tenth MOS MM10, the eleventh MOS MM11, the fourteenth MOS MM14, the fifteenth MOS MM15, the eighteenth MOS MM18, the nineteenth MOS MM19, the input of the first inverter INV1, the second inverter INV2, the third inverter INV3, and the fourth inverter INV4 are connected, and the connection end is the third input end of the analog-digital conversion unit; the source of the eleventh MOS MM11, the twelfth MOS MM12, the nineteenth MOS MM19, and the twentieth MOS MM20, and the gate of the twenty-second MOS MM22 are connected, and the connection end is the input and output end of the analog-digital conversion unit; the source of the fifth MOS MM5, the sixth MOS MM6, the thirteenth MOS MM13, and the fourteenth MOS MM14 are connected with the clock signal CLK; the gate of the thirteenth MOS MM13 and the sixteenth MOS MM16 is connected with the output of the fourth inverter INV4, the first input of the first OR gate OR1 is connected with the output of the sixth inverter INV6, the second input is connected with the output of the second OR gate OR2 and the second input of the fourth OR gate OR4 respectively, the output is connected with the first input of the second OR gate OR2 and the first input of the third OR gate OR3 respectively, the second input of the second OR gate OR2 is connected with the output of the fifth inverter INV5, the second input of the third OR gate OR3 is connected with the output of the fourth OR gate OR4, the output of the third OR gate OR3 is connected with the first input of the fourth OR gate OR4, and the connection end is the output end of the analog-digital conversion unit.

[0037] In the embodiment, the working principle of the analog-digital converter is that the twenty-fifth MOS MM25 and the twenty-sixth MOS MM26 in the six analog-digital conversion units are used as 12 PMOS tubes of the PMOS tube array in the analog-digital converter to form the PMOS tube array. The kth bit of the control signal Code<5:0> is recorded as Code <k-1>The kth bit of the comparison signal CMP<5:0> is denoted as CMP <k-1>, k=1, 2, 3, 4, 5, 6. When the control signal Ct connected to the third input terminal of the analog-to-digital converter is at a low level, the analog-to-digital converter is in a comparison state. In the kth analog-to-digital conversion unit, the fifth MOS transistor MM5, the sixth MOS transistor MM6, the ninth MOS transistor MM9, the tenth MOS transistor MM10, the thirteenth MOS transistor MM13, the fourteenth MOS transistor MM14, the seventeenth MOS transistor MM17, and the eighteenth MOS transistor MM18 are in a conducting state, and the seventh MOS transistor MM7, the eighth MOS transistor MM8, the eleventh MOS transistor MM11, the twelfth MOS transistor MM12, the fifteenth MOS transistor MM15, the sixteenth MOS transistor MM16, the nineteenth MOS transistor MM19, and The twentieth MOS transistor MM20 is in the off state; the gates of the second MOS transistor MM2, the fourth MOS transistor MM4, and the twenty-third MOS transistor MM23 are connected to the clock signal CLK. When the clock signal CLK is at a low level, the second MOS transistor MM2 and the fourth MOS transistor MM4 are turned on, and the twenty-third MOS transistor MM23 is turned off. At this time, the kth analog-to-digital conversion unit enters the pre-charging state; when the clock signal CLK is at a high level, the second MOS transistor MM2 and the fourth MOS transistor MM4 are turned off, and the twenty-third MOS transistor MM23 is turned on. At this time, the kth analog-to-digital conversion unit compares the signals connected to its first input terminal and the second input terminal, and generates a one-bit comparison signal CMP <k-1>The output terminal of the analog-to-digital converter outputs six-bit binary data, namely, the comparison signal CMP<5:0>. When the control signal Ct connected to the third input terminal of the analog-to-digital converter is at a high level, the analog-to-digital converter is in a PMOS array state. At this time, in each analog-to-digital conversion unit, the fifth MOS transistor MM5, the sixth MOS transistor MM6, the ninth MOS transistor MM9, the tenth MOS transistor MM10, the thirteenth MOS transistor MM13, the fourteenth MOS transistor MM14, the seventeenth MOS transistor MM17, the eighteenth MOS transistor MM18, and the twenty-third MOS transistor MM23 are in a turned-off state, and the seventh MOS transistor MM7, the eighth MOS transistor MM8, the eleventh MOS transistor MM11, the twelfth MOS transistor MM12, the fifteenth MOS transistor MM15, the sixteenth MOS transistor MM16, the nineteenth MOS transistor MM19, and the twentieth MOS transistor MM20 are in a turned-on state. When the control signal Code<5:0> connected to the fourth input terminal of the kth analog-to-digital conversion unit is at a high level, the analog-to-digital converter is in a PMOS array state. <k-1>When the level is low, in the analog-to-digital conversion unit, the twenty-fourth MOS tube MM24 and the twenty-fifth MOS tube MM25 are turned on, the twenty-sixth MOS tube MM26 and the twenty-seventh MOS tube MM27 are turned off, and the drains of the second MOS tube MM2 and the fourth MOS tube MM4 generate output voltages that are superimposed on the input and output terminals. When the fourth input terminal of the kth analog-to-digital conversion unit receives the control signal Code <k-1>When the level is high, in the analog-to-digital conversion unit, the twenty-fourth MOS transistor MM24 and the twenty-fifth MOS transistor MM25 are turned off, the twenty-sixth MOS transistor MM26 and the twenty-seventh MOS transistor MM27 are turned on, and the power supply voltage VDD is connected to the gate of the second MOS transistor MM2 and the fourth MOS transistor MM4, so that the second MOS transistor MM2 and the fourth MOS transistor MM4 are turned off and no voltage is output. Therefore, the control signal Code<5:0> is used to control the PMOS transistor array, so that the output voltage of the PMOS transistor array is superimposed on the voltage output by the MOS transistor array, and the output voltage V OUT Adjust and increase the output voltage V OUT precision.

[0038] Example 4: This example is basically the same as Example 3, except that: Figure 3 As shown, in this embodiment, the sample-and-hold dynamic comparator includes a twenty-eighth MOS transistor MM28, a twenty-ninth MOS transistor MM29, a thirtieth MOS transistor MM30, a thirty-first MOS transistor MM31, a thirty-second MOS transistor MM32, a thirty-third MOS transistor MM33, a thirty-fourth MOS transistor MM34, a thirty-fifth MOS transistor MM35, a thirty-sixth MOS transistor MM36, a thirty-seventh MOS transistor MM37, a thirty-eighth MOS transistor MM38, two capacitors, five inverters, two two-input AND gates, four two-input NOR gates, and two electronic switches. The twenty-eighth MOS transistor MM28, the twenty-second MOS transistor MM32, the thirty-third MOS transistor MM33, the thirty-fourth MOS transistor MM34, the thirty-fifth MOS transistor MM35, the thirty-sixth MOS transistor MM36, the thirty-seventh MOS transistor MM37, and the thirty-eighth MOS transistor MM38 The ninth MOS tube MM29, the thirtieth MOS tube MM30, the thirty-first MOS tube MM31, and the thirty-third MOS tube MM33 are all NMOS tubes. The thirty-second MOS tube MM32, the thirty-fourth MOS tube MM34, the thirty-fifth MOS tube MM35, the thirty-sixth MOS tube MM36, the thirty-seventh MOS tube MM37, and the thirty-eighth MOS tube MM38 are all PMOS tubes. The input terminals of the five inverters are all connected to the power supply voltage VDD, and the ground terminals are all grounded. The five inverters are respectively referred to as the eighth inverter INV8, the ninth inverter INV9, the tenth inverter INV10, and the eleventh inverter INV11. INV11, the twelfth inverter INV12, each two-input AND gate has a first input terminal, a second input terminal and an output terminal, the two two-input AND gates are respectively referred to as the first AND gate and the second AND gate, the four two-input NOR gates are respectively referred to as the fifth NOR gate OR5, the sixth NOR gate OR6, the seventh NOR gate OR7, and the eighth NOR gate OR8, each electronic switch has two connection terminals and a control terminal, the control terminal is used to receive a control signal that controls the two connection terminals to be turned on or off, the two electronic switches are respectively referred to as the first switch SW1 and the second switch SW2; the two capacitors are respectively referred to as the first capacitor C1 and the second capacitor C2, the first switch The control end of the switch SW1 is connected to the output end of the first AND gate; the first connection end of the first switch SW1 is connected to one end of the first capacitor C1 and the gate of the twenty-ninth MOS transistor MM29; the control end of the second switch SW2 is connected to the drains of the thirty-first MOS transistor MM31, the thirty-second MOS transistor MM32, the thirty-third MOS transistor MM33, and the thirty-fourth MOS transistor MM34; the first connection end of the second switch SW2 is connected to one end of the second capacitor C2 and the gate of the twenty-eighth MOS transistor MM28; the second connection ends of the first switch SW1 and the second switch SW2 are connected, and their connection ends are used to receive the output voltage V OUT The source electrodes of the thirty-fifth MOS transistor MM35, the thirty-sixth MOS transistor MM36, the thirty-seventh MOS transistor MM37 and the thirty-eighth MOS transistor MM38 are connected to the power voltage VDD; the input end of the twelfth inverter INV12 is connected to the drain electrodes of the thirty-seventh MOS transistor MM37 and the thirty-eighth MOS transistor MM38, the gate electrode of the thirty-sixth MOS transistor MM36 and the source electrode of the twenty-ninth MOS transistor MM29; the input end of the eighth inverter INV8 is connected to the drain electrodes of the thirty-fifth MOS transistor MM35 and the thirty-sixth MOS transistor MM36, the gate electrode of the thirty-seventh MOS transistor MM37 and the source electrode of the twenty-eighth MOS transistor MM28; the source electrodes of the thirty-first MOS transistor MM31 and the thirty-second MOS transistor MM32 are connected to the output end of the second AND gate; the output end of the ninth inverter INV9 is connected to the gate electrodes of the thirty-first MOS transistor MM31 and the thirty-fourth MOS transistor MM34; the first input end of the fifth OR gate OR5 is connected to the output end of the eighth inverter INV8, the second input end is connected to the output end of the sixth OR gate OR6 and the second input end of the eighth OR gate OR8 respectively, and the output end is connected to the first input end of the seventh OR gate OR7 and the first input end of the sixth OR gate OR6 respectively; the second input end of the sixth OR gate OR6 is connected to the output end of the twelfth inverter INV12, and the second input end of the seventh OR gate OR7 is connected to the output end of the eighth OR gate OR8; the output end of the seventh OR gate OR7 is connected to the first input end of the eighth OR gate OR8, and the connecting end is used for outputting the disturbance signal RD; the gate electrodes of the thirty-second MOS transistor MM32 and the thirty-third MOS transistor MM33 and the input end of the ninth inverter INV9 are connected, and the connecting end is used for inputting the control signal St; the input end of the tenth inverter INV10 and the first input end of the second AND gate are connected to the clock signal CLK, and the output end of the tenth inverter INV10 is connected to the first input end of the first AND gate; the input end of the eleventh inverter INV11, the second input end of the first AND gate and the second input end of the second AND gate are connected to the clock signal CLK2, wherein the period of the clock signal CLK2 is twice that of the clock signal CLK, and the amplitude and phase are consistent with those of the clock signal CLK; the output end of the eleventh inverter INV11, the gate electrodes of the thirty-fifth MOS transistor MM35, the thirty-eighth MOS transistor MM38 and the thirtieth MOS transistor MM30 are connected; the other end of the first capacitor C1, the other end of the second capacitor C2, the drain electrode of the thirtieth MOS transistor MM30 and the source electrodes of the thirty-third MOS transistor MM33 and the thirty-fourth MOS transistor MM34 are grounded; the drain electrode of the twenty-ninth MOS transistor MM29, the drain electrode of the twenty-eighth MOS transistor MM28 and the source electrode of the thirtieth MOS transistor MM30 are connected.

[0039] In this embodiment, the working principle of the sample-and-hold dynamic comparator is as follows: when the control signal St connected to the sample-and-hold dynamic comparator is at a low level, the 31st MOS transistor MM31 and the 32nd MOS transistor MM32 are turned on, and the 33rd MOS transistor MM33 and the 34th MOS transistor MM34 are turned off; when the clock signal CLK2 and the clock signal CLK are both at a high level, the 35th MOS transistor MM35 and the 38th MOS transistor MM38 are turned on, the 30th MOS transistor MM30 is turned off, and the sources of the 28th MOS transistor MM28 and the 29th MOS transistor MM29 are precharged. The output end of the second AND gate outputs a high-level signal to the control end of the second switch SW2, and the second switch SW2 controls the output voltage V OUT Sampling is performed, and the output end of the first AND gate outputs a low level signal to the control end of the first switch SW1, and the first switch SW1 is turned off; when the clock signal CLK2 is high and the clock signal CLK is low, the output end of the second AND gate outputs a low level signal to the control end of the second switch SW2, and the second switch SW2 is turned off. The output end of the first AND gate outputs a high level signal to the control end of the first switch SW1, and the first switch SW1 outputs a high level signal to the control end of the first switch SW1. OUT Sampling is performed; when the clock signal CLK2 is at a low level and the clock signal CLK is at a high level or a low level, the output of the first AND gate is low to the control end of the first switch SW1, and the first switch SW1 is turned off. The output of the second AND gate is low to the control end of the second switch SW2, and the second switch SW2 is turned off. The twenty-eighth MOS transistor MM28, the twenty-ninth MOS transistor MM29, and the thirtieth MOS transistor MM30 are turned on, the thirty-fifth MOS transistor MM35 and the thirty-eighth MOS transistor MM38 are turned off, and the disturbance signal RD is output.

[0040] Example 5: This example is basically the same as Example 4, except that: Figure 4 As shown, in this embodiment, the transient detector includes three inverters, five buffers, and two capacitors. The power supply terminals of the three inverters are all connected to the power supply voltage VDD. The three inverters are respectively referred to as the thirteenth inverter INV13, the fourteenth inverter INV14, and the fifteenth inverter INV15. The five buffers are respectively referred to as the first buffer BUFF1, the second buffer BUFF2, the third buffer BUFF3, the fourth buffer BUFF4, and the fifth buffer BUFF5. The two capacitors are respectively referred to as the third capacitor C3 and the fourth capacitor C4. The input terminals of the first buffer BUFF1 and the third buffer BUFF3 and one end of the third capacitor C3 and the fourth capacitor C4 are connected, and their connection terminals are connected to the output voltage V OUT The output terminal of the first buffer BUFF1 is connected to the input terminal of the fifteenth inverter INV15; the ground terminal of the fifteenth inverter INV15 is connected to the bias voltage V bias_D The output end of the fifteenth inverter INV15 is connected to the input end of the thirteenth inverter INV13 and the other end of the third capacitor C3; the output end of the thirteenth inverter INV13 is connected to the input end of the second buffer BUFF2; the output end of the second buffer BUFF2 is used to output the undershoot signal Droop, and the output end of the third buffer BUFF3 is connected to the input end of the fourteenth inverter INV14; the ground end of the fourteenth inverter INV14 is connected to the bias voltage V bias_U ; The output end of the fourteenth inverter INV14 is connected to the input end of the fourth buffer BUFF4 and the other end of the fourth capacitor C4; the output end of the fourth buffer BUFF4 is connected to the input end of the fifth buffer BUFF5; the output end of the fifth buffer BUFF5 is used to output the upstroke signal Up, and the ground ends of the thirteenth inverter INV13 and the fourteenth inverter INV14 are both grounded.

[0041] like Figure 5 As shown, in this embodiment, the inverter includes a thirty-ninth MOS transistor MM39 and a fortieth MOS transistor MM40; the thirty-ninth MOS transistor MM39 is a PMOS transistor, the fortieth MOS transistor MM40 is an NMOS transistor, the source of the thirty-ninth MOS transistor MM39 is a power supply terminal of the inverter; the drain of the thirty-ninth MOS transistor MM39 is connected to the source of the fortieth MOS transistor MM40 as the output terminal of the inverter; the gates of the thirty-ninth MOS transistor MM39 and the fortieth MOS transistor MM40 are connected as the input terminal of the inverter; and the drain of the fortieth MOS transistor MM40 is the ground terminal of the inverter.

[0042] In this embodiment, the working principle of the transient detector is: when the output voltage V OUT When the first buffer BUFF1 is unchanged, the first buffer BUFF1 outputs a high level signal to the fifteenth inverter INV15, and the fifteenth inverter INV15 connects the bias voltage V bias_D Output to the thirteenth inverter INV13, the thirteenth inverter INV13 outputs a low level signal to the second buffer BUFF2, at this time the undershoot signal Droop output by the second buffer BUFF2 is a low level signal; the third buffer BUFF3 outputs a high level signal to the fourteenth inverter INV14, the fourteenth inverter INV14 connects it to the bias voltage V bias_U Output to the fourth buffer BUFF4, the fourth buffer BUFF4 outputs a low level signal to the fifth buffer BUFF5, the up-shoot signal Up output by the fifth buffer BUFF5 is a low level signal; when the output voltage V OUT When undershoot occurs, in the first stage, the third capacitor C3 couples the output voltage V OUT To the input end of the thirteenth inverter INV13, the thirteenth inverter INV13 outputs a high level signal to the second buffer BUFF2, and the second buffer BUFF2 outputs the undershoot signal Droop as a high level signal. In the second stage, the fifteenth inverter INV15 connects the bias voltage V bias_D The output is sent to the thirteenth inverter INV13, the thirteenth inverter INV13 outputs a low-level signal to the second buffer BUFF2, and the second buffer BUFF2 outputs the undershoot signal Droop as a low-level signal. Combining the two stages, the undershoot signal Droop appears as a pulse signal; the third buffer BUFF3 outputs a high-level signal to the fourth buffer BUFF4, and the fourth buffer BUFF4 connects the bias voltage V bias_U Output to the fourteenth inverter INV14, the fourteenth inverter INV14 outputs a low level signal to the fifth buffer BUFF5, the fifth buffer BUFF5 outputs an undershoot signal Up as a low level; when the output voltage V OUT When an overshoot occurs, in the first stage, the fourth capacitor C4 couples the output voltage V OUT To the input end of the fourth buffer BUFF4, the fourth buffer BUFF4 outputs a high level signal to the fifth buffer BUFF5, and the fifth buffer BUFF5 outputs an undershoot signal Up as a high level signal. In the second stage, the fourteenth inverter INV14 connects the bias voltage V bias_U Output to the fourth buffer BUFF4, the fourteenth inverter INV14 outputs a low-level signal to the fourth buffer BUFF4, the fourth buffer BUFF4 outputs an up-shoot signal Up as a low-level signal. Combining the two stages, the up-shoot signal Up is a pulse signal; the first buffer BUFF1 outputs a high-level signal to the fifteenth inverter INV15, and the fifteenth inverter INV15 connects it to the bias voltage V bias_D The output is sent to the thirteenth inverter INV13, the thirteenth inverter INV13 outputs a low level signal to the second buffer BUFF2, and the second buffer BUFF2 outputs the overshoot signal Droop as a low level; thus, when the improved successive approximation logic control module is in the freeze mode, the output voltage V is monitored by the transient detector. OUT Whether there is fluctuation is fed back to the improved successive approximation logic control module, so that the improved successive approximation logic control module can be based on the output voltage V OUT Adaptively adjust the output voltage V according to the fluctuation situation OUT , to ensure the output voltage V OUT stability.

[0043] In order to verify the performance of the digital low-dropout linear regulator based on improved successive approximation logic of the present invention, the digital low-dropout linear regulator based on improved successive approximation logic of the present invention is used to power a load and perform experimental tests.

[0044] First, when the power supply voltage VDD is 0.9V and the reference voltage V REF is 0.85V, the period of the clock signal CLK is 10ns, the period of the clock signal CLK2 is 20ns, and V REF<5> is 0.87V, V REF<4> is 0.86V, V REF<3> is 0.855V, V REF<2> is 0.845V, V REF<1> is 0.84V, V REF<0> The test is carried out under the condition of 0.83V, and the load current I LOAD Change diagram, at the same time, the load current I LOAD The current changes from 30mA to 0.2mA within 1ns, and from 0.2mA to 30mA within 1ns, i.e., a current change of 29.8mA. Step , and get the output voltage V OUT The transient response diagram of Figure 7 shown.

[0045] analyze Figure 7 It can be seen that: when the load current I LOAD When the output voltage drops from 30mA to 0.2mA within 1ns edge time, the output voltage V OUT The overshoot is less than 50mV and returns to the reference voltage V quickly within 400ns. REF Nearby, at load current I LOAD When the current increases from 0.2mA to 30mA within 1ns, the output voltage V OUT The undershoot is 79mV and returns to the reference voltage V quickly within 100ns. REF It can be seen from this that the digital low-dropout linear regulator based on the improved successive approximation logic of the present invention has a fast transient response speed, high stability, and high output accuracy.

[0046] Then, when the power supply voltage VDD is 0.9V and the reference voltage V REF is 0.85V, the clock signal CLK period is 10ns, the clock signal CLK period is 20ns, V REF<5> is 0.87V, V REF<4> is 0.86V, V REF<3> is 0.855V, V REF<2> is 0.845V, V REF<1> is 0.84V, V REF<0> The test is carried out under the condition of 0.83V, the load current I LOAD1 When the load current is 2mA, I LOAD2 When a small disturbance of 200uA occurs, the output voltage V OUT The transient response diagram of Figure 8 shown.

[0047] analyze Figure 8 It can be seen that in the freeze mode, when the load current undergoes a small disturbance change, the output voltage V OUT Can return to the reference voltage V within a certain period of time REF Nearby, showing good robustness.

[0048] From the above test results, it can be seen that the digital low-dropout linear regulator based on improved successive approximation logic of the present invention has a fast transient response speed, and the output voltage V OUT During the adjustment process, no significant overshoot or undershoot occurs, and no ripple caused by the MOS tube switch is observed, with high accuracy; it can detect small disturbances in the load and restore it to the reference voltage V REF Nearby, showing good robustness.

[0049] In summary, the digital low-dropout linear regulator based on improved successive approximation logic of the present invention has high output voltage accuracy and can be used for high-precision on-chip power supplies. In addition, the transient response speed is not limited by the scale of the MOS tube array. The transient response speed is fast under any MOS tube array scale, and significant overshoot and undershoot phenomena will not be caused. The output voltage is highly stable and has broad application prospects.

Claims

1. A digital low-dropout linear regulator based on improved successive approximation logic, comprising a comparator and a MOS tube array, wherein the comparator is used to compare the output voltage V OUT With the preset reference voltage V REF Comparison shows the output voltage V OUT With reference voltage V REF The comparison signal CMP output of the size relationship is characterized by The digital low-dropout linear regulator also includes an improved successive approximation logic control module, a sample-and-hold dynamic comparator, an analog-to-digital converter, and a transient detector. The analog-to-digital converter is internally provided with a PMOS transistor array, which has a comparison state and a PMOS transistor array state. When it is in the comparison state, it is used to adjust the output voltage V OUT Compare with the preset reference voltage to get the output voltage V OUT With reference voltage V REF The comparison signal of the magnitude relationship is output to the improved successive approximation logic control module, and the output voltage V OUT The voltage output by the MOS transistor array is used to superimpose the output voltage with the voltage output by the MOS transistor array when it is in the PMOS transistor array state. At this time, the output voltage V OUT is the sum of the voltage output by the analog-to-digital converter and the voltage output by the MOS transistor array; the improved successive approximation logic control module is used to control the state switching of the analog-to-digital converter, the operation of the sample-and-hold dynamic comparator, and the internal on-off state of the MOS transistor array, and the improved successive approximation logic control module has an estimated binary search mode, a reverse binary search mode, a bidirectional search mode, and a freeze mode; When the improved successive approximation logic control module is in the estimated binary search mode, determining whether to switch from the estimated binary search mode to the reverse binary search mode according to the comparison signal output by the analog-to-digital converter; if not, determining the initial search bit number of the binary search strategy according to the comparison signal output by the analog-to-digital converter, and then adopting the binary search strategy to iterate according to the comparison signal CMP output by the comparator to control the internal on-off state of the MOS transistor array; When the improved successive approximation logic control module is in the reverse binary search mode, the internal on-off state of the MOS transistor array is controlled by a binary search strategy in a low-to-high order search according to the comparison signal output by the analog-to-digital converter; when the improved successive approximation logic control module is in the bidirectional search mode, the internal on-off state of the MOS transistor array and the on-off state of the PMOS transistor array inside the analog-to-digital converter are controlled by a bidirectional search strategy according to the comparison signal output by the analog-to-digital converter; when the improved successive approximation logic control module enters the freeze mode, the current state of the MOS transistor array and the analog-to-digital converter is kept unchanged, and the sample-and-hold dynamic comparator is controlled to start working; when the improved successive approximation logic control module is in the non-freeze mode, the sample-and-hold dynamic comparator is controlled not to work; the transient detector is used to detect the output voltage V OUT Detecting transient changes and sending the detection results to the improved successive approximation logic control module to control the improved successive approximation logic control module to enter an estimated binary search mode or maintain its current mode unchanged; The sample-hold dynamic comparator is used to detect the output voltage V OUT Whether a change occurs, and output the detection result to the improved successive approximation logic control module, controlling the improved successive approximation logic control module to maintain a freeze mode or enter a bidirectional search mode.

2. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 1, characterized in that The detection result output by the transient detector includes an output voltage V OUT The undershoot signal Droop indicates whether the undershoot occurs and the output voltage V OUT The improved successive approximation logic control module enters the estimated binary search mode when either the downstroke signal Droop or the upstroke signal Up is a pulse signal; the improved successive approximation logic control module maintains its current mode when both the downstroke signal Droop and the upstroke signal Up are low-level signals; the MOS transistor array includes a small-size PMOS transistor array and a large-size PMOS transistor array; the small-size PMOS transistor array consists of 2 8 PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 100n / 30n; the large-size PMOS tube array consists of 2 8 PMOS tubes, and the 2 8 The width-to-length ratio of each PMOS tube is 800n / 30n; the 2 8 PMOS tubes and 2 of the large-size PMOS tube array 8 The sources of the PMOS tubes are connected to the power supply voltage VDD, the gates are connected to the improved successive approximation logic control module, and the drains are connected together to output voltage; the improved successive approximation logic control module outputs a control signal C<255:0> to control the 2 in the large-size PMOS tube array 8 The output control signal S<255:0> controls the on / off of the PMOS tubes in the small-size PMOS tube array. 8 The control signals C<255:0> and S<255:0> are both 256-bit binary data, and the 256-bit data of the control signal C<255:0> are output to the large-size PMOS tube array in a one-to-one correspondence. 8 The gates of the PMOS tubes are controlled, and the 256-bit data of the control signal S<255:0> are output to the small-size PMOS tube array in a one-to-one correspondence. 8 The gate of a PMOS tube; when the gate of a PMOS tube in the MOS tube array is connected to 1, the PMOS tube is turned off, and when it is connected to 0, the PMOS tube is turned on; the comparison signal output by the analog-to-digital converter is recorded as CMP<5:0>, and the reference voltage connected to the analog-to-digital converter is recorded as V REF<5:0> , V REF<5:0> Including 6 reference voltage V REF<0> To V REF<5> The PMOS transistor array provided inside the analog-to-digital converter is composed of 12 PMOS transistors, and the width-to-length ratio of the 12 PMOS transistors is 100n / 30n; the sources of the 12 PMOS transistors in the PMOS transistor array provided inside the analog-to-digital converter are all connected to the power supply voltage VDD, the gates are respectively connected to the improved successive approximation logic control module, and the drains are connected together to output a voltage that is superimposed on the voltage output by the MOS transistor array to adjust the output voltage V OUT The improved successive approximation logic control module outputs a control signal Code<5:0> to control the on / off switching of the 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter. The control signal Code<5:0> is 6-bit binary data, and each bit of binary data controls the on / off switching of two PMOS transistors. The 6-bit data of the control signal Code<5:0> is output one-to-one to the gates of the 12 PMOS transistors in the PMOS transistor array of the analog-to-digital converter.

3. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 2, characterized in that The detection result output by the sample-hold dynamic comparator is called the disturbance signal RD. The improved successive approximation logic control module outputs a control signal St to control whether the sample-hold dynamic comparator works. When the control signal St is at a low level, the sample-hold dynamic comparator starts working and the output represents the output voltage V OUT A disturbance signal RD indicating whether a change has occurred is sent to the improved successive approximation logic control module. When the control signal St is at a high level, the sample-and-hold dynamic comparator does not work. The improved successive approximation logic control module outputs a control signal Ct to control the state of the analog-to-digital converter. When the improved successive approximation logic control module is in an estimated binary search mode, the output control signal Ct is at a low level, at which time the analog-to-digital converter is controlled to enter a comparison state. When the improved successive approximation logic control module is in a reverse binary search mode, a bidirectional search mode, or a freeze mode, the output control signal Ct is at a high level, at which time the analog-to-digital converter is controlled to enter a PMOS transistor array state.

4. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 3, characterized in that When the improved successive approximation logic control module is in the estimated binary search mode, the current control signal S<255:0> and the current control signal Code<5:0> are kept unchanged. At the same time, if CMP<5:0> is 6'b000111, the improved successive approximation logic control module switches from the estimated binary search mode to the reverse binary search mode. If CMP<5:0> is 6'b111111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 7th bit, performs code-raising iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thereby achieves the output voltage V OUT If CMP<5:0> is 6'b000000 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 6th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT If CMP<5:0> is 6'b011111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT If CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 5th bit, performs down-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, and changes the on-off state of the large-size PMOS array, thereby achieving the output voltage V OUT If CMP<5:0> is 6'b001111 and the comparison signal CMP is 1, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs up-scaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, changes the on-off state of the large-size PMOS array, and thus achieves the output voltage V OUT If CMP<5:0> is 6'b000011 and the comparison signal CMP is 0, the improved successive approximation logic control module adopts a binary search strategy, sets its initial search bit number to the 4th bit, performs downscaling iteration according to the current value of the comparison signal CMP, updates the control signal C<255:0>, and changes the on-off state of the large-size PMOS array, thereby achieving the output voltage V OUT Adjustment; When the improved successive approximation logic control module is in the reverse binary search mode, the current control signal C<255:0> and the current control signal Code<5:0> are kept unchanged, and a binary search strategy from low to high is adopted. The control signal S<255:0> is updated according to the current value of the comparison signal CMP, and the on-off state of the small-size PMOS array is changed, thereby achieving the output voltage V OUT Adjustment; When the improved successive approximation logic control module is in the bidirectional search mode, the current control signal C<255:0> is kept unchanged. If the disturbance signal RD is high, the current control signal Code<5:0> is kept unchanged, and the bidirectional search strategy is used to update the control signal S<255:0> to change the on-off state of the small-size PMOS array, thereby achieving the output voltage V OUT If the disturbance signal RD is low, the current control signal S<255:0> is kept unchanged, and the control signal Code<5:0> is updated using a bidirectional search strategy to change the on-off state of the PMOS array of the analog-to-digital converter to achieve the output voltage V OUT adjustments.

5. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 4, characterized in that The device also includes a bias voltage generating circuit, wherein the bias voltage generating circuit is used to generate two bias voltages V bias_D and V bias_U , where V bias_D Output to the analog-to-digital converter V bias_D and V bias_U output to the transient detector.

6. The digital low dropout linear regulator based on improved successive approximation logic according to claim 5, characterized in that The analog-to-digital converter has four input terminals, one output terminal and one input-output terminal. The four input terminals are respectively referred to as the first input terminal, the second input terminal, the third input terminal and the fourth input terminal. The first input terminal of the analog-to-digital converter is used to connect to the reference voltage V REF<5:0> The second input terminal is used to access the bias voltage V bias_D The third input terminal is used to access the control signal Ct, the fourth input terminal is used to access the control signal Code<5:0>, and the input and output terminals are used to access the output voltage V when the analog-to-digital converter is in the comparison state. OUT Or when the analog-to-digital converter is in a PMOS transistor array state, the output voltage is superimposed on the voltage output by the MOS transistor array, and the output end is used to output a comparison signal CMP<5:0>; the analog-to-digital converter includes six analog-to-digital conversion units, each of which has four input ends, one output end, and one input-output end. The four input ends are respectively referred to as the first input end, the second input end, the third input end, and the fourth input end. The first input ends of the six analog-to-digital conversion units constitute the first input end of the analog-to-digital converter; the second input ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the second input end of the analog-to-digital converter; the third input ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the third input end of the analog-to-digital converter; the fourth input ends of the six analog-to-digital conversion units constitute the fourth input end of the analog-to-digital converter; the input and output ends of the six analog-to-digital conversion units are connected, and the connection end thereof serves as the input and output end of the analog-to-digital converter; and the output ends of the six analog-to-digital conversion units constitute the output end of the analog-to-digital converter.

7. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 6, characterized in that Each analog-to-digital conversion unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a twenty-third MOS transistor, a twenty-fourth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, seven inverters and four two-input NOR gates, wherein the first MOS transistor, the The second MOS tube, the third MOS tube, the fourth MOS tube, the sixth MOS tube, the eighth MOS tube, the tenth MOS tube, the twelfth MOS tube, the fourteenth MOS tube, the sixteenth MOS tube, the eighteenth MOS tube, the twentieth MOS tube, the twenty-fifth MOS tube and the twenty-seventh MOS tube are all PMOS tubes, and the fifth MOS tube, the seventh MOS tube, the ninth MOS tube, the eleventh MOS tube, the thirteenth MOS tube, the fifteenth MOS tube, the seventeenth MOS tube, the nineteenth MOS tube, the twenty-first MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube The OS transistor and the twenty-sixth MOS transistor are both NMOS transistors. Each inverter has an input terminal, an output terminal, a power terminal, and a ground terminal. The power terminals of the seven inverters are all connected to the power supply voltage VDD, and the ground terminals are all grounded. The six inverters are respectively referred to as the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, and the seventh inverter. Each two-input NOR gate has a first input terminal, a second input terminal, and an output terminal. The four two-input NOR gates are respectively referred to as the first NOR gate, the second NOR gate, the third NOR gate, and the fourth NOR gate. The source electrodes of the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the twenty-sixth MOS transistor, and the twenty-seventh MOS transistor are connected to the power supply voltage VDD. are all connected to the power supply voltage VDD; the gates of the second MOS transistor and the fourth MOS transistor are connected to the drains of the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, and the eighth MOS transistor; the gate of the third MOS transistor is connected to the drains of the first MOS transistor, the second MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor, and the source of the twenty-second MOS transistor; the gate of the first MOS transistor is connected to the drains of the third MOS transistor, the fourth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor, and the source of the twenty-first MOS transistor;The gates of the twenty-fifth and twenty-sixth MOS transistors are connected to the input end of the seventh inverter, and their connection ends serve as the fourth input end of the analog-to-digital conversion unit. The output end of the seventh inverter is connected to the gates of the twenty-fourth and twenty-seventh MOS transistors. The sources of the fifteenth and sixteenth MOS transistors are grounded. The sources of the twenty-fourth and twenty-fifth MOS transistors are connected, and their connection ends serve as the second input end of the analog-to-digital conversion unit. The drains of the twenty-fourth, twenty-fifth, twenty-sixth, and twenty-seventh MOS transistors are connected to the sources of the seventh and eighth MOS transistors. The gates of the fifth and eighth MOS transistors are connected to the output end of the first inverter. The sources of the ninth and tenth MOS transistors are connected to the input end of the fifth inverter. The gates of the ninth and twelfth MOS transistors are connected to the output end of the second inverter. The sources of the seventeenth and eighteenth MOS transistors are connected to the input end of the sixth inverter; the gates of the seventeenth and twentieth MOS transistors are connected to the output end of the third inverter; the gate of the twenty-first MOS transistor is the first input end of the analog-to-digital conversion unit; the drains of the twenty-first and twenty-second MOS transistors are connected to the source of the twenty-third MOS transistor; the gate of the twenty-third MOS transistor is connected to the drains of the thirteenth, fourteenth, fifteenth, and sixteenth MOS transistors; the drain of the twenty-third MOS transistor is grounded; the gates of the sixth, seventh, tenth, eleventh, fourteenth, fifteenth, eighteenth, and nineteenth MOS transistors are connected to the input ends of the first, second, third, and fourth inverters, and their connection ends are the third input end of the analog-to-digital conversion unit; the eleventh MOS transistor is connected to the input end of the first, second, third, and fourth inverters. The sources of the S transistor, the twelfth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor, and the gate of the twenty-second MOS transistor are connected, and their connection ends are the input and output ends of the analog-to-digital conversion unit; the sources of the fifth MOS transistor, the sixth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are all connected to the clock signal CLK; the gates of the thirteenth MOS transistor and the sixteenth MOS transistor are connected to the output end of the fourth inverter; the first input end of the first NOR gate is connected to the output end of the sixth inverter, the second input end is respectively connected to the output end of the second NOR gate and the second input end of the fourth NOR gate, the output end is respectively connected to the first input end of the second NOR gate and the first input end of the third NOR gate, the second input end of the second NOR gate is connected to the output end of the fifth inverter, the second input end of the third NOR gate is connected to the output end of the fourth NOR gate, the output end of the third NOR gate is connected to the first input end of the fourth NOR gate, and their connection ends are the output end of the analog-to-digital conversion unit.

8. The digital low-dropout linear regulator based on improved successive approximation logic according to claim 2, characterized in that The sample-and-hold dynamic comparator includes a twenty-eighth MOS transistor, a twenty-ninth MOS transistor, a thirtieth MOS transistor, a thirty-first MOS transistor, a thirty-second MOS transistor, a thirty-third MOS transistor, a thirty-fourth MOS transistor, a thirty-fifth MOS transistor, a thirty-sixth MOS transistor, a thirty-seventh MOS transistor, a thirty-eighth MOS transistor, two capacitors, five inverters, two two-input AND gates, four two-input NOR gates, and two electronic switches. The twenty-eighth MOS transistor, the twenty-ninth MOS transistor, the thirtieth MOS transistor, the thirty-first MOS transistor, and the thirty-third MOS transistor are all NMOS transistors, and the thirty-second MOS transistor, the thirty-fourth MOS transistor, the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, and the thirty-eighth MOS transistor are all PMOS transistors. The input terminals of the five inverters are all connected to the power supply voltage VDD, and the ground terminals are all grounded. The five inverters are respectively referred to as an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, and a twelfth inverter. Each two-input AND gate has a an input terminal, a second input terminal, and an output terminal; the two two-input AND gates are referred to as a first AND gate and a second AND gate, respectively; the four two-input NOR gates are referred to as a fifth NOR gate, a sixth NOR gate, a seventh NOR gate, and an eighth NOR gate, respectively; each electronic switch has two connection terminals and a control terminal, the control terminal being used to receive a control signal that controls the two connection terminals to be turned on or off; the two electronic switches are referred to as a first switch and a second switch, respectively; the two capacitors are referred to as a first capacitor and a second capacitor, respectively; the control terminal of the first switch is connected to the output terminal of the first AND gate; the first connection terminal of the first switch is connected to one terminal of the first capacitor and the gate of the twenty-ninth MOS transistor; the control terminal of the second switch is connected to the drain of the thirty-first MOS transistor, the thirty-second MOS transistor, the thirty-third MOS transistor, and the thirty-fourth MOS transistor; the first connection terminal of the second switch is connected to one terminal of the second capacitor and the gate of the twenty-eighth MOS transistor; the second connection terminals of the first switch and the second switch are connected, and their connection terminals are used to receive an output voltage V OUT The sources of the thirty-fifth MOS transistor, the thirty-sixth MOS transistor, the thirty-seventh MOS transistor, and the thirty-eighth MOS transistor are all connected to the power supply voltage VDD; the input end of the twelfth inverter is connected to the drains of the thirty-seventh MOS transistor and the thirty-eighth MOS transistor, the gate of the thirty-sixth MOS transistor, and the source of the twenty-ninth MOS transistor; the input end of the eighth inverter is connected to the drains of the thirty-fifth MOS transistor and the thirty-sixth MOS transistor, the gate of the thirty-seventh MOS transistor, and the source of the twenty-eighth MOS transistor; the thirty-first MOS transistor, the thirty-third MOS transistor, and the thirty-sixth MOS transistor are connected to the drains of the thirty-seventh MOS transistor and the thirty-sixth MOS transistor, the gate of the thirty-seventh MOS transistor, and the source of the twenty-eighth MOS transistor; The source of the twelfth MOS transistor is connected to the output end of the second AND gate; the output end of the ninth inverter is connected to the gates of the thirty-first MOS transistor and the thirty-fourth MOS transistor; the first input end of the fifth NOR gate is connected to the output end of the eighth inverter, the second input end is respectively connected to the output end of the sixth NOR gate and the second input end of the eighth NOR gate, and the output end is respectively connected to the first input end of the seventh NOR gate and the first input end of the sixth NOR gate; the second input end of the sixth NOR gate is connected to the output end of the twelfth inverter, the second input end of the seventh NOR gate is connected to the output end of the eighth inverter, and the second input end of the seventh NOR gate is connected to the output end of the eighth NOR gate. The output end of the NOR gate is connected to the output end of the NOR gate; the output end of the seventh NOR gate is connected to the first input end of the eighth NOR gate, and its connection end is used to output the disturbance signal RD; the gates of the thirty-second MOS transistor and the thirty-third MOS transistor are connected to the input end of the ninth inverter, and their connection ends are used to receive the control signal St, the input end of the tenth inverter and the first input end of the second AND gate are connected to the clock signal CLK, and the output end of the tenth inverter is connected to the first input end of the first AND gate; the input end of the eleventh inverter, the second input end of the first AND gate, and the second input end of the second AND gate are connected to the input end of the eleventh inverter. A clock signal CLK2 is input to each of the transistors, wherein the period of the clock signal CLK2 is twice that of the clock signal CLK, and the amplitude and phase are consistent with those of the clock signal CLK. The output end of the eleventh inverter, the gates of the thirty-fifth MOS transistor, the thirty-eighth MOS transistor, and the thirtieth MOS transistor are connected. The other end of the first capacitor, the other end of the second capacitor, the drain of the thirtieth MOS transistor, the thirty-third MOS transistor, and the source of the thirty-fourth MOS transistor are all grounded. The drain of the twenty-ninth MOS transistor, the drain of the twenty-eighth MOS transistor, and the source of the thirtieth MOS transistor are connected.

9. The digital low dropout linear regulator based on improved successive approximation logic according to claim 2, characterized in that The transient detector includes three inverters, five buffers, and two capacitors. The power supply terminals of the three inverters are all connected to the power supply voltage VDD. The three inverters are respectively referred to as the thirteenth inverter, the fourteenth inverter, and the fifteenth inverter. The five buffers are respectively referred to as the first buffer, the second buffer, the third buffer, the fourth buffer, and the fifth buffer. The two capacitors are respectively referred to as the third capacitor and the fourth capacitor. The input terminals of the first buffer and the third buffer, and one end of the third capacitor and the fourth capacitor are connected, and their connection terminals are connected to the output voltage V OUT The output terminal of the first buffer is connected to the input terminal of the fifteenth inverter; the ground terminal of the fifteenth inverter is connected to the bias voltage V bias_D The output end of the fifteenth inverter is connected to the input end of the thirteenth inverter and the other end of the third capacitor; the output end of the thirteenth inverter is connected to the input end of the second buffer; the output end of the second buffer is used to output the undershoot signal Droop, and the output end of the third buffer is connected to the input end of the fourteenth inverter; the ground end of the fourteenth inverter is connected to the bias voltage V bias_U ; The output end of the fourteenth inverter is connected to the input end of the fourth buffer and the other end of the fourth capacitor; the output end of the fourth buffer is connected to the input end of the fifth buffer; the output end of the fifth buffer is used to output an upstroke signal Up, and the ground ends of the thirteenth inverter and the fourteenth inverter are both grounded.

10. The digital low dropout linear regulator based on improved successive approximation logic according to claim 9, characterized in that The inverter includes a 39th MOS tube and a 40th MOS tube; the 39th MOS tube is a PMOS tube, the 40th MOS tube is an NMOS tube, and the source of the 39th MOS tube is the power supply terminal of the inverter; The drain of the thirty-ninth MOS transistor is connected to the source of the fortieth MOS transistor as the output end of the inverter; the gates of the thirty-ninth MOS transistor and the fortieth MOS transistor are connected as the input end of the inverter; The drain of the fortieth MOS transistor serves as the ground terminal of the inverter.

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