Display panel and display apparatus

Abstract

Disclosed is a display panel. The display panel comprises a base substrate and a driving circuit layer. The driving circuit layer further comprises a plurality of pixel driving circuits, a plurality of data writing signal lines and a plurality of data leads. Each data lead comprises a first lead section located on a first wiring metal layer and a second lead section located on a second wiring metal layer, wherein one end of the first lead section is electrically connected to a data writing signal line located in an edge region, and the other end of the first lead section is electrically connected to one end of the second lead section; and the second lead segment extends from an intermediate region to a binding region. A semiconductor layer comprises a first conductive portion, wherein the first conductive portion comprises a second electrode of a first reset transistor. A second gate metal layer comprises a first shielding portion, wherein the first shielding portion is configured to have a constant-voltage signal. The orthographic projection of the first shielding portion on the base substrate, the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first lead segment on the base substrate overlap.

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410007705.X ​​filed on January 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) display devices have become one of the most competitive and promising display devices due to their advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display. Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel includes a display area and a binding area, the binding area being located on one side of the display area. The display area includes a central area and two edge areas, the central area being located between the two edge areas along a first direction. The display panel includes a base substrate and a drive circuit layer, the drive circuit layer being located on one side of the base substrate. The drive circuit layer includes a plurality of pixel drive circuits, a plurality of data write signal lines, and a plurality of data leads. The plurality of pixel drive circuits are arranged in multiple rows and columns within the display area. The pixel drive circuit includes a drive transistor and a first reset transistor. The control electrode of the drive transistor is electrically connected to a first node, the first electrode of the drive transistor is electrically connected to a second node, and the second electrode of the drive transistor is electrically connected to a third node. A first reset transistor is provided, wherein the control electrode of the first reset transistor is electrically connected to a first reset signal line, the first electrode of the first reset transistor is electrically connected to a first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the first node. Multiple data write signal lines are located in the display area, and the plurality of data write signal lines are arranged along the first direction and extend along a second direction, which intersects the first direction. A data write signal line connects a column of the pixel drive circuits. Multiple data leads are provided, each of which includes a first lead segment and a second lead segment. One end of the first lead segment is electrically connected to a data write signal line located in the edge region, and the other end of the first lead segment is electrically connected to one end of the second lead segment. The first lead segment extends along a first direction, and the second lead segment extends along a second direction, extending from the middle region to the binding region. In a direction away from the substrate, the drive circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer. The semiconductor layer includes a first conductive portion, the first conductive portion including the second electrode of the first reset transistor. The second gate metal layer includes a first shielding portion configured to provide a constant voltage signal. The first routing metal layer includes the first lead segment. The second routing metal layer includes the data write signal line and the second lead segment. The orthographic projection of the first shielding portion on the base substrate, the orthographic projection of the first conductive portion on the base substrate, and the orthographic projection of the first lead segment on the base substrate overlap.

[0005] In some embodiments, the second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

[0006] In some embodiments, the first initialization signal line includes a first auxiliary portion protruding toward the first reset transistor, wherein an orthographic projection of the first auxiliary portion on the base substrate overlaps an orthographic projection of the first conductive portion on the base substrate, and an orthographic projection of the first lead segment on the base substrate. The first auxiliary portion is multiplexed as the first shielding portion.

[0007] In some embodiments, the pixel driving circuit further includes a compensation transistor, wherein the control electrode of the compensation transistor is electrically connected to the second scanning signal line, the first electrode of the compensation transistor is electrically connected to the third node, and the second electrode of the compensation transistor is electrically connected to the first node. The compensation transistor is a dual-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode. The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion, one end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion. The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor, the orthographic projection of the second auxiliary portion on the base substrate at least partially overlapping with the orthographic projection of the second conductive portion on the base substrate.

[0008] In some embodiments, an orthographic projection of the second conductive portion on the base substrate is located within a boundary of an orthographic projection of the second auxiliary portion on the base substrate.

[0009] In some embodiments, the second conductive portion includes a first sub-portion, a second sub-portion, and a third sub-portion, wherein the first sub-portion, the second sub-portion, and the third sub-portion intersect at the same point. The first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion facing away from the second channel portion.

[0010] In some embodiments, the pixel driving circuit further includes a data write transistor and a second reset transistor. A control electrode of the data write transistor is connected to the first scan signal line, a first electrode of the data write transistor is electrically connected to the data write signal line, and a second electrode of the data write transistor is electrically connected to the second node. A control electrode of the second reset transistor is electrically connected to the first scan signal line, a first electrode of the second reset transistor is electrically connected to the second initialization signal line, and a second electrode of the second reset transistor is electrically connected to the fourth node. Along the first direction, the control electrodes of the data write transistor and the second reset transistor overlap.

[0011] In some embodiments, the pixel driving circuit further includes a first emission control transistor and a second emission control transistor. The control electrode of the first emission control transistor is electrically connected to the first enable signal line, the first electrode of the first emission control transistor is electrically connected to the first power signal line, and the second electrode of the first emission control transistor is electrically connected to the second node. The control electrode of the second emission control transistor is electrically connected to the second enable signal line, the first electrode of the second emission control transistor is electrically connected to the third node, and the second electrode of the second emission control transistor is electrically connected to the fourth node.

[0012] In some embodiments, the pixel driving circuit further includes a storage capacitor and a first capacitor. A first plate of the storage capacitor is electrically connected to the first node, and a second plate of the storage capacitor is electrically connected to a first power signal line. A first plate of the first capacitor is electrically connected to the second node, and a first plate of the first capacitor is electrically connected to the first power signal line.

[0013] In some embodiments, the pixel driving circuit includes a data writing transistor and a first light emission control transistor. The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first electrode of the driving transistor, a second electrode of the first light emission control transistor, and a second electrode of the data writing transistor. The second gate metal layer also includes a fourth conductive portion, one end of the fourth conductive portion is electrically connected to the second electrode plate of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to the first electrode of the first light emission control transistor. The orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate. The third conductive portion is multiplexed as the first electrode plate of the first capacitor, and the fourth conductive portion is multiplexed as the second electrode plate of the first capacitor.

[0014] In some embodiments, along the second direction, the third conductive portion is away from a side of the channel portion of the first light emission control transistor and protrudes from the channel portion of the driving transistor.

[0015] In some embodiments, along the first direction, two adjacent pixel driving circuits are symmetrical.

[0016] In some embodiments, along the first direction, the first electrode of the driving transistor in the nth pixel driving circuit is adjacent to the first electrode of the driving transistor in the (n+1)th pixel driving circuit, where n is a positive integer.

[0017] In some embodiments, the second plate of the storage capacitor in the nth pixel driving circuit is electrically connected to the second plate of the storage capacitor in the pixel driving circuit of the n+1th sub-pixel, where n is a positive integer.

[0018] In some embodiments, along the first direction, the second reset transistor in the n+1th pixel driving circuit is arranged adjacent to the second reset transistor in the n+2th pixel driving circuit, and the first electrode of the second reset transistor in the n+1th pixel driving circuit is reused as the first electrode of the second reset transistor in the n+2th pixel driving circuit.

[0019] In some embodiments, the first routing metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments corresponding one-to-one with the first lead segments, and the first lead segments and the first virtual lead segments are spaced apart along the first direction.

[0020] In some embodiments, the second routing metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one-to-one, and along the first direction, the second lead segments and the second virtual lead segments are spaced apart.

[0021] In some embodiments, the display panel further includes a bottom shielding layer located between the base substrate and the pixel driving circuit, wherein an orthographic projection of the bottom shielding layer on the base substrate covers an orthographic projection of the driving transistor on the base substrate.

[0022] In some embodiments, the display panel further comprises a light emitting device layer, the light emitting device layer being located on a side of the driving circuit layer away from the base substrate, the light emitting device layer comprising a plurality of light emitting devices, and the light emitting devices being electrically connected to the pixel driving circuit.

[0023] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is a structural diagram of a display panel according to some embodiments;

[0027] FIG3 is a cross-sectional view of a display panel according to some embodiments;

[0028] FIG4 is a circuit diagram of a pixel driving circuit according to some embodiments;

[0029] FIG5 is a circuit diagram of a pixel driving circuit according to some other embodiments;

[0030] FIG6 is a timing diagram of a pixel driving circuit according to some embodiments;

[0031] FIG7 is a circuit diagram of a pixel driving circuit according to yet other embodiments;

[0032] FIG8 is a film layer structure diagram of multiple pixel driving circuits according to some embodiments;

[0033] FIG9 is a film layer structure diagram of multiple pixel driving circuits according to some other embodiments;

[0034] FIG10 is a structural diagram of the semiconductor layer in FIG9;

[0035] FIG11 is a structural diagram of a semiconductor layer according to some embodiments;

[0036] FIG12 is a structural diagram of the first gate metal layer in FIG9 ;

[0037] FIG13 is a structural diagram of the second gate metal layer in FIG9 ;

[0038] FIG14 is a structural diagram of the semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG9 ;

[0039] FIG15 is a structural diagram of the first routing metal layer in FIG9 ;

[0040] FIG16 is a structural diagram of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the first routing metal layer in FIG9 ;

[0041] FIG17 is a structural diagram of the second routing metal layer in FIG9 ;

[0042] FIG18 is a film layer structure diagram of multiple pixel driving circuits according to yet other embodiments;

[0043] FIG19 is a structural diagram of the bottom shielding layer in FIG18 . DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0045] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", or "some examples" and the like are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0046] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0047] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood broadly. For example, "connected" can mean fixed, removable, or integrated; it can be directly connected or indirectly connected through an intermediary. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0048] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0049] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0050] As used herein, the term "if" is optionally interpreted to mean "when" or "at the time of" depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining that" depending on the context.

[0051] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0055] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] In the circuit provided in the embodiments of the present disclosure, the first node, the second node, the third node and the fourth node do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0058] FIG1 is a structural diagram of a display device according to some embodiments. Referring to FIG1 , some embodiments of the present disclosure provide a display device 200 , which includes a display panel 100 .

[0059] Exemplarily, the display device 200 further includes a frame and other electronic accessories.

[0060] Exemplarily, the display device 200 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0061] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0062] FIG. 2 is a structural diagram of a display panel according to some embodiments.

[0063] As shown in FIG2 , some embodiments of the present disclosure provide a display panel 100 , which includes a display area (full name in English: Active Area, AA area for short; also called effective display area) AA.

[0064] The display panel 100 may include a plurality of sub-pixels P, and the plurality of sub-pixels P are disposed in the display area AA, wherein the plurality of sub-pixels may be arranged in an array.

[0065] Sub-pixel P is the smallest unit for displaying images on the display panel 100. Multiple sub-pixels P may include red sub-pixels, blue sub-pixels, and green sub-pixels. By adjusting the brightness (grayscale) of sub-pixels of different colors, multiple colors can be displayed through color combination and superposition, thereby realizing full-color display of the display panel 100.

[0066] In some other examples, the display panel 100 may further include a white sub-pixel.

[0067] In some examples, the display area AA includes a middle area AA1 and two edge areas AA2 , and along the first direction X, the middle area AA1 is located between the two edge areas AA2 .

[0068] Exemplarily, along the first direction X, the widths of the two edge regions AA2 of the display area AA are the same or approximately the same.

[0069] FIG. 3 is a cross-sectional view of a display panel according to some embodiments.

[0070] As shown in FIG. 3 , each sub-pixel P may include a light-emitting device O and a pixel driving circuit Q for driving the light-emitting device O.

[0071] In addition, the display panel 100 may further include a plurality of signal lines. The plurality of signal lines may be electrically connected to the pixel driving circuit Q to provide the pixel driving circuit Q with the signals required by the pixel driving circuit Q. The functions of the plurality of signal lines electrically connected to the pixel driving circuit Q and their layout in the display panel 100 will be described in detail below.

[0072] 2 and 3 , the display panel 100 includes a base substrate 10 , a driving circuit layer 20 , and a light emitting device layer 30 , wherein the driving circuit layer 20 is located between the base substrate 10 and the light emitting device layer 30 .

[0073] In some examples, the substrate 10 may be a flexible substrate. For example, the substrate 10 may be made of an organic material. For example, the substrate 10 may be made of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0074] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0075] In some examples, the light emitting device layer 30 includes a plurality of light emitting devices O, and the plurality of light emitting devices O are electrically connected to a plurality of pixel driving circuits Q.

[0076] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be electrically connected in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be electrically connected to multiple light-emitting devices O, or multiple pixel driving circuits Q may be electrically connected to one light-emitting device O.

[0077] Below, the present disclosure takes the electrical connection between one pixel driving circuit Q and one light-emitting device O as an example to schematically illustrate the structure of the display panel 100 .

[0078] In some examples, the light-emitting device O includes an anode layer, a light-emitting layer, and a cathode layer stacked in sequence. In some examples, an electron transport layer is further provided between the cathode layer and the light-emitting layer, and a hole transport layer is further provided between the anode layer and the light-emitting layer. Exemplarily, the light-emitting device O may be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light by discharge), as long as they can emit light so that the display panel 100 can display a picture.

[0079] The driver circuit layer 20 further includes a plurality of pixel driver circuits Q. The plurality of pixel driver circuits Q are arranged in multiple rows and columns within the display area AA. The pixel driver circuits Q arranged in a row along the first direction X are referred to as a pixel driver circuit row, and the pixel driver circuits Q arranged in a row along the second direction Y are referred to as a pixel driver circuit column.

[0080] The first direction X and the second direction Y intersect.

[0081] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and in this case, the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0082] The pixel driving circuit Q is distributed in the film layer of the driving circuit layer 20 . The specific distribution of the pixel driving circuit Q in the driving circuit layer 20 will be described in detail below.

[0083] For the convenience of explanation, the above-mentioned multiple pixel driving circuits Q are described in the present disclosure by taking a matrix arrangement as an example.

[0084] In some examples, the structure of the pixel driving circuit Q includes multiple options, which can be selected according to actual needs. For example, the structure of the sub-pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C", or "8T1C". Here, "T" represents a thin film transistor, and the number before "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number before "C" represents the number of storage capacitors C. The following description uses the "7T1C" sub-pixel driving circuit as an example.

[0085] FIG. 4 is a circuit diagram of a pixel driving circuit according to some embodiments.

[0086] In some examples, as shown in FIG4 , the pixel driving circuit Q includes: a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second reset transistor T7 , and a storage capacitor Cst.

[0087] A gate g1 of the first reset transistor T1 is electrically connected to the first reset signal line R1, a first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, and a second electrode d1 of the first reset transistor T1 is electrically connected to the first node N1. The first reset transistor T1 is configured to, under control of a first reset signal received from the first reset signal line R1, transmit the first initialization signal received from the first initialization signal line Vinit1 to the first node N1, thereby resetting the first node N1.

[0088] A gate g2 of the compensation transistor T2 is electrically connected to the second scan signal line G2 , a first electrode s2 of the compensation transistor T2 is electrically connected to the first node N1 , and a second electrode d2 of the compensation transistor T2 is electrically connected to the third node N3 .

[0089] A gate g3 of the driving transistor T3 is electrically connected to the first node N1 , a first electrode s3 of the driving transistor T3 is electrically connected to the second node N2 , and a second electrode d3 of the driving transistor T3 is electrically connected to the third node N3 .

[0090] A gate g4 of the data writing transistor T4 is electrically connected to the first scanning signal line G1 , a first electrode s4 of the data writing transistor T4 is electrically connected to the data writing signal line Data, and a second electrode d4 of the data writing transistor T4 is electrically connected to the second node N2 .

[0091] A gate g5 of the first emission control transistor T5 is electrically connected to the first enable signal line EM1 , a first electrode s5 of the first emission control transistor T5 is electrically connected to the first power signal line VDD, and a second electrode d5 of the first emission control transistor T5 is electrically connected to the second node N2 .

[0092] The gate g6 of the second emission control transistor T6 is electrically connected to the first enable signal line EM1, the first electrode s6 of the second emission control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second emission control transistor T6 is electrically connected to the fourth node N4. The fourth node in the pixel driving circuit Q may be an output terminal of the pixel driving circuit. That is, the fourth node N4 of the pixel driving circuit Q may be electrically connected to the light-emitting device O. For example, the fourth node N4 of the pixel driving circuit Q may be electrically connected to the anode of the light-emitting device O. Furthermore, the cathode of the light-emitting device O may be electrically connected to the second power signal line VSS. The voltage of the first power signal provided by the first power signal line VDD is higher than the voltage of the second power signal provided by the second power signal line VSS.

[0093] The first light emitting control transistor T5 and the second light emitting control transistor T6 are configured to cooperate with the driving transistor T3 to transmit a driving signal to the light emitting device O under the control of the first enable signal from the first enable signal line EM1.

[0094] A gate electrode g7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, a first electrode s7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode d7 of the second reset transistor T7 is electrically connected to a fourth node N4. The second reset transistor T7 is configured to, under control of a second reset signal received from the second reset signal line R2, transmit the second initialization signal received from the second initialization signal line V2 to a fourth node N4, thereby resetting the fourth node N4. The fourth node N4 is electrically connected to the light-emitting device O. Resetting the fourth node N4 is equivalent to using this signal to reset the anode of the light-emitting device O, thereby improving the stability of the light-emitting device O.

[0095] A first plate Cst- 1 of the storage capacitor Cst is electrically connected to the first node N1 , and a second plate Cst- 2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0096] In some examples, the compensation transistor T2 may be an N-type transistor, and the first reset transistor T1 , the driving transistor T3 , the data writing transistor T4 , the first emission control transistor T5 , the second emission control transistor T6 , and the second reset transistor T7 may be P-type transistors.

[0097] In some examples, the compensation transistor T2 may be an oxide transistor, which may be an N-type transistor, and the other transistors may be LTPS (Low Temperature Poly Silicon) transistors, which may be P-type transistors.

[0098] Among them, the N-type transistor is turned on when the gate receives a high voltage signal, while the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turning-on condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, and the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turning-on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. The gate voltage signal that turns on the P-type transistor is called a low voltage signal, and the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0099] In some other examples, the plurality of transistors may all be P-type transistors, and in some other examples, the plurality of transistors may all be N-type transistors.

[0100] The pixel driving circuit Q shown in FIG4 is illustrated by taking as an example an arrangement in which the first reset transistor T1 and the compensation transistor T2 are N-type transistors, while the other transistors are P-type transistors. This arrangement can help reduce the risk of leakage in the compensation transistor T2 and the first reset transistor T1, and is more conducive to ensuring the stability of the voltage at the first node N1, that is, ensuring the stability of the control electrode g1 of the driving transistor T3.

[0101] FIG5 is a circuit diagram of a pixel driving circuit according to some other embodiments.

[0102] In some embodiments, as shown in FIG5 , the second scan signal line G2 used to drive the nth row of pixel drive circuits Q responds to the same signal terminal as the first reset signal line R1(n+m) for the n+mth row of pixel drive circuits Q. In other words, the second scan signal line G2 used to drive the nth row of pixel drive circuits Q can be reused as the first reset signal line R1(n+m) for the subsequent m rows of pixel drive circuits Q. Where n and m are both natural numbers, and n>m. FIG5 illustrates this by taking m=7 as an example.

[0103] It can also be understood that the first reset signal line R1 used to drive the n-th row of pixel driving circuits Q responds to the same signal terminal as the second scanning signal line G2(nm) used to drive the nm-th row of pixel driving circuits Q. That is, the first reset transistor T1 of the n-th row of pixel driving circuits Q can be driven by the second scanning signal line G2(nm) used to drive the nm-th row of pixel driving circuits Q. Based on this, the first reset signal line R1 used to drive the n-th row of pixel driving circuits Q will be referred to as the second scanning signal line G2(nm) below, while the second scanning signal line G2 will still be referred to as the second scanning signal line that drives the n-th row of pixel driving circuits Q.

[0104] Therefore, when the second scanning signal line G2 drives the compensation transistor T2 of the pixel driving circuit Q in the nth row to turn on, the first reset transistor T1 of the pixel driving circuit Q in the subsequent mth row may also be turned on to reset the first node N1.

[0105] As set above, the second scanning signal line G2 and the first reset signal line R1 (second scanning signal line G2 (nm)) used to drive the nth row pixel driving circuit Q respond to the same signal terminal, which can reduce the number of signal terminals in the display panel 100 and save space in the display panel 100.

[0106] In some examples, m=7. The first reset signal line R1 for driving the pixel driving circuit Q in the nth row responds to the same signal terminal as the second scanning signal line G2(n-7) for the pixel driving circuit Q in the n-7th row. In other words, the first reset transistor T1 of the pixel driving circuit Q in the nth row can be driven by the second scanning signal line G2(n-7) for driving the pixel driving circuit Q in the n-7th row. In FIG5 , G2(n-7) represents the second scanning signal line G2 electrically connected to the pixel driving circuit Q in the first 7 rows of the pixel driving circuit Q. In the following description, the first reset signal line R1 is represented by the second scanning signal line G2(n-7) for the pixel driving circuit Q in the n-7th row.

[0107] Based on this, when the second scanning signal line G2(n-7) drives the compensation transistor T2 of the pixel driving circuit Q in the n-7th row to turn on, it can also drive the first reset transistor T1 of the pixel driving circuit Q in the nth row to turn on, resetting the first node N1. Furthermore, it can ensure that the control electrode g3 (first node N1) of the driving transistor T3 is initialized before the compensation phase (data writing phase), thereby improving the stability of the driving transistor T3.

[0108] It is understandable that in other examples, m may be other natural numbers. For example, the pixel driving circuit Q in the nth row may be driven by the second scanning signal line G2 that drives the pixel driving circuit Q in the (n-3)th row.

[0109] Based on this, the first reset transistor T1 of the pixel driving circuit Q in the nth row can be driven by the second scanning signal line G2 (n-7) driving the pixel driving circuit Q in the n-7th row.

[0110] In some embodiments, as shown in FIG5 , the first scan signal line G1 can be multiplexed as the second reset signal line R2. When the first scan signal line G1 controls the data write transistor T4 to turn on, it can also control the second reset transistor T7 to turn on, transmitting the second initialization signal received from the second initialization signal line V2 to the fourth node N4, thereby resetting the fourth node N4. This resets the anode of the light-emitting device O, improving the stability of the light-emitting device O.

[0111] In some embodiments, as shown in Figure 5, the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7 and a storage capacitor Cst.

[0112] 5 , the first emission control transistor T5 and the second emission control transistor T6 may not be controlled by the same first enable signal line EM1 . That is, the first emission control transistor T5 and the second emission control transistor T6 may be controlled by two enable signal lines respectively.

[0113] Specifically, the control electrode g5 of the first light emitting control transistor T5 is electrically connected to the first enable signal line EM1 , and the control electrode g6 of the second light emitting control transistor T6 is electrically connected to the second enable signal line EM2 .

[0114] Based on this, two enable signal lines (first enable signal line EM1 and second enable signal line EM2) can be used to control two emission control transistors (first emission control transistor T5 and second emission control transistor T6) respectively. In addition, the first emission control transistor T5 and the second emission control transistor T6 can be controlled to turn on in sequence.

[0115] Thus, before the light-emitting device O receives the driving signal and emits light, the first power signal line pair and the second node N2 are first reset, so that the voltage at the first electrode s3 of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. This can improve the problem of afterimage caused by TFT characteristic drift and enhance the display quality of the display panel 100.

[0116] FIG. 6 is a timing diagram of a pixel driving circuit according to some embodiments.

[0117] 5 and 6 , the driving process of the pixel driving circuit Q is as follows: one frame period includes an initialization phase t1 , a data writing phase t2 and a light emitting phase t3 .

[0118] Initialization stage t1: the first enable signal line transmitted by the first enable signal line is a high voltage signal, the second enable signal line transmitted by the second enable signal line is a high voltage signal, the first scanning signal transmitted by the first scanning signal line G1 is a high voltage signal, the second scanning signal line G2 transmits the second scanning signal as a high voltage signal line, and the first reset signal line R1 (the first 7 rows of pixel driving circuits Q are electrically connected to the second scanning signal line G2) transmits the first reset signal (second scanning signal) as a low voltage signal.

[0119] At this time, the compensation transistor T2, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are in the off state. The first reset transistor T1 is in the on state, transmitting the first initialization signal transmitted by the first initialization signal line Vinit1 to the first node N1, thereby resetting the first node N1. At this time, the voltage at the first node N1 is the voltage V1 of the first initialization signal.

[0120] Data writing phase t2: the first enable signal line transmitted by the first enable signal line is a high voltage signal, the second enable signal line transmitted by the second enable signal line is a high voltage signal, and the first reset signal line R1 (the first 7 rows of pixel driving circuits Q are electrically connected to the second scan signal line G2) transmits a first reset signal (second scan signal) as a high voltage signal. In addition, the first scan signal transmitted by the first scan signal line G1 is a low voltage signal and the second scan signal transmitted by the second scan signal line G2 is a low voltage signal.

[0121] At this point, the first reset transistor T1, the first emission control transistor T5, and the second emission control transistor T6 are in the off state. The data write transistor T4 and the compensation transistor T2 are in the on state. At this point, the data write signal transmitted from the data write signal line Data can be transmitted to the second node N2 via the data write transistor T4. That is, the voltage at the second node N2 is the voltage Vdata of the data write signal. Therefore, Vgs of the drive transistor T3 equals V1 - Vdata, Vgs < Vth, and the drive transistor T3 is in the on state.

[0122] Since the data write transistor T4, the driving transistor T3 and the compensation transistor T2 are all in the open state during this stage, the data write signal line Data transmits the data write signal, which can be transmitted to the first node N1 through the data write transistor T4, the driving transistor T3 and the compensation transistor T2 in sequence, thereby compensating the first node N1. The potential of the first node N1 gradually rises to Vdata+Vth, the driving transistor T3 is turned off, and the storage capacitor Cst completes the charging process.

[0123] Wherein, Vdata is the voltage value of the data write signal provided by the data write signal line Data, and Vth is the threshold voltage of the driving transistor T3 in the pixel driving circuit Q.

[0124] Furthermore, since the first scan signal line G1 can be multiplexed as the second reset signal line R2, during this phase, the second reset transistor T7 can receive a low voltage signal from the first scan signal line G1 and turn on, transmitting the second initialization signal received from the second initialization signal line V2 to the fourth node N4, thereby resetting the fourth node N4. The fourth node N4 is electrically connected to the light-emitting device O. Resetting the fourth node N4 is equivalent to using this signal to reset the anode of the light-emitting device O, thereby improving the stability of the light-emitting device O.

[0125] In the light-emitting phase t3, the first scan signal transmitted by the first scan signal line G1 is a high voltage signal, the second scan signal transmitted by the second scan signal line G2 is a high voltage signal, and the first reset signal transmitted by the first reset signal line R1 (the second scan signal line G2(n-7)) is a high voltage signal. Furthermore, the first enable signal transmitted by the first enable signal line is a low voltage signal, and the second enable signal transmitted by the second enable signal line is a low voltage signal.

[0126] At this time, the first reset transistor T1, the compensation transistor T2, the data writing transistor T4 and the second reset transistor T7 are in the off state. The first emission control transistor T5 and the second emission control transistor T6 are turned on. In addition, the driving transistor T3 is continuously turned on during this stage.

[0127] Based on this, the constant voltage power signal provided by the first power signal line VDD can flow through the first light-emitting control transistor T5, the driving transistor T3, and the second light-emitting control transistor T6 in sequence to the anode of the light-emitting device O, and the cathode of the light-emitting device O can be electrically connected to the second power signal line VSS, thereby driving the light-emitting device O to emit light.

[0128] Furthermore, since the two emission control transistors (the first emission control transistor T5 and the second emission control transistor T6) are controlled by two enable signal lines (the first enable signal line EM1 and the second enable signal line EM2), respectively, the falling edge of the first enable signal transmitted by the first enable signal line EM1 occurs earlier than the falling edge of the second enable signal transmitted by the second enable signal line EM2. Consequently, the first emission control transistor T5 and the second emission control transistor T6 can be controlled to turn on sequentially.

[0129] During light-emitting phase t3, the first light-emitting control transistor T5 can be turned on under the control of a first enable signal from the first enable signal line EM1. The first power signal from the first power signal line VDD can be transmitted to the second node N2 (the first electrode s3 of the driving transistor T3) via the first light-emitting control transistor T5. Furthermore, the first power signal line can be used to reset the second node N2, so that the voltage at the first electrode s3 of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. Thereafter, the first light-emitting control transistor T5 remains turned on. Under the control of a second enable signal from the second enable signal line EM2, the second light-emitting control transistor T6 is turned on and cooperates with the driving transistor T3 to transmit the driving signal to the light-emitting device O.

[0130] Based on this, before the light-emitting device O receives the driving signal and emits light, the first power signal line pair and the second node N2 are first reset, so that the voltage at the first electrode s3 of the driving transistor T3 of the pixel driving circuit Q in a pixel driving circuit row remains consistent for a period of time. In this way, the problem of afterimage caused by TFT characteristic drift can be improved, thereby enhancing the display quality of the display panel 100.

[0131] FIG. 7 is a circuit diagram of a pixel driving circuit according to yet other embodiments.

[0132] In some embodiments, as shown in FIG7 , the pixel driving circuit Q further includes a first capacitor C1 , a first plate C1 - 1 of the first capacitor C1 is electrically connected to the first power signal line VDD, and a second plate C1 - 2 of the first capacitor C1 is electrically connected to the second node N2 .

[0133] The difference between the pixel driving circuit Q shown in FIG7 and the pixel driving circuit Q shown in FIG5 is that in the pixel driving circuit Q shown in FIG7 , a first capacitor is connected in series between the second node N2 and the first power signal line VDD, and other components are the same.

[0134] The driving process of the pixel driving circuit Q in FIG7 will be described below, taking the example that all seven transistors in the pixel driving circuit Q are P-type transistors.

[0135] As shown in Figures 6 and 7 , the driving process of the pixel driving circuit Q shown in Figure 7 is as follows: one frame period includes an initialization phase t1, a data writing phase t2, and a light-emitting phase t3. The initialization phase t1 and the light-emitting phase t3 of the driving process of the pixel driving circuit Q shown in Figure 7 are substantially the same as the driving process of the pixel driving circuit Q shown in Figure 5 above, and are not further described here.

[0136] The driving process of the pixel driving circuit Q shown in Figure 7 is different from the driving process of the pixel driving circuit Q shown in Figure 5 in that the data writing stage t2 in the driving process of the pixel driving circuit Q shown in Figure 7 not only includes the data writing stage t2 in the driving process of the pixel driving circuit Q shown in Figure 5, but also includes the following stages.

[0137] When the data write signal is transmitted to the second node N2, it is equivalent to transmitting the data write signal to the first capacitor C1. Based on this, the first capacitor C1 also synchronously stores the voltage of the data write signal during this stage.

[0138] In sub-phase t21 after the data write transistor T4 is turned off and before the compensation transistor T2 is turned off, the first capacitor C1 can be discharged to the first node N1 until the compensation transistor T2 is turned off. This can indirectly extend the writing time of the data write signal, which is beneficial for improving the display uniformity of the display panel.

[0139] FIG8 is a film layer structure diagram of multiple pixel driving circuits according to some embodiments. FIG8 takes two rows and four columns of pixel driving circuits Q in the display panel 100 as an example, but does not mean that the display panel 100 only includes the illustrated number of pixel driving circuits Q.

[0140] In some embodiments, as shown in Figures 2, 6, and 8, the driving circuit layer 20 includes a semiconductor layer POLY, a first gate metal layer Gate1, a first routing metal layer SD1, and a second routing metal layer SD2 stacked on a base substrate 10. The semiconductor layer POLY is located between the base substrate 10 and the first gate metal layer Gate1.

[0141] The driving circuit layer 20 further includes the aforementioned plurality of signal lines electrically connected to the driving circuit Q. Exemplarily, the driving circuit layer 20 includes a plurality of first scanning signal lines G1, a plurality of second scanning signal lines G2, a plurality of first initialization signal lines Vinit1, a plurality of second initialization signal lines Vinit2, a plurality of first power signal lines VDD, a plurality of second power signal lines VSS, and a plurality of data write signal lines Data.

[0142] The plurality of data writing signal lines Data are arranged along a first direction X and extend along a second direction Y. The data writing signal lines Data are configured to provide a data writing signal to the pixel driving circuit Q.

[0143] In some examples, multiple data write signal lines Data may be located in the second wiring metal layer SD2 , multiple data write signal lines Data are located in the display area AA, and one data write signal line Data is connected to a column of sub-pixel driving circuits Q.

[0144] Among them, a part of the multiple data write signal lines Data is located in an edge area AA2, another part of the multiple data write signal lines Data is located in another edge area AA2, and another part of the multiple data write signal lines Data is located in the middle area AA1.

[0145] In some examples, the number of data write signal lines Data in the two edge areas AA2 may be the same. In other examples, the number of data write signal lines Data in the two edge areas AA2 may be different.

[0146] In some examples, the number of data write signal lines Data in an edge area AA2 may be the same as the number of data write signal lines Data in the middle area AA1. In other examples, the number of data write signal lines Data in an edge area AA2 may be different from the number of data write signal lines Data in the middle area AA1.

[0147] In some examples, the display panel further includes a binding area BB. The binding area BB is located on one side of the display area AA. The driving circuit layer 20 in the display panel 100 further includes a plurality of data leads L. The data lead L includes a first lead segment L1 and a second lead segment L2. The second lead segment L2 is located in the middle area AA1, extends along the second direction Y, and extends to the binding area BB. In addition, the first lead segment L1 extends along the first direction X, one end of the first lead segment L1 is located in the edge area AA2, and the other end of the first lead segment L1 is located in the middle area AA2. One end of the first lead segment L1 can be electrically connected to a data write signal line Data located in the edge area AA2, and the other end of the first lead segment L1 can be electrically connected to one end of the second lead segment L2 located in the middle area AA1.

[0148] Based on this, the data write signal line Data in the edge area AA2 can be routed to the middle area AA1 using the first lead segment L1 of the data lead L, and then extended into the binding area BB using the second lead segment L2 of the data lead L. In other words, the signal lines that need to be electrically connected to the binding area BB (the second lead segment L2 electrically connected to the data write signal line Data in the edge area AA2 and the data write signal line Data in the middle area AA1) can be concentrated in the display area AA at the position corresponding to the driver chip IC, which is conducive to achieving a narrow bezel.

[0149] Therefore, the display panel 100 can adopt the FIAA technology and arrange the data leads L in the display area AA, which can be beneficial to achieving a narrow frame of the display panel 100.

[0150] In some examples, the bonding area BB includes a driver chip (English full name: Integrated Circuit, English abbreviation: IC).

[0151] However, since the data lead L is disposed in the display area AA, the orthographic projection of the data lead L on the base substrate 10 may easily overlap with the orthographic projection of some transistors in the pixel driving circuit Q on the base substrate 10, affecting the stability of the transistors.

[0152] Specifically, when the orthographic projection of the data lead L on the substrate 10 overlaps with the orthographic projection of the second electrode d1 of the first reset transistor T1 in the pixel driving circuit Q on the substrate 10, the data write signal can be a pulse signal. In other words, the data write signal is a constantly changing, non-constant signal. Due to capacitive coupling, when the data write signal transmitted by the data lead L changes, the potential of the second electrode d1 of the first reset transistor T1 also changes. This, in turn, indirectly causes the potential of the control electrode g3 of the driving transistor T3 to change, affecting the stability of the driving transistor T3.

[0153] Based on this, a third routing metal layer can be added to the driving circuit layer 20 to form the first lead segment L1 of the data lead L in the second routing metal layer SD2 and the second lead segment of the data lead L in the third routing metal layer. This increases the spacing between the transistors in the pixel driving circuit Q and the data lead L in a direction perpendicular to the substrate 10. This also alleviates the problem of potential jumps at the second electrode d1 of the first reset transistor T1 caused by jumps in the data write signal transmitted by the data lead L.

[0154] However, the inventors of the present disclosure have discovered that adding a third routing metal layer to the driver circuit layer 20 requires an additional patterning process during the manufacture of the display panel 100 to form the data write signal line Data and the second lead segment L2 of the data lead L in the third routing metal layer. Furthermore, because the third routing metal layer is located on the side of the second routing metal layer SD2 facing away from the first routing metal layer SD1, an insulating layer must be provided between the third routing metal layer and the second routing metal layer to prevent short circuits between the third routing metal layer and the second routing metal layer. The first lead segment L1 of the data lead L is formed on the second routing metal layer SD2. The first lead segment L1 and the second lead segment L2 of the data lead L need to be connected to each other. Therefore, a via hole must be formed in the insulating layer between the third routing metal layer and the second routing metal layer to facilitate connection between the first lead segment L1 of the data lead L located on the second routing metal layer SD2 and the second lead segment L2 of the data lead L located on the third routing metal layer. In other words, when manufacturing the display panel 100, an additional patterning process is required to form the via hole in the insulating layer between the third routing metal layer and the second routing metal layer.

[0155] In summary, the addition of the third wiring metal layer in the driving circuit layer 20 requires two additional patterning processes when manufacturing the display panel 100. This increases the cost of the display panel 100 and also increases the production cycle of the display panel 100, thereby reducing the production efficiency of the display panel 100.

[0156] Figure 9 is a diagram illustrating the film layer structure of multiple pixel driving circuits according to other embodiments. Figure 10 is a diagram illustrating the structure of the semiconductor layer in Figure 9 , Figure 11 is a diagram illustrating the structure of the semiconductor layer according to some embodiments, Figure 12 is a diagram illustrating the structure of the first gate metal layer in Figure 9 , Figure 13 is a diagram illustrating the structure of the second gate metal layer in Figure 9 , Figure 14 is a diagram illustrating the structure of the semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 9 , Figure 15 is a diagram illustrating the structure of the first routing metal layer in Figure 9 , Figure 16 is a diagram illustrating the structure of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the first routing metal layer in Figure 9 , and Figure 17 is a diagram illustrating the structure of the second routing metal layer in Figure 9 .

[0157] FIG9 is a diagram showing the four lower pixel driving circuits Q in FIG8 as an example, so that the structure of each pixel driving circuit Q can be observed more clearly.

[0158] Based on the above issues, and in conjunction with Figures 8 to 17 , in the display panel 100 provided in the embodiment of the present disclosure, the driving circuit layer 20 includes a semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a first routing metal layer SD1, and a second routing metal layer SD2, which are stacked on the base substrate 10 (as shown in Figure 3 ). The semiconductor layer POLY is located between the first gate metal layer Gate1 and the base substrate 10.

[0159] The first routing metal layer SD1 may include a first lead segment L1 of the data lead line L, and the second routing metal layer SD2 may include a data write signal line Data and a second lead segment L2 of the data lead line L.

[0160] Based on this, the data write signal line Data and the data lead L are separated into the space between the first routing metal layer SD1 and the second routing metal layer SD2. This eliminates the need to add a third routing metal layer to the drive circuit layer 20 of the display panel 100. Compared to display panels 100 equipped with a third routing metal layer, the display panel 100 provided by the present embodiment can eliminate two patterning processes. Consequently, the cost of the display panel 100 can be reduced, the production cycle of the display panel 100 can be shortened, and the production efficiency of the display panel 100 can be improved.

[0161] The above primarily describes shifting the data leads L and data write signal lines Data downward to eliminate the need for a third metal routing layer in the drive circuit layer, thereby reducing the cost of the display panel 100, shortening the production cycle of the display panel 100, and improving the production efficiency of the display panel 100. However, shifting the data leads L and data write signal lines Data downward toward the base substrate 10 reduces the spacing between the data leads L and data write signal lines Data and the transistors in the pixel drive circuit Q, potentially impacting transistor stability. The following describes how to reduce crosstalk between the data leads L and transistors, in conjunction with the structures within multiple film layers in the drive circuit layer.

[0162] In some examples, as shown in FIG10 , the semiconductor layer POLY further includes the channel portions of each transistor in the pixel driving circuit Q. Furthermore, the semiconductor layer POLY further includes a first conductive portion U1, which includes the second electrode d1 of the first reset transistor T1 and is connected to the channel portion a1 of the first reset transistor T1. Furthermore, the first conductive portion U1 may further include the second electrode d2 of the compensation transistor T2, thereby connecting the second electrode d1 of the first reset transistor T1 to the second electrode d2 of the compensation transistor T2.

[0163] Exemplarily, in the case where the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6 and a second reset transistor T7: the semiconductor layer POLY includes: a first electrode s1, a second electrode d1 and a channel portion a1 of the first reset transistor T1, a first electrode s2, a second electrode d2 and a channel portion a2 of the compensation transistor T2, a first electrode s3, a second electrode d3 and a channel portion a3 of the driving transistor T3, a first electrode s4, a second electrode d4 and a channel portion a4 of the data writing transistor T4, a first electrode s5, a second electrode d5 and a channel portion a5 of the first light-emitting control transistor T5, a first electrode s6, a second electrode d6 and a channel portion a6 of the second light-emitting control transistor T6, and a first electrode s7, a second electrode d7 and a channel portion a7 of the second reset transistor T7.

[0164] It should be noted that, in conjunction with Figures 9 and 10 , the orthographic projection of the semiconductor layer POLY on the base substrate 10 (as shown in Figure 3 ) overlaps with the orthographic projection of the first gate metal layer Gate1 on the base substrate 10. The portion of the semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the semiconductor layer POLY not covered by the first gate metal layer G1 is a conductive portion, constituting a portion of the first electrode or the second electrode of each transistor.

[0165] In some examples, as shown in FIG10 , the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10 is in the shape of an inverted "I." In this case, the channel portion a3 of the driving transistor T3 extends along the first direction X. The regular structure of the channel portion a3 of the driving transistor T3 facilitates the flexible arrangement of other transistors on the semiconductor layer POLY.

[0166] In other examples, as shown in FIG11 , the orthographic projection of the channel portion a3 of the driving transistor T3 on the substrate 10 is in the shape of a Chinese character "J." The Chinese character "J" can be understood as an Ω shape, or a shape similar to an Ω shape or a Chinese character "J." In other words, the channel portion a3 of the driving transistor T3 includes a protruding structure. This configuration can improve the stability of the driving transistor T3, allowing it to handle a larger driving current, thereby enhancing the display quality of the display panel 100.

[0167] In some examples, the material of the semiconductor layer POLY may include amorphous silicon, single crystal silicon, or polycrystalline silicon semiconductor material.

[0168] In some examples, as shown in Figures 9 and 12 , the first gate metal layer Gate1 is located on a side of the semiconductor layer POLY away from the substrate 10 (as shown in Figure 3 ). That is, the first gate metal layer Gate1 is located between the semiconductor layer POLY and the second gate metal layer Gate2 .

[0169] The first gate metal layer Gate1 may include control electrodes of various transistors in the pixel driving circuit Q. Exemplarily, when the pixel driving circuit Q includes a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a second reset transistor T7: the first gate metal layer Gate1 may include a control electrode g1 of the first reset transistor T1, a control electrode g2 of the compensation transistor T2, a control electrode g3 of the driving transistor T3, a control electrode g4 of the data writing transistor T4, a control electrode g5 of the first light emission control transistor T5, a control electrode g6 of the second light emission control transistor T6, and a control electrode g7 of the second reset transistor T7.

[0170] In addition, the first gate metal layer Gate1 can also be used to form a portion of signal lines. The portion of signal lines includes a plurality of first scan signal lines G1 and a plurality of second scan signal lines G2. The plurality of first scan signal lines G1 extend along a first direction X and are arranged along a second direction Y. Furthermore, the plurality of second scan signal lines G1 extend along the first direction X and are arranged along a second direction Y.

[0171] In some examples, the first scan signal line G1 located on the first gate metal layer Gate1 may include a first portion G11 , and the first portion G11 of the first scan signal line G1 may be multiplexed as a control electrode g4 of the data writing transistor T4 .

[0172] Based on this, the first portion G11 of the first scanning signal line G1 is directly used as the control electrode g4 of the data writing transistor T4. Not only does it not need to provide a separate control electrode g4 of the data writing transistor T4, but it also does not need to provide a conductive portion for connecting the control electrode g4 of the data writing transistor T4 and the first description signal line G1. Therefore, this arrangement not only simplifies the layout of the first gate metal layer Gate1, facilitates the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also helps save resources.

[0173] In some examples, when the first scan signal line G1 is multiplexed as the second reset signal line, the first scan signal line G1 located on the first gate metal layer Gate1 may further include a second portion G12, and the second portion G12 of the first scan signal line G1 may be multiplexed as the control electrode g7 of the second reset transistor T7.

[0174] Based on this, the second portion G12 of the first scanning signal line G1 is directly used as the control electrode g7 of the second reset transistor T7. Not only does it not need to separately provide the control electrode g7 of the second reset transistor T7, but it also does not need to provide a conductive portion for connecting the control electrode g7 of the second reset transistor T7 and the first scanning signal line G1. Therefore, this arrangement not only simplifies the layout of the first gate metal layer Gate1 and facilitates the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplifies the manufacturing process of the pixel driving circuit Q, which is beneficial for saving resources.

[0175] In some examples, the second scan signal line Gate2 located on the first gate metal layer Gate1 may include a first portion G21 , and the first portion G21 of the second scan signal line Gate2 may be reused as a control electrode g2 of the compensation transistor T2 .

[0176] Based on this, the first portion G21 of the second scanning signal line Gate2 is directly used as the control electrode g2 of the compensation transistor T2. Not only does it not need to separately provide the control electrode g2 of the compensation transistor T2, but it also does not need to provide a conductive portion for connecting the control electrode g2 of the compensation transistor T2 and the second scanning signal line Gate2. Therefore, this arrangement not only simplifies the layout of the first gate metal layer Gate1 and facilitates the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplifies the manufacturing process of the pixel driving circuit Q, which is beneficial for saving resources.

[0177] In some examples, the second scan signal line G2(n-7) / first reset signal line R1 located on the first gate metal layer Gate1 can include a first portion R11, and the first portion R11 of the second scan signal line G2(n-7) / first reset signal line R1 can be reused as the control electrode g1 of the first reset transistor T1.

[0178] Based on this, the second scanning signal line G2(n-7) / the first portion R11 of the first reset signal line R1 is directly used as the control electrode g1 of the first reset transistor T1. This eliminates the need for a separate control electrode g1 of the first reset transistor T1 and also eliminates the need for a conductive portion connecting the control electrode g1 of the first reset transistor T1 to the second scanning signal line G2(n-7) / the first reset signal line R1. Therefore, this arrangement not only simplifies the layout of the first gate metal layer Gate1 and facilitates the flexible arrangement of other conductive portions on the first gate metal layer Gate1, but also simplifies the manufacturing process of the pixel driving circuit Q, thereby saving resources.

[0179] In some examples, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0180] In some examples, a first gate insulating layer is disposed between the first semiconductor layer POLY1 and the first gate metal layer Gate1 , and the first gate insulating layer electrically insulates the first semiconductor layer POLY1 from the first gate metal layer Gate1 .

[0181] Exemplarily, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0182] In some examples, as shown in Figures 9, 13, and 14, the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the semiconductor layer POLY. That is, the second gate metal layer Gate2 is located between the first gate metal layer Gate1 and the first trace metal layer SD1.

[0183] In some examples, the pixel driving circuit Q further includes a storage capacitor Cst. A first plate Cst-1 of the storage capacitor Cst is electrically connected to the first node N1, and a second plate Cst-2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0184] The first gate metal layer Gate1 further includes a first electrode plate Cst-1 of a storage capacitor Cst. The orthographic projection of the first electrode plate Cst-1 of the storage capacitor Cst on the base substrate 10 (as shown in FIG. 3 ) can be arranged to overlap with the orthographic projection of the channel portion a3 of the drive transistor T3 on the base substrate 10 , so that the first electrode plate of the storage capacitor Cst can be reused as the control electrode g3 of the drive transistor T3 .

[0185] The second gate metal layer Gate2 includes a second plate Cst-2 of the storage capacitor Cst. The orthographic projection of the second plate Cst-2 of the storage capacitor Cst on the substrate 10 (as shown in FIG. 3 ) overlaps with the orthographic projection of the first plate Cst-1 of the storage capacitor Cst on the substrate 10 to form a storage capacitor Cst.

[0186] The first electrode plate Cst-1 of the storage capacitor Cst located on the first gate metal layer Gate1 can be reused as the control electrode g3 of the drive transistor T3. This eliminates the need for a separate control electrode g3 of the drive transistor T3, simplifying the manufacturing process of the pixel drive circuit Q. Furthermore, the first electrode plate Cst-1 of the storage capacitor Cst can be reused as the control electrode g3 of the drive transistor T3, allowing for a direct electrical connection between the first electrode plate Cst-1 of the storage capacitor Cst and the control electrode g3 of the drive transistor T3, eliminating the need for a separate connection portion. This also facilitates the layout of the pixel drive circuit Q.

[0187] In addition, the second gate metal layer Gate2 can also be used to form a portion of signal lines. These signal lines include multiple first initialization signal lines Vinit1 and multiple second initialization signal lines Vinit2. The multiple first initialization signal lines Vinit1 extend along a first direction X and are arranged along a second direction Y. Furthermore, the multiple second initialization signal lines Vinit2 extend along the first direction X and are arranged along a second direction Y.

[0188] In addition, since the second gate metal layer Gate2 is located between the semiconductor POLY and the first wiring metal layer SD1, a first shielding portion J1 may be provided on the second gate metal layer Gate2, wherein the first shielding portion J1 is configured to have a constant voltage signal.

[0189] Based on this, the orthographic projection of the first shielding portion J on the base substrate 10 may be set to partially overlap with the orthographic projection of the first conductive portion U1 on the base substrate 10 .

[0190] In some examples, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0191] In some examples, a second gate insulating layer may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1 . The second gate insulating layer electrically insulates the second gate metal layer Gate2 from the first gate metal layer Gate1 .

[0192] Exemplarily, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer may also include silicon dioxide, but the present disclosure is not limited thereto.

[0193] In some examples, as shown in Figures 9, 15, and 16, the first routing metal layer SD1 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. That is, the first routing metal layer SD1 is located between the second gate metal layer Gate2 and the second routing metal layer SD2.

[0194] Exemplarily, the material package of the first wiring metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0195] For example, a first planarization layer (PLN) is provided between the first wiring metal layer SD1 and the second gate metal layer Gate2 to electrically insulate the first wiring metal layer SD1 from the second gate metal layer Gate2.

[0196] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0197] Furthermore, the first routing metal layer SD1 can also be used to form a portion of signal lines. These portion of signal lines includes first lead segments L1 of a plurality of data leads L, a plurality of first enable signal lines EM1, and a plurality of second enable signal lines EM2. The plurality of first enable signal lines EM1 extend along a first direction X and are arranged along a second direction Y. Furthermore, the plurality of second enable signal lines EM2 extend along the first direction X and are arranged along a second direction Y.

[0198] In some embodiments, as shown in conjunction with Figures 8, 9, and 16, the first routing metal layer SD1 further includes a plurality of first dummy lead segments 31 extending along the first direction X and arranged in the second direction Y. The first dummy lead segments 31 correspond one-to-one with the first lead segments L1, and along the first direction X, the first dummy lead segments 31 are spaced apart from the first lead segments L1.

[0199] Based on this, multiple first virtual lead segments 31 and multiple first lead segments L1 can be used in combination to achieve uniform routing on the first routing metal layer SD1, thereby improving the uniformity of the first routing metal layer SD1's reflection of external ambient light, thereby improving the display effect of the display panel 100.

[0200] In some examples, the first dummy lead segment 31 can be configured to transmit a constant voltage signal. For example, the first dummy lead segment 31 can be electrically connected to the second power signal line VSS.

[0201] In some embodiments, the first routing metal layer SD1 further includes a plurality of connection portions.

[0202] The connecting portion includes a first connecting portion PAD1, which is used to connect the control electrode g3 of the driving transistor T3 located in the first gate metal layer Gate1 and the first conductive portion U1 located in the semiconductor layer POLY, so as to realize electrical connection between the control electrode g3 of the driving transistor T3, the second electrode d1 of the first reset transistor T1, and the second electrode d2 of the compensation transistor T2.

[0203] The first connecting portion PAD1 may be connected to the first conductive portion U1 through a via hole, and the first connecting portion PAD1 may be connected to the control electrode g3 of the driving transistor T3 through another via hole.

[0204] The connecting portion also includes a second connecting portion PAD2, which is used to connect the first initialization signal line Vinit1 located in the second gate metal layer Gate2 and the first electrode s1 of the first reset transistor T1 located in the semiconductor layer POLY, so as to realize the electrical connection between the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1.

[0205] The second connection portion PAD2 may be connected to the first initialization signal line Vinit1 through a via hole, and the second connection portion PAD2 may be further connected to the first electrode s1 of the first reset transistor T1 through another via hole.

[0206] The connection portion may further include a third connection portion PAD3 , which may be used to connect the second plate Cst- 2 of the storage capacitor Cst and the first power signal line VDD.

[0207] The third connection portion PAD3 may be connected to the second electrode plate Cst- 2 of the storage capacitor Cst through a via hole, and the third connection portion PAD3 may be further connected to the first power signal line VDD through another via hole.

[0208] The connecting portion may further include a fourth connecting portion PAD4, which is used to connect the second electrode d6 of the second light-emitting control transistor T6, the second electrode d7 of the second reset transistor T7 and the anode of the light-emitting device, so as to realize that the second electrode d6 of the second light-emitting control transistor T6, the second electrode d7 of the second reset transistor T7 are electrically connected to the anode of the light-emitting device.

[0209] The fourth connection portion PAD4 can be connected to the second electrode d6 of the second light emitting control transistor T6 and the second electrode d7 of the second reset transistor T7 through a via hole, and can also be connected to the anode of the light emitting device through another via hole.

[0210] The connecting portion may also include a fifth connecting portion PAD5, which is used to connect the first electrode s7 of the second reset transistor T7 located in the semiconductor layer POLY and the second initialization signal line Vinit2 located in the second gate metal layer Gate2, so as to realize the electrical connection between the first electrode s7 of the second reset transistor T7 and the second initialization signal line Vinit2.

[0211] The fifth connection portion PAD5 may be connected to the first electrode s7 of the second reset transistor T7 through a via hole, and the fifth connection portion PAD5 may be further connected to the second initialization signal line Vinit2 through another via hole.

[0212] The connection portion may also include a sixth connection portion PAD6, which is used to connect the first electrode s4 of the data write transistor T4 located in the semiconductor layer POLY and the first scanning signal line G1 located in the first gate metal layer Gate1, so as to realize the electrical connection between the first electrode s4 of the data write transistor T4 and the first scanning signal line G1.

[0213] In some examples, as shown in FIG. 8 , FIG. 9 , and FIG. 17 , the second routing metal layer SD2 is located on a side of the first routing metal layer SD1 away from the second gate metal layer Gate2 .

[0214] In some examples, the material of the second routing metal layer SD2 may be the same as that of the first routing metal layer SD1. Alternatively, in other examples, the material of the second routing metal layer SD2 may be different from that of the first routing metal layer SD1. The embodiments of the present disclosure are not limited in this regard.

[0215] In some examples, a second planarization layer is disposed between the second routing metal layer SD2 and the first routing metal layer SD1 , and the second planarization layer electrically insulates the second routing metal layer SD2 from the first routing metal layer SD1 .

[0216] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0217] In some embodiments, as shown in conjunction with FIG8 and FIG9 , the second routing metal layer SD2 further includes a plurality of second dummy lead segments 32 , which extend along the second direction Y and are arranged in the first direction X. The second dummy lead segments 32 correspond one-to-one with the second lead segments L2 , and along the second direction Y, the second dummy lead segments 32 are spaced apart from the second lead segments L2 .

[0218] Based on this, multiple second dummy lead segments 32 can be used in conjunction with multiple second lead segments L2 to achieve a uniform routing arrangement on the second routing metal layer SD2, thereby improving the uniformity of the second routing metal layer SD2 in reflecting ambient light, thereby improving the display effect of the display panel 100.

[0219] In some examples, the second dummy lead segment 32 can be configured to transmit a constant voltage signal. For example, the second dummy lead segment 32 can be electrically connected to the second power signal line VSS.

[0220] In some examples, within the same data lead L, the orthographic projection of the first lead segment L1 on the base substrate 10 overlaps with the orthographic projection of the second lead segment L2 on the base substrate 10. This facilitates connection between the first lead segment L1 and the second lead segment L2 through a punching process.

[0221] Furthermore, the width of the first portion of the second lead segment L2 can be set to be greater than the width of the second portion. The orthographic projection of the first portion of the second lead segment L2 on the substrate 10 overlaps with the orthographic projection of the first lead segment L1 on the substrate 10, while the orthographic projection of the second portion of the second lead segment L2 on the substrate 10 does not overlap with the orthographic projection of the first lead segment L1 on the substrate 10. Based on this, the area of ​​the overlapping region between the orthographic projections of the first lead segment L1 and the second lead segment L2 on the substrate 10 can be increased, thereby reducing the difficulty of the punching process and facilitating the connection between the first lead segment L1 and the second lead segment L2 through the punching process.

[0222] In some examples, the orthographic projection of the first lead segment L1 on the base substrate 10 overlaps with the orthographic projection of the data writing signal line Data on the base substrate 10. Based on this, the first lead segment L1 and the data writing signal line Data can be easily connected through a punching process.

[0223] In some embodiments, as shown in conjunction with FIG2 , FIG6 , and FIG8 , the second lead segment L2 of the data lead L is located between two adjacent pixel driving circuits Q in the first direction X. That is, the second lead segment L2 of the data lead L is located in a region of the driving transistor T3 that is close to an edge of the pixel driving circuit Q in the first direction X, so that the orthographic projection of the second lead segment L2 of the data lead L on the base substrate 10 (referring to FIG3 ) does not overlap with the orthographic projection of the driving transistor T3 on the base substrate 10.

[0224] In this way, the data write signal transmitted by the second lead segment L2 of the data lead L can be prevented from affecting the potentials of the various electrodes of the driving transistor T3 when it jumps, which is beneficial to improving the stability of the driving transistor T3 in the pixel driving circuit Q, thereby helping to improve the brightness uniformity of the display panel 100.

[0225] As shown in Figures 9 to 16 , based on the above description of the structures of the various film layers in the driver circuit layer 20, the first conductive portion U1 in the semiconductor layer POLY includes the second electrode d1 of the first reset transistor T1, and the second gate metal layer Gate2 is provided with a first shielding portion J having a constant voltage signal. The first routing metal layer SD1 is provided with the first lead segment L1 of the data lead L. That is, in a direction perpendicular to the base substrate 10 (as shown in Figure 3 ), the first shielding portion J is located between the first conductive portion U1 and the first lead segment.

[0226] Furthermore, it may be configured that the orthographic projection of the first conductive portion U1 on the base substrate 10 , the orthographic projection of the first shielding portion J on the base substrate 10 , and the orthographic projection of the first lead segment L1 on the base substrate 10 overlap.

[0227] Based on this, the first shielding portion J, which carries a constant voltage signal, can be used to isolate the first conductive portion U1 from the first lead segment L1, thereby reducing voltage jumps at the first conductive portion U1 caused by jumps in the data write signal transmitted by the first lead segment L1. Because the second electrode d1 of the first reset transistor T1 and the control electrode g3 of the drive transistor T3 are both electrically connected to the first node, the first conductive portion U1 is electrically connected to the control electrode g3 of the drive transistor T3, thereby indirectly improving the stability of the control electrode g3 of the drive transistor T3 and facilitating optimized brightness uniformity of the display panel 100.

[0228] In some embodiments, as shown in conjunction with FIG9 to FIG16 , the first reset transistor T1 and the compensation transistor T2 are located on the same side of the driving transistor T3 in the second direction Y. In the second direction Y, the control electrode g1 of the first reset transistor T1 is located on a side of the compensation transistor T2 away from the driving transistor T3 , the first electrode s1 and the second electrode d1 of the first reset transistor T1 are both located between the control electrode g1 of the first reset transistor T1 and the driving transistor, and the second electrode d1 of the first reset transistor T1 is adjacent to the second electrode d2 of the compensation transistor T2 .

[0229] Based on this, the second electrode d1 of the first reset transistor T1 can be connected to the second electrode d2 of the compensation transistor T2, so as to be electrically connected to the control electrode g3 of the driving transistor T3 in a synchronous manner.

[0230] In some examples, the second electrode d1 of the first reset transistor T1 is multiplexed as the second electrode d2 of the compensation transistor T2 .

[0231] Based on this, it is easy to realize that the second electrode d1 of the first reset transistor T1 can be connected to the second electrode d2 of the compensation transistor T2, and it is also beneficial to save the space of the semiconductor layer POLY.

[0232] In some embodiments, as shown in Figures 9 to 16 , the second gate metal layer Gate2 further includes a plurality of first initialization signal lines Vinit1. Since the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1, the first initialization signal line Vinit1 can be located between the control electrode g1 of the first reset transistor T1 and the first electrode s1 and the second electrode d1 of the first reset transistor T1.

[0233] Based on this, the distance between the first initialization signal line Vinit1 and the first electrode s1 of the first reset transistor T1 can be shortened, so as to facilitate electrical connection between the two.

[0234] In some embodiments, as shown in FIG9 to FIG16 , since the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal, the first initialization signal line Vinit1 can be electrically connected to the first shield portion J to transmit the constant voltage signal to the first shield portion J using the first initialization signal line.

[0235] Based on this, the first shielding portion J can be provided with a constant voltage signal, thereby isolating the first lead segment L1 from the first conductive portion U1. This alleviates the problem of voltage jumps on the first conductive portion U1 caused by the data write signal transmitted by the first lead segment L1. Furthermore, there is no need to provide an independent constant voltage signal line in the driver circuit layer, which can save space and resources in the driver circuit layer.

[0236] In some examples, the first initialization signal line Vinit1 is in the same layer as the first shielding portion J. The first initialization signal line Vinit1 and the first shielding portion J can be formed using one patterning process, thereby simplifying the manufacturing process of the pixel driving circuit Q.

[0237] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0238] In some embodiments, as shown in Figures 9 to 16 , the first initialization signal line Vinit1 can include a main portion B1 and a first auxiliary portion F1, with the first auxiliary portion F1 located on a side of the main portion B1 near the first reset transistor T1. That is, the first auxiliary portion F1 is the portion of the first initialization signal line Vinit1 that protrudes toward the first reset transistor T1.

[0239] At this time, the orthographic projection of the first auxiliary portion F1 of the first initialization signal line Vinit1 on the base substrate 10 (as shown in FIG3 ), the orthographic projection of the first conductive portion U1 on the base substrate 10 , and the orthographic projection of the first lead segment L1 on the base substrate 10 overlap.

[0240] Therefore, the first auxiliary part F1 of the first initialization signal line Vinit1 can be reused as the first shielding part J to isolate the first lead segment L1 from the first conductive part U1, thereby improving the problem of voltage jump of the first conductive part U1 caused by the data write signal transmitted by the first lead segment L1.

[0241] Furthermore, since the first auxiliary portion F1 of the first initialization signal line Vinit1 is reused as the first shielding portion J, there is no need to separately provide the first shielding portion J, which can simplify the manufacturing process of the display panel.

[0242] Furthermore, because the orthographic projection of the body B1 of the first initialization signal line Vinit1 on the base substrate 10 at least partially overlaps with the orthographic projection of the first conductive portion U1 on the base substrate 10, the relative area between the first initialization signal line Vinit1 and the first conductive portion U1 can be increased, further improving the stability of the first conductive portion U1 and thereby improving the stability of the driving transistor T3.

[0243] In some embodiments, as shown in FIG. 9 to FIG. 14 , the control electrode g2 of the compensation transistor T2 includes a first control electrode g1 and a second control electrode g2 .

[0244] The channel portion a2 of the compensation transistor T2 includes a first channel portion a21 and a second channel portion a22. The semiconductor layer POLY also includes a second conductive portion U2 located between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2. One end of the second conductive portion U2 is connected to the first channel portion a21 of the compensation transistor T2, and the other end of the second conductive portion U2 is connected to the second channel portion a22 of the compensation transistor T2, thereby connecting the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 via the second conductive portion U2.

[0245] It should be noted that the first channel portion a21 of the compensation transistor T2 is opposite to the first control electrode g21 of the compensation transistor T2. That is, the orthographic projection of the first channel portion a21 of the compensation transistor T2 on the base substrate 10 overlaps with the orthographic projection of the first control electrode g21 of the compensation transistor T2 on the base substrate 10. Furthermore, the second channel portion a22 of the compensation transistor T2 is opposite to the second control electrode g22 of the compensation transistor T2. That is, the orthographic projection of the second channel portion a22 of the compensation transistor T2 on the base substrate 10 overlaps with the orthographic projection of the second control electrode g22 of the compensation transistor T2 on the base substrate 10.

[0246] As described above, the compensation transistor T2 can be a dual-gate transistor, which can improve the problem of leakage to the first node N1 through the compensation transistor T2. Furthermore, it is beneficial to improve the stability of the control electrode g3 of the driving transistor T3 and improve the brightness uniformity of the display panel 100.

[0247] In some embodiments, as shown in conjunction with Figures 9 to 14 , and in some examples, as shown in conjunction with Figures 13 and 14 , the first initialization signal line Vinit1 further includes a second auxiliary portion F2. The second auxiliary portion F2 is located on the side of the main portion B1 of the first initialization signal line Vinit1 that is closer to the driving transistor. That is, the portion of the first initialization signal line Vinit that protrudes toward the driving transistor T3 is the second auxiliary portion F2. The orthographic projection of the second auxiliary portion F2 on the base substrate 10 at least partially overlaps with the orthographic projection of the second conductive portion U2 on the base substrate 10.

[0248] This is equivalent to arranging the orthographic projection of the second auxiliary portion F2 on the base substrate 10 to at least partially overlap with the orthographic projection of the conductive portion (second conductive portion U2) between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 on the base substrate 10. Therefore, the second auxiliary portion F2 of the first initialization signal line Vinit1 can form a capacitor with the second conductive portion U2 between the first channel portion a21 and the second channel portion a22 of the compensation transistor T2.

[0249] Because the first initialization signal transmitted by the first initialization signal line Vinit1 is a constant voltage signal, the stability of the compensation transistor T2 can be improved, and the leakage problem to the first node N1 through the compensation transistor T2 can be alleviated. This further helps to improve the stability of the control electrode g3 of the driving transistor T3 and enhance the brightness uniformity of the display panel 100.

[0250] The orthographic projection of the second auxiliary portion F2 on the base substrate 10 at least partially overlaps with the orthographic projection of the second conductive portion U2 on the base substrate 10 , which may include the following two situations.

[0251] The first type: The orthographic projection of the second auxiliary portion F2 on the base substrate 10 overlaps with the orthographic projection of a portion of the second conductive portion U2 on the base substrate 10. In other words, the orthographic projection of a portion of the second conductive portion U2 on the base substrate 10 is located within the boundary of the orthographic projection of the second auxiliary portion F2 on the base substrate 10.

[0252] The second type: the orthographic projections of the second conductive portion U2 on the base substrate 10 are all located within the boundaries of the orthographic projections of the second auxiliary portion F2 on the base substrate 10 .

[0253] Regardless of any of the overlapping situations of the second auxiliary portion F2 and the second conductive portion U2 , a capacitor can be formed between the two, thereby improving the stability of the compensation transistor T2 and alleviating the problem of leakage to the first node N1 through the compensation transistor T2 .

[0254] The second approach can further increase the overlapping area of ​​the orthographic projection between the second conductive portion U2 and the second auxiliary portion F2 compared to the first approach. This helps increase the capacitance formed between the second conductive portion U2 and the second auxiliary portion F2, thereby further improving the stability of the control electrode g3 of the driving transistor T3 and enhancing the brightness uniformity of the display panel 100.

[0255] In some embodiments, as shown in Figures 9 to 14 , the second conductive portion U2 includes a first sub-portion U21 and a second sub-portion U22. The first sub-portion U21 of the second conductive portion U2 that protrudes toward the first channel portion a21 of the compensation transistor T2 can be electrically connected to the first channel portion a21, and the second sub-portion U22 of the second conductive portion U2 that protrudes toward the second channel portion a22 of the compensation transistor T2 can be electrically connected to the second channel portion a22.

[0256] Based on this, the first channel portion a21 and the second channel portion a22 of the compensation transistor T2 are electrically connected by utilizing the second conductive portion U2 .

[0257] In some examples, the second conductive portion U2 may include a third sub-portion U23 in addition to the first sub-portion U21 and the second sub-portion U22. The first sub-portion U21, the second sub-portion U22, and the third sub-portion U23 intersect at the same point, and the third sub-portion U23 is located on the side of the second sub-portion U22 facing away from the second channel portion a22. The orthographic projection of the second conductive portion U2, which is composed of the first sub-portion U21, the second sub-portion U22, and the third sub-portion U23, on the substrate 10 (as shown in FIG. 3 ), forms the shape of a character "├".

[0258] Because the third sub-portion U23 is located on the side of the second sub-portion U22 facing away from the second channel portion a22, that is, the main body B1 of the first initialization signal line Vinit1 of the third sub-portion U23, the orthographic projection of the third sub-portion U23 on the base substrate 10 is located within the boundary of the orthographic projection of the second auxiliary portion F2 on the base substrate 10. This is equivalent to using the third sub-portion U23 to increase the size of the second conductive portion U2, thereby increasing the facing area between the second conductive portion U2 and the second auxiliary portion F2, thereby increasing the capacitance of the capacitor formed between the second conductive portion U2 and the second auxiliary portion F2, thereby further improving the stability of the control electrode g3 of the driving transistor T3 and enhancing the brightness uniformity of the display panel 100.

[0259] In some embodiments, as shown in FIG9 to FIG16 , the pixel driving circuit Q further includes a first light emitting control transistor T5 and a second light emitting control transistor T6 , and the first light emitting control transistor T5 and the second light emitting control transistor T6 are located on the same side of the driving transistor T3 .

[0260] Furthermore, the first emission control transistor T5 and the second emission control transistor T6 overlap along the first direction X. In other words, the first emission control transistor T5 and the second emission control transistor T6 are arranged side by side along the first direction X. The first emission control transistor T5 is closer to the first electrode s3 of the driving transistor T3 than the second emission control transistor T6, and the second emission control transistor T6 is closer to the second electrode d3 of the driving transistor T3 than the first emission control transistor T5.

[0261] Based on this, the distance between the first light-emitting control transistor T5 and the first electrode s3 of the driving transistor T3 can be shortened, as can the distance between the second light-emitting control transistor T6 and the second electrode d3 of the driving transistor T3. This facilitates connecting the second electrode d5 of the first light-emitting control transistor T5 to the first electrode s3 of the driving transistor T3, and connecting the first electrode s6 of the second light-emitting control transistor T6 to the second electrode d3 of the driving transistor T3.

[0262] In some embodiments, as shown in FIG. 9 to FIG. 16 , the first routing metal layer SD1 further includes a first enable signal line EM1 and a second enable signal line EM2 .

[0263] When the first emission control transistor T5 and the second emission control transistor T6 are located on the same side of the driving transistor T3, the first enable signal line EM1 electrically connected to the first emission control transistor T5 is located between the control electrodes g5 and g6 of the first emission control transistor T5 and the second emission control transistor T6, and the control electrode g3 of the driving transistor T3 along the second direction Y. That is, the first enable signal line EM1 is located on the side of the control electrodes g5 and g6 of the first emission control transistor T5 and the second emission control transistor T6 that is closer to the control electrode g3 of the driving transistor T3. Furthermore, the second enable signal line EM2 electrically connected to the second emission control transistor T6 is located on the side of the control electrodes g5 and g6 of the first emission control transistor T5 and the second emission control transistor T6 that is farther away from the control electrode g3 of the driving transistor T3.

[0264] In other words, one of the first enable signal line EM1 and the second enable signal line EM2 can be set on one side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6, and the other of the first enable signal line EM1 and the second enable signal line EM2 can be set on the other side of the control electrode g5 of the first light-emitting control transistor T5 and the control electrode g6 of the second light-emitting control transistor T6.

[0265] In this way, two enable signal lines can be used to drive two light-emitting control transistors respectively, and the space of the first wiring metal layer SD1 of the display panel can be fully utilized to increase the spacing between the first enable signal line EM1 and the second enable signal line EM2 to avoid the conductive components in the first wiring metal layer SD1 located between the first enable signal line EM1 and the second enable signal line EM2.

[0266] In some embodiments, as shown in conjunction with Figures 9 to 16 , the first enable signal line EM1 includes a first portion and a second portion. Along the second direction Y, the first portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g6 of the second emission control transistor T6, and the second portion is located between the control electrode g3 of the driving transistor T3 and the control electrode g5 of the first emission control transistor T5.

[0267] A first portion of the first enable signal line EM1 can be arranged closer to the control electrode g3 of the driving transistor T3 than a second portion of the first enable signal line EM1, and at the same time, this portion of the first enable signal line EM1 and the second light-emitting control transistor T6 can be enlarged to prevent the orthographic projection of the first enable signal line EM1 on the substrate from overlapping with the orthographic projection of the second light-emitting control transistor T6 on the substrate, so as to prevent the subsequent electrical connection between the second light-emitting control transistor T6 and the second reset transistor T7 from being affected.

[0268] In some embodiments, as shown in FIG. 9 to FIG. 16 , the second enable signal line EM2 further includes a second auxiliary portion F2 protruding toward the control electrode g6 of the second light emitting control transistor T6 , and the second auxiliary portion F2 extends along the second direction Y.

[0269] Based on this, the second auxiliary portion F2 can be used to move the second enable signal line EM away from the drive transistor T3. This can increase the distance between the second enable signal line EM2 and the first emission control transistor T5. This avoids the need for conductive components in the first routing metal layer SD1 between the first enable signal line EM1 and the second enable signal line EM2.

[0270] In some embodiments, in combination with Figures 9 to 14, on the basis of multiplexing the first scan signal line G1 as the second reset signal line R2: the control electrode of the second reset transistor T7 is electrically connected to the first scan signal line G1, and the control electrode g4 of the data write transistor T4 is also electrically connected to the first scan signal line G1.

[0271] Therefore, along the first direction X, the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7 overlap.

[0272] The first scanning signal line G1 can be electrically connected to the control electrode g4 of the data writing transistor T4 and the control electrode g7 of the second reset transistor T7. No bending portion or avoidance portion is required on the first scanning signal line G1, which can simplify the film layer structure layout of the pixel driving circuit Q.

[0273] In some embodiments, as shown in conjunction with Figures 9 to 14 , the semiconductor layer POLY includes a first electrode s1 of the drive transistor T3, a second electrode d5 of the first emission control transistor T5, and a second electrode d4 of the data write transistor T4. The semiconductor layer POLY also includes a third conductive portion U3, which electrically connects the first electrode s1 of the drive transistor T3, the second electrode d5 of the first emission control transistor T5, and the second electrode d4 of the data write transistor T4. That is, the third connecting portion L3 electrically connects the first electrode s1, the second electrode d5 of the first emission control transistor T5, and the second electrode d4 of the data write transistor T4 to the second node N2 (as shown in Figure 6).

[0274] The second gate metal layer Gate2 further includes a fourth conductive portion U4. One end of the fourth conductive portion U4 is electrically connected to the second plate Cst-2 of the storage capacitor Cst, and the other end of the fourth conductive portion U4 is electrically connected to the first electrode s5 of the first emission control transistor T5. Subsequently, the fourth conductive portion U4 is electrically connected to the first power signal line VDD, thereby electrically connecting the second plate Cst-2 of the storage capacitor Cst and the first electrode s5 of the first emission control transistor T5 to the first power signal line VDD.

[0275] Since the first plate C1 - 1 of the first capacitor C1 is electrically connected to the second node N2 , the second plate C1 - 2 of the first capacitor C1 is electrically connected to the first electrode s5 of the first light emission control transistor T5 .

[0276] Therefore, the orthographic projection of the fourth conductive portion U4 on the base substrate 10 is arranged to overlap with the orthographic projection of the third conductive portion U3 on the base substrate 10, so that the third conductive portion U3 is reused as the first plate C1-1 of the first capacitor C1, and the fourth conductive portion U4 is reused as the second plate C1-2 of the first capacitor C1.

[0277] Based on this, there is no need to separately manufacture the first electrode plate C1 - 1 and the second electrode plate C1 - 2 of the first capacitor C1 , which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100 .

[0278] In addition, since the fourth conductive portion U4 (the second plate C1-2 of the first capacitor C1) is electrically connected to the second plate Cst-2 of the storage capacitor Cst, it can be understood that the second plate C1-2 of the first capacitor C1 and the second plate Cst-2 of the storage capacitor Cst are integral. Furthermore, the size of the second plate Cst-2 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1. Thus, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data write transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the time for writing the data write signal can be further extended, which is beneficial for improving the display uniformity of the display panel.

[0279] In some examples, the fourth conductive portion U4 is disposed in the same layer as the second plate Cst- 2 of the storage capacitor Cst.

[0280] Based on this, the fourth conductive portion U4 and the second electrode plate Cst- 2 of the storage capacitor Cst can be formed by using one patterning process, which can simplify the manufacturing process of the pixel driving circuit Q.

[0281] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0282] In some embodiments, as shown in Figures 10 and 14 , the third conductive portion U3 is located near one side of the channel portion a5 of the first emission control transistor T5 and is connected to the channel portion a5 of the first emission control transistor T5. In other words, the third conductive portion U3 extends along the second direction Y to the position of the channel portion a5 of the first emission control transistor T5 and is connected to the channel portion a5 of the first emission control transistor T5.

[0283] Thus, the length of the third conductive portion U3 along the second direction Y can be increased. Furthermore, the size of the first electrode plate C1 - 1 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1 .

[0284] Based on this, the discharge time of the first capacitor C1 to the first node N1 can be increased after the data write transistor T4 is turned off and before the compensation transistor T2 is turned off. Therefore, the writing time of the data write signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0285] In some embodiments, as shown in Figures 10 and 14 , the third conductive portion U3 is located close to one side of the channel portion a3 of the driving transistor T3 and is connected to the channel portion a3 of the driving transistor T3. In other words, the third conductive portion U3 is extended to the position of the channel portion a3 of the driving transistor T3 and is connected to the channel portion a3 of the driving transistor T3, thereby increasing the size of the third conductive portion U3.

[0286] As a result, the size of the first plate C1-1 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased during the period between the turning off of the data write transistor T4 and the turning off of the compensation transistor T2. Consequently, the writing time of the data write signal can be further extended, which helps improve the display uniformity of the display panel.

[0287] In some embodiments, as shown in Figures 10 and 14 , the third conductive portion U3 is located close to one side of the channel portion a4 of the data write transistor T4 and is connected to the channel portion a4 of the data write transistor T4. In other words, the third conductive portion U3 is extended to the position of the channel portion a4 of the data write transistor T4 and connected to the channel portion a4 of the data write transistor T4, thereby increasing the size of the third conductive portion U3.

[0288] As a result, the size of the first plate C1-1 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased during the period between the turning off of the data write transistor T4 and the turning off of the compensation transistor T2. Consequently, the writing time of the data write signal can be further extended, which helps improve the display uniformity of the display panel.

[0289] In some embodiments, as shown in FIG. 10 and FIG. 14 , along the second direction Y, the third conductive portion U3 is away from a side of the channel portion a5 of the first light emission control transistor T5 and protrudes from the channel portion a5 of the driving transistor T3 .

[0290] This is equivalent to extending the third conductive portion U3 out of the channel portion a5 of the driving transistor T3 along the second direction Y, so as to maximize the length of the third conductive portion U3 within the space in the second direction Y of the semiconductor layer POLY.

[0291] As a result, the size of the first plate C1-1 of the first capacitor C1 can be increased, thereby increasing the capacitance of the first capacitor C1. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased during the period between the turning off of the data write transistor T4 and the turning off of the compensation transistor T2. Consequently, the writing time of the data write signal can be further extended, which helps improve the display uniformity of the display panel.

[0292] In some embodiments, as shown in Figures 13 and 14, the fourth conductive portion U4 includes a fourth auxiliary portion F4 that protrudes toward the control electrode g5 of the first emission control transistor T5. The orthographic projection of the fourth auxiliary portion F4 on the base substrate (as shown in Figure 3) at least partially overlaps with the second electrode d5 of the first emission control transistor T5.

[0293] This allows the size of the second plate C1-2 of the first capacitor C1 to be increased, thereby increasing the capacitance of the first capacitor C1. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased during the period between the shutdown of the data write transistor T4 and the shutdown of the compensation transistor T2. Consequently, the data write signal writing time can be further extended, which helps improve the display uniformity of the display panel.

[0294] In some embodiments, as shown in FIG9 , two adjacent pixel driving circuits Q are symmetrical along the first direction X. Exemplarily, along the first direction X, two adjacent pixel driving circuits Q are mirror-symmetrical.

[0295] Based on this, the regularity of the pixel driving circuit Q in the display panel 100 can be improved, which facilitates the simplification of the layout of the pixel driving circuit Q in the display panel 100 .

[0296] In some embodiments, as shown in FIG9 to FIG17 , when two adjacent pixel driving circuits Q are symmetrically arranged along the first direction X, the first electrode s3 of the driving transistor T3 of the n-th pixel driving circuit Q can be arranged adjacent to the first electrode s3 of the driving transistor T3 in the (n+1)-th pixel driving circuit Q along the first direction X. Wherein, n is a positive integer.

[0297] When the first electrodes s3 of the driving transistors T3 of two adjacent pixel driving circuits Q are adjacent to each other along the first direction X, the second electrode plate Cst-2 of the storage capacitor Cst located on the second gate metal layer Gate2 does not need to avoid the second electrode d3 of the driving transistor T3. The orthographic projection of the second electrode plate Cst-2 of the storage capacitor Cst on the base substrate 10 (as shown in FIG. 3 ) can cover the orthographic projection of the first electrode s3 of the driving transistor T3 on the base substrate 10.

[0298] As a result, the second plates Cst-2 of the storage capacitors Cst in two adjacent pixel driving circuits Q can be directly filled with the space between the second plates Cst-2 of the storage capacitors Cst in the two pixel driving circuits Q without having to consider the issue of avoidance. In other words, the horizontal space utilization of the driving circuit layer can be fully utilized, and the size of the second plate Cst-2 of the storage capacitor Cst can be increased, which is beneficial for increasing the capacitance of the storage capacitor Cst and the first capacitor C1.

[0299] In some examples, n=1 is used as an example for description. In the first direction X, the first electrode s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 of the second pixel driving circuit Q. Wherein, n is a positive integer.

[0300] Thus, the second electrode d3 of the driving transistor T3 of the first pixel driving circuit Q is located on a side of the first pixel driving circuit Q facing away from the second pixel driving circuit Q. Furthermore, the second electrode d3 of the driving transistor T3 in the second pixel driving circuit Q is located on a side of the second pixel driving circuit Q facing away from the first pixel driving circuit Q.

[0301] Based on this, the orthographic projection of the second plate Cst-2 of the storage capacitor Cst on the base substrate 10 (as shown in FIG. 3 ) can cover the orthographic projection of the first electrode s3 of the driving transistor T3 on the base substrate 10, and the second plate Cst-2 of the storage capacitor Cst does not need to avoid the second electrode d3 of the driving transistor T3. In other words, the second plate Cst-2 of the storage capacitor Cst can directly cover the space between the second electrodes d3 of the driving transistors T3 of the two pixel driving circuits Q, fully utilizing the horizontal space utilization of the driving circuit layer.

[0302] In some embodiments, as shown in FIG9 to FIG17 , when two adjacent pixel driving circuits Q are symmetrically arranged along the first direction X, the second plate Cst-2 of the storage capacitor Cst in the n-th pixel driving circuit Q can be electrically connected to the second plate Cst-2 of the storage capacitor Cst in the (n+1)-th pixel driving circuit Q. Wherein, n is a positive integer.

[0303] Based on this, the size of the second plate Cst-2 of the storage capacitor Cst in the pixel drive circuit Q can be increased. Consequently, the size of the second plate C1-2 of the first capacitor C1 can also be increased, thereby increasing the capacitance of the first capacitor C1. Furthermore, the discharge time of the first capacitor C1 to the first node N1 can be increased during the period between the shutdown of the data write transistor T4 and the shutdown of the compensation transistor T2. Consequently, the data write signal write time can be further extended, which helps improve the display uniformity of the display panel.

[0304] In some examples, n=1 is used as an example for description. In the first direction X, the first electrode s3 of the driving transistor T3 of the first pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 of the second pixel driving circuit Q. Wherein, n is a positive integer.

[0305] As a result, the second plate Cst-2 of the storage capacitor Cst of the first pixel driving circuit Q is electrically connected to the second plate Cst-2 of the storage capacitor Cst of the second pixel driving circuit Q. Furthermore, this is equivalent to providing a third conductive portion U3 corresponding to the first pixel driving circuit Q and connecting it to the third conductive portion U3 corresponding to the second pixel driving circuit Q.

[0306] Based on this, the size of the second plate Cst-2 of the storage capacitor Cst and the second plate C1-2 of the first capacitor C1 can be increased in the pixel driving circuit Q. Therefore, the writing time of the data writing signal can be further extended, which is beneficial to improving the display uniformity of the display panel.

[0307] In some embodiments, as shown in FIG9 to FIG17 , since the second reset transistor T7 and the second electrode d2 of the driving transistor T3 are respectively located on either side of the pixel driving circuit Q along the first direction X, on the basis that the first electrode s3 of the driving transistor T3 in the nth pixel driving circuit Q is adjacent to the first electrode s3 of the driving transistor T3 in the n+1th pixel driving circuit Q, the second reset transistor T7 in the n+1th pixel driving circuit Q can be arranged adjacent to the second reset transistor T7 in the n+2th pixel driving circuit Q, where n is a positive integer.

[0308] Furthermore, the first electrode s7 of the second reset transistor T7 in the (n+1)th pixel driving circuit Q may be arranged adjacent to the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q.

[0309] Based on this, the first initialization signal line Vinit1 can be electrically connected to the first electrode s7 of the second reset transistor T7 in the (n+1)th pixel driving circuit Q, and to the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q. There is no need to provide a bend or avoidance portion on the first initialization signal line Vinit1, thereby simplifying the film layer structure layout of the pixel driving circuit Q.

[0310] In some examples, the first electrode s7 of the second reset transistor T7 in the (n+1)th pixel driving circuit Q is multiplexed as the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q.

[0311] Based on this, there is no need to separately provide the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q, which can simplify the manufacturing process of the pixel driving circuit Q in the display panel 100. In addition, because the first electrode s7 of the second reset transistor T7 in the (n+1)th pixel driving circuit Q is directly reused as the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q, the first initialization signal line Vinit1 is directly electrically connected to the first electrode s7 of the second reset transistor T7 in the (n+1)th pixel driving circuit Q, and thus can be simultaneously electrically connected to the first electrode s7 of the second reset transistor T7 in the (n+2)th pixel driving circuit Q.

[0312] Therefore, the film structure of the pixel driving circuit Q can be simplified, which facilitates the simplification of the manufacturing process of the pixel driving circuit Q.

[0313] FIG18 is a diagram illustrating the film layer structures of multiple pixel driving circuits according to further embodiments, and FIG19 is a diagram illustrating the structure of the bottom shielding layer in FIG18 . The difference between the pixel driving circuit Q shown in FIG18 and the pixel driving circuit Q shown in FIG9 is that the display panel 100 further includes a bottom shielding layer 40 .

[0314] In some embodiments, as shown in Figures 18 and 19, the display panel 100 further includes a bottom shield metal (BSM) 40. The bottom shield metal 40 is located between the base substrate 10 (as shown in Figure 3) and the pixel driving circuit Q. The orthographic projection of the bottom shield metal 40 on the base substrate 10 covers the orthographic projection of the driving transistor T3 on the base substrate 10.

[0315] Based on this, the bottom shielding layer 40 can be used to shield the driving transistor T3 from static electricity. In addition, the bottom shielding layer 40 can also serve as a light shielding layer to reduce the impact of external light incident from the base substrate 10 on the semiconductor layer POLY, thereby improving the performance of the semiconductor layer POLY.

[0316] In some examples, the orthographic projection of the driving transistor T3 on the base substrate 10 is located within the boundary of the orthographic projection of the bottom shielding layer 40 on the base substrate 10 , so that the bottom shielding layer 40 can completely cover the driving transistor T3 to shield the driving transistor T3 from the influence of static electricity.

[0317] In some examples, the bottom shielding layer 40 is configured to receive a first power signal, thereby reducing static electricity accumulation on the bottom shielding layer 40 .

[0318] In addition, the two bottom shielding layers 40 corresponding to two adjacent pixel driving circuits Q can be electrically connected via a connecting portion, thereby reducing the impedance of the bottom shielding layer 40 .

[0319] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising a display area and a bonding area, wherein the bonding area is located on one side of the display area; the display area includes a middle area and two edge areas, and along a first direction, the middle area is located between the two edge areas; The display panel includes: a substrate; and, a driving circuit layer located on one side of the substrate; the driving circuit layer includes: a plurality of pixel driving circuits arranged in multiple rows and columns in the display area; the pixel driving circuit includes a driving transistor and a first reset transistor; The control electrode of the driving transistor is electrically connected to a first node, the first electrode of the driving transistor is electrically connected to a second node, and the second electrode of the driving transistor is electrically connected to a third node; The control electrode of the first reset transistor is electrically connected to a first reset signal line, the first electrode of the first reset transistor is electrically connected to a first initialization signal line, and the second electrode of the first reset transistor is electrically connected to the first node; a plurality of data writing signal lines located in the display area, and the plurality of data writing signal lines are arranged along the first direction and extend along a second direction, and the second direction intersects with the first direction; one data writing signal line is connected to one column of the pixel driving circuits; a plurality of data leads, the data leads include a first lead segment and a second lead segment, one end of the first lead segment is electrically connected to a data writing signal line located in the edge area, and the other end of the first lead segment is electrically connected to one end of the second lead segment; the first lead segment extends along the first direction, the second lead segment extends along the second direction, and the second lead segment extends from the middle area to the bonding area; Along the direction away from the substrate, the driving circuit layer includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer and a second routing metal layer; The semiconductor layer includes a first conductive portion, and the first conductive portion includes the second electrode of the first reset transistor; the second gate metal layer includes a first shielding portion configured to have a constant voltage signal; the first routing metal layer includes the first lead segment; the second routing metal layer includes the data writing signal line and the second lead segment; wherein, the orthographic projection of the first shielding portion on the substrate, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first lead segment on the substrate overlap.

2. The display panel according to claim 1, wherein, The second gate metal layer further includes the first initialization signal line, and the first reset signal line is connected to the first shielding portion.

3. The display panel according to claim 2, wherein, The first initialization signal line includes a first auxiliary portion protruding towards the first reset transistor, and the orthographic projection of the first auxiliary portion on the substrate, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the first lead segment on the substrate overlap; the first auxiliary portion is multiplexed as the first shielding portion.

4. The display panel according to any one of claims 1 to 3, wherein, The pixel driving circuit further includes: A compensation transistor, wherein a control electrode of the compensation transistor is electrically connected to a second scan signal line, a first pole of the compensation transistor is electrically connected to the third node, and a second pole of the compensation transistor is electrically connected to the first node; The compensation transistor is a double-gate transistor, and the control electrode of the compensation transistor includes a first control electrode and a second control electrode; The semiconductor layer further includes: a first channel portion of the compensation transistor, a second channel portion of the compensation transistor, and a second conductive portion, one end of the second conductive portion is connected to the first channel portion, and the other end of the second conductive portion is connected to the second channel portion; The first initialization signal line further includes a second auxiliary portion protruding toward the driving transistor, and a positive projection of the second auxiliary portion on the substrate at least partially overlaps with a positive projection of the second conductive portion on the substrate.

5. The display panel according to claim 4, wherein, A positive projection of the second conductive portion on the substrate is located within a boundary of a positive projection of the second auxiliary portion on the substrate.

6. The display panel according to claim 4 or 5, wherein, The second conductive portion includes a first sub-portion, a second sub-portion, and a third sub-portion, and the first sub-portion, the second sub-portion, and the third sub-portion intersect at the same point; wherein, the first sub-portion is electrically connected to the first channel portion, the second sub-portion is electrically connected to the second channel portion, and the third sub-portion is located on a side of the second sub-portion away from the second channel portion.

7. The display panel according to any one of claims 1 to 6, wherein, The pixel driving circuit further includes: A data writing transistor, wherein a control electrode of the data writing transistor is connected to a first scan signal line, a first pole of the data writing transistor is electrically connected to the data writing signal line, and a second pole of the data writing transistor is electrically connected to the second node; A second reset transistor, wherein a control electrode of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to a second initialization signal line, and a second pole of the second reset transistor is electrically connected to the fourth node; Along the first direction, the control electrodes of the data writing transistor and the second reset transistor overlap.

8. The display panel according to any one of claims 1 to 7, wherein, The pixel driving circuit further includes: A first light-emitting control transistor, wherein a control electrode of the first light-emitting control transistor is electrically connected to a first enable signal line, a first pole of the first light-emitting control transistor is electrically connected to a first power supply signal line, and a second pole of the first light-emitting control transistor is electrically connected to the second node; A second light-emitting control transistor, wherein a control electrode of the second light-emitting control transistor is electrically connected to a second enable signal line, a first pole of the second light-emitting control transistor is electrically connected to the third node, and a second pole of the second light-emitting control transistor is electrically connected to the fourth node.

9. The display panel according to any one of claims 1 to 8, wherein, The pixel driving circuit further includes: A storage capacitor, wherein a first electrode plate of the storage capacitor is electrically connected to the first node, and a second electrode plate of the storage capacitor is electrically connected to the first power supply signal line; A first capacitor, wherein a first electrode plate of the first capacitor is electrically connected to the second node, and a first electrode plate of the first capacitor is electrically connected to the first power supply signal line.

10. The display panel according to claim 9, wherein, The pixel driving circuit includes a data writing transistor and a first light-emitting control transistor; The semiconductor layer includes a third conductive portion, and the third conductive portion includes a first electrode of the driving transistor, a second electrode of the first light emission control transistor, and a second electrode of the data writing transistor; The second gate metal layer further includes a fourth conductive portion, one end of the fourth conductive portion is electrically connected to the second electrode of the storage capacitor, and the other end of the fourth conductive portion is electrically connected to the first electrode of the first light emission control transistor; The orthographic projection of the fourth conductive portion on the base substrate at least partially overlaps with the orthographic projection of the third conductive portion on the base substrate; The third conductive portion is multiplexed as the first plate of the first capacitor, and the fourth conductive portion is multiplexed as the second plate of the first capacitor.

11. The display panel according to claim 10, wherein, Along the second direction, the third conductive portion is away from a side of the channel portion of the first light emission control transistor and protrudes out of the channel portion of the driving transistor.

12. The display panel according to any one of claims 1 to 11, wherein, Along the first direction, two adjacent pixel driving circuits are symmetrical.

13. The display panel according to claim 12, wherein: Along the first direction, the first electrode of the driving transistor in the nth pixel driving circuit is adjacent to the first electrode of the driving transistor in the (n+1)th pixel driving circuit; wherein n is a positive integer.

14. The display panel according to claim 12 or 13, wherein The second plate of the storage capacitor of the nth pixel driving circuit is electrically connected to the second plate of the storage capacitor in the pixel driving circuit of the n+1th sub-pixel; wherein n is a positive integer.

15. The display panel according to any one of claims 12 to 14, wherein: Along the first direction, the second reset transistor in the n+1th pixel driving circuit is arranged adjacent to the second reset transistor in the n+2th pixel driving circuit, and the first electrode of the second reset transistor in the n+1th pixel driving circuit is reused as the first electrode of the second reset transistor in the n+2th pixel driving circuit.

16. The display panel according to any one of claims 1 to 15, wherein: The first routing metal layer further includes a plurality of first virtual lead segments, the first virtual lead segments correspond to the first lead segments one by one, and along the first direction, the first lead segments and the first virtual lead segments are arranged at intervals.

17. The display panel according to any one of claims 1 to 15, wherein: The second routing metal layer further includes a plurality of second virtual lead segments, the second virtual lead segments correspond to the second lead segments one by one, and along the first direction, the second lead segments and the second virtual lead segments are arranged at intervals.

18. The display panel according to any one of claims 1 to 17, further comprising a bottom shielding layer located between the base substrate and the pixel driving circuit, wherein the orthographic projection of the bottom shielding layer on the base substrate covers the orthographic projection of the driving transistor on the base substrate.

19. The display panel according to any one of claims 1 to 18, further comprising: The light-emitting device layer is located on the side of the driving circuit layer away from the substrate; the light-emitting device layer includes a plurality of light-emitting devices, and the light-emitting devices are electrically connected to the pixel driving circuit.

20. A display device, comprising the display panel according to any one of claims 1 to 19.

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