Display panel and control method therefor, and display apparatus

Abstract

A display panel, comprising a plurality of pixel circuits, a plurality of initialization voltage signal lines and a plurality of scan signal lines. The plurality of pixel circuits are arranged in a plurality of rows and columns. The plurality of initialization voltage signal lines are arranged at intervals along a first direction and extend in a second direction. One initialization voltage signal line is electrically connected to one column of pixel circuits, and any two initialization voltage signal lines are electrically insulated from each other. The plurality of scan signal lines are arranged at intervals in the second direction and extend in the first direction, and one scan signal line is electrically connected to one row of pixel circuits. Each pixel circuit is configured to transmit an initialization voltage signal from an initialization voltage signal line to a circuit node of the pixel circuit under the control of a scan signal from a scan signal line, so as to perform voltage initialization on the circuit node. The first direction is a row direction in which the plurality of pixel circuits are arranged, and the second direction is a column direction in which the plurality of pixel circuits are arranged.

Description

Display panel, control method thereof, and display device

[0001] This application claims priority to Chinese patent application No. 202410015872.9, filed on January 3, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel, a control method thereof, and a display device. Background Art

[0003] With the continuous development of display technology, organic light-emitting diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent performance, such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, fast response speed, flexibility, wide operating temperature range, and simple structure and process. OLED display panels are widely used in terminal products such as smartphones, tablets, TVs, and wearable devices (such as watches). Among them, the use of high refresh rates in parts of display panels is a key development direction. How to reduce the display differences between different areas caused by different refresh rates in different areas is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] On the one hand, a display panel is provided. The display panel includes a plurality of pixel circuits, a plurality of initialization voltage signal lines, and a plurality of scanning signal lines. The plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns. The plurality of initialization voltage signal lines are arranged at intervals along a first direction, and the plurality of initialization voltage signal lines all extend along a second direction. An initialization voltage signal line is electrically connected to a column of pixel circuits, and any two initialization voltage signal lines are electrically insulated from each other. The plurality of scanning signal lines are arranged at intervals along the second direction, and the plurality of scanning signal lines all extend along the first direction, and a scanning signal line is electrically connected to a row of pixel circuits. The pixel circuit is configured to transmit an initialization voltage signal from an initialization voltage signal line to a circuit node of the pixel circuit under the control of a scanning signal from a scanning signal line, thereby performing voltage initialization on the circuit node. The first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged.

[0005] In some embodiments, the multiple initialization voltage signal lines include multiple first initialization voltage signal lines, any two of the first initialization voltage signal lines are electrically insulated from each other, and a column of pixel circuits is electrically connected to one first initialization voltage signal line. The multiple scan signal lines include multiple first scan signal lines, one first scan signal line being electrically connected to a row of pixel circuits. The pixel circuit includes a drive transistor, a data write transistor, a compensation transistor, and a first reset transistor. The control electrode of the drive transistor is electrically connected to a first node, a first electrode is electrically connected to a second node, and a second electrode is electrically connected to a third node. The control electrode of the data write transistor is electrically connected to a first gate line, a first electrode is electrically connected to a data line, and a second electrode is electrically connected to the second node. The control electrode of the compensation transistor is electrically connected to a second gate line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to the first node. The control electrode of the first reset transistor is electrically connected to one of the first scan signal lines, a first electrode is electrically connected to one of the first initialization voltage signal lines, and a second electrode is electrically connected to the second node. The first reset transistor is configured to transmit the first initialization voltage signal from the first initialization voltage signal line to the second node under control of a first scan signal from the first scan signal line.

[0006] In some embodiments, the first initialization voltage signal line is configured to transmit first initialization voltage signals with different voltage values ​​in different time periods.

[0007] In some embodiments, the multiple initialization voltage signal lines further include multiple second initialization voltage signal lines, any two of which are electrically insulated from each other; and a column of pixel circuits is electrically connected to a second initialization voltage signal line. The multiple scan signal lines further include multiple second scan signal lines, with a second scan signal line electrically connected to a row of pixel circuits. The pixel circuit further includes a first emission control transistor and a second reset transistor. The control electrode of the first emission control transistor is electrically connected to the emission control signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node. The control electrode of the second reset transistor is electrically connected to a second scan signal line, the first electrode is electrically connected to a second initialization voltage signal line, and the second electrode is electrically connected to the fourth node. The second reset transistor is configured to transmit the second initialization voltage signal from the second initialization voltage signal line to the fourth node under control of the second scan signal from the second scan signal line.

[0008] In some embodiments, the second initialization voltage signal line is configured to transmit second initialization voltage signals with different voltage values ​​in different time periods.

[0009] In some embodiments, the first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are configured to transmit the same scan signal, and the first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are the same signal line.

[0010] In some embodiments, the first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are configured to transmit different scan signals, and the first scan signal line and the second scan signal line are different signal lines.

[0011] In some embodiments, the pixel circuit further includes: a second light emission control transistor, a third reset transistor, and a storage capacitor. The second light emission control transistor has a control electrode electrically connected to the light emission control signal line, a first electrode electrically connected to the first voltage signal line, and a second electrode electrically connected to the second node. The third reset transistor has a control electrode electrically connected to the third gate line, a first electrode electrically connected to the second voltage signal line, and a second electrode electrically connected to the first node. One plate of the storage capacitor is electrically connected to the first voltage signal line, and the other plate is electrically connected to the first node.

[0012] In some embodiments, the pixel circuit further includes a second emission control transistor, a third reset transistor, and a storage capacitor. The second emission control transistor has a control electrode electrically connected to the emission control signal line, a first electrode electrically connected to the first voltage signal line, and a second electrode electrically connected to the second node. The third reset transistor has a control electrode electrically connected to the third gate line, a first electrode electrically connected to the second voltage signal line, and a second electrode electrically connected to the second node. One plate of the storage capacitor is electrically connected to the first voltage signal line, and the other plate is electrically connected to the first node.

[0013] In some embodiments, the second voltage signal line includes a plurality of first sub-lines, the plurality of first sub-lines being arranged at intervals along the first direction and extending along the second direction, one first sub-line being electrically connected to the third reset transistor of a column of pixel circuits, and any two first sub-lines being electrically insulated from each other. Alternatively, the second voltage signal line includes a plurality of second sub-lines, the plurality of second sub-lines being arranged at intervals along the second direction and extending along the first direction, one second sub-line being electrically connected to the third reset transistor of a row of pixel circuits, and any two second sub-lines being electrically insulated from each other. Alternatively, the second voltage signal line includes a plurality of first sub-lines and a plurality of second sub-lines, the plurality of first sub-lines being arranged at intervals along the first direction and extending along the second direction, the plurality of second sub-lines being arranged at intervals along the second direction and extending along the first direction, the plurality of first sub-lines being electrically connected to the plurality of second sub-lines, and the first electrode of the third reset transistor being electrically connected to the first sub-line or the second sub-line.

[0014] In some embodiments, the display panel includes a first display mode. In the first display mode, the plurality of pixel circuits include at least one first pixel circuit and at least one second pixel circuit. The refresh frequency of the first pixel circuit is greater than the refresh frequency of the second pixel circuit. The voltage value of the initialization voltage signal transmitted by the plurality of initialization voltage signal lines to the first pixel circuit is a first voltage, and the voltage value of the initialization voltage signal transmitted to the second pixel circuit is a second voltage. The first voltage is less than the second voltage.

[0015] In another aspect, a method for controlling a display panel is provided, for controlling the display panel described in any of the above embodiments. The display panel includes a first display mode. In the first display mode, the display panel includes a plurality of first pixel circuits and a plurality of second pixel circuits, and the refresh frequency of the plurality of first pixel circuits is greater than the refresh frequency of the plurality of second pixel circuits. The control method includes: a plurality of scanning signal lines controlling a plurality of initialization voltage signal lines, transmitting an initialization voltage signal having a first voltage value to the plurality of first pixel circuits, and transmitting an initialization voltage signal having a second voltage value to the second pixel circuits. The first voltage is less than the second voltage.

[0016] In some embodiments, the plurality of initialization voltage signal lines include at least one target initialization voltage signal line, the target initialization voltage signal line being electrically connected to at least one second pixel circuit. The control method further comprises: when the target initialization voltage signal line transmits an initialization voltage signal to the second pixel circuit under the control of the scan signal line, the initialization voltage signal transmits a second voltage. When the initialization voltage signal transmits an initialization voltage signal to the first pixel circuit under the control of the scan signal line, the target initialization voltage signal line transmits a first voltage.

[0017] In some embodiments, the multiple initialization voltage signal lines include multiple first initialization voltage signal lines, the multiple scan signal lines include multiple first scan signal lines; the pixel circuit includes a driving transistor, a data writing transistor, a compensation transistor, and a first reset transistor. A frame period includes a data writing phase and a second reset phase located after the data writing phase. The control method further includes: during the data writing phase, the data writing transistor and the compensation transistor of the first pixel circuit transmit the compensated data signal to the first node, and the data writing transistor and the compensation transistor of the second pixel circuit are both in the off state. During the second reset phase, the first reset transistor of the first pixel circuit transmits a first initialization voltage signal of a first voltage to the second node, and the first reset transistor of the second pixel circuit transmits a first initialization voltage signal of a second voltage to the second node.

[0018] In some embodiments, the plurality of initialization voltage signal lines further include a plurality of second initialization voltage signal lines, the plurality of scan signal lines further include a plurality of second scan signal lines, and the pixel circuit further includes a first light emission control transistor and a second reset transistor. The control method further includes, during the second reset phase, the second reset transistor of the first pixel circuit transmitting a second initialization voltage signal having a third voltage value to a fourth node, and the first reset transistor of the second pixel circuit transmitting a second initialization voltage signal having a fourth voltage value to the fourth node. The third voltage is less than the fourth voltage.

[0019] In some embodiments, the pixel circuit further includes a second light emission control transistor, a third reset transistor, and a storage capacitor. A frame period further includes a first reset phase preceding the data writing phase. The control method further includes: during the first reset phase, the third reset transistor of the first pixel circuit transmits a second voltage signal to the first node; and the third reset transistor of the second pixel circuit is in a stopped state.

[0020] In another aspect, a display device is provided. The display device includes a driver circuit board and a display panel according to any of the above embodiments. The driver circuit board is electrically connected to the display panel and configured to transmit a control signal to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0022] FIG1 is a structural diagram of a display device according to some embodiments;

[0023] FIG2 is a block diagram of a display device according to some embodiments;

[0024] FIG3 is a schematic structural diagram of a display panel according to some embodiments;

[0025] FIG4A is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0026] FIG4B is another equivalent circuit diagram of a pixel circuit according to some embodiments;

[0027] FIG5A is a control timing diagram of a pixel circuit according to some embodiments;

[0028] FIG5B is another control timing diagram of a pixel circuit according to some embodiments;

[0029] FIG6 is another schematic structural diagram of a display panel according to some embodiments;

[0030] FIG7 is a schematic diagram of another structure of a display panel according to some embodiments;

[0031] FIG8 is another structural schematic diagram of a display panel according to some embodiments;

[0032] FIG9 is a schematic diagram of another structure of a display panel according to some embodiments;

[0033] FIG10 is a schematic diagram of another structure of a display panel according to some embodiments;

[0034] FIG11 is another structural schematic diagram of a display panel according to some embodiments;

[0035] FIG12 is another structural schematic diagram of a display panel according to some embodiments;

[0036] FIG. 13 is a timing diagram of voltage signals transmitted by a first initialization voltage signal line and a second initialization voltage signal line according to some embodiments. DETAILED DESCRIPTION

[0037] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] The transistors used in the pixel circuits provided in the embodiments of the present disclosure may be thin film transistors (TFTs), metal oxide semiconductors (MOSs), or other switching devices with the same characteristics. The transistors in the embodiments of the present disclosure are described using thin film transistors as an example. The thin film transistors may be P-type transistors or N-type transistors. P-type transistors are turned on by a low voltage level and turned off by a high voltage level; N-type transistors are turned on by a high voltage level and turned off by a low voltage level.

[0051] The control electrode of each thin-film transistor used in the pixel circuit is the gate of the thin-film transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally the same. In other words, the first electrode and the second electrode of the thin-film transistor in the embodiments of the present disclosure can be structurally the same. For example, the first electrode of the thin-film transistor is the source, and the second electrode is the drain.

[0052] The various circuit nodes in the pixel circuit, such as the first node, the second node, etc., do not represent actual components, but represent the confluence points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the confluence points of related electrical connections in the circuit diagram.

[0053] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0054] For example, the display device 1000 may be a mobile phone, a wireless device, a personal digital assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, an automotive display (e.g., an odometer display), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, packaging, and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. For example, as shown in FIG1 , the display device 1000 may be a mobile phone.

[0055] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED), etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The following takes an organic light-emitting diode display device that is rectangular and flat as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display devices may also be considered as long as the same technical ideas are applied.

[0056] Referring to Figure 2, in some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor voltage divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed one by one in the embodiments of the present disclosure. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0057] Continuing with FIG. 2 , the display panel 1100 includes a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. For example, the peripheral area BB surrounds the display area AA. The display area AA is the area on the display panel 1100 used to display images. The display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used to display images. The peripheral area BB can be used, for example, to configure a gate driver on array (GOA) circuit and control signal lines (such as clock signal lines and power supply voltage signal lines). Of course, the functions of the peripheral area BB are not limited thereto, and non-disclosed embodiments will not be described in detail here.

[0058] The multiple sub-pixels P can emit light of different colors. For example, the multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, so that the display panel can achieve color display. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted.

[0059] In some embodiments, with the development of display technology, display panels 1100 with variable refresh rates and display panels 1100 with local high refresh rates have received increasing attention. Display panels 1100 with variable refresh rates can change their refresh rates based on display needs. For example, when displaying a still image, the refresh rate of the display panel 1100 can be reduced to reduce power consumption. When displaying dynamic images, the refresh rate of the display panel 1100 can be increased to improve the display quality of the display panel.

[0060] A display panel using a local high refresh rate may include at least two display areas with different refresh rates. For example, the display panel may include a first display mode. In the first display mode, the display panel includes a first display area and a second display area. The refresh rate of the sub-pixels P in the first display area may be, for example, a first refresh rate, and the refresh rate of the sub-pixels P in the second display area may be, for example, a second refresh rate. The areas of the first display area and the second display area in the display panel may be arbitrarily selected and divided as needed, and the refresh rates of the first display area and the second display area may also be adjusted according to actual needs. This is not specifically limited in the embodiments of the present disclosure.

[0061] For example, the first refresh rate is greater than the second refresh rate, and the first refresh rate can be, for example, 120 Hz, and the second refresh rate can be, for example, 1 Hz. In this way, dynamic images can be displayed in the first display area, and static images can be displayed in the second display area. Compared to displaying images at a high refresh rate for all sub-pixels P, a local high refresh rate can significantly reduce the power consumption of the display panel. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted.

[0062] It is understood that the display panel 1100 may also include other display modes. For example, the display panel 1100 may also include a second display mode. In the second display mode, the refresh rates of the display areas of the display panel 1100 may be the same, that is, the entire display panel 1100 displays at the same refresh rate. Of course, the embodiments of the present disclosure are not limited thereto, and the display mode of the display panel 1100 may be flexibly set as required.

[0063] Each sub-pixel P includes a pixel circuit 100 and a light-emitting device 200. The multiple pixel circuits 100 included in the multiple sub-pixels P can be arranged into multiple rows and columns. The multiple rows of pixel circuits 100 are arranged along a first direction Y, and the multiple rows of pixel circuits 100 each include multiple pixel circuits 100 arranged along a second direction X, where the first direction Y intersects with the second direction X. The multiple columns of pixel circuits 100 are arranged along the second direction X, and the multiple columns of pixel circuits 100 each include multiple pixel circuits 100 arranged along the first direction Y. A row of pixel circuits 100 may include multiple pixel circuits 100 arranged along the second direction X, and a column of pixel circuits 100 may include multiple pixel circuits arranged along the first direction Y. The first direction X is the row direction in which the multiple pixel circuits 100 are arranged, and the second direction Y is the column direction in which the multiple pixel circuits 100 are arranged. The first direction Y intersects with the second direction X. Exemplarily, the first direction Y is perpendicular to the second direction X.

[0064] The pixel circuit 100 includes a plurality of thin film transistors (TFT) and at least one capacitor Cst, and the plurality of thin film transistors include at least a driving transistor. The pixel circuit 100 can be used to drive the light-emitting device 200 to emit light. For example, the pixel circuit 100 can be a "7T2C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits can also be considered as long as the same technical ideas are applied. Among them, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0065] After the pixel circuit 100 has been operating for a period of time, the characteristics of the driving transistor may shift. That is, the driving transistor may exhibit hysteresis after operating for a certain period of time. This hysteresis may cause the sub-pixel P to have problems such as short-term afterimages and decreased response speed.

[0066] Some pixel circuits disclosed in the related art, by adding a reset transistor, reset the drive transistor (gate and / or source) to reduce the hysteresis problem of the drive transistor. However, for sub-pixels with different refresh rates, the hysteresis degree of the drive transistor (the degree of characteristic deviation of the drive transistor) is not consistent. For example, for sub-pixels with relatively low refresh rates, the drive transistor of its pixel circuit is in the same bias state (the voltage difference Vgs between the gate and source of the drive transistor) for a longer time, and the hysteresis degree of the drive transistor will be more serious. For sub-pixels with relatively high refresh rates, the drive transistor of its pixel circuit is reset more times in the same time (it can be reset at least once in each frame), and the bias state of the drive transistor may be inconsistent in different display frames, so the hysteresis degree of its drive transistor may be relatively mild. Due to the inconsistent hysteresis degree of sub-pixels with different refresh rates, the brightness and chromaticity displayed by sub-pixels with different refresh rates when displaying the same grayscale will be different. That is, the display panel may have a split-screen problem, where different brightness and chromaticity are displayed when the same grayscale is required in areas with different refresh rates. Furthermore, for sub-pixels with different refresh frequencies, leakage currents of circuit nodes of pixel circuits are also different. The difference in leakage currents may also adversely affect the split-screen display problem of the display panel.

[0067] In order to solve the above technical problems, referring to FIG3 , the display panel 1100 provided in an embodiment of the present disclosure further includes a plurality of initialization voltage signal lines Vinit and a plurality of scanning signal lines GL. The plurality of scanning signal lines GL are arranged at intervals along the second direction Y and all extend along the first direction X. One scanning signal line GL is electrically connected to a row of pixel circuits 100. The scanning signal line GL can be used to control the conduction or cutoff of the thin film transistors of the pixel circuits 100 electrically connected to the scanning signal lines GL. The plurality of initialization voltage signal lines Vinit are arranged at intervals along the first direction X and all extend along the second direction Y. One initialization voltage signal line Vinit is electrically connected to a column of pixel circuits 100, and any two initialization voltage signal lines Vinit are electrically insulated from each other. In other words, one initialization voltage signal line Vinit is only used to transmit the initialization voltage signal to a column of pixel circuits 100 electrically connected to the initialization voltage signal line Vinit. The pixel circuit 100 is configured to transmit an initialization voltage signal from an initialization voltage signal line Vinit to a circuit node of the pixel circuit 100 under the control of a scan signal from a scan signal line GL, thereby resetting (initializing) the voltage of the circuit node of the pixel circuit 100. For example, different initialization voltage signal lines Vinit can transmit initialization voltage signals with different voltage values, and can cooperate with the scan signal line GL to transmit initialization voltage signals with different voltage values ​​to different circuit nodes of the pixel circuit 100. Based on this, initialization voltage signals with different voltage values ​​can be transmitted to the pixel circuits 100 of sub-pixels P with different refresh frequencies, so that the pixel circuits 100 with different refresh frequencies can receive initialization voltage signals with different voltage values, and then reset the driving transistors with different hysteresis degrees with different voltage values. In other words, the driving transistors with different refresh frequencies can be repaired to different degrees, thereby reducing the display split-screen problem of the display panel 1100 caused by different refresh frequencies and different hysteresis degrees of the driving transistors, improving the display uniformity of sub-pixels with different refresh frequencies of the display panel 1100 in the local high refresh frequency display scenario, and improving the display quality of the display panel 1100.

[0068] The plurality of scanning signal lines GL progressively scan the plurality of rows of pixel circuits 100 along the second direction Y. When one scanning signal line GL transmits a scanning signal, if a row of pixel circuits 100 electrically connected to the scanning signal line GL includes pixel circuits 100 with a first refresh rate (a first pixel circuit) and pixel circuits 100 with a second refresh rate (a second pixel circuit), the initialization voltage signal line Vinit electrically connected to the first pixel circuit and the initialization voltage signal line Vinit electrically connected to the second pixel circuit transmit initialization voltage signals of different voltage values. In other words, different initialization voltage signal lines Vinit can transmit different voltage signals at the same time.

[0069] For the same column of pixel circuits 100, if there are both a first pixel circuit and a second pixel circuit, the initialization voltage signal line Vinit electrically connected to the column of pixel circuits 100 can transmit a voltage value of V when the scanning signal line GL electrically connected to the first pixel circuit transmits a scanning signal. 01 When the scanning signal line GL is electrically connected to the second pixel circuit to transmit the scanning signal, the initialization voltage signal line Vinit can transmit a voltage value of V 02 Initialization voltage signal, where V 01 and V 02 That is, the same initialization voltage signal line Vinit can transmit initialization voltage signals with different voltage values ​​in different time periods.

[0070] For example, the pixel circuit 100 included in the sub-pixel P with a higher refresh frequency is a first pixel circuit. The hysteresis degree of the driving transistor of the first pixel circuit is relatively small. Therefore, an initialization voltage signal with a smaller voltage value (absolute value of voltage) can be applied to the driving transistor P of the first pixel circuit with a higher refresh frequency. Conversely, the pixel circuit 100 included in the sub-pixel P with a lower refresh frequency is a second pixel circuit. The driving transistor of the second pixel circuit has a greater hysteresis degree due to being in the same bias state for a long time. Therefore, an initialization voltage signal with a larger voltage value (absolute value of voltage) can be applied to the driving transistor of the second pixel circuit with a lower refresh frequency so that the initialization voltage signal can better (to a greater extent) repair the hysteresis problem of the driving transistor. The hysteresis degree of the driving transistor after the repair is balanced, which is beneficial to the display uniformity of the display panel 1100.

[0071] Furthermore, before the display stage, initialization voltage signals with different voltage values ​​can be transmitted to the circuit nodes of the first pixel circuit and the second pixel circuit respectively to reduce the impact of different leakage currents of the circuit nodes of the first pixel circuit and the second pixel circuit on display uniformity.

[0072] In some embodiments, the plurality of scan signal lines GL include a plurality of first scan signal lines GL1 and a plurality of second scan signal lines GL2, one first scan signal line GL1 is electrically connected to a row of pixel circuits 100, and one second scan signal line GL2 is electrically connected to a row of pixel circuits 100. The plurality of initialization voltage signal lines Vinit include a plurality of first initialization voltage signal lines Vinit1 and a plurality of second initialization voltage signal lines Vinit2.

[0073] 4A and 4B , an embodiment of the present disclosure provides an "8T1C" pixel circuit 100, i.e., the pixel circuit 100 includes eight thin-film transistors and one capacitor. Specifically, the pixel circuit 100 may include a drive transistor DT, a first reset transistor T1, a second reset transistor T2, a third reset transistor T3, a data write transistor T4, a compensation transistor T5, a first emission control transistor T6, a second emission control transistor T7, and a storage capacitor Cst. A first scan signal line GL1 may be electrically connected to the first reset transistors T1 of a row of pixel circuits 100. A second scan signal line GL2 may be electrically connected to the second reset transistors T2 of a row of pixel circuits 100. A first initialization voltage signal line Vinit1 may be electrically connected to the first reset transistors T1 of a column of pixel circuits 100. A second initialization voltage signal line Vinit2 may be electrically connected to the second reset transistors T2 of a column of pixel circuits 100.

[0074] Among them, the first initialization voltage signal line Vinit1 is configured to transmit first initialization voltage signals with different voltage values ​​in different time periods. In this way, in the first display mode, the first initialization voltage signal line Vinit1 can transmit first initialization voltage signals with different voltage values ​​to different pixel circuits 100 in a column of pixel circuits 100, that is, the first initialization voltage signal line Vinit1 can transmit first initialization voltage signals with different voltage values ​​to different pixel circuits.

[0075] The second initialization voltage signal line Vinit2 is configured to transmit second initialization voltage signals with different voltage values ​​in different time periods. In this way, in the first display mode, the second initialization voltage signal line Vinit2 can transmit second initialization voltage signals with different voltage values ​​to different pixel circuits 100 in a column of pixel circuits 100. That is, the second initialization voltage signal line Vinit2 can transmit second initialization voltage signals with different voltage values ​​to different pixel circuits.

[0076] It should be noted that when the display panel is in other display modes, for example, when the refresh frequencies of all sub-pixels of the display panel are the same, the first initialization voltage signal line Vinit1 can also transmit a first initialization voltage signal with the same voltage value, and the second initialization voltage signal line Vinit2 can also transmit a second initialization voltage signal with the same voltage value.

[0077] The control electrode of the driving transistor DT is electrically connected to the first node N1, the first electrode (e.g., the source electrode) is electrically connected to the second node N2, and the second electrode (e.g., the drain electrode) is electrically connected to the third node N3. The driving transistor DT is configured to generate a driving current under the control of a voltage difference Vgs between the gate and source electrodes of the driving transistor DT. As shown in FIG4A or FIG4B , when the driving transistor DT is a P-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the second node N2. In this case, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the second node N2, and drives the light-emitting device 200 to emit light according to the driving current. Of course, when the driving transistor DT is an N-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the third node N3. In other words, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the third node N3, and drives the light-emitting device 200 to emit light according to the driving current.

[0078] The data write transistor T4 has a control electrode electrically connected to the first gate line G1, a first electrode electrically connected to the data line DL, and a second electrode electrically connected to the second node N2. The data write transistor T4 is configured to be turned on under the control of a first control signal from the first gate line G1 to transmit the data signal Data from the data line DL to the second node N2.

[0079] The compensation transistor T5 has a control electrode electrically connected to the second gate line G2, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the first node N1. The compensation transistor T5 is configured to be turned on under the control of a second control signal from the second gate line G2, thereby conducting the connection between the first node N1 and the third node N3.

[0080] The first emission control transistor T6 has a control electrode electrically connected to the emission control signal line EM (in some cases, the emission control signal line EM may also be referred to as an enable signal line, etc.), a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the fourth node N4. The first emission control transistor T6 is configured to be turned on under the control of a light emission control signal from the emission control signal line EM, thereby conducting a connection between the third node N3 and the fourth node N4. The fourth node N4 is configured to be electrically connected to the light-emitting device 200. The second emission control transistor T7 has a control electrode electrically connected to the emission control signal line EM, a first electrode electrically connected to the first voltage signal line VDD, and a second electrode electrically connected to the second node N2. The second emission control transistor T7 is configured to transmit a first voltage signal Vdd from the first voltage signal line VDD to the second node N2 under the control of the emission control signal from the emission control signal line EM. The first and second emission control transistors T6 and T7 are configured to be turned on during the display phase to transmit the drive current generated by the drive transistor DT to the light-emitting device 200, thereby driving the light-emitting device 200 to emit light.

[0081] The control stage of the first reset transistor T1 is electrically connected to the first scan signal line GL1, the first electrode is electrically connected to the first initialization voltage signal line Vinit1, and the second electrode is electrically connected to the second node N2. The first reset transistor T1 is configured to transmit the initialization voltage signal from the first initialization voltage signal line Vinit1 to the second node N2 under the control of the first scan signal from the first scan signal line GL1, thereby resetting (initializing) the voltage of the second node N2.

[0082] The control electrode of the second reset transistor T2 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the second initialization voltage signal line Vinit2, and the second electrode is electrically connected to the fourth node N4. The second reset transistor T2 is configured to transmit the initialization voltage signal from the second initialization voltage signal line Vinit2 to the fourth node N4 under the control of the second scan signal from the second scan signal line GL2, so as to reset the voltage of the fourth node N2.

[0083] In some embodiments, as shown in Figure 4A, the control electrode of the third reset transistor T3 is electrically connected to the third gate line G3, the first electrode is electrically connected to the second voltage signal line VX, and the second electrode is electrically connected to the first node N1. The third reset transistor T3 is configured to be turned on under the control of a third control signal from the third gate line G3, and transmits the second voltage signal from the second voltage signal line VX to the first node N1 to reset the voltage of the first node N1.

[0084] As shown in FIG4A , when the second electrode of the third reset transistor T3 is electrically connected to the first node N1, the compensation transistor T5 and the third reset transistor T3 can be N-type transistors. Furthermore, the compensation transistor T5 and the third reset transistor T3 can be oxide thin-film transistors. In other words, the compensation transistor T5 and the third reset transistor T3 can be N-type oxide thin-film transistors. N-type oxide thin-film transistors have a relatively low leakage current, which can reduce the leakage current of the first node N1, thereby reducing the leakage of the first node N1 through the compensation transistor T5 and the third reset transistor T3 during the light-emitting phase. At the same time, the driving transistor DT, the first reset transistor T1, the second reset transistor T2, the data writing transistor T4, the first emission control transistor T6, and the second emission control transistor T7 can all be P-type transistors, and the driving transistor DT, the first reset transistor T1, the second reset transistor T2, the data writing transistor T4, the first emission control transistor T6, and the second emission control transistor T7 can all be low-temperature polysilicon thin-film transistors. In other words, the driving transistor DT, the first reset transistor T1, the second reset transistor T2, the data writing transistor T4, the first emission control transistor T6, and the second emission control transistor T7 can all be P-type low-temperature polysilicon thin-film transistors. P-type low-temperature polysilicon thin-film transistors have high carrier mobility, which is conducive to achieving a display panel 1100 with high resolution, high response speed, and high aperture ratio.

[0085] In other embodiments, as shown in Figure 4B, the control electrode of the third reset transistor T3 is electrically connected to the third gate line G3, the first electrode is electrically connected to the second voltage signal line VX, and the second electrode can also be electrically connected to the third node N3. The third reset transistor T3 is configured to be turned on under the control of the third control signal from the third gate line G3, and transmits the second voltage signal from the second voltage signal line VX to the third node N3 to reset the voltage of the first node N3.

[0086] Referring to FIG. 4B , when the second electrode of the third reset transistor T3 is electrically connected to the third node N3, the third reset transistor T3 may be an N-type oxide thin-film transistor, which can reduce leakage current of the third reset transistor T3 and, in turn, reduce leakage current from the first node N1 through the third reset transistor T3 during the light-emitting phase. Furthermore, the drive transistor DT, the first reset transistor T1, the second reset transistor T2, the data write transistor T4, the compensation transistor T5, the first emission control transistor T6, and the second emission control transistor T7 may all be P-type low-temperature polysilicon thin-film transistors. P-type low-temperature polysilicon thin-film transistors have high carrier mobility, which facilitates achieving high resolution, high response speed, and a high aperture ratio for the display panel 1100.

[0087] One plate of the storage capacitor Cst is electrically connected to the first node N1 , and the other plate is electrically connected to the first voltage signal line VDD. The storage capacitor Cst is configured to maintain the voltage of the first node N1 .

[0088] In some embodiments, as shown in FIG4A , the first scan signal line GL1 and the second scan signal line GL2 electrically connected to the same row of pixel circuits 100 are configured to transmit the same scan signal. Thus, the first scan signal line GL1 and the second scan signal line GL2 electrically connected to the same row of pixel circuits 100 are the same signal line. This reduces the number of gate drive circuits required for the display panel, which helps reduce the border width of the display panel 1100, simplifies the structure of the display panel 1100, reduces the manufacturing cost of the display panel 1100, and simplifies the control method for the pixel circuits 100.

[0089] Of course, in other embodiments, as shown in FIG4B , the first scan signal line GL1 and the second scan signal line GL2 electrically connected to the same row of pixel circuits 100 are configured to transmit different scan signals. Thus, the first scan signal line GL1 and the second scan signal line GL2 are different signal lines. Based on this, the first reset transistor T1 and the second reset transistor T2 can be independently controlled. In other words, the first reset transistor T1 and the second reset transistor T2 can be the same or different, which helps to improve the control flexibility of the pixel circuit 100.

[0090] It is understood that whether the first scan signal line GL1 and the second scan signal line GL2 are the same signal line has no necessary relationship to the circuit node to which the second electrode of the third reset transistor T3 is connected. In other words, regardless of whether the third reset transistor T3 is electrically connected to the third node N3 or the first node N1, the first scan signal line GL1 and the second scan signal line GL2 can be the same signal line or different signal lines.

[0091] Some embodiments of the present disclosure also provide a control method for a display panel 1100. It is understandable that, when the display panel 1100 is in the first display mode, if the first pixel circuit and the second pixel circuit are both in the refresh frame, the control method of the first pixel circuit and the second pixel circuit are the same. However, if the first pixel circuit is in the refresh frame and the second pixel circuit is in the hold frame, there are certain differences between the control method of the first pixel circuit and the control method of the second pixel circuit. Below, the control method of the pixel circuit is exemplarily described by taking the first pixel circuit in the refresh frame and the second pixel circuit in the hold frame as an example. Of course, when the second pixel circuit is also in the refresh frame, the control method of the second pixel circuit has reference to the control method of the first pixel circuit, and the embodiments of the present disclosure will not be repeated here. Among them, a frame period may include a first reset phase D1, a data write phase D2, a second reset phase D3 and a light emitting phase D4 which are arranged in sequence.

[0092] In some embodiments, when the first scanning signal line GL1 and the second scanning signal line GL2 connected to the same row of pixel circuits 100 are the same signal line, and the pixel circuits 100 adopt the connection method shown in FIG4A (the second electrode of the third reset transistor T3 is electrically connected to the first node N1), the control method of the display panel 1100 includes:

[0093] In the first reset phase D1, referring to FIG5A , for the first pixel circuit, the third gate line G3 transmits a third control signal. Under the control of the third control signal, the third reset transistor T3 of the first pixel circuit is turned on. The third reset transistor T3 transmits the second voltage signal from the second voltage signal line VX to the first node N1, resetting the voltage at the first node N1. The voltage difference (Vgs) between the gate (first node N1) and source (second node N2) of the drive transistor DT is greater than the threshold voltage Vth of the drive transistor DT, where Vgs = the voltage at the first node N1 - the voltage at the second node N2. At this point, the drive transistor DT is turned on.

[0094] In the first reset phase D1, for the second pixel circuit, since the second pixel circuit is in a hold frame, the third gate line G3 connected to the second pixel circuit does not transmit the third control signal, and the third reset transistor T3 of the second pixel circuit is in an off state. The voltage of the first node N1 remains unchanged (not shown in the figure).

[0095] In the data writing phase D2, referring to FIG5A , for the first pixel circuit, the first gate line G1 transmits a first control signal, and the second gate line G2 transmits a second control signal. The data writing transistor T4 is turned on under the control of the first control signal, and the compensation transistor T5 is turned on under the control of the second control signal. The data writing transistor T4 transmits the data signal Data transmitted by the data line DL to the second node N2. The driving transistor DT is in the on state and drains power from the second node N2 to the third node N3 until the voltage at the third node N3 reaches Data-Vth. Furthermore, the compensation transistor T5 transmits the voltage (Data-Vth) at the third node N3 to the first node N1.

[0096] In the data writing phase D2, for the second pixel circuit, because the second pixel circuit is in a hold frame, the first gate line G1 and the second gate line G2 electrically connected to the second pixel circuit do not transmit corresponding control signals, and the data writing transistor T4 and the compensation transistor T5 of the second pixel circuit are both in the off state. The voltages of the first node N1, the second node N2, and the third node N3 remain unchanged.

[0097] In the second reset phase D3, for the first pixel circuit, the first scan signal line GL1 transmits a first scan signal, and the first reset transistor T1 and the second reset transistor T2 are turned on under the control of the first scan signal. The first reset transistor T1 transmits the first initialization voltage signal transmitted by the first initialization voltage signal line Vinit1 to the second node N2, thereby initializing the voltage of the second node N2. The second reset transistor T2 transmits the second initialization voltage signal from the second initialization voltage signal line Vinit2 to the fourth node N4, thereby initializing the voltage of the fourth node N4.

[0098] During the second reset phase D3, for the second pixel circuit, the first scan signal line GL1 transmits a first scan signal. The first reset transistor T1 and the second reset transistor T2 are turned on under the control of the first scan signal. The first reset transistor T1 transmits a first initialization voltage signal from the first initialization voltage signal line Vinit1 to the second node N2, thereby initializing the voltage of the second node N2. The second reset transistor T2 transmits a second initialization voltage signal from the second initialization voltage signal line Vinit2 to the fourth node N4, thereby initializing the voltage of the fourth node N4. In other words, during the second reset phase D3, the first pixel circuit and the second pixel circuit are controlled in the same manner.

[0099] For example, during the second reset phase D3, first initialization voltage signals having different voltage values ​​may be transmitted to the second node N2 of the first pixel circuit and the second node N2 of the second pixel circuit, respectively, to reduce the impact of the leakage difference between the second nodes of the first pixel circuit and the second pixel circuit on display uniformity. For example, the leakage current of the second node N2 of the first pixel circuit is generally smaller than the leakage current of the second node N2 of the second pixel circuit. Based on this, a first initialization voltage signal having a voltage value of the second voltage V2 may be applied to the second node N2 of the first pixel circuit, and a first initialization voltage signal having a voltage value of the second voltage V2 may be applied to the second node N2 of the second pixel circuit. The first voltage V1 is smaller than the second voltage V2.

[0100] During the light-emitting phase D4, the light-emitting control signal line EM transmits a light-emitting control signal. Under the control of the light-emitting control signal, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on. The second light-emitting control transistor T7 transmits the first voltage signal from the first voltage signal line VDD to the second node N2. The drive transistor DT generates a drive current under the interaction of the first node N1 and the second node N2. The first light-emitting control transistor T6 transmits the drive current to the fourth node N4, which is then further transmitted to the light-emitting device 200. The light-emitting device 200 emits light under the drive current.

[0101] In other embodiments, when the first scanning signal line GL1 and the second scanning signal line GL2 connected to the same row of pixel circuits 100 are different signal lines, and the pixel circuits 100 adopt a connection method as shown in FIG4B (the second electrode of the third reset transistor T3 is electrically connected to the third node N3), the control method of the display panel includes:

[0102] In the first reset phase D1, referring to FIG5B , for the first pixel circuit, the second gate line G2 transmits the second control signal, the third gate line G3 transmits the third control signal, and the second scan signal line GL2 may transmit the second scan signal. The third reset transistor T3 of the first pixel circuit is turned on under the control of the third control signal. The third reset transistor T3 transmits the second voltage signal from the second voltage signal line VX to the third node N1. The compensation transistor T5 is turned on under the control of the second control signal and transmits the voltage of the third node N1 to the first node N1. The second reset transistor T2, under the control of the second scan signal, transmits the second initialization signal from the second initialization voltage signal line Vinit2 to the fourth node N4, thereby initializing the voltage of the fourth node N4.

[0103] During the first reset phase D1, for the second pixel circuit, since the second pixel circuit is in a hold frame, the third reset transistor T3 and the compensation transistor T5 of the second pixel circuit are both in an off state. The voltage of the first node N1 remains unchanged. The second reset transistor T2 can be turned on under the control of the second scan signal, transmitting the second initialization signal to the fourth node N4, thereby initializing the voltage of the fourth node N4.

[0104] In the data writing phase D2, referring to FIG5B , for the first pixel circuit, the first gate line G1 transmits the first control signal, the second gate line G2 continues to transmit the second control signal, and the second scanning signal line GL2 continues to transmit the second scanning signal. The data writing transistor T4 is turned on under the control of the first control signal, and the compensation transistor T5 remains turned on under the control of the second control signal. The data writing transistor T4 transmits the data signal Data transmitted by the data line DL to the second node N2. The driving transistor DT is turned on and leaks power from the second node N2 to the third node N3 until the voltage of the third node N3 reaches Data-Vth. Furthermore, the compensation transistor T5 transmits the voltage of the third node N3 to the first node N1.

[0105] During the data writing phase D2, for the second pixel circuit, since the second pixel circuit is in the hold frame, the data writing transistor T4 and the compensation transistor T5 of the second pixel circuit are both in the off state. The voltages of the first node N1, the second node N2, and the third node N3 remain unchanged. The second reset transistor T2 remains on.

[0106] In the second reset phase D3, referring to FIG. 5B , for the first pixel circuit, the first scan signal line GL1 transmits the first scan signal, and the first reset transistor T1 is turned on under the control of the first scan signal GL1. The first reset transistor T1 transmits the first initialization voltage signal transmitted by the first initialization voltage signal line Vinit1 to the second node N2, thereby initializing the voltage of the second node N2. The second scan signal line GL2 can continue to transmit the second scan signal, and the second reset transistor T2 initializes the voltage of the fourth node N4.

[0107] During the second reset phase D3, for the second pixel circuit, the first scan signal line GL1 transmits the first scan signal. The first reset transistor T1 is turned on under the control of the first scan signal GL1. The first reset transistor T1 transmits the first initialization voltage signal transmitted by the first initialization voltage signal line Vinit1 to the second node N2, thereby initializing the voltage of the second node N2. The second scan signal line GL2 can continue to transmit the second scan signal, and the second reset transistor T2 initializes the voltage of the fourth node N4. In other words, during the second reset phase D3, the first and second pixel circuits are controlled in the same manner.

[0108] For example, during the second reset phase D3, first initialization voltage signals having different voltage values ​​may be transmitted to the second node N2 of the first pixel circuit and the second node N2 of the second pixel circuit, respectively, to reduce the impact of the leakage difference between the second nodes of the first pixel circuit and the second pixel circuit on display uniformity. For example, the leakage current of the second node N2 of the first pixel circuit is generally smaller than the leakage current of the second node N2 of the second pixel circuit. Based on this, a first initialization voltage signal having a voltage value of the second voltage V2 may be applied to the second node N2 of the first pixel circuit, and a first initialization voltage signal having a voltage value of the second voltage V2 may be applied to the second node N2 of the second pixel circuit. The first voltage V1 is smaller than the second voltage V2.

[0109] During the light-emitting phase D4, the light-emitting control signal line EM transmits a light-emitting control signal. Under the control of the light-emitting control signal, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on. The second light-emitting control transistor T7 transmits the first voltage signal from the first voltage signal line VDD to the second node N2. The drive transistor DT generates a drive current under the interaction of the first node N1 and the second node N2. The first light-emitting control transistor T6 transmits the drive current to the fourth node N4, which is then further transmitted to the light-emitting device 200. The light-emitting device 200 emits light under the drive current.

[0110] Of course, the control method of the display panel of the embodiment of the present disclosure is not limited to this. For example, a frame period may further include a bias phase located before the first reset phase D1, in which the second node may be reset by the first reset transistor to weaken or even eliminate the bias state of the driving transistor in the previous frame, and first initialization voltage signals with different voltage values ​​may be transmitted to the second node N2 of the first pixel circuit and the second node N2 of the second pixel circuit, respectively, thereby resetting the driving transistors with different hysteresis degrees with different voltage values. In other words, driving transistors with different refresh frequencies may be repaired to different degrees, thereby reducing the display split-screen problem of the display panel 1100 caused by different refresh frequencies and different hysteresis degrees of the driving transistors, improving the display uniformity of sub-pixels with different refresh frequencies in the local high refresh frequency display scenario of the display panel 1100, and improving the display quality of the display panel 1100.

[0111] In some embodiments, referring to FIG. 6 , a plurality of first initialization voltage signal lines Vinit1 are arranged at intervals along a first direction X, and each of the plurality of first initialization voltage signal lines Vinit1 extends along a second direction Y. Any two first initialization voltage signal lines Vinit1 are electrically insulated from each other, and a column of pixel circuits 100 is electrically connected to a first initialization voltage signal line Vinit1. Specifically, a first initialization voltage signal line Vinit1 is electrically connected to a first electrode of a first reset transistor T1 in a column of pixel circuits 100. In other words, the first electrode of the first reset transistor T1 in each column of pixel circuits 100 is electrically connected to a first initialization voltage signal line Vinit1, and different first initialization voltage signal lines Vinit1 are electrically insulated from each other. Based on this, the first reset transistor T1 can be controlled by the plurality of first scanning signal lines GL1 to transmit first initialization voltage signals of the same or different voltage values ​​to the second node N2 of each pixel circuit.

[0112] When the display panel 1100 displays in the first display mode, that is, when the multiple pixel circuits 100 include multiple first pixel circuits and multiple second pixel circuits, and the refresh frequency of the first pixel circuit is greater than the refresh frequency of the second pixel circuit, the first reset transistor T1 can be controlled by multiple first scanning signal lines GL1 to transmit a first initialization voltage signal with a voltage value of the first voltage V1 to the second node N2 of the first pixel circuit, and to transmit a first initialization voltage signal with a voltage value of the second voltage V2 to the second node N2 of the second pixel circuit.

[0113] The first voltage V1 is less than the second voltage V2. For example, when the driving transistor DT is a P-type low-temperature multi-transistor thin-film transistor, the value of the first initialization voltage signal may be positive, that is, both the first voltage V1 and the second voltage V2 are greater than 0V (volts). In this case, the first voltage V1 is less than the second voltage V2. In other embodiments, when the driving transistor DT is an N-type thin-film transistor, the value of the first initialization voltage signal may be negative. In this case, both the first voltage V1 and the second voltage V2 are less than 0V (volts). In this case, the absolute value of the first voltage V1 is less than the absolute value of the second voltage V2.

[0114] Of course, when all pixel circuits 100 of the display panel 1100 have the same refresh frequency, the first reset transistor T1 can be controlled by multiple first scanning signal lines GL1 to transmit a first initialization voltage signal with the same voltage value to the second node N2 of each pixel circuit.

[0115] In some embodiments, as shown in FIG7 , a plurality of second initialization voltage signal lines Vinit2 can be spaced apart along the second direction Y, and the plurality of second initialization voltage signal lines Vinit2 all extend along the first direction X, and one second initialization voltage signal line Vinit2 is electrically connected to the first electrode of the second reset transistor T2 of a row of pixel circuits 100. In this way, the second initialization voltage signal line Vinit2 and the first initialization voltage signal line Vinit1 can be provided on different conductive layers, which helps to reduce the wiring density of the conductive layer where the first initialization voltage signal line Vinit1 is located, thereby reducing the wiring difficulty of the display panel 1100. In FIG7 , in order to distinguish different signal lines, the first initialization voltage signal line Vinit1, the second initialization voltage signal line Vinit2, the first scanning signal line GL1, and the second scanning signal line GL2 are drawn using different line types (such as line width, dashed line, and implementation, etc.). However, different line types do not represent the line width of the corresponding signal line or the continuity of the signal line. In addition, similar drawing methods are used in the following multiple figures of the specification.

[0116] In other embodiments, as shown in FIG8 , the plurality of second initialization voltage signal lines Vinit2 may include a plurality of third sub-lines VL3 and a plurality of fourth sub-lines VL4. The plurality of third sub-lines VL3 may be spaced apart along the second direction Y and each of the plurality of third sub-lines VL3 extends along the first direction X. One third sub-line VL3 is electrically connected to the first electrode of the second reset transistor T2 of a row of pixel circuits 100. The plurality of fourth sub-lines VL4 may be spaced apart along the first direction X and each of the plurality of fourth sub-lines VL4 extends along the first direction X. In other words, the second initialization voltage signal line Vinit2 is interconnected with the plurality of third sub-lines VL3 via the plurality of fourth sub-lines VL4 to form a mesh structure, thereby reducing the resistance of the second initialization voltage signal line Vinit2.

[0117] Research has found that over time, the material properties of the light-emitting device 200 gradually deteriorate, causing the brightness of the light-emitting device 200 to continuously decrease. In other words, the light-emitting device 200 has aged. Furthermore, the degree of aging varies among sub-pixels with different refresh rates. Resetting the voltage of the fourth node N4 can help improve the aging of the light-emitting device.

[0118] Based on the above reasons, in some embodiments, referring to FIG. 9 , similar to the first initialization voltage signal line Vinit1, a plurality of second initialization voltage signal lines Vinit2 are arranged at intervals along the first direction X, and the plurality of second initialization voltage signal lines Vinit2 extend along the second direction Y. Any two second initialization voltage signal lines Vinit2 are electrically insulated from each other, and a column of pixel circuits 100 is electrically connected to a second initialization voltage signal line Vinit2. Specifically, a second initialization voltage signal line Vinit2 is electrically connected to the first electrode of the second reset transistor T2 of a column of pixel circuits 100. In other words, the first electrode of the second reset transistor T2 of each column of pixel circuits 100 is electrically connected to a second initialization voltage signal line Vinit2, and different second initialization voltage signal lines Vinit2 are electrically insulated from each other. In this way, the second reset transistors T2 can be controlled by the plurality of second scanning signal lines GL2 to transmit second initialization voltage signals of the same or different voltage values ​​to the fourth nodes N2 of different pixel circuits 100. Based on this, a second initialization voltage signal with different voltage values ​​can be transmitted to the fourth node N4 of the first pixel circuit and the second pixel circuit, so that light-emitting devices with different aging degrees can be improved to different degrees, which is beneficial to reducing the impact of the aging degree of the light-emitting device 200 at different refresh frequencies on the luminous brightness of the light-emitting device 200.

[0119] For example, in sub-pixels with a lower refresh rate (sub-pixels corresponding to the second pixel circuit), the light-emitting devices have a greater degree of aging due to long-term display of the same grayscale. Therefore, a second initialization voltage signal with a higher voltage value (absolute value of the voltage) can be applied to the light-emitting devices of the sub-pixels with a lower refresh rate, so that the second initialization voltage signal can better restore the degree of aging of the light-emitting devices. Conversely, in sub-pixels with a higher refresh rate (sub-pixels corresponding to the first pixel circuit), the light-emitting devices display different brightnesses in different frames, resulting in relatively less aging. Therefore, a second initialization voltage signal with a smaller voltage value (absolute value of the voltage) can be applied to the fourth node N4 of the sub-pixels with a higher refresh rate. For example, the second reset transistor T2 can be controlled by multiple second scan signal lines GL2 to transmit a second initialization voltage signal with a voltage value of the third voltage V3 to the fourth node N4 of the first pixel circuit, and a second initialization voltage signal with a voltage value of the fourth voltage V4 to the fourth node N4 of the second pixel circuit. The voltage of the second initialization voltage signal is typically a negative voltage, that is, the voltage of the second initialization voltage signal is typically a negative value. The absolute value of the fourth voltage V4 is greater than the absolute value of the third voltage V3.

[0120] In some embodiments, referring to FIG. 10 , the second voltage signal line VX includes a plurality of first sub-lines VX1 , which are arranged at intervals along a first direction X and extend along a second direction Y. One first sub-line VX1 is electrically connected to the third reset transistor T3 of a column of pixel circuits 100 , and any two first sub-lines are electrically insulated from each other. In other words, the second voltage signal line VX adopts a wiring method similar to that of the first initialization signal line Vinit1. Based on this, the third reset transistor T3 can be controlled by multiple third gate lines G3 to transmit a first initialization voltage signal with the same or different voltage values ​​to the first node N1 of each pixel circuit 100, so as to input a reset voltage with the same or different voltage values ​​to the first node N1, and then reset the driving transistors with different hysteresis degrees with different voltage sizes. In other words, the driving transistors with different refresh frequencies can be repaired to different degrees, thereby reducing the display split-screen problem of the display panel 1100 caused by different refresh frequencies and different hysteresis degrees of the driving transistors, improving the display uniformity of the sub-pixels of different refresh frequencies of the display panel 1100 in the local high refresh frequency display scenario, and improving the display quality of the display panel 1100.

[0121] Of course, in other embodiments, as shown in FIG11 , the second voltage signal line VX includes a plurality of second sub-lines VX2 , which are arranged at intervals along the second direction Y and extend along the first direction X. One second sub-line VX2 is electrically connected to the third reset transistors T3 of a row of pixel circuits 100 , and any two second sub-lines VX2 are electrically insulated from each other. In this way, the second sub-lines VX2 and the first initialization voltage signal line Vinit1 can be provided on a different conductive layer, which helps reduce the wiring density of the conductive layer where the first initialization voltage signal line Vinit1 is provided, thereby reducing the wiring difficulty of the display panel 1100 .

[0122] Alternatively, in some other embodiments, referring to FIG. 12 , the second voltage signal line VX includes a plurality of first straight lines VX1 and a plurality of second sub-lines VX2. The plurality of first sub-lines VX1 are arranged at intervals along the first direction X and extend along the second direction Y. The plurality of second sub-lines VX2 are arranged at intervals along the second direction Y and extend along the first direction X. The plurality of first sub-lines VX1 and the plurality of second sub-lines VX2 are electrically connected, and the first electrode of the third reset transistor T3 is electrically connected to either the first sub-line VX1 or the second sub-line VX2. The plurality of first straight lines VX1 and the plurality of second sub-lines VX2 are interconnected to form a mesh structure to reduce the resistance of the second voltage signal line VX.

[0123] Some embodiments of the present disclosure further provide a method for controlling a display panel 1100, for controlling the display panel 1100 of any of the above embodiments. The display panel 1100 includes a first display mode. In the first display mode, the display panel 1100 includes a plurality of first pixel circuits and a plurality of second pixel circuits, and a refresh frequency of the plurality of first pixel circuits is greater than a refresh frequency of the plurality of second pixel circuits.

[0124] The control method of the display panel 1100 includes:

[0125] The plurality of scanning signal lines GL control the plurality of initialization voltage signal lines Vinit1, transmitting an initialization voltage signal of a first voltage V1 to the first pixel circuit and transmitting an initialization voltage signal of a second voltage V2 to the second pixel circuit. The value of the first voltage V1 (the absolute value of the first voltage) is less than the value of the second voltage V2 (the absolute value of the first voltage).

[0126] It is understood that the control method for the display panel 1100 described above can be used in the second reset stage D3 described above. It is understood that the control method described above is merely an example, and the embodiments of the present disclosure are not limited thereto. For example, a bias stage can be added before the first reset stage D1, and the control method described above can be implemented in the bias stage. Alternatively, any other suitable control sequence can be used to reset the second node N2 to different voltage values, as long as the same technical concept is employed.

[0127] Taking the circuit shown in FIG. 4A and FIG. 4B as an example, as shown in FIG. 13 , the control method of the display panel may include:

[0128] The plurality of first scanning signal lines GL1 control the plurality of first initialization voltage signal lines Vinit1 through the plurality of first reset transistors T1, transmitting a first initialization voltage signal having a voltage value of a first voltage V1 to the first pixel circuit 101, and transmitting a first initialization voltage signal having a voltage value of a second voltage V2 to the second pixel circuit 102. The first voltage V1 is less than the second voltage V2. In other words, when the first initialization voltage signal line Vinit1 transmits the first initialization voltage signal to the first pixel circuit 101 (holding the frame), the voltage value of the first initialization voltage signal line Vinit1 is the first voltage V1, and when the first initialization voltage signal is transmitted to the second pixel circuit 102, the voltage value of the first initialization voltage signal line Vinit1 is the second voltage V2.

[0129] It is understandable that when the first pixel circuit 101 is in a refresh frame, the first initialization voltage signal line Vinit1 can transmit first initialization voltage signals with the same or different voltage values ​​to the first pixel circuit 101 and the second pixel circuit 102 respectively.

[0130] As shown in FIG13 , the plurality of second scanning signal lines GL2 control the plurality of second initialization voltage signal lines Vinit2 via the plurality of second reset transistors T2, transmitting a second initialization voltage signal having a voltage value of the third voltage V3 to the first pixel circuit 101, and transmitting a second initialization voltage signal having a voltage value of the fourth voltage V4 to the second pixel circuit 102. The third voltage V3 is less than the fourth voltage V4. In other words, when the second initialization voltage signal line Vinit2 transmits the second initialization voltage signal to the first pixel circuit 101 (holding the frame), the voltage value of the second initialization voltage signal line Vinit2 is the third voltage V3, and when the second initialization voltage signal is transmitted to the second pixel circuit 102, the voltage value of the second initialization voltage signal line Vinit2 is the fourth voltage V4.

[0131] It is understandable that when the first pixel circuit 101 is in a refresh frame, the second initialization voltage signal line Vinit2 can transmit first initialization voltage signals with the same or different voltage values ​​to the first pixel circuit 101 and the second pixel circuit 102 respectively.

[0132] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, comprising: A plurality of pixel circuits arranged in multiple rows and multiple columns; A plurality of initialization voltage signal lines spaced apart along a first direction and all extending along a second direction. One initialization voltage signal line is electrically connected to one column of pixel circuits, and any two initialization voltage signal lines are electrically insulated from each other. The first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged; A plurality of scan signal lines spaced apart along the second direction and all extending along the first direction. One scan signal line is electrically connected to one row of pixel circuits; The pixel circuit is configured to, under the control of a scan signal from one scan signal line, transmit an initialization voltage signal from the initialization voltage signal line to a circuit node of the pixel circuit to initialize the voltage of the circuit node.

2. The display panel according to claim 1, wherein The plurality of initialization voltage signal lines include a plurality of first initialization voltage signal lines, and any two first initialization voltage signal lines are electrically insulated from each other. One column of pixel circuits is electrically connected to one first initialization voltage signal line. The plurality of scan signal lines include a plurality of first scan signal lines, and one first scan signal line is electrically connected to one row of pixel circuits; The pixel circuit includes: A driving transistor, the control electrode of the driving transistor is electrically connected to a first node, the first electrode is electrically connected to a second node, and the second electrode is electrically connected to a third node; A data writing transistor, the control electrode of the data writing transistor is electrically connected to a first gate line, the first electrode is electrically connected to a data line, and the second electrode is electrically connected to the second node; A compensation transistor, the control electrode of the compensation transistor is electrically connected to a second gate line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first node; A first reset transistor, the control electrode of the first reset transistor is electrically connected to one of the first scan signal lines, the first electrode is electrically connected to one of the first initialization voltage signal lines, and the second electrode is electrically connected to the second node. The first reset transistor is configured to, under the control of a first scan signal from the first scan signal line, transmit a first initialization voltage signal from the first initialization voltage signal line to the second node.

3. The display panel according to claim 2, wherein, The first initialization voltage signal line is configured to transmit first initialization voltage signals with different voltage values in different time periods.

4. The display panel according to claim 2 or 3, wherein The plurality of initialization voltage signal lines further include a plurality of second initialization voltage signal lines, and any two second initialization voltage signal lines are electrically insulated from each other. One column of pixel circuits is electrically connected to one second initialization voltage signal line. The plurality of scan signal lines further include a plurality of second scan signal lines, and one second scan signal line is electrically connected to one row of pixel circuits; The pixel circuit further includes: A first light-emitting control transistor, the control electrode of the first light-emitting control transistor is electrically connected to a light-emitting control signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to a fourth node; A second reset transistor, wherein a control electrode of the second reset transistor is electrically connected to one of the second scan signal lines, a first electrode is electrically connected to one of the second initialization voltage signal lines, and a second electrode is electrically connected to the fourth node; the second reset transistor is configured to transmit a second initialization voltage signal from the second initialization voltage signal line to the fourth node under the control of a second scan signal from the second scan signal line.

5. The display panel according to claim 4, wherein, The second initialization voltage signal line is configured to transmit second initialization voltage signals with different voltage values in different time periods.

6. The display panel according to claim 4 or 5, wherein, The first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are configured to transmit the same scan signal, and the first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are the same signal line.

7. The display panel according to claim 4 or 5, wherein The first scan signal line and the second scan signal line electrically connected to the same row of pixel circuits are configured to transmit different scan signals, and the first scan signal line and the second scan signal line are different signal lines.

8. The display panel according to any one of claims 2 to 7, wherein, The pixel circuit further includes: A second light-emitting control transistor, wherein a control electrode of the second light-emitting control transistor is electrically connected to a light-emitting control signal line, a first electrode is electrically connected to a first voltage signal line, and a second electrode is electrically connected to the second node; A third reset transistor, wherein a control electrode of the third reset transistor is electrically connected to a third gate line, a first electrode is electrically connected to a second voltage signal line, and a second electrode is electrically connected to the first node; A storage capacitor, wherein one plate of the storage capacitor is electrically connected to the first voltage signal line, and the other plate is electrically connected to the first node.

9. The display panel according to any one of claims 2 to 7, wherein, The pixel circuit further includes: A second light-emitting control transistor, wherein a control electrode of the second light-emitting control transistor is electrically connected to a light-emitting control signal line, a first electrode is electrically connected to a first voltage signal line, and a second electrode is electrically connected to the second node; A third reset transistor, wherein a control electrode of the third reset transistor is electrically connected to a third gate line, a first electrode is electrically connected to a second voltage signal line, and a second electrode is electrically connected to the second node; A storage capacitor, wherein one plate of the storage capacitor is electrically connected to the first voltage signal line, and the other plate is electrically connected to the first node.

10. The display panel according to claim 8 or 9, wherein, The second voltage signal line includes: A plurality of first sub-lines, the plurality of first sub-lines are arranged at intervals along the first direction and all extend along the second direction, one first sub-line is electrically connected to a third reset transistor of a column of pixel circuits, and any two first sub-lines are electrically insulated from each other; or, A plurality of second sub-lines, the plurality of second sub-lines are arranged at intervals along the second direction and all extend along the first direction, one second sub-line is electrically connected to a third reset transistor of a row of pixel circuits, and any two second sub-lines are electrically insulated from each other; or, A plurality of first sub-lines and a plurality of second sub-lines, the plurality of first sub-lines are arranged at intervals along the first direction and all extend along the second direction, the plurality of second sub-lines are arranged at intervals along the second direction and all extend along the first direction, and the plurality of first sub-lines and the plurality of second sub-lines are electrically connected, and the first electrode of the third reset transistor is electrically connected to the first sub-line or the second sub-line.

11. The display panel according to any one of claims 1 to 10, wherein, The display panel includes a first display mode. In the first display mode, the plurality of pixel circuits include at least one first pixel circuit and at least one second pixel circuit, and the refresh frequency of the first pixel circuit is greater than that of the second pixel circuit; The initialization voltage signals transmitted by the plurality of initialization voltage signal lines to the first pixel circuit are a first voltage, and the initialization voltage signals transmitted to the second pixel circuit are a second voltage; the first voltage is less than the second voltage.

12. A control method for a display panel, configured to control the display panel according to any one of claims 1 to 11. The display panel includes a first display mode. In the first display mode, the display panel includes a plurality of first pixel circuits and a plurality of second pixel circuits, and the refresh frequency of the plurality of first pixel circuits is greater than that of the plurality of second pixel circuits; The control method includes: A plurality of scan signal lines control a plurality of initialization voltage signal lines to transmit initialization voltage signals with a voltage value of the first voltage to the plurality of first pixel circuits and transmit initialization voltage signals with a voltage value of the second voltage to the second pixel circuits; the first voltage is less than the second voltage.

13. The control method according to claim 12, wherein, The control method includes: When the initialization voltage signal line transmits an initialization voltage signal to the second pixel circuit under the control of the scan signal line, the initialization voltage signal line transmits the second voltage; When the initialization voltage signal line transmits an initialization voltage signal to the first pixel circuit under the control of the scan signal line, the initialization voltage signal line transmits the first voltage.

14. The control method according to claim 12 or 13, wherein The plurality of initialization voltage signal lines include a plurality of first initialization voltage signal lines, and the plurality of scan signal lines include a plurality of first scan signal lines; the pixel circuit includes a driving transistor, a data writing transistor, a compensation transistor, and a first reset transistor; One frame period includes a data writing stage and a second reset stage following the data writing stage; the control method further includes: In the data writing stage, the data writing transistor and the compensation transistor of the first pixel circuit transmit the compensated data signal to the first node, and the data writing transistor and the compensation transistor of the second pixel circuit are both in a cut-off state; In the second reset stage, the first reset transistor of the first pixel circuit transmits a first initialization voltage signal with the first voltage to the second node, and the first reset transistor of the second pixel circuit transmits a first initialization voltage signal with the second voltage to the second node.

15. The control method according to claim 14, wherein, The plurality of initialization voltage signal lines further include a plurality of second initialization voltage signal lines, and the plurality of scan signal lines further include a plurality of second scan signal lines; the pixel circuit further includes a first light-emitting control transistor and a second reset transistor; The control method further includes: In the second reset stage, the second reset transistor of the first pixel circuit transmits a second initialization voltage signal with the first voltage to the fourth node, and the first reset transistor of the second pixel circuit transmits a second initialization voltage signal with the second voltage to the fourth node.

16. The control method according to claim 14 or 15, wherein, The pixel circuit further includes a second light-emitting control transistor, a third reset transistor, and a storage capacitor; one frame period further includes a first reset stage before the data writing stage; The control method further includes: In the first reset stage, the third reset transistor of the first pixel circuit transmits a second voltage signal to the first node; the third reset transistor of the second pixel circuit is in an off state.

17. A display device, comprising: The display panel according to any one of claims 1 to 11; A driving circuit board, electrically connected to the display panel and configured to transmit control signals to the display panel.

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