Power amplification circuit and power amplification device

Abstract

A power amplification circuit according to the present invention comprises: a first carrier amplifier that amplifies a first branch signal branched from a first signal which is one from among balanced signals and that outputs a first amplified signal from a first output terminal; a first peak amplifier that amplifies a second branch signal which is branched from the first signal and which is different in phase from the first branch signal and that outputs a second amplified signal from a second output terminal; a second carrier amplifier that amplifies a third branch signal branched from a second signal which is the other from among the balanced signals and that outputs a third amplified signal from a third output terminal; a second peak amplifier that amplifies a fourth branch signal which is branched from the second signal and which is different in phase from the third branch signal and that outputs a fourth amplified signal from a fourth output terminal; first wiring; second wiring; and third wiring that is electromagnetically coupled to the first wiring and the second wiring and that is connected to a ground, wherein the first wiring is provided so as to be closer to the third wiring than to the second wiring, and the second wiring is provided so as to be closer to the third wiring than to the first wiring.

Description

Power amplifier circuit and power amplifier device

[0001] The present invention relates to a power amplifier circuit and a power amplifier device.

[0002] There is a power amplifier circuit in which a Doherty amplifier has a differential configuration and a transformer for impedance conversion is connected to the differential output terminals (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-90557

[0004] In the power amplifier circuit described in Patent Document 1, the output characteristics may change depending on the wiring layout.

[0005] The present invention has been made in view of the above circumstances, and has as its object to provide a power amplifier circuit and a power amplifier device that can achieve good output characteristics.

[0006] A power amplifier circuit according to one aspect of the present invention includes a first carrier amplifier that amplifies a first branched signal branched from a first signal, which is one of balanced signals, and outputs the first amplified signal from a first output terminal; a first peak amplifier that amplifies a second branched signal branched from the first signal and having a phase different from that of the first branched signal, and outputs the second amplified signal from a second output terminal; a second carrier amplifier that amplifies a third branched signal branched from a second signal, which is the other of the balanced signals, and outputs the third amplified signal from a third output terminal; a second peak amplifier that amplifies a fourth branched signal branched from the second signal and having a phase different from that of the third branched signal, and outputs the fourth amplified signal from a fourth output terminal; one end connected to the first output terminal; a first capacitor having one end connected to the second output terminal and the other end connected to the fourth output terminal; a second capacitor having one end connected to the second output terminal and the other end connected to the fourth output terminal; a first wiring having a first end connected to the first output terminal and a second end connected to the second output terminal; a second wiring having a third end connected to the third output terminal and a fourth end connected to the fourth output terminal; a balun connected between the first wiring and the second wiring; and a third wiring electromagnetically coupled to the first wiring and the second wiring, respectively, and connected to ground, wherein the first wiring is arranged closer to the third wiring than the second wiring, and the second wiring is arranged closer to the third wiring than the first wiring.

[0007] A power amplifier device according to one aspect of the present invention is a power amplifier device having the above-described power amplifier circuit, and includes a semiconductor chip on which the first carrier amplifier, the first peak amplifier, the second carrier amplifier, and the second peak amplifier are formed, and a substrate on which the first wiring, the second wiring, the balun, and the third wiring are formed and on which the semiconductor chip is provided.

[0008] According to the present invention, it is possible to provide a power amplifier circuit and a power amplifier device that can achieve good output characteristics.

[0009] FIG. 1 is a circuit diagram of a power amplifier circuit 101. FIG. 2 is a diagram schematically showing cross sections parallel to the xy plane of a power amplifier device 11 in which the power amplifier circuit 101 is formed. FIG. 3 is a perspective view schematically showing the power amplifier device 11. FIG. 4 is a circuit diagram of a power amplifier circuit 102. FIG. 5 is a diagram schematically showing cross sections parallel to the xy plane of a power amplifier device 12 in which the power amplifier circuit 102 is formed. FIG. 6 is a diagram schematically showing a cross section parallel to the zx plane of a power amplifier device 13 in which the power amplifier circuit 101 or 102 is formed. FIG. 7 is a diagram schematically showing a cross section parallel to the zx plane of a power amplifier device 14 in which the power amplifier circuit 101 or 102 is formed. FIG. 8 is a diagram schematically showing a cross section parallel to the zx plane of a power amplifier device 15 in which the power amplifier circuit 101 or 102 is formed.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the same elements are given the same reference numerals, and redundant explanations will be omitted as much as possible.

[0011] [First Embodiment] A power amplifier circuit 101 according to the first embodiment will be described. Fig. 1 is a circuit diagram of the power amplifier circuit 101. As shown in Fig. 1, the power amplifier circuit 101 includes a first wiring 21, a second wiring 22, a third wiring 23, a balun 61, a differential pair 141, capacitors 201 (first capacitor), 202 (second capacitor), and 205, and harmonic traps 301, 302, 303, and 304.

[0012] The differential pair 141 includes Doherty amplifiers 151 and 153. The Doherty amplifier 151 includes a carrier amplifier 51 (first carrier amplifier) ​​and a peak amplifier 52 (first peak amplifier). The Doherty amplifier 153 includes a carrier amplifier 53 (second carrier amplifier) ​​and a peak amplifier 54 (second peak amplifier).

[0013] The power amplifier circuit 101 amplifies one of the balanced signals (hereinafter sometimes referred to as the first signal) and the other (hereinafter sometimes referred to as the second signal) using the Doherty amplifiers 151 and 153 that make up the differential pair 141, and outputs an output signal RFout, which is a single-ended signal.

[0014] In detail, the first signal and the second signal are signals generated by dividing an input signal, which is, for example, a single-ended signal, by a balun (not shown). The input signal is, for example, a radio frequency (RF) signal.

[0015] The phase of the first signal is different from the phase of the second signal. In this embodiment, the phase of the first signal is different from the phase of the second signal by approximately 180°. Note that, depending on the imbalance in the wiring lengths of the circuits, the phase difference between the first signal and the second signal may be significantly different from 180°.

[0016] The carrier amplifier 51 in the Doherty amplifier 151 of the differential pair 141 amplifies the branch signal RF1 (first branch signal) branched from the first signal, and outputs the amplified signal RF5 (first amplified signal) from the output terminal 51a (first output terminal).

[0017] The peak amplifier 52 amplifies a branch signal RF2 (second branch signal) that is branched from the first signal and has a different phase from the branch signal RF1, and outputs an amplified signal RF6 (second amplified signal) from an output terminal 52a (second output terminal).

[0018] The branch signals RF1 and RF2 are, for example, signals generated by dividing the first signal by a divider (not shown). The phases of the branch signals RF1 and RF2 immediately after being output from the divider are, for example, aligned.

[0019] The branch signal RF2 is supplied to the peak amplifier 52 via, for example, a quarter-wave line (not shown), while the branch signal RF1 is supplied directly to the carrier amplifier 51. For this reason, the phase of the branch signal RF2 supplied to the peak amplifier 52 lags behind the phase of the branch signal RF1 supplied to the carrier amplifier 51 by approximately 90 degrees.

[0020] The carrier amplifier 53 in the Doherty amplifier 153 of the differential pair 141 amplifies the branch signal RF3 (third branch signal) branched from the second signal, and outputs the amplified signal RF7 (third amplified signal) from the output terminal 53a (third output terminal).

[0021] The peak amplifier 54 amplifies a branch signal RF4 (fourth branch signal) that is branched from the second signal and has a different phase from the branch signal RF3, and outputs an amplified signal RF8 (fourth amplified signal) from an output terminal 54a (fourth output terminal).

[0022] The branch signals RF3 and RF4 are, for example, signals generated by dividing the second signal by a divider (not shown). The phases of the branch signals RF3 and RF4 immediately after being output from the divider are, for example, aligned.

[0023] The branch signal RF4 is supplied to the peak amplifier 54 via, for example, a quarter-wave line (not shown), while the branch signal RF3 is supplied directly to the carrier amplifier 53. For this reason, the phase of the branch signal RF4 supplied to the peak amplifier 54 lags behind the phase of the branch signal RF3 supplied to the carrier amplifier 53 by approximately 90 degrees.

[0024] The capacitor 201 has one end connected to the output terminal 51 a of the carrier amplifier 51 and the other end connected to the output terminal 53 a of the carrier amplifier 53. The capacitor 202 has one end connected to the output terminal 52 a of the peak amplifier 52 and the other end connected to the output terminal 54 a of the peak amplifier 54.

[0025] Each of the first wiring 21, the second wiring 22, and the third wiring 23 can be treated as a distributed constant circuit. That is, each wiring has an inductance per unit length in the direction of extension. In addition, between the wirings, there is a capacitance per unit length in the direction of extension of the wiring.

[0026] The first wiring 21 has a first end connected to the output terminal 51 a of the carrier amplifier 51 and a second end connected to the output terminal 52 a of the peak amplifier 52. In this embodiment, the first wiring 21 includes wirings 211, 212, and 213. The first wiring 21 is provided with a node N1 (first node) located between the first end and the second end, and a node N2 (second node) located between the first end and the node N1. The wirings 211, 212, and 213 are, for example, electrodes or vias.

[0027] The wiring 211 has one end connected to the output terminal 51 a of the carrier amplifier 51, i.e., a first end, and the other end connected to the node N2. The wiring 212 has one end connected to the node N2 and the other end connected to the node N1. The wiring 213 has one end connected to the node N1 and the other end connected to the output terminal 52 a of the peak amplifier 52, i.e., a second end.

[0028] In this embodiment, the inductance of the wiring 211 is substantially the same as the inductance of the wiring 212. The inductance of the wiring 213 is smaller than the inductance of the wiring 211 and the inductance of the wiring 212.

[0029] The second wiring 22 has a third end connected to the output terminal 53 a of the carrier amplifier 53 and a fourth end connected to the output terminal 54 a of the peak amplifier 54. In this embodiment, the second wiring 22 includes wirings 221, 222, and 223. The second wiring 22 is provided with a node N3 (third node) located between the third end and the fourth end, and a node N4 (fourth node) located between the third end and node N3. The wirings 221, 222, and 223 are, for example, electrodes or vias.

[0030] The wiring 221 has one end connected to the output terminal 53 a of the carrier amplifier 53 (i.e., the third end) and the other end connected to the node N4. The wiring 222 has one end connected to the node N4 and the other end connected to the node N3. The wiring 223 has one end connected to the node N3 and the other end connected to the output terminal 54 a of the peak amplifier 54 (i.e., the fourth end).

[0031] In this embodiment, the inductance of the wiring 221 is substantially the same as the inductance of the wiring 222. The inductance of the wiring 223 is smaller than the inductance of the wiring 221 and the inductance of the wiring 222.

[0032] The third wiring 23 is electromagnetically coupled to the first wiring 21 and the second wiring 22, and is connected to ground. In this embodiment, the third wiring 23 includes wirings 231 and 232. The wirings 231 and 232 are, for example, electrodes or vias.

[0033] Wiring 231 has one open end and the other open end, and is electromagnetically coupled to wirings 211 and 221. Wiring 232 has one end connected to the other end of wiring 231 and the other end connected to ground, and is electromagnetically coupled to wirings 212 and 222. In other words, wiring 231 is electromagnetically coupled to wiring 211 and also to wiring 221. Wiring 232 is electromagnetically coupled to wiring 212 and also to wiring 222.

[0034] Although the configuration in which the other end of the wiring 232 is connected to ground has been described, the present invention is not limited to this. One end of the wiring 232 or a portion between one end and the other end of the wiring 232 may be connected to ground. Alternatively, multiple portions of the wiring 232 may be connected to ground.

[0035] Furthermore, although a configuration in which the wiring 231 and the wiring 232 are electrically connected has been described, the present invention is not limited to this. The wiring 231 and the wiring 232 may not be electrically connected, and may instead be connected to two separate grounds. In this case, one end or the other end of the wiring 231, or the area between one end and the other end of the wiring 231, may be connected to ground. Alternatively, a configuration in which multiple portions of the wiring 231 are connected to ground may be used. Alternatively, the wirings 231 and 232 may be formed by a single wiring.

[0036] The first wiring 21 is provided closer to the third wiring 23 than the second wiring 22. The second wiring 22 is provided closer to the third wiring 23 than the first wiring 21. Details of the arrangement of the first wiring 21, the second wiring 22, and the third wiring 23 will be described later.

[0037] The balun 61 is connected between the first wiring 21 and the second wiring 22. In this embodiment, the balun 61 is connected between the node N1 and the node N3. Specifically, the balun 61 includes inductors 61a and 61b.

[0038] The inductor 61a has one end connected to the node N1 and the other end connected to the node N3. The inductor 61b has one end connected to the output terminal 32, through which the output signal RFout is output, and the other end connected to ground, and is electromagnetically coupled to the inductor 61a.

[0039] Harmonic traps 301, 302, 303 and 304 are connected between the output terminal 51a of the carrier amplifier 51, the output terminal 52a of the peak amplifier 52, the output terminal 53a of the carrier amplifier 53 and the output terminal 54a of the peak amplifier 54, respectively, and the ground.

[0040] Specifically, the harmonic trap 301 includes an inductor 301a and a capacitor 301b. The inductor 301a has one end connected to the output terminal 51a of the carrier amplifier 51, and the other end. The capacitor 301b has one end connected to the other end of the inductor 301a, and the other end connected to ground.

[0041] The harmonic trap 302 includes an inductor 302 a and a capacitor 302 b. The inductor 302 a has one end connected to the output terminal 52 a of the peak amplifier 52, and the other end. The capacitor 302 b has one end connected to the other end of the inductor 302 a, and the other end connected to ground.

[0042] The harmonic trap 303 includes an inductor 303 a and a capacitor 303 b. The inductor 303 a has one end connected to the output terminal 53 a of the carrier amplifier 53, and the other end. The capacitor 303 b has one end connected to the other end of the inductor 303 a, and the other end connected to ground.

[0043] The harmonic trap 304 includes an inductor 304 a and a capacitor 304 b. The inductor 304 a has one end connected to the output terminal 54 a of the peak amplifier 54, and the other end. The capacitor 304 b has one end connected to the other end of the inductor 304 a, and the other end connected to ground.

[0044] Capacitor 205 has one end connected to node N2 and the other end connected to node N4.

[0045] Each drawing may show an x-axis, a y-axis, and a z-axis. The x-axis, y-axis, and z-axis form a right-handed three-dimensional Cartesian coordinate system. Hereinafter, the direction of the x-axis arrow may be referred to as the x-axis + side, and the direction opposite to the arrow may be referred to as the x-axis - side, and the same applies to the other axes. The z-axis + side and z-axis - side may be referred to as the "upper side" and "lower side," respectively. The z-axis direction may also be referred to as the "stacking direction." Furthermore, planes perpendicular to the x-axis, y-axis, or z-axis may also be referred to as the yz-plane, zx-plane, or xy-plane. Here, the clockwise rotation direction when viewed from above to below is defined as the clockwise direction (cw). The counterclockwise rotation direction when viewed from above to below is defined as the counterclockwise direction (ccw).

[0046] 2A and 2B are diagrams showing cross sections parallel to the xy plane of the power amplifier device 11 in which the power amplifier circuit 101 is formed. FIG. 3 is a perspective view showing the power amplifier device 11.

[0047] 2 and 3 , the power amplifier device 11 includes a laminated substrate 401 and a semiconductor chip 501. The laminated substrate 401 includes conductive layers 411 (first conductive layer) and 412 (second conductive layer) and dielectric layers 421 and 422. The dielectric layers 421 and 422 are provided in this order from top to bottom.

[0048] Each of the dielectric layers 421 and 422 has an upwardly facing surface (hereinafter sometimes referred to as the upper surface) that is substantially parallel to the xy plane, and a downwardly facing surface (hereinafter sometimes referred to as the lower surface) that is substantially parallel to the xy plane. The upper surface of the dielectric layer 422 faces the lower surface of the dielectric layer 421 located above the dielectric layer 422. The same applies to the other dielectric layers. The upper and lower surfaces may have irregularities that occur during manufacturing, or depressions for providing wiring layers.

[0049] A conductive layer 411 is provided on the upper surface of the dielectric layer 421. A conductive layer 412 is provided on the upper surface of the dielectric layer 422.

[0050] A part of the first wiring 21, a part of the second wiring 22, and a part of the third wiring 23 are provided on the conductive layer 411. Another part of the first wiring 21, a part of the second wiring 22, and a part of the third wiring 23 are provided on the conductive layer 412.

[0051] Specifically, the laminated substrate 401 is formed with a first wiring 21, a second wiring 22, a third wiring 23, and a balun 61. The semiconductor chip 501 is formed with a carrier amplifier 51, a peak amplifier 52, a carrier amplifier 53, and a peak amplifier 54, which are not shown.

[0052] Electrodes 211E, 221E, 231E, and 61aE are formed on the conductive layer 411. Electrodes 212E, 222E, and 232E are formed on the conductive layer 412.

[0053] Vias 212Va, 212Vb, 222Va, 222Vb, and 231V extending in the stacking direction are formed in the dielectric layer 421. A via 232V extending in the stacking direction is formed in the dielectric layer 422.

[0054] The electrode 211E of the conductive layer 411 has an end 211Ef electrically connected to the output terminal 51a of the carrier amplifier 51, and an end 211Es connected to the upper end of the via 212Va.

[0055] When the power amplifier device 11 is viewed from above, the electrode 211E has a shape that extends from the end 212Ef toward the end 212Es while changing its extension direction (see FIGS. 2 and 3).

[0056] In this embodiment, when viewed on the xy plane so that the directions toward the positive y-axis side, the positive x-axis side, the negative y-axis side, and the negative x-axis side are the north, east, south, and west directions, respectively, the electrode 212E extends from the end 211Ef to the end 211Es while changing its extension direction in the southwesterly direction and then the southerly direction. The electrode 211E functions as the wiring 211 in the power amplifier circuit 101.

[0057] The electrode 221E has an end 221Ef electrically connected to the output terminal 53a of the carrier amplifier 53, and an end 221Es connected to the upper end of the via 222Va.

[0058] Ends 221Ef and 221Es of the electrode 221E are provided on the positive x-axis side of ends 211Ef and 211Es of the electrode 211E, respectively.

[0059] When the power amplifier device 11 is viewed from above, the electrode 221E has a shape that extends from the end 221Ef toward the end 221Es while changing its extension direction (see FIGS. 2 and 3).

[0060] In this embodiment, the electrode 221E extends from the end 221Ef to the end 221Es while changing its extension direction in the southwest direction and then in the south direction. The electrode 221E functions as the wiring 221 in the power amplifier circuit 101.

[0061] A component 201D that functions as the capacitor 201 in the power amplifier circuit 101 is connected to the upper sides of the ends 211Ef and 221Ef (see FIG. 2).

[0062] A component 205D (see FIG. 2) that functions as the capacitor 205 in the power amplifier circuit 101 is connected to the upper sides of the ends 211Es and 221Es. The components 201D and 205D are, for example, surface mount devices (SMD).

[0063] The ends 211Es and 221Es are nodes N2 and N4 in the power amplifier circuit 101, respectively.

[0064] The electrode 231E is provided between the electrode 211E and the electrode 221E. The electrode 231E extends along the y-axis. The electrode 231E functions as the wiring 231 in the power amplifier circuit 101.

[0065] An end 231Ef of electrode 231E on the positive y-axis side is located closer to the negative y-axis side than end 211Ef of electrode 211E and end 221Ef of electrode 221E. An end 231Es of electrode 231E on the negative y-axis side is located closer to the positive y-axis side than end 211Es of electrode 211E and end 221Es of electrode 221E. The length of electrode 231E is shorter than the lengths of electrodes 211E and 212E.

[0066] The end 231Ef and the end 231Es of the electrode 231E are connected to the upper ends of the two vias 231V, respectively.

[0067] The electrode 61aE is provided on the positive x-axis side of the electrode 221E, and is wound in the plane in which the conductive layer 411 extends. In detail, the electrode 61aE has an end 61aEf on the negative x-axis side and an end 61aEs on the positive x-axis side, which are electrically connected to the output terminal 52a of the peak amplifier 52 and the output terminal 54a of the peak amplifier 54, respectively.

[0068] An end 61aEf of the electrode 61aE is located on the positive x-axis side of the end 221Ef of the electrode 221E, and is connected to the upper ends of the two vias 212Vb.

[0069] An end 61aEs of the electrode 61aE is located on the positive x-axis side of the end 61aEf, and is connected to the upper ends of the two vias 222Vb.

[0070] When the power amplifier device 11 is viewed from above, the electrode 61aE is wound in the xy plane from the end 61aEf to the end 61aEs in a counterclockwise direction ccw by at least 3 / 4 turn but less than 1 turn.

[0071] A component 202D (see FIG. 2) that functions as the capacitor 202 in the power amplifier circuit 101 is connected to the upper sides of the ends 61aEf and 61aEs. The component 202D is, for example, a surface-mounted device.

[0072] The ends 61aEf and 61aEs are nodes N1 and N3 in the power amplifier circuit 101, respectively.

[0073] The electrode 212E in the conductive layer 412 has an end 212Ef connected to the lower end of the via 212Va and an end 212Es connected to the lower ends of the two vias 212Vb. The electrode 212E and the vias 212Va and 212Vb function as the wiring 212 in the power amplifier circuit 101.

[0074] When the power amplifier device 11 is viewed from above, the electrode 212E has a shape that extends from the end 212Ef to the end 212Es while changing its extension direction (see FIGS. 2 and 3).

[0075] In this embodiment, the electrode 212E extends from an end 212Ef to an end 212Es while changing its extension direction in the order of north, northeast, and east.

[0076] The electrode 222E has an end 222Ef connected to the lower end of the via 222Va and an end 222Es connected to the lower ends of the two vias 222Vb. The electrode 222E and the vias 222Va and 222Vb function as the wiring 222 in the power amplifier circuit 101.

[0077] When the power amplifier device 11 is viewed from above, the electrode 222E has a shape that extends from the end 222Ef to the end 222Es while changing its extension direction (see FIGS. 2 and 3).

[0078] In this embodiment, the electrode 222E extends from the end 222Ef to the end 222Es while changing its extension direction in the eastward direction and then in the northeastward direction.

[0079] The electrode 232E is provided between the electrode 212E and the electrode 222E. An end 232Ef of the electrode 232E is located between the end 212Ef of the electrode 212E and the end 222Ef of the electrode 222E. The electrode 232E functions as the wiring 232 in the power amplifier circuit 101.

[0080] When the power amplifier device 11 is viewed from above, the electrode 232E has a shape that extends from the end 232Ef to the end 232Es while changing its extension direction (see FIGS. 2 and 3).

[0081] In this embodiment, the electrode 232E extends from the end 232Ef to the end 232Es while changing its extension direction in the north direction and then in the east direction.

[0082] The upper surface of the electrode 232E is connected to the lower ends of two vias 231V, and the lower surface of the electrode 232E is connected to ground through five vias 232V.

[0083] (Effect) If the first wiring 21 and the second wiring 22 are provided close to each other in a configuration in which the third wiring 23 is not provided, the electromagnetic coupling between the first wiring 21 and the second wiring 22 increases. Therefore, when the output of the Doherty amplifier 151 and the output of the Doherty amplifier 153 in the differential pair 141 are transmitted to the first wiring 21 and the second wiring 22, respectively, the inductance of the first wiring 21 and the second wiring 22 decreases, and the impedance seen from each of the Doherty amplifier 151 and the Doherty amplifier 153 changes. This changes the characteristics of the output signal.

[0084] In contrast, in the power amplifier circuit 101, the first wiring 21 is provided closer to the third wiring 23 than the second wiring 22, the second wiring 22 is provided closer to the third wiring 23 than the first wiring 21, and the third wiring 23 is connected to ground, which makes it possible to suppress electromagnetic coupling between the first wiring 21 and the second wiring 22. This suppresses a decrease in the inductance of the first wiring 21 and the second wiring 22, and makes it possible to suppress fluctuations in the characteristics of the output signal due to changes in the impedance seen from each of the Doherty amplifiers 151 and 153.

[0085] Although the first wiring 21, the second wiring 22, and the third wiring 23 are each described as being formed across two layers, the conductive layer 411 and the conductive layer 412, the present invention is not limited to this. Each of the first wiring 21, the second wiring 22, and the third wiring 23 may be formed in one conductive layer, or may be formed across three or more conductive layers.

[0086] Second Embodiment A power amplifier circuit 102 according to a second embodiment will be described. From the second embodiment onward, descriptions of matters common to the first embodiment will be omitted, and only differences will be described. In particular, similar effects due to similar configurations will not be mentioned in each embodiment.

[0087] Fig. 4 is a circuit diagram of the power amplifier circuit 102. As shown in Fig. 4, the power amplifier circuit 102 differs from the power amplifier circuit 101 according to the first embodiment in that the power amplifier circuit 102 includes capacitors 203 and 204 instead of the capacitor 205 and the harmonic traps 301, 302, 303, and 304.

[0088] Capacitor 203 has one end connected to node N2 and the other end connected to ground, and capacitor 204 has one end connected to node N4 and the other end connected to ground.

[0089] In this embodiment, the inductance of the wiring 211 is approximately the same as the inductance of the wiring 212. The inductance of the wiring 221 is approximately the same as the inductance of the wiring 222.

[0090] FIG. 5 is a diagram showing schematic cross sections parallel to the xy plane of the power amplifier device 12 in which the power amplifier circuit 102 is formed.

[0091] As shown in FIG. 5, in the power amplifier device 12, electrodes 203E and 204E are further formed on the conductive layer 411 compared to the conductive layer 411 shown in FIGS.

[0092] The electrode 203E is, for example, a pad, and is provided on the -y-axis side of the end 211Es of the electrode 211E. The electrode 203E is electrically connected to the ground through a via 203V.

[0093] A component 203D that functions as the capacitor 203 in the power amplifier circuit 102 is connected to the upper side of the electrode 203E and the end portion 211Es. The component 203D is, for example, a surface-mounted device.

[0094] The electrode 204E is, for example, a pad, and is provided on the negative y-axis side of the end 221Es of the electrode 221E and on the positive x-axis side of the electrode 203E. The electrode 204E is electrically connected to the ground through a via 204V.

[0095] A component 204D that functions as the capacitor 204 in the power amplifier circuit 102 is connected to the upper side of the electrode 204E and the end portion 221Es. The component 204D is, for example, a surface-mounted device.

[0096] When the power amplifier device 12 is viewed from above, the electrode 231E has a shape that extends from an end 231Ef to an end 231Es while changing its extension direction.

[0097] In this embodiment, the electrode 231E extends from the end 231Ef to the end 231Es while changing its extension direction in the southwest direction and then in the south direction.

[0098] When the power amplifier device 12 is viewed from above, the electrode 232E of the conductive layer 412 has a shape that extends from the end 232Ef to the end 232Es while changing its extension direction.

[0099] In this embodiment, the electrode 232E extends from the end 232Ef to the end 232Es while changing its extension direction in the order of north, northeast, east, and northeast.

[0100] Third Embodiment A power amplifier device 13 according to a third embodiment will be described. Fig. 6 is a diagram schematically showing a cross section parallel to the zx plane of the power amplifier device 13 in which a power amplifier circuit 101 or 102 is formed.

[0101] In the power amplifier devices 11 and 12, the configuration in which the electrodes 211E, 221E, and 231E are provided on the conductive layer 411 and the configuration in which the electrodes 212E, 222E, and 232E are provided on the conductive layer 412 have been described, but the present invention is not limited to this. The first wiring 21, the second wiring 22, and the third wiring 23 may be provided on different conductive layers.

[0102] In this embodiment, the laminated substrate 401 in the power amplifier device 13 includes conductive layers 411, 412, and 413 (third conductive layers) and dielectric layers 421, 422, and 423. The dielectric layers 421, 422, and 423 are provided in this order from top to bottom.

[0103] The conductive layer 413 is located between the conductive layer 411 and the conductive layer 412. Specifically, the conductive layer 411 is provided on the upper surface of the dielectric layer 421. The conductive layer 413 is provided on the upper surface of the dielectric layer 422. The conductive layer 412 is provided on the upper surface of the dielectric layer 423.

[0104] The first wiring 21, the second wiring 22, and the third wiring 23 are provided on the conductive layer 411a, the conductive layer 411b, and the conductive layer 411c, respectively.

[0105] Specifically, the conductive layer 411 includes an electrode 22E that functions as the second wiring 22. The conductive layer 412 includes an electrode 21E that functions as the first wiring 21. The conductive layer 413 includes an electrode 23E that functions as the third wiring 23.

[0106] In the power amplifier device 13, when viewed from above, the electrodes 22E and 21E do not overlap. Specifically, the electrode 21E is located below the electrode 22E and on the positive side of the x-axis. The electrode 23E is located between the electrodes 22E and 21E.

[0107] [Fourth Embodiment] A power amplifier device 14 according to a fourth embodiment will be described. Fig. 7 is a diagram schematically showing a cross section parallel to the zx plane of the power amplifier device 14 in which a power amplifier circuit 101 or 102 is formed.

[0108] As shown in FIG. 7, the power amplifier device 14 according to the fourth embodiment differs from the power amplifier device 13 according to the third embodiment in that, when the power amplifier device 14 is viewed from above, the electrode 22E and the electrode 21E overlap.

[0109] Specifically, the electrode 21E is located below the electrode 22E, and the electrode 23E is located between the electrode 22E and the electrode 21E.

[0110] Fifth Embodiment A power amplifier device 15 according to a fifth embodiment will be described. Fig. 8 is a diagram schematically showing a cross section parallel to the zx plane of the power amplifier device 15 in which the power amplifier circuit 101 or 102 is formed.

[0111] As shown in Figure 8, the power amplifier device 15 of the fifth embodiment differs from the power amplifier device 13 of the third embodiment and the power amplifier device 14 of the fourth embodiment in that the electrode 23E is not provided between the electrode 21E and the electrode 22E.

[0112] In the power amplifier device 15, the electrode 21E is provided closer to the electrode 23E than the electrode 22E. That is, the distance between the electrode 21E and the electrode 23E is smaller than the distance between the electrode 21E and the electrode 22E.

[0113] The electrode 22E is provided closer to the electrode 23E than the electrode 21E. In other words, the distance between the electrode 22E and the electrode 23E is smaller than the distance between the electrode 22E and the electrode 21E.

[0114] Specifically, electrode 22E is provided on the upper surface of dielectric layer 421. Electrode 23E is located below electrode 22E and on the +x-axis side, and is embedded below the upper surface of dielectric layer 421. Electrode 21E is located above electrode 23E and on the +x-axis side, and is provided on the upper surface of dielectric layer 421.

[0115] In the present embodiment, the third wiring 23 is not provided between the wiring 213 and the wiring 223. However, the present invention is not limited to this. The third wiring 23 may be provided between the wiring 213 and the wiring 223.

[0116] Moreover, the third wiring 23 is preferably provided at a position where the first wiring 21 and the second wiring 22 are closest to each other, like the electrode 232E shown in FIG.

[0117] The above describes an exemplary embodiment of the present invention. In the power amplifier circuits 101 and 102, the carrier amplifier 51 amplifies a branch signal RF1 branched from a first signal, which is one of the balanced signals, and outputs an amplified signal RF5 from the output terminal 51a. The peak amplifier 52 amplifies a branch signal RF2 branched from the first signal and having a phase different from that of the branch signal RF1, and outputs an amplified signal RF6 from the output terminal 52a. The carrier amplifier 53 amplifies a branch signal RF3 branched from a second signal, which is the other of the balanced signals, and outputs an amplified signal RF7 from the output terminal 53a. The peak amplifier 54 amplifies a branch signal RF4 branched from the second signal and having a phase different from that of the branch signal RF3, and outputs an amplified signal RF8 from the output terminal 54a. The capacitor 201 has one end connected to the output terminal 51a and the other end connected to the output terminal 53a. The capacitor 202 has one end connected to the output terminal 52a and the other end connected to the output terminal 54a. The first wiring 21 has a first end connected to the output terminal 51a and a second end connected to the output terminal 52a. The second wiring 22 has a third end connected to the output terminal 53a and a fourth end connected to the output terminal 54a. The balun 61 is connected between the first wiring 21 and the second wiring 22. The third wiring 23 is electromagnetically coupled to the first wiring 21 and the second wiring 22, respectively, and is connected to ground. The first wiring 21 is disposed closer to the third wiring 23 than the second wiring 22. The second wiring 22 is disposed closer to the third wiring 23 than the first wiring 21.

[0118] In this manner, the first wiring 21 is provided closer to the third wiring 23 than the second wiring 22, the second wiring 22 is provided closer to the third wiring 23 than the first wiring 21, and the third wiring 23 is connected to ground, thereby suppressing electromagnetic coupling between the first wiring 21 and the second wiring 22. This suppresses a decrease in inductance of the first wiring 21 and the second wiring 22, and prevents excessive current from flowing through the first wiring 21 and the second wiring 22. Therefore, it is possible to provide a power amplifier circuit that can achieve good output characteristics.

[0119] In the power amplifier circuit 102, the first wiring 21 is provided with a node N1 located between the first end and the second end, and a node N2 located between the first end and node N1. The second wiring 22 is provided with a node N3 located between the third end and the fourth end, and a node N4 located between the third end and node N3. The balun 61 is connected between nodes N1 and N3. The capacitor 203 has one end connected to node N2 and the other end connected to ground. The capacitor 204 has one end connected to node N4 and the other end connected to ground.

[0120] The configuration of capacitor 201, wiring 211 having inductance, capacitor 203, wiring 212 having inductance, and capacitor 202 can function as a quarter-wave line for the fundamental wave. Similarly, the configuration of capacitor 201, wiring 221 having inductance, capacitor 204, wiring 222 having inductance, and capacitor 202 can function as a quarter-wave line for the fundamental wave. When viewed from carrier amplifier 51 toward peak amplifier 52, the configuration of wiring 211 and capacitor 203 can function as an LC series resonant circuit for the second harmonic wave. Therefore, a second harmonic termination circuit similar to harmonic trap 301 in power amplifier circuit 101 can be realized with a small circuit scale. The configuration of wiring 221 and capacitor 204 has the same effect as the configuration of wiring 211 and capacitor 203. Furthermore, when looking at the carrier amplifier 51 side from the peak amplifier 52, the configuration of the wiring 212 and the capacitor 203 can be made to function as an LC series resonant circuit for the second harmonic wave, so that a termination circuit for the second harmonic wave similar to the harmonic trap 302 in the power amplifier circuit 101 can be realized with a small circuit scale. The configuration of the wiring 222 and the capacitor 204 has the same effect as the configuration of the wiring 212 and the capacitor 203.

[0121] In the power amplifier circuits 101 and 102 , the third wiring 23 is provided between the first wiring 21 and the second wiring 22 .

[0122] With this configuration, the third wiring 23 can be positioned so that the line of sight from the first wiring 21 to the second wiring 22 is blocked, thereby effectively suppressing electromagnetic coupling between the first wiring 21 and the second wiring 22.

[0123] In the power amplifier circuits 101 and 102, the first wiring 21 is provided with a node N1 located between the first end and the second end. The second wiring 22 is provided with a node N3 located between the third end and the fourth end. The balun 61 is connected between the nodes N1 and N3. The third wiring 23 is provided between at least a portion of the first wiring 21 from the first end to the node N1 and at least a portion of the second wiring 22 from the third end to the node N3.

[0124] The first wiring 21 from the first end to the node N1 and the second wiring 22 from the third end to the node N3 function as quarter-wavelength lines, and because the line lengths are long, electromagnetic coupling between the first wiring 21 and the second wiring 22 is likely to be large. In contrast, by providing the third wiring 23 between at least a portion of the first wiring 21 from the first end to the node N1 and at least a portion of the second wiring 22 from the third end to the node N3, it is possible to effectively suppress electromagnetic coupling between the first wiring 21 and the second wiring 22.

[0125] In the power amplifier devices 11 to 15, a carrier amplifier 51, a peak amplifier 52, a carrier amplifier 53, and a peak amplifier 54 are formed on a semiconductor chip 501. On a laminated substrate 401, a first wiring 21, a second wiring 22, a third wiring 23, and a balun 61 are formed, and the semiconductor chip 501 is also provided.

[0126] In this way, the configuration in which the first wiring 21, the second wiring 22, the third wiring 23, and the balun 61, which have large circuit scales, are formed on the laminated substrate 401, increases the degree of freedom in the layout of the first wiring 21, the second wiring 22, the third wiring 23, and the balun 61. This makes it possible to easily realize an arrangement in which the third wiring 23 effectively suppresses electromagnetic coupling between the first wiring 21 and the second wiring 22.

[0127] In the power amplifier devices 11 and 12, the laminated substrate 401 includes a conductive layer 411. At least a portion of the first wiring 21, at least a portion of the second wiring 22, and at least a portion of the third wiring 23 are provided on the conductive layer 411.

[0128] With this configuration, for example, when the output terminal 51a of the carrier amplifier 51 and the output terminal 53a of the carrier amplifier 53 are provided on the same conductive layer and the first wiring 21 and the second wiring 22 are routed on that wiring layer, the third wiring 23 can be easily arranged so that the line of sight from the first wiring 21 to the second wiring 22 is blocked, for example, by routing the wiring.

[0129] In the power amplifier devices 13 and 14, the laminated substrate 401 includes a conductive layer 411, a conductive layer 412, and a conductive layer 413 between the conductive layers 411 and 412. The first wiring 21, the second wiring 22, and the third wiring 23 are provided on the conductive layers 411, 412, and 413, respectively.

[0130] With this configuration, for example, when the output terminal 51a of the carrier amplifier 51 and the output terminal 53a of the carrier amplifier 53 are provided on the conductive layers 411 and 412, respectively, and the first wiring 21 and the second wiring 22 are routed on different wiring layers, it is possible to easily realize, for example, an arrangement of the third wiring 23 such that the line of sight from the first wiring 21 to the second wiring 22 is blocked by routing the wiring.

[0131] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the scope of the present invention. The present invention may be modified or improved without departing from its spirit, and equivalents are also included within the scope of the present invention. In other words, designs modified by those skilled in the art as appropriate are also encompassed within the scope of the present invention as long as they incorporate the characteristics of the present invention. For example, the elements and their arrangements, materials, conditions, shapes, sizes, etc. of the embodiments are not limited to those illustrated and can be modified as appropriate. Furthermore, the embodiments are merely examples, and partial substitutions or combinations of the configurations shown in different embodiments are naturally possible. These are also encompassed within the scope of the present invention as long as they incorporate the characteristics of the present invention.

[0132] <1> A first carrier amplifier that amplifies a first branch signal branched from a first signal that is one of the balanced signals, and outputs the first amplified signal from a first output terminal; a first peak amplifier that amplifies a second branch signal branched from the first signal and having a phase different from that of the first branch signal, and outputs the second amplified signal from a second output terminal; a second carrier amplifier that amplifies a third branch signal branched from a second signal that is the other of the balanced signals, and outputs the third amplified signal from a third output terminal; a second peak amplifier that amplifies a fourth branch signal branched from the second signal and having a phase different from that of the third branch signal, and outputs the fourth amplified signal from a fourth output terminal; a first capacitor having one end connected to the first output terminal and the other end connected to the third output terminal; a second capacitor having one end connected to the second output terminal and the other end connected to the fourth output terminal; a first wiring having a first end connected to the first output terminal and a second end connected to the second output terminal; a second wiring having a third end connected to the third output terminal and a fourth end connected to the fourth output terminal; a balun connected between the first wiring and the second wiring; and a third wiring electromagnetically coupled to the first wiring and the second wiring, respectively, and connected to ground, wherein the first wiring is provided closer to the third wiring than the second wiring, and the second wiring is provided closer to the third wiring than the first wiring.

[0133] <2> The power amplifier circuit according to <1>, wherein the first wiring is provided with a first node located between the first end and the second end, and a second node located between the first end and the first node; the second wiring is provided with a third node located between the third end and the fourth end, and a fourth node located between the third end and the third node; the balun is connected between the first node and the third node; and the power amplifier circuit further includes: a third capacitor having one end connected to the second node and the other end connected to ground; and a fourth capacitor having one end connected to the fourth node and the other end connected to ground.

[0134] <3> The power amplifier circuit according to <1> or <2>, wherein the third wiring is provided between the first wiring and the second wiring.

[0135] <4> The power amplifier circuit according to any one of <1> to <3>, wherein the first wiring is provided with a first node located between the first end and the second end, the second wiring is provided with a third node located between the third end and the fourth end, the balun is connected between the first node and the third node, and the third wiring is provided between at least a portion of the first wiring from the first end to the first node and at least a portion of the second wiring from the third end to the third node.

[0136] <5> A power amplifier device having the power amplifier circuit according to any one of <1> to <4>, comprising: a semiconductor chip on which the first carrier amplifier, the first peak amplifier, the second carrier amplifier, and the second peak amplifier are formed; and a substrate on which the first wiring, the second wiring, the third wiring, and the balun are formed and on which the semiconductor chip is provided.

[0137] <6> The power amplifier circuit according to <5>, wherein the substrate includes a first conductive layer, and at least a portion of the first wiring, at least a portion of the second wiring, and at least a portion of the third wiring are provided on the first conductive layer.

[0138] <7> The power amplifier device according to <5> or <6>, wherein the substrate includes a first conductive layer, a second conductive layer, and a third conductive layer between the first conductive layer and the second conductive layer, and the first wiring, the second wiring, and the third wiring are provided on the first conductive layer, the second conductive layer, and the third conductive layer, respectively.

[0139] A first carrier amplifier that amplifies a first branched signal branched from a first signal that is one of the balanced signals, and outputs the first amplified signal from a first output terminal; a first peak amplifier that amplifies a second branched signal branched from the first signal and having a phase different from that of the first branched signal, and outputs the second amplified signal from a second output terminal; a second carrier amplifier that amplifies a third branched signal branched from a second signal that is the other of the balanced signals, and outputs the third amplified signal from a third output terminal; a second peak amplifier that amplifies a fourth branched signal branched from the second signal and having a phase different from that of the third branched signal, and outputs the fourth amplified signal from a fourth output terminal; a first capacitor having one end connected to the first output terminal and the other end connected to the third output terminal; a second capacitor having one end connected to the second output terminal and the other end connected to the fourth output terminal; a first wiring having a first end connected to the first output terminal and a second end connected to the second output terminal; a second wiring having a third end connected to the third output terminal and a fourth end connected to the fourth output terminal; a balun connected between the first wiring and the second wiring; and a third wiring electromagnetically coupled to the first wiring and the second wiring, respectively, and connected to ground, wherein the first wiring is provided with a first node located between the first end and the second end and a second node located between the first end and the first node, and the second wiring is provided with a third node located between the third end and the fourth end and a fourth node located between the third end and the third node, the balun being connected between the first node and the third node, and the power amplifier circuit further comprising: a third capacitor having one end connected to the second node and the other end connected to ground, and a fourth capacitor having one end connected to the fourth node and the other end connected to ground.

[0140] REFERENCE SIGNS LIST 11, 12, 13, 14, 15...power amplifier device 21...first wiring 211, 212, 213...wiring 21E, 211E...electrode 212E...electrode 212Va, 212Vb...via 22...second wiring 221, 222, 223...wiring 22E, 221E, 222E...electrode 222Va, 222Vb...via 23...third wiring 231, 232...wiring 23E, 231E, 232E...electrode 231V, 232V...via 32...output terminal 32 51, 53...carrier amplifier 52, 54...peak amplifier 51a, 52a, 53a, 54a...output terminal 61...balun 61a, 61b...inductor 61aE...electrode DESCRIPTION OF SYMBOLS 101, 102... Power amplifier circuit 141... Differential pair 151, 153... Doherty amplifier 201, 202, 203, 204, 205... Capacitors 201D, 202D, 203D, 204D, 205D... Components 203E, 204E... Electrodes 203V, 204V... Vias 301, 302, 303, 304... Harmonic trap 401... Laminated substrate 411, 412, 413... Conductive layers 421, 422, 423... Dielectric layers 501... Semiconductor chip N1, N2, N3, N4... Nodes

Claims

1. A first carrier amplifier that amplifies a first branch signal branched from a first signal that is one of the balanced signals and outputs a first amplified signal from a first output terminal; a first peak amplifier that amplifies a second branch signal branched from the first signal and having a different phase from the first branch signal and outputs a second amplified signal from a second output terminal; a second carrier amplifier that amplifies a third branch signal branched from a second signal that is the other of the balanced signals and outputs a third amplified signal from a third output terminal; a second peak amplifier that amplifies a fourth branch signal branched from the second signal and having a different phase from the third branch signal and outputs a fourth amplified signal from a fourth output terminal; a first capacitor having one end connected to the first output terminal and the other end connected to the third output terminal; a second capacitor having one end connected to the second output terminal and the other end connected to the fourth output terminal; a first wiring having a first end connected to the first output terminal and a second end connected to the second output terminal; a second wiring having a third end connected to the third output terminal and a fourth end connected to the fourth output terminal; a balun connected between the first wiring and the second wiring; and a third wiring electromagnetically coupled to the first wiring and the second wiring and connected to ground, wherein the first wiring is provided closer to the third wiring than the second wiring, and the second wiring is provided closer to the third wiring than the first wiring, a power amplification circuit.

2. The power amplification circuit according to claim 1, wherein the first wiring is provided with a first node located between the first end and the second end and a second node located between the first end and the first node; the second wiring is provided with a third node located between the third end and the fourth end and a fourth node located between the third end and the third node; the balun is connected between the first node and the third node; and the power amplification circuit further includes a third capacitor having one end connected to the second node and the other end connected to ground, and a fourth capacitor having one end connected to the fourth node and the other end connected to ground, a power amplification circuit.

3. The power amplification circuit according to claim 1 or 2, wherein the third wiring is provided between the first wiring and the second wiring. Power amplification circuit.

4. The power amplification circuit according to any one of claims 1 to 3, wherein a first node located between the first end and the second end is provided on the first wiring, and a third node located between the third end and the fourth end is provided on the second wiring. The balun is connected between the first node and the third node, and the third wiring is provided between at least a part of the first wiring from the first end to the first node and at least a part of the second wiring from the third end to the third node. Power amplification circuit.

5. A power amplification device having the power amplification circuit according to any one of claims 1 to 4, comprising: a semiconductor chip in which the first carrier amplifier, the first peak amplifier, the second carrier amplifier, and the second peak amplifier are formed; and a substrate on which the first wiring, the second wiring, the third wiring, and the balun are formed and on which the semiconductor chip is provided. Power amplification device.

6. The power amplification device according to claim 5, wherein the substrate includes a first conductive layer, and at least a part of the first wiring, at least a part of the second wiring, and at least a part of the third wiring are provided on the first conductive layer. Power amplification device.

7. The power amplification device according to claim 5 or 6, wherein the substrate includes a first conductive layer, a second conductive layer, and a third conductive layer between the first conductive layer and the second conductive layer, and the first wiring, the second wiring, and the third wiring are provided on the first conductive layer, the second conductive layer, and the third conductive layer, respectively. Power amplification device.

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