Arithmetic unit and electronic equipment

Abstract

[Problem] To provide an arithmetic unit and electronic equipment with which it is possible to improve arithmetic efficiency while reducing a layout area. [Solution] An arithmetic device according to the present disclosure comprises a plurality of capacitor units including a plurality of first capacitors each having one end connected to a first signal line, and a plurality of first switch circuits respectively connected to the other ends of the plurality of first capacitors. The plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors on the basis of a first digital value, convert the first digital value to a second digital value, and multiply the second digital value and the first input voltage. The plurality of capacitor units output a voltage corresponding to the multiplication result of the first input voltage and the second digital value to the first signal line.

Description

Computing and Electronic Devices

[0001] The present disclosure relates to computing devices and electronic devices.

[0002] Machine learning such as deep learning requires repeated multiply-and-accumulate operations using neural networks, and there is a need to perform these operations efficiently and in a small area.

[0003] Hechen Wang et,al. “A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference”VLSI2022,IntelGopalAdhikari, Richen Jiang, Haruo Kobayashi ”Study of Gray Code Input DAC Using MOSFETs for Glitch Reduction”2016IEEE extension: / / efaidnbmnnnibpcajpcglclefindmkaj / https: / / kobaweb.ei.st.gunma-u.ac.jp / news / pdf / 2016 / S06-3.pdfextension: / / efaidnbmnnnibpcajpcglclefindmkaj / https: / / kobaweb.ei.st.gunma-u.ac.jp / lecture / GrayCodeDAC.pdf

[0004] Japanese Patent Application Laid-Open No. 2022-061162

[0005] However, conventional multipliers used in multiply-and-accumulate operations convert the Gray code from a CMOS (Complementary Metal Oxide Semiconductor) Image Sensor (CIS) into a binary code before performing the multiplication. In this case, a Gray code-to-binary code conversion circuit is required separately from the multiplier, which causes a deterioration in calculation efficiency and an increase in layout area.

[0006] Therefore, the present disclosure provides a computing device and electronic equipment that can improve computing efficiency while reducing the layout area.

[0007] An arithmetic device according to one aspect of the present disclosure includes a plurality of capacitor units, each including a plurality of first capacitors, one end of which is connected to a first signal line, and a plurality of first switch circuits, each connected to the other end of the plurality of first capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors based on a first digital value to convert the first digital value to a second digital value and multiply the second digital value by the first input voltage, and the plurality of capacitor units output a voltage to the first signal line according to the multiplication result of the first input voltage and the second digital value.

[0008] The capacitance of the plurality of first capacitors is 2 ｎ (n is an integer of 0 or more).

[0009] Another aspect of the present disclosure provides an arithmetic device including a plurality of capacitor units including a first capacitor connected between a first node and a reference voltage source, a plurality of second capacitors connected in series between the first node and a first signal line, a plurality of third capacitors each having one end connected to the first node and a second node between adjacent second capacitors, and a plurality of first switch circuits each connected to the other end of the plurality of third capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of third capacitors based on a first digital value to convert the first digital value to a second digital value and multiply the second digital value by the first input voltage, and the plurality of capacitor units output a voltage to the first signal line according to the multiplication result of the first input voltage and the second digital value.

[0010] At least one of the first input voltage and the first digital value is a digital signal expressed in Gray code, and the second digital value is a binary code.

[0011] The outputs from the plurality of capacitor units are added together in charge on a first signal line to form an analog value.

[0012] A computing device according to another aspect of the present disclosure further includes a first wiring that transmits a first input voltage and a second wiring that transmits a reference voltage, and the plurality of first switch circuits include a first switch element that makes the first wiring conductive or non-conductive, a second switch element that makes the second wiring conductive or non-conductive, and third and fourth switch elements that make the first wiring and the second wiring conductive or non-conductive, the third switch element being connected between one end of the first switch element and the other end of the second switch element, and the fourth switch element being connected between the other end of the first switch element and one end of the second switch element.

[0013] The plurality of first switch circuits each input one bit of a first digital value, and when the corresponding bit of the first digital value is a first logic, the first and second switch elements are in a conductive state and the third and fourth switch elements are in a non-conductive state, and when the corresponding bit of the first digital value is a second logic, the first and second switch elements are in a non-conductive state and the third and fourth switch elements are in a conductive state.

[0014] The plurality of capacitor units receive the same first digital value and each receive a first input voltage that is set for each capacitor unit.

[0015] The capacitance of the second capacitor is approximately twice the capacitance of the first and third capacitors.

[0016] The plurality of capacitor units include a plurality of fourth capacitors each having one end connected to the first node and a second node between adjacent second capacitors, and a plurality of second switch circuits each connected to the other end of the plurality of fourth capacitors, the plurality of second switch circuits applying either a first input voltage or a reference voltage to the other ends of the plurality of fourth capacitors based on the first digital value, and converting the first digital value into a second digital value together with the plurality of first switch circuits.

[0017] At least one of the first input voltage and the first digital value is a digital signal expressed in Gray code, and the second digital value is a binary code.

[0018] The outputs from the plurality of capacitor units are added together in charge on a first signal line to form an analog value.

[0019] The arithmetic device further includes a third wiring that transmits a first input voltage and a fourth wiring that transmits a reference voltage, and the plurality of second switch circuits include a fifth switch element that makes the third wiring conductive or non-conductive, a sixth switch element that makes the fourth wiring conductive or non-conductive, and seventh and eighth switch elements that make the third wiring and the fourth wiring conductive or non-conductive, the seventh switch element being connected between one end of the fifth switch element and the other end of the sixth switch element, and the eighth switch element being connected between the other end of the fifth switch element and one end of the sixth switch element.

[0020] The plurality of second switch circuits each input one bit of the first digital value, and when the corresponding bit of the first digital value is a first logic, the fifth and sixth switch elements are in a conductive state and the seventh and eighth switch elements are in a non-conductive state, and when the corresponding bit of the first digital value is a second logic, the fifth and sixth switch elements are in a non-conductive state and the seventh and eighth switch elements are in a conductive state.

[0021] The plurality of second switch circuits input a first digital value that is separate from the plurality of first switch circuits, and input a first input voltage that is set to the plurality of second switch circuits separately from the plurality of first switch circuits.

[0022] The third and fourth capacitors have approximately the same capacitance.

[0023] The arithmetic device includes a ninth switch element provided between the first wiring and the third wiring, a tenth switch element connected to the first wiring and transmitting or not transmitting a third digital value to the first wiring, and an eleventh switch element connected to the third wiring and transmitting or not transmitting a fourth digital value to the third wiring.

[0024] The ninth switch element and the tenth or eleventh switch element are alternately turned on and off to generate a first input voltage, and when a voltage corresponding to the multiplication of the first input voltage and the first digital value is output to the first signal line, the ninth switch element is turned on and the tenth and eleventh switch elements are turned off, thereby maintaining the first input voltage on the first and second input voltage lines.

[0025] The ninth to eleventh switch elements are digital-to-analog conversion circuits.

[0026] The arithmetic unit further includes an analog-to-digital conversion circuit connected to the first signal line.

[0027] The arithmetic device includes a first semiconductor layer having a light receiving portion that photoelectrically converts incident light to generate an electrical signal, and a second semiconductor layer stacked on the first semiconductor layer and having a circuit that AD converts the electrical signal.

[0028] The arithmetic device further includes a third semiconductor layer stacked on the first and second semiconductor layers and including a plurality of first switch circuits and a plurality of capacitor units.

[0029] The second semiconductor layer further includes a storage unit that temporarily stores the first digital value or the multiplication result.

[0030] An electronic device according to one aspect of the present disclosure includes a plurality of capacitor units each including a plurality of first capacitors, one end of which is connected to a first signal line, and a plurality of first switch circuits, each connected to the other end of the plurality of first capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors based on a first digital value to convert the first digital value to a second digital value, and the plurality of capacitor units output a voltage to the first signal line corresponding to the multiplication of the first input voltage and the second digital value.

[0031] The electronic device is a CMOS image sensor.

[0032] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. 2 is a block diagram showing an example of the configuration of a solid-state imaging element according to the first embodiment. 3 is a block diagram showing an example of the configuration of a column ADC according to the first embodiment. 4 is a block diagram showing an example of the configuration of a computing unit according to the first embodiment. 5 is a circuit diagram showing an example of the configuration of a switch circuit. 6 is a conceptual diagram showing the switching state of a switch circuit. 7 is a conceptual diagram showing the switching state of a switch circuit. 8 is a block diagram showing an example of the configuration of a computing unit according to a third embodiment. 9 is a timing diagram showing an example of the operation of an input generation circuit. 10 is a block diagram showing an input generation circuit according to a fourth embodiment. 11 is a block diagram showing an example of the configuration of an imaging device according to a fifth embodiment. 12 is a block diagram showing an example of the configuration of a column ADC according to a sixth embodiment. 13 is a block diagram showing an example of the configuration of a column ADC according to a seventh embodiment. 14 is a block diagram showing an example of the configuration of a column ADC according to an eighth embodiment. 15 is a timing diagram showing an example of the operation of an imaging device according to a ninth embodiment. 16 is a timing diagram showing an example of the operation of an imaging device according to a tenth embodiment. 17 is a timing diagram showing an example of the operation of an imaging device according to an eleventh embodiment. 18 is a timing diagram showing an example of the operation of an imaging device according to a twelfth embodiment. 1 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0033] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0034] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment. The imaging device 100 is, for example, a CIS that captures image data, and includes an optical unit 110, a solid-state imaging element 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 also includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 may be, for example, a digital camera such as a digital still camera, as well as a smartphone, personal computer, or in-vehicle camera that has an imaging function.

[0035] The optical unit 110 is an optical system that collects light from a subject and guides it to the solid-state imaging device 200. The solid-state imaging device 200 generates image data through photoelectric conversion in synchronization with a vertical synchronization signal VSYNC. The vertical synchronization signal VSYNC is a periodic signal with a predetermined frequency that indicates the timing of imaging. The solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0036] The DSP circuit 120 performs predetermined signal processing on the image data from the solid-state imaging device 200. The DSP circuit 120 outputs the processed image data via the bus 150 to a frame memory 160 or the like.

[0037] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0038] The bus 150 is a common path for the optical unit 110, solid-state image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0039] The frame memory 160 temporarily stores image data. The frame memory 160 may be, for example, a static random access memory (SRAM), a dynamic RAM (DRAM), or a flash memory. The storage unit 170 stores various data such as image data. The storage unit 170 may be a solid state drive (SSD), a hard disk drive (HDD), or the like. The power supply unit 180 supplies power to the solid-state imaging element 200, the DSP circuit 120, the display unit 130, and the like.

[0040] 2 is a block diagram showing an example of the configuration of a solid-state imaging device 200 according to the first embodiment. The solid-state imaging device 200 includes a timing control unit 210, a vertical scanning circuit 220, a pixel array unit 230, a column ADC (Analog to Digital Converter) 300, and a horizontal transfer circuit 240. In the pixel array unit 230, a plurality of pixels 231 are two-dimensionally arranged in a matrix.

[0041] The timing control section 210 controls the operation timing of each of the vertical scanning circuit 220, the column ADC 300, and the horizontal transfer circuit 240 in synchronization with the vertical synchronization signal VSYNC.

[0042] The vertical scanning circuit 220 sequentially drives rows of the pixels 231 to output analog pixel signals. The pixels 231 photoelectrically convert incident light to generate pixel signals under the control of the vertical scanning circuit 220, and output the pixel signals to the column ADC 300.

[0043] The column ADC 300 performs AD (Analog to Digital) conversion on pixel signals of each column, and supplies the AD-converted digital signals to the horizontal transfer circuit 240 as pixel data.

[0044] The horizontal transfer circuit 240 sequentially outputs the pixel data to the DSP circuit 120. The image data in which the pixel data is arranged is processed by the DSP circuit 120.

[0045] 3 is a block diagram showing an example of the configuration of a column ADC 300 according to the first embodiment. The column ADC 300 includes a phase-locked loop 310, a Gray code counter 320, and a DAC (Digital to Converter) 330. The column ADC 300 also includes, for each column, a comparator 340, a Gray code TDC 400, and an arithmetic unit 360. When the number of columns is K (K is an integer), K comparators 340, Gray code TDCs 400, and arithmetic units 360 are provided.

[0046] The phase locked loop 310 generates a predetermined periodic signal. For example, the phase locked loop 310 generates a clock signal CLKp as the periodic signal and supplies it to the Gray code counter 320.

[0047] The Gray code counter 320 counts a count value in synchronization with the clock signal CLKp. The Gray code counter 320 generates a Gray code indicating the count value as an upper code MGC and supplies it to the DAC 330 and each of the Gray code TDCs 400. The data size of the upper code MGC is M (M is an integer) bits. The mth (m is an integer from 0 to M-1) bit of the upper code MGC is defined as MGC[m]. Of the M bits, MGC[0] is the least significant bit (LSB), and this bit is also supplied to each of the Gray code TDCs 400.

[0048] The DAC 330 generates a predetermined reference signal RMP by digital-to-analog conversion in synchronization with the upper code MGC from the Gray code counter 320. For example, a sawtooth ramp signal is generated as the reference signal RMP. The DAC 330 supplies the reference signal RMP to each of the comparators 340.

[0049] The selection unit 235 selectively sends either the pixel signal Vin from the pixel array unit 230 or the calculation result from the calculator 360 to the comparator 340. The selection unit 235 can also output the calculation result from the calculator 360 to the outside. In this way, the selection unit 235 is configured with a switch circuit so that the input signal to the comparator 340 can be switched.

[0050] The comparator 340 has two input terminals. One of the input terminals receives the pixel signal Vin (analog signal) from the pixel in the corresponding column or the product-sum operation result (analog signal) from the calculator 360, and the other receives the reference signal RMP from the DAC 330. The comparator 340 compares the pixel signal Vin with the reference signal RMP and outputs the comparison result CMP to the Gray code TDC 400.

[0051] The Gray code TDC 400 continues to write data to itself until the comparison result CMP in the comparator 340 is inverted, and latches the time code at the same time as the inversion. The Gray code TDC 400 supplies the Gray code to the arithmetic unit 360. The data size is N bits (N is an integer).

[0052] The Gray code TDC 400 includes a latch circuit and supplies the held Gray code to the calculator 360.

[0053] The calculator 360 is composed of multiple capacitor units that convert the Gray code from the Gray code TDC 400 into a binary code and multiply the binary code by a set voltage. Furthermore, the calculator 360 adds the charges of the multiplication results from the multiple capacitor units and outputs the result as an analog value. That is, the calculator 360 performs a multiply-and-accumulate operation on the binary code and the set voltage and outputs the result as an analog value. The analog value resulting from the multiply-and-accumulate operation may be returned to the selection unit 235 and input again to the comparator 340 of each column. Alternatively, the analog value resulting from the multiply-and-accumulate operation may be output from the selection unit 235 and AD-converted to a binary code or Gray code. When further performing a multiply-and-accumulate operation on the analog value resulting from the multiply-and-accumulate operation, the analog value resulting from the multiply-and-accumulate operation may be input to the same column ADC 300 and subjected to the multiply-and-accumulate operation therein, or may be subjected to the multiply-and-accumulate operation in another column ADC. The calculator 360 may output the analog value resulting from the multiply-and-accumulate operation to an external device.

[0054] The control circuit 370 controls the voltage of the input value Iact input to the arithmetic unit 360. The voltage of the input value Iact is a voltage multiplied by the Gray code, and is set to a predetermined value for each of the plurality of capacitor units.

[0055] FIG. 4 is a block diagram showing an example configuration of a computing unit 360 according to the first embodiment. The computing unit 360 includes a plurality of capacitor units CU1 and CU2. The plurality of capacitor units CU1 and CU2 in the same column are commonly connected to the same signal line VSL of the corresponding column. Note that FIG. 4 illustrates two capacitor units CU1 and CU2 in the same column. However, the number of capacitor units CU may be three or more. Similarly, a plurality of capacitor units CU are connected to the signal line VSL of other columns.

[0056] Since the plurality of capacitor units CU1 and CU2 each have the same configuration, the configuration of the capacitor unit CU1 will be described, and the description of the configuration of the other capacitor unit CU2 will be omitted.

[0057] The capacitor unit CU1 includes a plurality of capacitors C1 to C4 and a plurality of switch circuits SWC1 to SWC4. The switch circuits SWC1 to SWC4 are provided corresponding to the capacitors C1 to C4, respectively. The number of capacitors C and the number of switch circuits SWC are not limited.

[0058] The capacitors C1 to C4 may be MIM capacitances or parasitic capacitances such as wiring capacitances. One end of each of the capacitors C1 to C4 is connected to the signal line VSL. The other end of each of the capacitors C1 to C4 is connected to a plurality of switch circuits SWC1 to SWC4. The capacitances of the plurality of capacitors C1 to C4 are 1c, 2c, 4c, and 8c (c is an arbitrary unit capacitance), respectively. That is, the capacitances of the plurality of capacitors C1 to C4 are 2 ｎ (n is an integer of 0 or more).

[0059] The switch circuits SWC1 to SWC4 receive Gray codes (W0[0], W0[1], W0[2], W0[3]) as digital values. The Gray codes (W0[0], W0[1], W0[2], W0[3]) are Gray codes output from the Gray code TDC 400. The Gray codes (W0[0], W0[1], W0[2], W0[3]) are, for example, composed of four bits, but the number of bits of the Gray code is not limited. W0[0] to W0[3] each represent one bit of one Gray code.

[0060] The switch circuits SWC1 to SWC4 are connected in series to an input voltage line Lact that transmits an input value Iact_p[0]. The input value Iact_p[0] is a signal output from the control circuit 370, and its voltage may be an analog value that is set arbitrarily in advance. The switch circuits SWC1 to SWC4 are connected in series to a reference voltage line Lgnd that transmits a reference voltage (for example, a ground voltage).

[0061] The switch circuits SWC1 to SWC4 apply either the input value Iact_p[0] or a reference voltage to the other ends of the capacitors C1 to C4 based on the Gray code (W0[0], W0[1], W0[2], W0[3]). As a result, the switch circuits SWC1 to SWC4 convert the Gray code (W0[0], W0[1], W0[2], W0[3]) into a binary code and apply either the input value Iact_p[0] or a reference voltage to the capacitors C1 to C4. The capacitor unit CU1 outputs a voltage (multiplication result) corresponding to the multiplication of the input value Iact_p[0] and the binary code converted from the Gray code (W0[0], W0[1], W0[2], W0[3]) to the signal line VSL.

[0062] The capacitor units CU1 and CU2 in the same column are connected to a single signal line VSL. The capacitor units CU1 and CU2 receive input values ​​Iact_p[0] and Iact_p[1], respectively. The capacitor units CU1 and CU2 may receive different Gray codes or may receive a common Gray code (W0[0], W0[1], W0[2], W0[3]). As a result, the capacitor units CU1 and CU2 output voltages (multiplication results) corresponding to the multiplication of the input values ​​Iact_p[0] and Iact_p[1] by the binary code converted from the Gray code (W0[0], W0[1], W0[2], W0[3]) to the signal line VSL. The multiplication results of the capacitor units CU1 and CU2 are added together as charges on the signal line VSL and transmitted as analog values. This analog value may be converted into a digital value by an ADC connected to the signal line VSL. In this way, the calculator 360 can perform a multiply-and-accumulate operation between the input value and the binary code converted from the Gray code.

[0063] 5 is a circuit diagram showing an example of the configuration of the switch circuit SWC1. The configuration of the switch circuits SWC2 to SWC4 may be the same as that of the switch circuit SWC1, so detailed description thereof will be omitted.

[0064] The switch circuit SWC1 includes switch elements SW1 to SW4. The switch element SW1 is provided on the line L1 and turns the line L1 on or off. When the switch element SW1 is on, it electrically connects the input In1 and the output Out1. The switch element SW2 is provided on the line L2 and turns the line L2 on or off. When the switch element SW2 is on, it electrically connects the input In2 and the output Out2.

[0065] The switch element SW3 is connected between the output Out1 side end of the switch element SW1 and the input In2 side end of the switch element SW2, and turns the line L1 and the line L2 into a conductive state (ON) or a non-conductive state (OFF). The switch element SW4 is connected between the input In1 side end of the switch element SW1 and the output Out2 side end of the switch element SW2, and turns the line L1 and the line L2 into a conductive state (ON) or a non-conductive state (OFF). In this way, the switch elements SW3 and SW4 are cross-connected, and turn the output Out1 and the input In2, and the output Out2 and the input In1 into a conductive state (ON) or a non-conductive state (OFF), respectively.

[0066] The switch elements SW1 to SW4 may be configured, for example, by MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0067] The switch elements SW1 and SW2 and the switch elements SW3 and SW4 operate complementarily. Therefore, when the switch elements SW1 and SW2 are on, the switch elements SW3 and SW4 are off, and when the switch elements SW3 and SW4 are on, the switch elements SW1 and SW2 are off.

[0068] This allows the switch circuit SWC1 to assume the switching states shown in FIGS.

[0069] 6 and 7 are conceptual diagrams showing the switching states of the switch circuit SWC1. FIG. 6 shows the switching states when switch elements SW1 and SW2 are on and switch elements SW3 and SW4 are off. In this case, line L1 connects input In1 to output Out1, and line L2 connects input In2 to output Out2. Thus, line L1 and L2 are connected in parallel. On the other hand, FIG. 7 shows the switching states when switch elements SW3 and SW4 are on and switch elements SW1 and SW2 are off. In this case, line L1 connects input In2 to output Out1, and line L2 connects input In1 to output Out2. Thus, line L1 and L2 are cross-connected.

[0070] The switching state in FIG. 6 is defined as the first bit of the Gray code being the first logic (e.g., W0[0]=0), and the switching state in FIG. 7 is defined as the first bit of the Gray code being the second logic (e.g., W0[0]=1).

[0071] The switch circuits SWC2 to SWC4 have the same configuration as the switch circuit SWC1. The output Out1 of each of the switch circuits SWC1 to SWC4 is connected to the input In1, and the output Out2 is connected to the input In2. The switch circuits SWC1 to SWC4 are connected in series as shown in Figure 4, with the input In1 of the switch circuit SWC4 at one end connected to the input voltage line Lact and the input In2 of the switch circuit SWC4 connected to the reference voltage line Lgnd.

[0072] Referring again to Figure 4, the switch circuits SWC1 to SWC4 each receive the Gray code bits W0[0], W0[1], W0[2], and W0[3] and enter a switching state according to the logic of each bit. As a result, the wiring L1 and L2 of the switch circuits SWC1 to SWC4 are connected in parallel (Figure 6) or cross-connected (Figure 7), and electrically connected to either the input voltage line Lact or the reference voltage line Lgnd.

[0073] 4, the switch circuits SWC1 to SWC4 are connected in series, and the inputs In1 and In2 of the switch circuit SWC4 at one end are connected to the input voltage line Lact and the reference voltage line Lgnd. Therefore, for example, the switch circuit SWC3 is connected to the input voltage line Lact and the reference voltage line Lgnd via the switch circuit SWC4, the switch circuit SWC2 is connected to the input voltage line Lact and the reference voltage line Lgnd via the switch circuits SWC3 and SWC4, and the switch circuit SWC1 is connected to the input voltage line Lact and the reference voltage line Lgnd via the switch circuits SWC2 to SWC4. Therefore, depending on the switching state of the switch circuit SWC4, the voltage line connected to the inputs In1 and In2 of the switch circuit SWC3 switches between the input voltage line Lact and the reference voltage line Lgnd. Depending on the switching states of the switch circuits SWC3 and SWC4, the voltage lines connected to the inputs In1 and In2 of the switch circuit SWC2 switch between the input voltage line Lact and the reference voltage line Lgnd. Depending on the switching states of the switch circuits SWC2 to SWC4, the voltage lines connected to the inputs In1 and In2 of the switch circuit SWC1 switch between the input voltage line Lact and the reference voltage line Lgnd.

[0074] With this configuration, the switch circuits SWC1 to SWC4 of the capacitor unit CU1 selectively apply either the input value Iact_p[0] or a reference voltage to the other ends of the capacitors C1 to C4 based on the Gray code (W0[0], W0[1], W0[2], W0[3]) as the first digital value. As a result, the switch circuits SWC1 to SWC4 convert the Gray code (W0[0], W0[1], W0[2], W0[3]) into a binary code as the second digital value, and multiply the converted binary code by the input value Iact_p[0].

[0075] The parallel-connected capacitors C1 to C4 output a voltage according to the multiplication result of the input value and the gray code converted into binary code. The capacitance of the capacitors C1 to C4 is 2 ｎ Therefore, a voltage (analog value) according to the multiplication result is transmitted to the signal line VSL.

[0076] The other capacitor unit CU2 operates in the same manner as the capacitor unit CU1. The capacitor unit CU2 receives a Gray code (W1[0], W1[1], W1[2], W1[3]) different from that of the capacitor unit CU1, and receives an input value Iact_p[1] set separately from the input value Iact_p[0]. The Gray code and the input value Iact_p[1] may be different from or the same as W0 and the input value Iact_p[0].

[0077] The switch circuits SWC1 to SWC4 of the capacitor unit CU2 selectively apply either the input value Iact_p[1] or a reference voltage to the other ends of the capacitors C1 to C4 of the capacitor unit CU2 based on the Gray code (W1[0], W1[1], W1[2], W1[3]). As a result, the switch circuits SWC1 to SWC4 convert the Gray code (W1[0], W1[1], W1[2], W1[3]) into a binary code and multiply the Gray code (W1[0], W1[1], W1[2], W1[3]) by the input value Iact_p[1]. That is, in capacitor unit CU2, the Gray code (W1[0], W1[1], W1[2], W1[3]) is converted into a binary code, multiplied by the input value Iact_p[1], and applied to the other ends of capacitors C1 to C4.

[0078] In the capacitor unit CU2, the parallel-connected capacitors C1 to C4 output a voltage according to the multiplication result of the input value and the gray code converted into binary code. ｎ Therefore, a voltage (analog value) according to the multiplication result is transmitted to the signal line VSL.

[0079] The multiplication results output from the capacitor units CU1 and CU2 to the signal line VSL are added together as charges on the signal line VSL. If there are other capacitor units CU3, CU4, etc. connected to the same signal line VSL, the multiplication results of these capacitor units CU3, CU4, etc. are also added together as charges on the signal line VSL.

[0080] Furthermore, a plurality of signal lines VSL may be provided. A plurality of capacitor units CU may be provided on each signal line VSL. The plurality of capacitor units CU connected to each signal line VSL operate in the same manner as capacitor units CU1 and CU2. The plurality of capacitor units CU connected to each signal line VSL may input a common Gray code, or may input different Gray codes from each other. The plurality of capacitor units CU connected to each signal line VSL may input a common input value, or may input different input values ​​from each other.

[0081] 4, for example, assume that a plurality of signal lines VSL extending in the Z direction are arranged in the X and Y directions. In this case, the capacitor units CU of the plurality of signal lines VSL arranged in the X direction may input a common input value Iact_p[i] (i is an integer equal to or greater than 2), and the capacitor units CU of the plurality of signal lines VSL arranged in the Y direction may input different input values ​​Iact_p[i]. The plurality of signal lines VSL may input different Gray codes (Wi[0], Wi[1], Wi[2], Wi[3]).

[0082] In this way, the calculator 360 can output the sum-of-products operation of the Gray code (Wi[0], Wi[1], Wi[2], Wi[3]) and the input value Iact_p[i] as an analog value on multiple signal lines VSL.

[0083] According to this embodiment, the switch circuits SWC1 to SWC4 perform both the conversion from Gray code to binary code and the switching for multiplying the binary code by the input value. Therefore, there is no need to provide a separate Gray code to binary code conversion circuit. Therefore, since there is no need to convert Gray code to binary code by outputting the data to the outside of the pixel array unit 230 and the ADC 300, it is possible to provide the arithmetic unit 360 in another semiconductor layer directly below the semiconductor layer of the pixel array unit 230, for example, and perform a product-sum operation between the Gray code and the input value. As a result, the arithmetic efficiency is improved and the layout area of ​​the circuit is reduced.

[0084] Furthermore, if the result of the product-sum operation output from the calculator 360 is AD converted into a Gray code, the Gray code can be further recursively fed back to the calculator 360. This allows the calculator 360 to be applied to a neural network.

[0085] Second Embodiment Fig. 8 is a block diagram showing an example of the configuration of a computing unit 360 according to a second embodiment. Although Fig. 8 illustrates one signal line VSL, multiple signal lines VSL may be provided, as in the first embodiment. The number of capacitor units CU is also not limited, and may be two or more.

[0086] The second embodiment differs from the first embodiment in the configuration of the capacitors C11 to C13.

[0087] The capacitor unit CU1 includes capacitors C11 to C13. One capacitor C11 is connected between a node N1 and a reference voltage source (e.g., ground). A plurality of capacitors C12 are connected in series between the node N1 and a signal line VSL. One end of each of the plurality of capacitors C13 is connected to the node N1 and a node N2 between adjacent plurality of capacitors C12. The capacitors C11 and C13 have approximately the same capacitance c, and the capacitor C12 has a capacitance 2c that is approximately twice the capacitance of the capacitors C11 and C13.

[0088] The switch circuits SWC1 to SWC4 are connected to the other ends of the plurality of capacitors C13, respectively.

[0089] Other configurations of the second embodiment may be the same as those of the first embodiment.

[0090] Even with the capacitor configuration of the second embodiment, the calculator 360 can output the product-sum operation of the Gray code and the input value as an analog value on the multiple signal lines VSL. Therefore, the second embodiment can have a configuration similar to that of the first embodiment.

[0091] 9 is a block diagram showing an example of the configuration of a computing unit 360 according to a third embodiment. Although one signal line VSL is shown in FIG. 9, multiple signal lines VSL may be provided, as in the first embodiment. Furthermore, the number of capacitor units CU is not limited, and may be two or more.

[0092] In the third embodiment, each of the plurality of capacitors C13 in the second embodiment is divided into a capacitor C13a and a capacitor C13b. The capacitances of capacitors C13a-C13a and capacitors C13b-C13b are equal to 0.5c, which is half the capacitance c of capacitor C11. One ends of capacitors C13a and C13b corresponding to switch circuits SWC1a and SWC1b at the ends of capacitor unit CU1 are connected to node N1. One ends of the remaining plurality of capacitors C13a and C13b are connected to multiple nodes N2.

[0093] The switch circuits SWC1a to SWC4a correspond to the switch circuits SWC1 to SWC4 in the second embodiment. Furthermore, in the third embodiment, switch circuits SWC1b to SWC4b are added. The switch circuits SWC1a to SWC4a serving as first switch circuits are connected to the other ends of the plurality of capacitors C13a, respectively. The switch circuits SWC1b to SWC4b serving as second switch circuits are connected to the other ends of the plurality of capacitors C13b, respectively. The switch circuits SWC1a to SWC4a and the switch circuits SWC1b to SWC4b each input a common Gray code (W0[0], W0[1], W0[2], W0[3]).

[0094] The internal configuration of each of the switch circuits SWC1a to SWC4a and SWC1b to SWC4b may be the same as that of the switch circuit SWC1. In this case, for example, if the configuration of FIG. 5 is applied to the switch circuit SWC1b as the second switch circuit, the switch circuit SWC1b includes a switch element SW1 that turns on or off a line L1 (e.g., Lact), a switch element SW2 that turns on or off a line L2 (e.g., Lgnd), and switch elements SW3 and SW4 that turn on or off the connection between the line L1 and the line L2. The switch element SW3 is connected between one end of the switch element SW1 and the other end of the switch element SW2. The switch element SW4 is connected between the other end of the switch element SW1 and one end of the switch element SW2.

[0095] 9, switch circuits SWC1b to SWC4b each receive one bit of Gray code (W0[0], W0[1], W0[2], W0[3]). Depending on the logic of the corresponding bits of Gray code (W0[0], W0[1], W0[2], W0[3]), switch elements SW1 and SW2 in FIG. 5 are conductive and switch elements SW3 and SW4 are non-conductive, or switch elements SW3 and SW4 are conductive and switch elements SW1 and SW2 are non-conductive.

[0096] Therefore, the switch circuits SWC1b to SWC4b apply either the input values ​​Iact_p[0], Iact_n[0] or a reference voltage to the other ends of the capacitors C13b based on the Gray code, and convert the Gray code to binary code together with the switch circuits SWC1a to SWC4a. Note that the input values ​​Iact_p[0], Iact_n[0] are set to the same analog value in the input generation circuit GENIact.

[0097] The input generating circuit GENIact is connected to two input parts of the capacitor unit CU1, which are analog input values ​​Iact_p[0] and Iact_n[0]. The input generating circuit GENIact includes switch elements SWp, SWn, and SWshort.

[0098] The switch elements SWp and SWn can receive digital values ​​and transmit them to the input side of the capacitor unit CU1. For example, the switch element SWp is connected to a line Lactp and is controlled to be on or off based on a control signal INCTRLp. The switch element SWp transmits or does not transmit the digital value ACTp to one input section (line Lactp) of the capacitor unit CU1. For example, the switch element SWn is connected to a line Lactn and is controlled to be on or off based on a control signal INCTRLn. The switch element SWn transmits or does not transmit the digital value ACTn to the other input section (line Lactn) of the capacitor unit CU1. The digital values ​​ACTp and ACTn are basically digital values ​​of opposite logic, but may also be digital values ​​of the same logic. The high level of the digital value may be, for example, a power supply voltage. The low level of the digital value may be, for example, a ground voltage.

[0099] The switch element SWshort is connected between the two input parts of the capacitor unit CU1 (i.e., between the line Lactp and the line Lactn) and is controlled to be on or off based on the control signal INSHORT. The switch element SWshort shorts or separates the line Lactp and the line Lactn.

[0100] The switch elements SWp, SWn, and SWshort may be configured, for example, by n-type MOSFETs.

[0101] With this configuration, the input generation circuit GENIact receives the digital values ​​ACTp and ACTn and generates analog input values ​​Iact_p[0] and Iact_n[0]. The input generation circuit GENIact transmits the input values ​​Iact_p[0] and Iact_n[0] to the wirings Lactp and Lactn, respectively.

[0102] To generate the input values ​​Iact_p[0] and Iact_n[0], the input generating circuit GENIact operates at least one of the switch elements SWp and SWn and the switch element SWshort in a complementary manner. Therefore, when at least one of the switch elements SWp and SWn is in the on state, the switch element SWshort is in the off state, and when the switch element SWshort is in the on state, both the switch elements SWp and SWn are in the off state.

[0103] Switch circuits SWC1b to SWC4b input the same Gray code (W0[0], W0[1], W0[2], W0[3]) as switch circuits SWC1a to SWC4a, and input the input value Iact_n[0] set in switch circuits SWC1b to SWC4b separately from the input value Iact_p[0] of switch circuits SWC1a to SWC4a.

[0104] 10 is a timing diagram showing an example of the operation of the input generation circuit GENIact. When the input values ​​Iact_p[0] and Iact_n[0] are set to the desired voltages, the switch circuits SWC1a to SWC4a and SWC1b to SWC4b are maintained in a parallel connection state. Therefore, the capacitances of the lines Lactp and Lactn are approximately equal to each other.

[0105] Between t1 and t2, the control signals INCTRLp and INCTRLn are activated to a high level. At this time, the control signal INSHORT is maintained at a low level. This turns on the switch elements SWp and SWn, and turns off the switch element SWshort. As a result, a high-level voltage ACTn (e.g., power supply voltage Vdd) and a low-level voltage ACTp (e.g., ground voltage GND) of digital values ​​are transmitted to the lines Lactp and Lactn as input values ​​Iact_p[0] and Iact_n[0], respectively. The voltages transmitted to the lines Lactp and Lactn are maintained by the capacitances of the lines Lactp and Lactn.

[0106] After the control signals INCTRLp and INCTRLn are set to low level, the control signal INSHORT is activated to high level from t3 to t4. The control signals INCTRLp and INCTRLn remain at low level. This turns on the switch element SWshort and turns off the switch elements SWp and SWn. As a result, the lines Lactp and Lactn are shorted to each other. Since the capacitances of the lines Lactp and Lactn are approximately equal, both input values ​​Iact_p[0] and Iact_n[0] become an intermediate voltage (Vdd / 2) between the high-level voltage ACTn and the low-level voltage ACTp.

[0107] After the control signal INSHORT is set to low level, the control signal INCTRLp is activated to high level from t5 to t6. The control signals INSHORT and INCTRLp remain low level. This turns on the switch element SWp and turns off the switch elements SWshort and SWn. As a result, the line Lactp becomes a high-level voltage ACTp while the line Lactn remains at the intermediate voltage (Vdd / 2).

[0108] After the control signal INCTRLp is set to low level, the control signal INSHORT is activated to high level from t7 to t8. The control signals INCTRLp and INCTRLn remain low level. This turns on the switch element SWshort and turns off the switch elements SWp and SWn. As a result, the lines Lactp and Lactn are short-circuited to each other, and both the input values ​​Iact_p[0] and Iact_n[0] become an intermediate voltage ((3 / 4)Vdd) between the high-level voltage ACTn and the intermediate voltage (Vdd / 2).

[0109] Furthermore, after the control signal INSHORT is set to low level, the voltage ACTp is set to low level voltage in the same manner as the voltage ACTn from t8 to t9.

[0110] Between t9 and t10, the control signal INCTRLp is activated to a high level. The control signals INSHORT and INCTRLp are maintained at a low level. This turns on the switch element SWp and turns off the switch elements SWshort and SWn. As a result, the line Lactp becomes a low-level voltage ACTp while the line Lactn maintains the intermediate voltage ((3 / 4)Vdd).

[0111] After the control signal INCTRLp is set to low level, the control signal INSHORT is activated to high level from t11 to t12. The control signals INCTRLp and INCTRLn remain low level. This turns on the switch element SWshort and turns off the switch elements SWp and SWn. As a result, the lines Lactp and Lactn are short-circuited with each other, and both the input values ​​Iact_p[0] and Iact_n[0] become an intermediate voltage ((3 / 8)Vdd) between the low-level voltage ACTp and the intermediate voltage ((3 / 4)Vdd).

[0112] At this time, if the capacitor unit CU1 performs an operation while maintaining the voltages of the wirings Lactp and Lactn at (3 / 8)Vdd, the input values ​​Iact_p[0] and Iact_n[0] are set to the intermediate voltage (3 / 8)Vdd. In this way, in the third embodiment, by arbitrarily switching the switch elements SWshort, SWp, and SWn, the input generation circuit GENIact can generate an arbitrary analog value from a digital value. In other words, the input generation circuit GENIact functions as a DA conversion circuit.

[0113] In this way, the input generation circuit GENIact according to the third embodiment generates an input value by alternately turning on and off the switch element SWp or SWn and the switch element SWshort. When multiplying the input value by the Gray code, the input generation circuit GENIact maintains the input values ​​Iact_p[0] and Iact_n[0] on the wirings Lactp and Lactn by turning on the switch element SWshort and turning off the switch elements SWp and SWn.

[0114] Other configurations of the third embodiment may be the same as those of the second embodiment, and therefore the third embodiment can achieve the same effects as the second embodiment.

[0115] 11 is a block diagram showing an input generation circuit GENIact according to a fourth embodiment. The input generation circuit GENIact receives Gray code (G[0], G[1], G[2], G[3], G[4]), converts it to binary code (B[0], B[1], B[2], B[3], B[4]), and generates an input value Iact_p[i] by performing DA conversion on the binary code (B[0], B[1], B[2], B[3], B[4]).

[0116] The input generation circuit GENIact includes, for example, multiple exclusive OR (XOR) circuits and a DAC 380. The XOR circuits input two adjacent bits (e.g., G[i], G[i+1]) of a Gray code (G[0], G[1], G[2], G[3], G[4]) and output their exclusive OR. The output of the multiple XOR circuits is a binary code (B[0], B[1], B[2], B[3], B[4]). That is, the multiple XOR circuits convert the Gray code (G[0], G[1], G[2], G[3], G[4]) into a binary code (B[0], B[1], B[2], B[3], B[4]).

[0117] The DAC 380 generates an analog input value Iact_p[i] based on the binary code (B[0], B[1], B[2], B[3], B[4]). The DAC 380 may generate the analog input value Iact_p[i] by resistively dividing the power supply voltage Vdd using a variable resistor (not shown) that is set based on the binary code (B[0], B[1], B[2], B[3], B[4]).

[0118] In this way, the input generation circuit GENIact can generate the input value Iact_p[i] based on the Gray code (G[0], G[1], G[2], G[3], G[4]).

[0119] According to the fourth embodiment, not only the weighted Gray code (W0[0], W0[1], W0[2], W0[3]) used for multiplication in the capacitor unit CU, but also the Gray code (G[0], G[1], G[2], G[3], G[4]) can be used for the signal for generating the input value Iact_p[i].

[0120] Other configurations of the fourth embodiment may be the same as those of any of the first to third embodiments, and therefore the fourth embodiment can achieve the same effects as those of any of the first to third embodiments.

[0121] 12 is a block diagram showing an example of the configuration of an image pickup device 100 according to a fifth embodiment. The image pickup device 100 is, for example, a CIS. The image pickup device 100 according to the fifth embodiment has a stacked structure of three semiconductor layers S1 to S3. Each of the semiconductor layers S1 to S3 is, for example, a semiconductor substrate.

[0122] The semiconductor layer S1 includes, for example, a pixel array section 230. The pixel array section 230 has a plurality of pixels 231 that photoelectrically convert incident light to generate an electric signal.

[0123] The semiconductor layer S2 includes, for example, an ADC 300 other than the arithmetic unit 360. The ADC 300 may be a column-parallel ADC or a pixel-parallel ADC. For the purposes of the following description, it is assumed that the ADC 300 is a column-parallel ADC. The column ADC 300 may have a structure shown in FIG. 3.

[0124] The semiconductor layer S3 includes, for example, the computing unit 360 of the column ADC 300. The computing unit 360 may have the structure shown in FIG.

[0125] The semiconductor layers S1 and S2 are electrically connected to each other by interconnections (e.g., Cu interconnections) connecting them together via interconnection bonding (e.g., Cu-Cu bond) CC1. The semiconductor layers S2 and S3 are also electrically connected to each other by interconnection bonding (e.g., Cu-Cu bond) CC2 by interconnection bonding (e.g., Cu interconnections).

[0126] The semiconductor layer S3 may be provided with components other than the arithmetic unit 360 of the column ADC 300. The semiconductor layers S2 and S3 may be formed as a single semiconductor layer. That is, the column ADC 300 including the arithmetic unit 360 may be provided in a single semiconductor layer.

[0127] The Gray code TDC 400 includes a latch circuit 401. The latch circuit 401 temporarily holds a Gray code (W0[0], W0[1], W0[2], W0[3]). This Gray code is sent to the semiconductor layer S3 via the wiring coupling CC2 and subjected to a product-sum operation in the arithmetic unit 360.

[0128] 4, the output from the arithmetic unit 360 may be converted into a digital value (Gray code) and written back to the latch circuit 401 in the semiconductor layer S2. This Gray code may be sent to the semiconductor layer S3 via the wiring coupling CC2 and subjected to a product-sum operation in the arithmetic unit 360. This allows the product-sum operation to be repeatedly performed.

[0129] The pixel array unit 230, the column ADC 300, and the calculator 360 may be driven for all pixels (all columns). However, in order to reduce the calculation load, the column ADC 300 and the calculator 360 may be thinned out and driven for only some pixels (some columns) (for example, intermittently). This reduces the amount of calculation performed by the column ADC 300 and the calculator 360.

[0130] 13 is a block diagram showing an example of the configuration of a column ADC 300 according to a sixth embodiment. According to the sixth embodiment, the Gray code is fed back to a calculator 360 and subjected to repeated product-sum calculations.

[0131] The column ADC 300 further includes, for each column, an AD converter 382 and a memory 384. The selection unit 235 is omitted.

[0132] The AD converter 382 converts the analog value resulting from the sum-of-products operation from the arithmetic unit 360 into a gray code.

[0133] The memory 384 temporarily stores the gray code output from the AD converter 382. The gray code stored in the memory 384 may be output to the outside of the column ADC 300, or may be fed back to the calculator 360.

[0134] When the Gray code is fed back from the memory 384 to the calculator 360, the calculator 360 performs a further multiply-and-accumulate operation using this Gray code. At this time, the input value Iact may remain the same or may be changed to a different voltage.

[0135] In this way, the column ADC 300 can repeat the product-sum operation multiple times on a pixel signal that has been input once.

[0136] Other configurations of the sixth embodiment may be the same as those of the first embodiment, and therefore the sixth embodiment can achieve the same effects as the first embodiment.

[0137] 14 is a block diagram showing a configuration example of a column ADC 300 according to a seventh embodiment. The column ADC 300 according to the seventh embodiment further includes two memories 384_1 and 384_2 connected to the outputs of the AD converters 382 of the respective columns, an arithmetic unit 386, and a selection unit 388.

[0138] The memory 384_1 temporarily stores, for example, in gray code, pixel signals (reset signals) when the pixels of the pixel array unit 230 are in a reset state where they are not receiving light. The memory 384_2 temporarily stores, for example, in gray code, pixel signals (data signals) when the pixels of the pixel array unit 230 are receiving light.

[0139] The calculator 386 subtracts the reset signal stored in the memory 384_1 from the data signal stored in the memory 384_2, and outputs the differential Gray code to the selector 388. That is, in the column ADC 300, CDS (Correlated Double Sampling) processing is performed.

[0140] The selection unit 388 selectively inputs either the differential Gray code or the Gray code of the reference input to the calculator 360. The Gray code of the reference input is a signal used to obtain the circuit offset of the calculator.

[0141] When the differential Gray code is fed back to the calculator 360, the calculator 360 further executes a product-sum operation using this differential Gray code. At this time, the setting of the input value Iact may remain the same or may be changed.

[0142] In this way, the column ADC 300 can repeat the product-sum operation multiple times on a pixel signal that has been input once.

[0143] Other configurations of the seventh embodiment may be the same as those of the sixth embodiment, and therefore the seventh embodiment can achieve the same effects as the sixth embodiment.

[0144] 15 is a block diagram showing an example of the configuration of a column ADC 300 according to the eighth embodiment. In the column ADC 300 according to the eighth embodiment, a Gray code TDC 400 includes two memories 384_1 and 384_2. The selection unit 235 includes a switch mechanism that selectively transmits to the column ADC 300 one of a pixel signal from the pixel array unit 230, a product-sum operation result fed back from the calculator 360, and a reference input. The reference input is, for example, a zero input, and is a signal used to acquire a circuit offset of the calculator.

[0145] When a pixel signal is input to the column ADC 300, the reset level and pixel signal of the pixel are stored in memories 384_1 and 384_2, respectively. In this case, one of the memories 384_1 and 384_2 temporarily stores the reset signal, after which it is subtracted in 386 and the signal is sent to 360.

[0146] When the product-sum operation result fed back from the calculator 360 is input to the column ADC 300, the Gray code after AD conversion of the product-sum operation result is stored in one of the memories 384_1 and 384_2. When the reference input is input to the column ADC 300, the Gray code after AD conversion of the reference input is stored in the other of the memories 384_1 and 384_2. Then, the calculator 386 transmits the differential Gray code between the Gray code of the product-sum operation result and the Gray code of the reference input to the calculator 360.

[0147] The calculator 360 may further perform a product-sum operation on this differential Gray code using the input value Iact, and may further feed back the result of the product-sum operation to the column ADC 300. At this time, the input value Iact may be updated. The fed-back product-sum operation result is AD-converted into a Gray code and stored in one of the memories 384_1 and 384_2. The Gray code of the reference input stored in the other of the memories 384_1 and 384_2 may remain as is, or a reference signal may be input again for each operation.

[0148] In this way, the column ADC 300 can repeat the product-sum operation multiple times on a pixel signal that has been input once.

[0149] Other configurations of the eighth embodiment may be the same as those of the first embodiment, and therefore the eighth embodiment can achieve the same effects as the first embodiment.

[0150] 16 is a timing chart showing an example of the operation of the image pickup device 100 according to the ninth embodiment. In the ninth embodiment, the image pickup device 100 will be described as a CIS having a three-layer structure of semiconductor layers S1 to S3, as shown in FIG.

[0151] At times t1 to t5, the pixel array unit 230 is exposed to light. The pixel array unit 230 first generates pixel signals in a dark state to generate a reset signal. Then, the pixel array unit 230 photoelectrically converts incident light to generate pixel signals to generate data signals. The reset signal and the data signal are sent to the column ADC 300.

[0152] At t2, the column ADC 300 is initialized. In the calculator 360, an input value Iact is set.

[0153] At t 3 , the column ADC 300 receives a reset signal, compares this reset signal with the reference signal RMP, converts the time until the output of the comparator 340 is inverted into a Gray code, and latches it in the Gray code TDC 400 .

[0154] At t4, the calculator 360 converts this Gray code into a binary code and executes a product-sum operation on the input value Iact.

[0155] At t5, the column ADC 300 receives the exposure signal, compares this exposure signal with the reference signal RMP, and converts the time until the output of the comparator 340 is inverted into a gray code and latches it in the gray code TDC 400.

[0156] At t6, the calculator 360 converts this Gray code into a binary code and executes a multiply-and-accumulate operation on the input value Iact.

[0157] At t7, the column ADC 300 calculates the difference between the product-sum operation result of the reset signal and the product-sum operation result of the data signal, and feeds this difference back to the Gray code TDC 400 in the semiconductor layer S2 and stores it in the latch circuit within the Gray code TDC 400.

[0158] The difference is output to the outside of the column ADC 300 .

[0159] When the Gray code TDC 400 of the column ADC 300 has many latch circuits, the product-sum operation result of the arithmetic unit 360 of the semiconductor layer S3 may be returned to the Gray code TDC 400 of the semiconductor layer S2 in this manner.

[0160] The ninth embodiment is applicable to the imaging device 100 according to the first embodiment.

[0161] 17 is a timing chart showing an example of operation of the imaging device 100 according to the tenth embodiment. In the tenth embodiment, after the example of operation according to the ninth embodiment is performed, at t8, the differential Gray code is fed back to the calculator 360, and further, the calculator 360 performs a product-sum operation on the differential Gray code and the input value Iact.

[0162] At t9, the product-sum operation result of the arithmetic unit 360 is fed back to the Gray code TDC 400 in the semiconductor layer S2 and stored in the latch circuit within the Gray code TDC 400.

[0163] Thereafter, the feedback and product-sum operation of t8 and t9 are repeated an arbitrary number of times, and the product-sum operation result is output to the outside of the column ADC 300.

[0164] In this way, the column ADC 300 can repeat the product-sum operation multiple times on a pixel signal that has been input once. Therefore, the tenth embodiment is applicable to the imaging device 100 of any of the sixth to eighth embodiments.

[0165] 18 is a timing chart showing an example of operation of the imaging device 100 according to the 11th embodiment. In the 11th embodiment, when repeatedly executing the sum-of-products operation in the example of operation according to the 10th embodiment, the calculator 360 resets the input value Iact and executes the sum-of-products operation. In this way, the column ADC 300 may change the input value Iact each time the sum-of-products operation is repeated.

[0166] The eleventh embodiment is applicable to the imaging device 100 of any of the sixth to eighth embodiments.

[0167] 19 is a timing chart showing an example of the operation of the image pickup device 100 according to the twelfth embodiment. The twelfth embodiment is applied to a case where, like the eighth embodiment, a Gray code after AD conversion of the product-sum operation result is stored in one of the memories 384_1 and 384_2, and a Gray code after AD conversion of a reference input (for example, a zero input) is stored in the other of the memories 384_1 and 384_2.

[0168] For example, from t8 to t9, the Gray code of the product-sum operation result is transmitted to the calculator 360, which then converts the Gray code of the product-sum operation result into a binary code and executes the product-sum operation. Furthermore, the Gray code of the reference input is transmitted to the calculator 360, which then converts the Gray code of the reference input into a binary code and executes the product-sum operation.

[0169] At t9, the calculator 360 converts the Gray code of the product-sum operation result into a Gray code of the difference between the product-sum operation result and the Gray code of the product-sum operation result with zero input, and feeds it back to the calculator 360. This differential Gray code is stored in one of the memories 384_1 and 384_2 and updated.

[0170] Thereafter, the feedback and product-sum operation of t8 and t9 are repeated an arbitrary number of times, and the product-sum operation result is output to the outside of the column ADC 300.

[0171] In this way, the column ADC 300 can repeat the product-sum operation multiple times on a pixel signal that has been input once. Therefore, the twelfth embodiment is applicable to the image pickup device 100 of the eighth embodiment.

[0172] In the above embodiment, the Gray code of the pixel signal is input as a weighting, but it may be input to the input side as an input value Iact. In this case, the analog value input as the input value Iact is converted into a Gray code and input to the weighting side.

[0173] (Application Example to a Mobile Body) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0174] FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0175] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 20 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0176] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0177] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0178] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0179] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0180] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0181] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0182] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0183] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0184] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 20, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0185] FIG. 21 is a diagram showing an example of the installation position of the imaging unit 12031.

[0186] In FIG. 21, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0187] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0188] 21 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0189] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0190] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0191] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0192] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0193] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capture unit 12031 and other electronic devices in the above-described configuration.

[0194] The present technology can be configured as follows.

[0195] (1) A computing device comprising a plurality of capacitor units including: a plurality of first capacitors, each having one end connected to a first signal line; and a plurality of first switch circuits, each connected to the other end of the plurality of first capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors based on a first digital value to convert the first digital value to a second digital value and multiply the second digital value by the first input voltage; and the plurality of capacitor units output a voltage to the first signal line according to a multiplication result of the first input voltage and the second digital value.

[0196] (2) The capacitance of the plurality of first capacitors is 2 ｎ (n is an integer equal to or greater than 0).

[0197] (3) A computing device comprising a plurality of capacitor units including: a first capacitor connected between a first node and a reference voltage source; a plurality of second capacitors connected in series between the first node and a first signal line; a plurality of third capacitors, each having one end connected to the first node and a second node between adjacent ones of the plurality of second capacitors; and a plurality of first switch circuits connected to the other ends of the plurality of third capacitors, respectively; wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of third capacitors based on a first digital value to convert the first digital value to a second digital value and multiply the second digital value by the first input voltage; and the plurality of capacitor units output a voltage to the first signal line according to a multiplication result of the first input voltage and the second digital value.

[0198] (4) The arithmetic device according to any one of (1) to (3), wherein at least one of the first input voltage and the first digital value is a digital signal expressed in Gray code, and the second digital value is a binary code.

[0199] (5) The arithmetic device according to any one of (1) to (4), wherein outputs from the plurality of capacitor units are added together in the first signal line to form an analog value.

[0200] (6) The arithmetic device according to any one of (1) to (5), further comprising: a first wiring that transmits the first input voltage; and a second wiring that transmits the reference voltage, wherein the plurality of first switch circuits include: a first switch element that makes the first wiring conductive or non-conductive; a second switch element that makes the second wiring conductive or non-conductive; and third and fourth switch elements that make the first wiring and the second wiring conductive or non-conductive, wherein the third switch element is connected between one end of the first switch element and the other end of the second switch element, and the fourth switch element is connected between the other end of the first switch element and one end of the second switch element.

[0201] (7) The arithmetic device according to (5), wherein the plurality of first switch circuits each input one bit of the first digital value; when a corresponding bit of the first digital value is a first logic, the first and second switch elements are in a conductive state and the third and fourth switch elements are in a non-conductive state; and when a corresponding bit of the first digital value is a second logic, the first and second switch elements are in a non-conductive state and the third and fourth switch elements are in a conductive state.

[0202] (8) The arithmetic device according to any one of (1) to (7), wherein the plurality of capacitor units receive the same first digital value as an input and the first input voltage as an input that is set for each of the capacitor units.

[0203] (9) The arithmetic device according to any one of (3) to (8), wherein the capacitance of the second capacitor is approximately twice the capacitance of the first and third capacitors.

[0204] (10) The arithmetic device according to (3), wherein the plurality of capacitor units include a plurality of fourth capacitors each having one end connected to the first node and a second node between adjacent ones of the plurality of second capacitors, and a plurality of second switch circuits each connected to the other end of the plurality of fourth capacitors, wherein the plurality of second switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of fourth capacitors based on the first digital value, and convert the first digital value to a second digital value together with the plurality of first switch circuits.

[0205] (11) The arithmetic device according to (10), wherein at least one of the first input voltage and the first digital value is a digital signal expressed in Gray code, and the second digital value is a binary code.

[0206] (12) The arithmetic device according to (10) or (11), wherein outputs from the plurality of capacitor units are added together in the first signal line to form an analog value.

[0207] (13) The arithmetic device according to any one of (10) to (12), further comprising: a third wiring that transmits the first input voltage; and a fourth wiring that transmits the reference voltage, wherein the plurality of second switch circuits include: a fifth switch element that makes the third wiring conductive or non-conductive; a sixth switch element that makes the fourth wiring conductive or non-conductive; and seventh and eighth switch elements that make the third wiring and the fourth wiring conductive or non-conductive, wherein the seventh switch element is connected between one end of the fifth switch element and the other end of the sixth switch element, and the eighth switch element is connected between the other end of the fifth switch element and one end of the sixth switch element.

[0208] (14) The arithmetic device according to (13), wherein the plurality of second switch circuits each input one bit of the first digital value; when a corresponding bit of the first digital value is a first logic, the fifth and sixth switch elements are in a conductive state and the seventh and eighth switch elements are in a non-conductive state; and when a corresponding bit of the first digital value is a second logic, the fifth and sixth switch elements are in a non-conductive state and the seventh and eighth switch elements are in a conductive state.

[0209] (15) The arithmetic device according to any one of (10) to (14), wherein the second switch circuits receive the first digital value separate from that received by the first switch circuits, and the first input voltage set to the second switch circuits is received separately from the first switch circuits.

[0210] (16) The arithmetic device according to any one of (10) to (15), wherein the third and fourth capacitors have approximately the same capacitance.

[0211] (17) The arithmetic device according to (13) or (14), comprising: a ninth switch element provided between the first wiring and the third wiring; a tenth switch element connected to the first wiring and transmitting or not transmitting a third digital value to the first wiring; and an eleventh switch element connected to the third wiring and transmitting or not transmitting a fourth digital value to the third wiring.

[0212] (18) The arithmetic device according to (17), wherein the ninth switch element and the tenth or eleventh switch element are alternately turned on and off to generate the first input voltage, and when a voltage according to the multiplication of the first input voltage and the first digital value is output to the first signal line, the ninth switch element is turned on and the tenth and eleventh switch elements are turned off, thereby maintaining the first input voltage on the first and second input voltage lines.

[0213] (19) The arithmetic device according to (17) or (18), wherein the ninth to eleventh switch elements are digital-analog conversion circuits.

[0214] (20) The arithmetic device according to any one of (1) to (19), further comprising an analog-to-digital conversion circuit connected to the first signal line.

[0215] (21) The arithmetic device according to any one of (1) to (20), comprising: a first semiconductor layer including a light receiving unit that performs photoelectric conversion on incident light to generate an electrical signal; and a second semiconductor layer stacked on the first semiconductor layer and including a circuit that performs AD conversion on the electrical signal.

[0216] (22) The arithmetic device according to (21), further comprising: a third semiconductor layer stacked on the first and second semiconductor layers, the third semiconductor layer including the plurality of first switch circuits and the plurality of capacitor units.

[0217] (23) The arithmetic device according to (21), wherein the second semiconductor layer further includes a storage unit that temporarily stores the first digital value or the multiplication result.

[0218] (24) An electronic device comprising a plurality of capacitor units including: a plurality of first capacitors, each having one end connected to a first signal line; and a plurality of first switch circuits, each connected to the other end of the plurality of first capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors based on a first digital value to convert the first digital value to a second digital value; and the plurality of capacitor units output a voltage to the first signal line according to the multiplication of the first input voltage and the second digital value.

[0219] (25) The electronic device according to (24), wherein the electronic device is a CMOS image sensor.

[0220] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0221] 100 Imaging device 110 Optical unit 200 Solid-state imaging element 120 DSP circuit 210 Timing control unit 220 Vertical scanning circuit 230 Pixel array unit 300 Column ADC 240 Horizontal transfer circuit 231 Pixel 310 Phase synchronization circuit 320 Gray code counter 330 DAC 235 Selection unit 340 Comparator 400 Gray code TDC 360 Arithmetic unit CU1, CU2 Capacitor units C1 to C4 Capacitors SWC1 to SWC4 Switch circuit W0[0] to W0[3] Gray code Iact_p[0] Input value

Claims

1. A computing device comprising a plurality of capacitor units, each capacitor unit including: a plurality of first capacitors each having one end connected to a first signal line; and a plurality of first switch circuits each connected to the other end of one of the plurality of first capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of first capacitors based on a first digital value to convert the first digital value into a second digital value, multiply the second digital value by the first input voltage, and the plurality of capacitor units output a voltage corresponding to the multiplication result of the first input voltage and the second digital value to the first signal line.

2. The capacitance of the plurality of first capacitors is 2 ｎ (n is an integer of 0 or more), the arithmetic unit according to claim 1.

3. A computing device comprising a plurality of capacitor units, each capacitor unit including: a first capacitor connected between a first node and a reference voltage source; a plurality of second capacitors connected in series between the first node and a first signal line; a plurality of third capacitors each having one end connected to the first node and a second node between the adjacent plurality of second capacitors; and a plurality of first switch circuits each connected to the other end of one of the plurality of third capacitors, wherein the plurality of first switch circuits apply either a first input voltage or a reference voltage to the other ends of the plurality of third capacitors based on a first digital value to convert the first digital value into a second digital value, multiply the second digital value by the first input voltage, and the plurality of capacitor units output a voltage corresponding to the multiplication result of the first input voltage and the second digital value to the first signal line.

4. The computing device according to claim 1, wherein at least one of the first input voltage and the first digital value is a digital signal represented in Gray code, and the second digital value is in binary code.

5. The computing device according to claim 1, wherein the output from the plurality of capacitor units is charge-added on the first signal line to become an analog value.

6. The apparatus further includes a first wiring for transmitting the first input voltage and a second wiring for transmitting the reference voltage, wherein the plurality of first switch circuits include a first switch element for making the first wiring conductive or non-conductive, a second switch element for making the second wiring conductive or non-conductive, and third and fourth switch elements for making the connection between the first wiring and the second wiring conductive or non-conductive, the third switch element is connected between one end of the first switch element and the other end of the second switch element, and the fourth switch element is connected between the other end of the first switch element and one end of the second switch element. The arithmetic unit according to claim 1.

7. The plurality of first switch circuits each input the first digital value one bit at a time. When the corresponding bit of the first digital value is of the first logic, the first and second switch elements are in a conductive state, and the third and fourth switch elements are in a non-conductive state. When the corresponding bit of the first digital value is of the second logic, the first and second switch elements are in a non-conductive state, and the third and fourth switch elements are in a conductive state. The arithmetic unit according to claim 6.

8. The plurality of capacitor units input the same first digital value and the first input voltage set for each of them. The arithmetic unit according to claim 1.

9. The capacitance of the second capacitor is about twice the capacitance of the first and third capacitors. The arithmetic unit according to claim 3.

10. The plurality of capacitor units include a plurality of fourth capacitors each having one end connected to the first node and a second node between the plurality of adjacent second capacitors, and a plurality of second switch circuits each connected to the other end of the plurality of fourth capacitors. The plurality of second switch circuits apply either the first input voltage or the reference voltage to the other end of the plurality of fourth capacitors based on the first digital value, and together with the plurality of first switch circuits, convert the first digital value into a second digital value. The arithmetic unit according to claim 3.

11. At least one of the first input voltage and the first digital value is a digital signal represented in Gray code, and the second digital value is in binary code. The arithmetic unit according to claim 10.

12. The arithmetic unit according to claim 10, wherein the outputs from the plurality of capacitor units are charge-added on the first signal line to obtain an analog value.

13. The arithmetic unit according to claim 10, further comprising: a first wiring for transmitting the first input voltage; a second wiring for transmitting the reference voltage; a third wiring for transmitting the first input voltage; and a fourth wiring for transmitting the reference voltage, wherein the plurality of second switch circuits include: a fifth switch element for making the third wiring conductive or non-conductive; a sixth switch element for making the fourth wiring conductive or non-conductive; and seventh and eighth switch elements for making the connection between the third wiring and the fourth wiring conductive or non-conductive, wherein the seventh switch element is connected between one end of the fifth switch element and the other end of the sixth switch element, and the eighth switch element is connected between the other end of the fifth switch element and one end of the sixth switch element.

14. The arithmetic unit according to claim 13, wherein each of the plurality of second switch circuits inputs the first digital value bit by bit, and when the corresponding bit of the first digital value is of the first logic, the fifth and sixth switch elements are in a conductive state and the seventh and eighth switch elements are in a non-conductive state, and when the corresponding bit of the first digital value is of the second logic, the fifth and sixth switch elements are in a non-conductive state and the seventh and eighth switch elements are in a conductive state.

15. The arithmetic unit according to claim 10, wherein the plurality of second switch circuits input the first digital value that is individual from the plurality of first switch circuits, and input the first input voltage set for the plurality of second switch circuits separately from the plurality of first switch circuits.

16. The arithmetic unit according to claim 10, wherein the capacitances of the third and fourth capacitors are substantially equal.

17. The arithmetic unit according to claim 13, further comprising: a ninth switch element provided between the first wiring and the third wiring; a tenth switch element connected to the first wiring for transmitting or not transmitting a third digital value to the first wiring; and an eleventh switch element connected to the third wiring for transmitting or not transmitting a fourth digital value to the third wiring.

18. The arithmetic unit according to claim 17, wherein the ninth switch element and the tenth or eleventh switch element alternately become conductive and non-conductive to generate the first input voltage, and when a voltage corresponding to the multiplication of the first input voltage and the first digital value is output to the first signal line, the ninth switch element becomes conductive and the tenth and eleventh switch elements become non-conductive, thereby maintaining the first input voltage on the first and second input voltage lines.

19. The arithmetic unit according to claim 17, wherein the ninth to eleventh switch elements are digital-to-analog conversion circuits.

20. The arithmetic unit according to claim 1, further comprising an analog-to-digital conversion circuit connected to the first signal line.

21. The arithmetic unit according to claim 1, comprising a first semiconductor layer including a light receiving portion that photoelectrically converts incident light to generate an electrical signal, and a second semiconductor layer laminated on the first semiconductor layer and including a circuit that performs AD conversion on the electrical signal.

22. The arithmetic unit according to claim 21, further comprising a third semiconductor layer laminated on the first and second semiconductor layers and including the plurality of first switch circuits and the plurality of capacitor units.

23. The arithmetic unit according to claim 21, wherein the second semiconductor layer further includes a storage portion that temporarily stores the first digital value or the multiplication result.

24. An electronic device comprising a plurality of capacitor units including a plurality of first capacitors each having one end connected to a first signal line, and a plurality of first switch circuits each connected to the other end of the plurality of first capacitors, wherein the plurality of first switch circuits convert the first digital value to a second digital value by applying either a first input voltage or a reference voltage to the other end of the plurality of first capacitors based on the first digital value, and the plurality of capacitor units output a voltage corresponding to the multiplication of the first input voltage and the second digital value to the first signal line.

25. The electronic device according to claim 24, wherein the electronic device is a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

Images