Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device configured to include: a semiconductor substrate; a nanosheet laminate provided on the semiconductor substrate; an entire-circumference gate transistor configured by using the nanosheet laminate; and a planar transistor configured by using the nanosheet laminate. The planar transistor includes: a gate insulation film provided to an upper section of the nanosheet laminate; a gate electrode provided on the gate insulation film; and a source / drain diffusion layer provided to the nanosheet laminate at both sides of the gate insulation film and the gate electrode.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] As a technology relating to a semiconductor device and a method for manufacturing the same device, the following Non-Patent Document 1 discloses a configuration in which a bulk FinFET and a bulk planar FET are provided on the same wafer. Furthermore, the following Non-Patent Document 1 describes a manufacturing process for a semiconductor device with such a configuration, in which a silicon substrate is patterned using a silicon nitride hard mask, and then the hard mask in the planar FET region is removed using a polysilicon gate electrode as a mask.

[0003] Hirohisa Kawasaki and 17 others, "Embedded Bulk FinFET SRAM Cell Technology with Planar FET Peripheral Circuit for hp32 nm node and beyond," published June 13-15, 2006, journal name: 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers, [searched October 18, 2023], Internet: <URL: https: / / ieeexplore.ieee.org / document / 1705221 / metrics#metrics>

[0004] In order to further enhance the functionality of semiconductor devices, a gate-all-around (GAA) FET has been proposed, in which a nanosheet-structured semiconductor thin film is surrounded entirely by a gate insulating film and a gate electrode. Such gate-all-around transistors have low breakdown voltage characteristics because the gate insulating film is very thin. However, in the circuit design of semiconductor devices, high-voltage transistors are essential for constructing circuits with high breakdown voltage characteristics, such as input / output circuits. Furthermore, in order to reduce wafer costs and achieve compatibility in circuit design, a technology is needed to form gate-all-around transistors and high-voltage transistors on the same semiconductor substrate while minimizing the increase in process steps.

[0005] Therefore, an object of the present invention is to provide a semiconductor device having an all-around gate transistor and a high-voltage transistor provided on the same semiconductor substrate while minimizing the increase in the number of processes, and a method for manufacturing the semiconductor device.

[0006] To achieve this objective, the present invention is a semiconductor device comprising a semiconductor substrate, a nanosheet laminate provided on the semiconductor substrate, a full-circumference gate transistor constructed using the nanosheet laminate, and a planar transistor constructed using the nanosheet laminate, wherein the planar transistor comprises a gate insulating film provided on top of the nanosheet laminate, a gate electrode provided on the gate insulating film, and source / drain diffusion layers provided in the nanosheet laminate on both sides of the gate insulating film and the gate electrode.

[0007] According to the present invention, it is possible to provide a semiconductor device having a gate-all-around transistor and a high-voltage transistor that are provided while minimizing an increase in the number of processes, and a method for manufacturing the semiconductor device.

[0008] FIG. 1 is a cross-sectional view of a main portion of a semiconductor device of the first embodiment; FIG. 2 is a process diagram (1) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 3 is a process diagram (3) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 4 is a process diagram (4) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 5 is a process diagram (5) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 6 is a process diagram (6) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 7 is a process diagram (7) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 8 is a process diagram (8) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 9 is a process diagram (9) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 10 is a process diagram (11) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 12 is a process diagram (13) showing a method for manufacturing a semiconductor device of the first embodiment; FIG. 14 is a process diagram (14) showing a method for manufacturing a semiconductor device of the first embodiment; and FIG. 15 is a process diagram (15) showing a method for manufacturing a semiconductor device of the first embodiment. FIG. 16 is a process diagram (part 16) showing a manufacturing method of a semiconductor device according to the first embodiment; FIG. 1 is a process diagram (part 1) showing a characteristic part of a manufacturing method of a semiconductor device according to a second embodiment; FIG. 2 is a process diagram (part 2) showing a characteristic part of a manufacturing method of a semiconductor device according to the second embodiment; FIG. 3 is a process diagram (part 3) showing a characteristic part of a manufacturing method of a semiconductor device according to the second embodiment; FIG. 1 is a process diagram (part 1) showing a characteristic part of a manufacturing method of a semiconductor device according to a third embodiment; FIG. 2 is a process diagram (part 3) showing a characteristic part of a manufacturing method of a semiconductor device according to the third embodiment; FIG. 4 is a process diagram (part 5) showing a characteristic part of a manufacturing method of a semiconductor device according to the third embodiment; FIG. 1 is a process diagram (part 1) showing a characteristic part of a manufacturing method of a semiconductor device according to a fourth embodiment; FIG. 2 is a process diagram (part 2) showing a characteristic part of a manufacturing method of a semiconductor device according to the fourth embodiment; FIG. 3 is a cross-sectional view of a main part of a semiconductor device according to a fifth embodiment; FIG. 1 is a process diagram (part 1) showing a characteristic part of a manufacturing method of a semiconductor device according to the fifth embodiment; FIG. 2 is a process diagram (part 2) showing a characteristic part of a manufacturing method of a semiconductor device according to the fifth embodiment.10A and 10B are process diagrams (part 3 and part 4) illustrating characteristic parts of the method for manufacturing a semiconductor device according to the fifth embodiment;

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the embodiments described below, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0010] First Embodiment Configuration of Semiconductor Device 1 of First Embodiment Fig. 1 is a cross-sectional view of a main portion of a semiconductor device 1 of a first embodiment. The semiconductor device 1 shown in Fig. 1 has a gate-around transistor 1a and a planar transistor 1b on one main surface of a semiconductor substrate 100. Fig. 1 shows cross sections of the gate-around transistor 1a and the planar transistor 1b in the gate length direction [Lg] and the gate width direction [Wd].

[0011] The all-around gate transistor 1 a and the planar transistor 1 b are configured using a nanosheet laminate 103 formed on one main surface of a semiconductor substrate 100 .

[0012] Of these, the all-around gate transistor 1a is used, for example, as a device constituting a logic circuit. Such a all-around gate transistor 1a is constructed using multiple silicon layers 102 that constitute a nanosheet laminate 103. The multiple silicon layers 102 are stacked at intervals, and the all-around gate transistor 1a has a GAA (Gate All Around) structure in which a gate insulating film 123i and a gate electrode 124g are provided to surround the entire periphery of each silicon layer 102. The all-around gate transistor 1a also has source / drains 114sd erected on the semiconductor substrate 100 at both ends of the silicon layer 102 in the gate length direction [Lg].

[0013] On the other hand, the planar transistor 1b is used as a high-voltage device that constitutes an input / output circuit. Such a planar transistor 1b has a gate insulating film 107i and a gate electrode 108g provided on a nanosheet laminate 103 in which silicon germanium layers 101 and silicon layers 102 are alternately stacked. The silicon layer 102 is the same layer as the silicon layer 102 of the all-around gate transistor 1a. The gate insulating film 107i is thicker than the gate insulating film 123i of the all-around gate transistor 1a. The planar transistor 1b also has source / drain diffusion layers 103sd provided in the nanosheet laminate 103 on both sides of the gate insulating film 107i and the gate electrode 108g in the gate length direction [Lg].

[0014] 2 to 17 are process diagrams (1) to (16) showing the method for manufacturing the semiconductor device according to the first embodiment. The detailed configuration of the semiconductor device 1 described above will be described below in accordance with the manufacturing process order of the semiconductor device 1 shown in FIGS.

[0015] First, as shown in FIG. 2, a nanosheet laminate 103 is formed on one main surface of a semiconductor substrate 100 made of single-crystal silicon, by alternately stacking silicon germanium layers 101 and silicon layers 102 (e.g., three layers each). The nanosheet laminate 103 is then patterned and separated into an active region (hereinafter referred to as GAA region 10a) for forming the all-around gate transistor 1a and an active region (hereinafter referred to as planar region 10b) for forming the planar transistor 1b. Here, the nanosheet laminate 103 is separated in both the gate length direction [Lg] and the gate width direction [Wd]. At this time, the one main surface side of the semiconductor substrate 100 is also etched back to form a groove 100a.

[0016] Next, as shown in FIG. 3, a trench 100a formed on one main surface of the semiconductor substrate 100 is filled with an insulating material to form a shallow trench isolation (STI) 104. Thereafter, a silicon oxide film 105 is formed to cover the surfaces of the nanosheet laminate 103 and the trench isolation 104. Next, a resist pattern 106 is formed on the silicon oxide film 105, covering the GAA region 10a and exposing the planar region 10b. Next, a channel diffusion layer 103ch is formed in the surface layer of the nanosheet laminate 103 in the planar region 10b by ion implantation (I / I) using the resist pattern 106 as a mask. After the ion implantation to form the channel diffusion layer 103ch, the resist pattern 106 is removed.

[0017] In forming the channel diffusion layer 103ch, ion implantation is performed using separate masks in the n-channel transistor formation region and the p-channel transistor formation region. After the ion implantation, the silicon oxide film 105 is removed.

[0018] 4, an insulating film 107, a gate electrode layer 108, a first hard mask layer 109, and a second hard mask layer 110 are formed in this order on one main surface of the semiconductor substrate 100 on which the nanosheet laminate 103 has been formed. For example, the insulating film 107 is silicon oxide, the gate electrode layer 108 is polysilicon containing impurities, the first hard mask layer 109 is silicon nitride, and the second hard mask layer 110 is silicon oxide.

[0019] Next, using a resist pattern (not shown) as a mask, the second hard mask layer 110 and the first hard mask layer 109 are etched, and further the gate electrode layer 108 and the insulating film 107 are etched, thereby forming gate patterns 110a and 110b in the GAA region 10a and the planar region 10b.

[0020] 5, a high-dielectric film 111 is formed on one main surface of the semiconductor substrate 100 so as to cover the gate patterns 110a and 110b. A resist pattern 112 is then formed on the high-dielectric film 111, covering the planar region 10b and exposing the GAA region 10a. Next, the high-dielectric film 111 is etched using the resist pattern 112 as a mask, to form sidewalls 111sw of the high-dielectric film 111 on the sidewalls of the gate pattern 110a in the GAA region 10a. After the sidewalls 111sw are formed, the resist pattern 112 is removed.

[0021] Next, as shown in FIG. 6, the nanosheet laminate 103 in the GAA region 10a is etched using the high dielectric film 111, the sidewalls 111sw, and the gate pattern 110a as a mask.

[0022] Next, as shown in Figure 7, the silicon germanium layer 101 exposed on the sidewall of the nanosheet laminate 103 is selectively reduced in film thickness by isotropic etching. Next, inner spacers 113sp are formed on the exposed sidewall of the silicon germanium layer 101 so as to fill the spaces between the silicon layers 102. To form the inner spacers 113sp, first, a silicon nitride film is formed by isotropic film formation so as to fill the spaces between the silicon layers 102. Then, the silicon nitride film is etched back by anisotropic etching. This leaves the silicon nitride film only between the silicon layers 102, and the silicon nitride film remaining between the silicon layers 102 is formed as the inner spacers 113sp.

[0023] 8, source / drains 114sd are formed at both ends in the gate length direction [Lg] of the nanosheet laminate 103 in the GAA region 10a. At this time, the source / drains 114sd made of impurity-containing silicon are formed by epitaxial growth from the exposed surfaces of the silicon layer 102 and the semiconductor substrate 100. After the epitaxial growth step, a step of cutting unnecessary portions of the epitaxial layer is carried out.

[0024] In forming the source / drain 114sd, epitaxial growth is performed using separate masks in the n-channel transistor formation region and the p-channel transistor formation region.

[0025] Thereafter, a liner film 115 made of silicon nitride is formed so as to cover the upper side of one main surface of the semiconductor substrate 100 .

[0026] 9, the liner film 115 and the high-dielectric film 111 in the planar region 10b are etched back by anisotropic etching. This exposes the gate pattern 110b and the nanosheet laminate 103 on both sides of the gate pattern 110b in the channel length direction [Lg]. Thereafter, source / drain diffusion layers 103sd are formed on the surface side of the exposed nanosheet laminate 103 by ion implantation.

[0027] The above steps are performed with the GAA region 10a covered with a resist pattern (not shown). Furthermore, in forming the source / drain diffusion layers 103sd, ion implantation is performed using separate resist patterns as masks in the n-channel transistor formation region and the p-channel transistor formation region. After the steps are completed, the resist patterns are removed.

[0028] 10, a second liner film 116 made of silicon nitride is formed so as to cover the upper portion of one main surface side of the semiconductor substrate 100, and furthermore, a buried insulating film 117 made of silicon oxide is buried above the upper portion of one main surface side of the semiconductor substrate 100. Thereafter, a planarization process is performed by chemical mechanical polishing (CMP) until the first hard mask layer 109 made of silicon nitride is exposed.

[0029] 11 , a third hard mask layer 118 made of silicon nitride is formed above one main surface of the semiconductor substrate 100, and a resist pattern 119 is formed on top of the third hard mask layer 118. The resist pattern 119 is a pattern for determining the size of the gate width direction [Wd] of the planar transistor formed in the planar region 10b. The third hard mask layer 118, the first hard mask layer 109, the gate electrode layer 108, the insulating film 107, and the nanosheet laminate 103 in the planar region 10b are patterned by etching using the resist pattern 119 as a mask.

[0030] As a result, a gate insulating film 107i is formed in the planar region 10b by patterning the insulating film 107, and a gate electrode 108g is formed by patterning the gate electrode layer 108. As a result, a planar transistor 1b is formed in the planar region 10b.

[0031] 12, a liner film 120 made of silicon nitride is formed on the exposed sidewalls in the gate width direction [Wd] of planar region 10b and on the exposed surface of semiconductor substrate 100. Thereafter, the etched portion of planar region 10b is filled with a buried insulating film 121 made of silicon oxide. Thereafter, resist pattern 119 is removed.

[0032] Next, as shown in FIG. 13, a planarization process is performed by CMP until the first hard mask layer 109 is exposed.

[0033] 14, a resist pattern 122 is formed to cover the planar region 10b. Thereafter, using the resist pattern 122 as a mask, the second liner film 116 made of silicon nitride, the liner film 115, the first hard mask layer 109, and the sidewall 111sw made of the high-dielectric film 111 are selectively etched to expose the gate electrode layer 108. Furthermore, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched away to expose the insulating film 107 made of silicon oxide.

[0034] 15, in the GAA region 10a, the insulating film 107 made of silicon oxide and the silicon germanium layer 101 of the nanosheet laminate 103 are selectively removed, and then the resist pattern 122 is removed.

[0035] 16, in the GAA region 10a, an insulating film 123 made of a laminate of a silicon oxide layer and a high dielectric film is isotropically formed over the entire surface of one main surface of the semiconductor substrate 100, covering the entire periphery of the exposed silicon layer 102. Next, an electrode material layer 124 is formed on the insulating film 123 so as to fill the spaces between the silicon layers 102 in the GAA region 10a with the electrode material layer 124, and the exposed surface of the silicon layer 102 is covered with the electrode material layer 124 via the insulating film 123.

[0036] 17, the insulating film 123 and the electrode material layer 124 are patterned to form a gate insulating film 123i and a gate electrode 124g in the GAA region 10a. Furthermore, an electrode material layer 125 connected to the gate electrode 124g and a buried plug 126 are patterned in the GAA region 10a. This forms a gate-all-around transistor 1a in the GAA region 10a.

[0037] 1, a cap insulating film 127 is formed to cover the upper portion of one main surface of the semiconductor substrate 100. Thereafter, vias 128 connected to the source / drain 114sd and gate electrode 124g of the all-around gate transistor 1a, and further connected to the source / drain diffusion layer 103sd and gate electrode 108g of the planar transistor 1b, are formed, thereby obtaining the semiconductor device 1 described above.

[0038] Effect of the First Embodiment According to the first embodiment described above, the all-around gate transistor 1a and the planar transistor 1b can be formed on the same semiconductor substrate 100 using the same nanosheet laminate 103. Furthermore, the gate insulating film 107i of the planar transistor 1b is formed in a process separate from the gate insulating film 123i of the all-around gate transistor 1a, allowing for a high degree of freedom in adjusting the film thickness. Therefore, the film thickness of the gate insulating film 107i can be increased to provide a high-voltage planar transistor 1b.

[0039] As a result, by using the same nanosheet laminate 103, it is possible to obtain a semiconductor device 1 in which a full-gate transistor 1a and a high-voltage planar transistor 1b are provided on the same semiconductor substrate 100 while minimizing the increase in processes.

[0040] Second Embodiment The second embodiment is a modification of the method for manufacturing semiconductor device 1 described in the first embodiment, and is an example in which the timing for separating planar region 10b is different. Figures 18 to 20 are process diagrams (parts 1) to (part 3) illustrating characteristic parts of the method for manufacturing a semiconductor device according to the second embodiment. Hereinafter, the manufacturing method according to the second embodiment, which is a modification of the method for manufacturing semiconductor device 1 described above, will be described with reference to Figures 18 to 20.

[0041] 18, a nanosheet laminate 103 is formed on one main surface of a semiconductor substrate 100, in which silicon germanium layers 101 and silicon layers 102 are alternately stacked (e.g., three layers each). The nanosheet laminate 103 is then patterned and separated into an active region (hereinafter referred to as GAA region 10a) for forming the all-around gate transistor 1a and an active region (hereinafter referred to as planar region 10b) for forming the planar transistor 1b. In this case, the planar region 10b is separated only in the gate length direction [Lg], and the gate width direction [Wd] is left continuous without being separated.

[0042] Thereafter, the steps described in the first embodiment with reference to FIGS. 3 to 17 may be carried out in the same manner as described in the first embodiment.

[0043] In this case, in the step shown in FIG. 19 corresponding to the step shown in FIG. 10 of the first embodiment, the upper side of one main surface of the semiconductor substrate 100 is flattened in the same manner as in the first embodiment.

[0044] 20, which corresponds to the process shown in FIG. 11 of the first embodiment, the third hard mask layer 118, the first hard mask layer 109, the gate electrode layer 108, the insulating film 107, and the nanosheet laminate 103 in the planar region 10b are patterned by etching using a resist pattern 119 as a mask. This process is also performed in the same manner as in the first embodiment, but in this process, the gate width direction [Wg] in the planar region 10b is separated.

[0045] <Effects of Second Embodiment> Even with the above-described process sequence, it is possible to obtain a semiconductor device 1 similar to that of the first embodiment, and to obtain similar effects.

[0046] Third Embodiment The third embodiment is a modification of the first embodiment, and is an example in which the procedure for forming the channel diffusion layer 103ch of the planar transistor 1b is different. Figures 21 to 25 are process diagrams (parts 1) to (part 5) illustrating characteristic parts of the manufacturing method for the semiconductor device of the third embodiment. Below, the manufacturing method of the third embodiment, which is a modification of the manufacturing method for the semiconductor device 1 described above, will be described using the drawings used in the description of the first embodiment and Figures 21 to 25.

[0047] First, as explained in the first embodiment with reference to Fig. 2, the GAA region 10a and the planar region 10b are separated from each other. Then, the steps explained with reference to Figs. 4 to 13 are carried out without forming the channel diffusion layer 103ch explained with reference to Fig. 3.

[0048] 21 , in both the GAA region 10 a and the planar region 10 b, the second liner film 116 made of silicon nitride, the liner film 115, the first hard mask layer 109, and the high-dielectric film 111 are selectively etched to expose the gate electrode layer 108. Furthermore, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and then the insulating film 107 made of silicon oxide is also etched away.

[0049] 22, a resist pattern 301 is formed to cover the GAA region 10a. Next, a sacrificial oxide film (not shown) is formed, and then ions are implanted through the sacrificial oxide film to form a channel diffusion layer 103ch in the silicon layer 102 that constitutes the surface layer of the nanosheet laminate 103 in the planar region 10b. Next, after removing the sacrificial oxide film, an insulating film 107 made of silicon oxide is again formed in the planar region 10b, and this serves as the gate insulating film 107i of the planar transistor.

[0050] 15 to 17 in the first embodiment, except that when forming the gate insulating film and gate electrode in the GAA region 10a, the gate insulating film and gate electrode are also formed in the planar region 10b in the same process.

[0051] 23, a resist pattern 122 is first formed to cover the planar region 10b. Using this resist pattern 122 as a mask, the silicon germanium layer 101 of the nanosheet laminate 103 in the GAA region 10a is selectively removed. Thereafter, the resist pattern 122 is removed.

[0052] 24, in the GAA region 10a, an insulating film 123 made of a laminate of a silicon oxide layer and a high-dielectric film is isotropically formed over the entire main surface of the semiconductor substrate 100, covering the entire periphery of the exposed silicon layer 102. As a result, in the planar region 10b, an insulating film 123 made of a laminate of a silicon oxide layer and a high-dielectric film is formed on the insulating film 107 made of silicon oxide.

[0053] Next, an electrode material layer 124 is formed on the insulating film 123 so as to fill the spaces between the silicon layers 102 in the GAA region 10a with the electrode material layer 124, and the exposed surfaces of the silicon layers 102 are covered with the electrode material layer 124 via the insulating film 123. As a result, the electrode material layer 124 is formed on the insulating film 123 in the planar region 10b.

[0054] 25, the electrode material layer 124 and the insulating film 123 are patterned to form a gate electrode 124g and a gate insulating film 123i in the GAA region 10a, and a gate electrode 124g' and a gate insulating film 107i' in the planar region 10b. The gate insulating film 107i' in the planar region 10b is made of a stacked film of insulating films 107 and 123.

[0055] Furthermore, electrode material layers 125 and 125′ connected to the gate electrodes 124g and 124g′ and buried plugs 126 and 126′ are patterned, thereby forming a gate-all-around transistor 1a in the GAA region 10a and a planar transistor 1b in the planar region 10b.

[0056] Advantages of the Third Embodiment The steps of the third embodiment described above make it possible to obtain a semiconductor device 1 similar to that of the first embodiment, in which the gate electrodes 124g, 124g' of the all-around gate transistor 1a and the planar transistor 1b have the same configuration. Furthermore, the gate insulating film 107i' of the planar transistor 1b is formed of a stack of insulating films 107 and 123, which makes it even easier to adjust (increase) the film thickness.

[0057] Fourth Embodiment The fourth embodiment is a modification of the third embodiment, and is an example in which, in a p-channel planar transistor 1b, the channel diffusion layer 103ch is formed in the silicon germanium layer 101. Figures 26 and 27 are process diagrams (part 1) and (part 2) illustrating characteristic steps of a method for manufacturing a semiconductor device according to the fourth embodiment. Below, the manufacturing method of the fourth embodiment, which is a modification of the method for manufacturing the semiconductor device 1 described above, will be described using the drawings used in the description of the first embodiment and Figures 26 to 27.

[0058] First, as explained in the first embodiment with reference to Fig. 2, the GAA region 10a and the planar region 10b are separated from each other. Then, the steps explained with reference to Figs. 4 to 13 are carried out without forming the channel diffusion layer 103ch explained with reference to Fig. 3.

[0059] 26, in both the GAA region 10a and the planar region 10b, the second liner film 116 made of silicon nitride, the liner film 115, the first hard mask layer 109, and the high dielectric film 111 are selectively etched to expose the gate electrode layer 108. Furthermore, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and then the insulating film 107 made of silicon oxide is also etched away.

[0060] Thereafter, a resist pattern 302 is formed that covers the n-channel transistor formation region in the GAA region 10a and the planar region 10b and exposes the p-channel transistor formation region in the planar region 10b. Next, using this resist pattern 302 as a mask, the silicon layer 102 below the insulating film 107 in the p-channel transistor formation region in the planar region 10b is etched away. This exposes the silicon germanium layer 101 in the p-channel transistor formation region in the planar region 10b.

[0061] Next, as shown in FIG. 27, an insulating film 107 made of silicon oxide is formed again on the planar region 10b, and this serves as a gate insulating film 107i of the planar transistor.

[0062] Thereafter, ion implantation using the resist pattern 302 as a mask forms a p-type channel diffusion layer 103ch' in the silicon germanium layer 101 of the surface layer of the nanosheet laminate 103. In the n-channel transistor formation region of the planar region 10b, an insulating film 107 is formed using another mask, and an n-channel diffusion layer is formed in the silicon layer 102 that constitutes the surface layer of the nanosheet laminate 103 by ion implantation.

[0063] Thereafter, the steps described in the third embodiment with reference to FIGS. 23 to 25 may be carried out in the same manner.

[0064] <Effects of the Fourth Embodiment> According to the fourth embodiment described above, by forming the p-type channel diffusion layer 103ch′ in the silicon germanium layer 101, in addition to the effects of the first embodiment, a p-channel planar transistor 1b with high mobility can be obtained.

[0065] Fifth Embodiment Figure 28 is a cross-sectional view of a main portion of a semiconductor device 5 according to a fifth embodiment, showing a cross section in the channel length direction [Lg] of a transistor included in the semiconductor device 5. The semiconductor device 5 shown in Figure 28 differs from the semiconductor device 1 according to the first embodiment in that a planar transistor 1b' is provided in a silicon laminate 303 formed using a nanosheet laminate. The configuration of the all-around gate transistor 1a is the same as that of the first embodiment.

[0066] The planar transistor 1b' is used as a high-voltage device that constitutes an input / output circuit. Such a planar transistor 1b' is provided on a silicon laminate 303. The silicon laminate 303 has a configuration in which single-crystal silicon layers 303a are stacked, and is formed by processing a nanosheet laminate in which silicon germanium layers and silicon layers are alternately stacked, as described below. The planar transistor 1b' has a gate insulating film 107i' and a gate electrode 124g' provided on the silicon laminate 303. The planar transistor 1b' also has source / drain diffusion layers 303sd provided in the silicon laminate 303 as a nanosheet laminate, on both sides of the gate insulating film 107i' and the gate electrode 124g' in the gate length direction [Lg].

[0067] 29 to 32 are process diagrams (parts 1) to (part 4) illustrating characteristic steps of a method for manufacturing a semiconductor device 5 according to a fifth embodiment. The method for manufacturing the semiconductor device 5 according to the fifth embodiment will be described below with reference to the drawings used in the description of the first embodiment and with reference to FIGS.

[0068] First, as explained in the first embodiment with reference to Fig. 2, the GAA region 10a and the planar region 10b are separated from each other. Then, the steps explained with reference to Figs. 4 to 13 are carried out without forming the channel diffusion layer 103ch explained with reference to Fig. 3.

[0069] 29, in both the GAA region 10a and the planar region 10b, the second liner film 116 made of silicon nitride, the liner film 115, the first hard mask layer 109, and the high dielectric film 111 are selectively etched to expose the gate electrode layer 108. Furthermore, the gate electrode layer 108 made of polysilicon containing impurities is selectively etched, and then the insulating film 107 made of silicon oxide is also etched away.

[0070] 30 , in the GAA region 10a and the planar region 10b, the silicon germanium layer 101 of the nanosheet laminate 103 is selectively removed, leaving only the silicon layer 102. As a result, the source / drain diffusion layer 103sd formed in the planar region 10b is divided in the stacking direction of the nanosheet laminate 103.

[0071] Next, as shown in FIG. 31 , a resist pattern 304 is formed to cover the GAA region 10a. Then, using the resist pattern 304 as a mask, silicon is epitaxially grown from the silicon layer 102 in the planar region 10b and the semiconductor substrate 100. This results in a silicon stack 303 in which a single-crystal silicon layer 303a made of single-crystal silicon is stacked on the semiconductor substrate 100 in the planar region 10b. This silicon stack 303 has a meeting surface between the upper and lower silicon layers 102 (see FIG. 30 ) and the single-crystal silicon layer 303a epitaxially grown from the semiconductor substrate 100. Furthermore, impurities are diffused from the source / drain diffusion layer 103sd into the portion of the silicon stack 303 that has grown epitaxially from the separated source / drain diffusion layer 103sd. This results in a source / drain diffusion layer 303sd that is continuous in the depth direction of the silicon stack 303.

[0072] 32, a sacrificial oxide film (not shown) is formed, and then ions are implanted through the sacrificial oxide film to form a channel diffusion layer 303ch in the surface layer of the silicon stack 303 in the planar region 10b. Next, after removing the sacrificial oxide film, an insulating film 107 made of silicon oxide is again formed in the planar region 10b, and this serves as the gate insulating film 107i of the planar transistor.

[0073] 23 to 25 in the third embodiment are carried out in the same manner. <Effects of the Fifth Embodiment> According to the fifth embodiment described above, the planar transistor 1b is formed on the silicon stack 303 in which the single crystal silicon layer 303a is stacked, and thus in addition to the effects of the first embodiment, it is possible to obtain performance equivalent to that of a planar transistor formed on a normal semiconductor substrate. In particular, improvement in punch-through resistance is expected.

[0074] 1, 5...Semiconductor device 1a...Gate-all-around transistor 1b, 1b'...Planar transistor 10a...GAA region 10b...Planar region 100...Semiconductor substrate 101...Silicon germanium layer 102...Silicon layer 103...Nanosheet laminate 103ch...Channel diffusion layer 103ch'...P-type channel diffusion layer 103sd...Source / drain diffusion layer 107...Insulating film 107i, 107i'...Gate insulating film 108...Gate electrode layer 108g...Gate electrode 110a, 110b...Gate pattern 111...High dielectric film 114sd...Source / drain 123...Insulating film 123i...Gate insulating film 124...Electrode material layer 124g...Gate electrode 124g'...Gate electrode 125...Electrode material layer 303...Silicon laminate 303a...Single crystal silicon layer 303ch...Channel diffusion layer 303sd...source / drain diffusion layer

Claims

1. A semiconductor device having a semiconductor substrate, a nanosheet stack provided on the semiconductor substrate, a full-around gate transistor configured using the nanosheet stack, and a planar transistor configured using the nanosheet stack, wherein the planar transistor includes a gate insulating film provided on top of the nanosheet stack, a gate electrode provided on the gate insulating film, and source / drain diffusion layers provided in the nanosheet stack on both sides of the gate insulating film and the gate electrode.

2. The semiconductor device according to claim 1, wherein the nanosheet stack constituting the full-around gate transistor and the nanosheet stack constituting the planar transistor are configured using the same silicon layer, the full-around gate transistor has a gate insulating film surrounding the entire circumference of the silicon layer, and the gate insulating film of the planar transistor is thicker than the gate insulating film of the full-around gate transistor.

3. The semiconductor device according to claim 1, wherein the nanosheet stack constituting the full-around gate transistor has a structure in which a plurality of silicon layers are stacked with intervals therebetween, the nanosheet stack constituting the planar transistor has a structure in which a plurality of silicon layers and a plurality of silicon germanium layers are alternately stacked, and the nanosheet stack constituting the full-around gate transistor and the nanosheet stack constituting the planar transistor are configured using the same silicon layer.

4. The semiconductor device according to claim 3, comprising a plurality of the planar transistors on the semiconductor substrate, wherein the n-channel transistors among the plurality of planar transistors have an n-type channel diffusion layer in the silicon layer, and the gate insulating film is provided in contact with the n-type channel diffusion layer, and the p-channel transistors among the plurality of planar transistors have a p-type channel diffusion layer in the silicon germanium layer, and the gate insulating film is provided in contact with the p-type channel diffusion layer.

5. The nanosheet laminate constituting the all-around gate transistor has a structure in which a plurality of silicon layers are stacked with intervals therebetween, and the nanosheet laminate constituting the planar transistor has a structure in which a plurality of silicon layers are stacked. The semiconductor device according to claim 1.

6. The nanosheet laminate constituting the planar transistor has a structure in which single crystal silicon layers are stacked. The semiconductor device according to claim 5.

7. The gate electrode of the all-around gate transistor and the gate electrode of the planar transistor are made of the same electrode material layer. The semiconductor device according to claim 1.

8. A step of forming a nanosheet laminate in which a first semiconductor layer and a second semiconductor layer on a semiconductor substrate are alternately stacked; a step of forming a gate pattern in an all-around gate region and a planar region on the nanosheet laminate; a step of patterning the nanosheet laminate in the all-around gate region using the gate pattern as a mask and forming source / drain by epitaxial growth from the exposed surface of the second semiconductor layer; a step of forming a source / drain diffusion layer in the nanosheet laminate in the planar region by ion implantation using the gate pattern as a mask; a step of removing the gate pattern in the all-around gate region, further removing the first semiconductor layer selectively with respect to the second semiconductor layer, and then forming a gate insulating film and a gate electrode surrounding the entire circumference of the second semiconductor layer in the all-around gate region; and a step of forming a gate insulating film and a gate electrode on the upper portion of the nanosheet laminate in the planar region. A method of manufacturing a semiconductor device.

9. The gate pattern has an insulating layer provided in contact with the nanosheet laminate and an electrode layer on the upper portion thereof, and a gate insulating film made of the insulating layer and a gate electrode made of the electrode layer are formed in the planar region. The method of manufacturing a semiconductor device according to claim 8.

10. Before forming the gate pattern on the nanosheet laminate, the method includes a step of forming a channel diffusion layer in the surface layer of the nanosheet laminate in the planar region. The method of manufacturing a semiconductor device according to claim 8.

11. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of patterning the nanosheet laminate before forming the gate pattern on the nanosheet laminate.

12. The method of manufacturing a semiconductor device according to claim 11, further comprising a step of patterning the nanosheet laminate in the plainer region after forming a source / drain diffusion layer in the plainer region.

13. The method of manufacturing a semiconductor device according to claim 8, further comprising: a step of removing the gate pattern in the plainer region; a step of forming an insulating layer on an exposed surface of the nanosheet laminate in the plainer region; and a step of forming a channel diffusion layer on a surface layer of the nanosheet laminate in the plainer region, after forming the source / drain diffusion layer in the plainer region.

14. The method of manufacturing a semiconductor device according to claim 13, further comprising: a step of selectively removing the first semiconductor layer with respect to the second semiconductor layer in the entire circumference gate region, forming a gate insulating film surrounding the entire circumference of the second semiconductor layer in the entire circumference gate region and in contact with the insulating layer in the plainer region; and a step of forming an electrode material layer for filling between the second semiconductor layers in the entire circumference gate region on the gate insulating film in the entire circumference gate region and the plainer region, after forming the channel diffusion layer.

15. The first semiconductor layer is a silicon germanium layer, the second semiconductor layer is a silicon layer, after removing the gate pattern in the plainer region, further removing a silicon layer constituting a surface layer of the nanosheet laminate to expose the silicon germanium layer, and in the step of forming the channel diffusion layer in the plainer region, forming a p-type channel diffusion layer on the silicon germanium layer. The method of manufacturing a semiconductor device according to claim 13.

16. After forming the source / drain diffusion layer in the plenary region, removing the gate pattern in the entire peripheral gate region and the plenary region, and further selectively removing the first semiconductor layer with respect to the second semiconductor layer; and forming a nanosheet laminate composed of a second semiconductor layer obtained by epitaxially growing and integrating the second semiconductor layer in the plenary region. The method of manufacturing a semiconductor device according to claim 8.

17. The laminate of the second semiconductor layer is a laminate of single crystal silicon layers. The method of manufacturing a semiconductor device according to claim 16.

18. Forming an insulating layer on the exposed surface of the nanosheet laminate composed of the second semiconductor layer in the plenary region; and forming a channel diffusion layer on the nanosheet laminate composed of the second semiconductor layer exposed in the plenary region. The method of manufacturing a semiconductor device according to claim 16.

19. After forming the channel diffusion layer, forming a gate insulating film surrounding the entire circumference of the second semiconductor layer in the entire peripheral gate region and in contact with the insulating layer in the plenary region; and forming an electrode material layer filling between the second semiconductor layers in the entire peripheral gate region on the gate insulating film in the entire peripheral gate region and the plenary region. The method of manufacturing a semiconductor device according to claim 18.

Images