Semiconductor structure and forming method therefor

Abstract

A semiconductor structure and a forming method therefor. The forming method comprises: forming an initial gate on a part of a substrate; forming initial first side walls on the side walls of the initial gate; upon forming the initial first side walls, forming second side walls on the side walls of the initial first side walls, wherein the material of the second side walls is different from that of the initial first side walls, and the second side walls expose the top surfaces of the initial first side walls; etching the exposed initial first side walls, so that a part of the top surface and side wall surfaces of the initial gate is exposed to form first side walls; and carrying out metal silicide treatment on the exposed top surface and side wall surfaces of the initial gate to form a contact layer, the initial gate under the contact layer forming a gate. The size of the contact layer is increased, which is conducive to reducing the contact resistance, and is thus conducive to the low noise performance of LNA devices.

Description

Semiconductor structure and method for forming the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 8, 2024, with application number 202410026780.0 and invention name “Semiconductor structure and method for forming the same”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0003] Low noise amplifier (LNA) has been widely used in microwave communications, GPS receivers, remote sensing and remote control, radar, electronic countermeasures, radio astronomy, geodetic mapping, television and various high-precision measurement systems. It is an indispensable and important circuit.

[0004] Low-noise amplifiers (LNAs) based on silicon-based complementary metal oxide semiconductor (CMOS) technology have the advantages of low cost, low power consumption, and high integration, making them a hot topic of research. For LNAs, noise performance is a very important indicator.

[0005] However, the performance of existing MOS transistors limits the low noise performance of LNA devices.

[0006] Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0008] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a gate located on a portion of the substrate; a contact layer located on the top surface and a portion of the top sidewall surface of the gate, the material of the contact layer including metal silicide; a first sidewall located on the sidewall surface of the gate, the first sidewall exposing a portion of the contact layer; a second sidewall located on the sidewall of the first sidewall, the second sidewall and the first sidewall being made of a different material.

[0009] Optionally, a first distance exists between the top surface of the first sidewall and the top surface of the contact layer, the gate has a first thickness, and a ratio of the first distance to the first thickness is greater than or equal to 1 / 3.

[0010] Optionally, the contact layer has a second thickness, and the ratio of the second thickness to the first thickness of the gate is greater than or equal to 1 / 4; the total height of the gate and the contact layer is a third height, the first side wall has a fourth height, and the ratio of the third height to the fourth height is greater than or equal to 1.5.

[0011] Optionally, it further includes: a source / drain region in the substrate located on both sides of the gate, the first sidewall and the second sidewall; and a lightly doped region in the substrate located at the bottom of the second sidewall.

[0012] Optionally, the material of the first side wall includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride; the material of the first side wall includes silicon oxide.

[0013] Optionally, the material of the second side wall includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbide nitride; the material of the second side wall includes silicon nitride.

[0014] Optionally, it further includes: a third sidewall spacer located between the first sidewall spacer and the second sidewall spacer, the material of the third sidewall spacer is different from that of the second sidewall spacer, and the third sidewall spacer is also located between the bottom of the second sidewall spacer and the substrate.

[0015] Optionally, the material of the third sidewall includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbon nitride; the material of the third sidewall includes silicon oxide.

[0016] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming an initial gate on a portion of the substrate; forming an initial first sidewall on the sidewall of the initial gate; after forming the initial first sidewall, forming a second sidewall on the sidewall of the initial first sidewall, the second sidewall and the initial first sidewall being made of different materials, the second sidewall exposing the top surface of the initial first sidewall; etching the exposed initial first sidewall so that the top sidewall surface of the initial gate is partially exposed to form a first sidewall; performing metal silicide treatment on the exposed top surface and sidewall surface of the initial gate to form a contact layer, and forming a gate with the initial gate under the contact layer.

[0017] Optionally, the method for forming the second sidewall spacer includes: forming a second sidewall spacer material layer on the substrate after forming the initial first sidewall spacer; and etching back the second sidewall spacer material layer.

[0018] Optionally, after forming the initial first side wall and before forming the second side wall material layer, it also includes: forming a third side wall material layer on the substrate, the second side wall material layer is located on the third side wall material layer, and the materials of the third side wall material layer and the second side wall material layer are different; the method for forming the second side wall also includes: etching back the second side wall material layer until the third side wall material layer is exposed.

[0019] Optionally, before forming the first spacer, the third spacer material layer is further etched to expose the top surface of the initial first spacer, and a third spacer is formed with the third spacer material layer.

[0020] Optionally, the process of etching the exposed initial first sidewall spacer includes a wet etching process.

[0021] Optionally, the method for forming the initial first spacer includes: forming a first spacer material layer on the substrate; and etching back the first spacer material layer until the substrate surface is exposed.

[0022] Optionally, the process of etching back the first sidewall material layer includes a dry etching process.

[0023] Optionally, it also includes: after forming the initial first side wall and before forming the second side wall, using the initial first side wall as a mask to form an initial lightly doped region in the substrate on both sides of the initial gate; after forming the second side wall and before forming the contact layer, using the first side wall and the second side wall as masks to form source and drain regions in the substrate on both sides of the initial gate, and using the initial lightly doped region outside the source and drain region as a lightly doped region.

[0024] Optionally, the initial gate has a first height, the exposed top sidewall of the initial gate has a second height, and the ratio of the second height to the first height is greater than or equal to 1 / 3.

[0025] Compared with the existing technology, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the exposed first sidewall is etched to expose a portion of the top sidewall surface of the initial gate, and the exposed top surface and sidewall surface of the initial gate are subjected to metal silicide treatment to form a contact layer. A gate is formed with the initial gate under the contact layer, so that the top surface of the formed gate and a portion of the top sidewall surface have a contact layer, thereby increasing the size of the contact layer, which is beneficial to reducing the contact resistance and further beneficial to the low noise performance of the LNA device.

[0027] Furthermore, after forming the first sidewall spacer and before forming the second sidewall spacer material layer, a third sidewall spacer material layer is formed on the substrate, the second sidewall spacer material layer is located on the third sidewall spacer material layer, and the third sidewall spacer material layer and the second sidewall spacer material layer are made of different materials. The third sidewall spacer material layer acts as an etch stop layer in the back-etching process for forming the second sidewall spacer, reducing etching damage to the substrate and the initial gate surface caused by the back-etching process, thereby improving device performance. In addition, by controlling the back-etching time, the height of the second sidewall spacer can be controlled. During the process of forming the second sidewall spacer, the third sidewall material layer is partially etched. The presence of the third sidewall material layer facilitates precise control of the height of the second sidewall spacer, and further facilitates control of the height of the subsequently exposed top sidewall of the initial gate.

[0028] In the semiconductor structure provided by the technical solution of the present invention, the contact layer is located on the top surface of the gate and part of the top sidewall surface, so that the size of the contact layer is larger, which is conducive to reducing the contact resistance and further promoting the low noise performance of the LNA device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic cross-sectional view of a semiconductor structure;

[0030] 2 to 6 are schematic structural diagrams of respective steps of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0032] As described in the background art, the performance of existing MOS transistors limits the low-noise performance of LNA devices. This is now explained and analyzed in conjunction with a MOSFET structure.

[0033] FIG1 is a schematic cross-sectional view of a semiconductor structure.

[0034] Please refer to Figure 1, the semiconductor structure includes: a substrate 100; a gate 101 located on the substrate 100; a first spacer structure located on the sidewall of the gate 101 and a second spacer structure located on the sidewall of the first spacer structure, the first spacer structure including a first spacer 102 and a second spacer 103 located on the sidewall of the first spacer 102, the second spacer structure including a third spacer 104 and a fourth spacer 105 located on the sidewall of the third spacer 104; source and drain regions 107 in the substrate 100 on both sides of the gate 101, the first spacer structure and the second spacer structure; a lightly doped region 106 in the substrate 100 located at the bottom of the second spacer structure; and a contact layer 108 located on a portion of the top surface of the gate 101.

[0035] In the above structure, the materials of the first and second sidewall structures are ONON materials, that is, the first sidewall 102 is silicon oxide, the second sidewall 103 is silicon nitride, the third sidewall 104 is silicon oxide, and the fourth sidewall 105 is silicon nitride. In which, the first sidewall structure is formed by depositing a first silicon oxide material layer (not shown in the figure) and a first silicon nitride material layer (not shown in the figure) on the substrate 100, and then etching back until the substrate 100 is exposed, forming the first sidewall 102 with the first silicon oxide material layer, and forming the second sidewall 103 with the first silicon nitride material layer; after the first sidewall structure is formed, a second silicon oxide material layer (not shown in the figure) and a second silicon nitride material layer (not shown in the figure) are deposited on the substrate 100, and then etching back until the substrate 100 is exposed to form the second sidewall structure, forming the first sidewall 102 with the first silicon oxide material layer, and forming the second sidewall 103 with the first silicon nitride material layer; the contact layer 108 is formed by a metal silicide process after the source and drain regions 107 are formed.

[0036] However, since the first and second sidewall spacers completely wrap the sidewalls of the gate 101 , the contact layer 108 formed on the top surface of the gate 101 is narrow, resulting in still large contact resistance, which limits the low noise performance of the LNA device.

[0037] To address the above-mentioned problem, the present invention provides a semiconductor structure and a method for forming the same, in which the exposed first sidewall spacer is etched to expose a portion of the top sidewall surface of the initial gate. The exposed top surface and sidewall surface of the initial gate are subjected to metal silicide treatment to form a contact layer. A gate is formed using the initial gate under the contact layer, so that the top surface of the formed gate and a portion of the top sidewall surface have a contact layer, thereby increasing the size of the contact layer, which is beneficial to reducing contact resistance and, in turn, facilitating the low-noise performance of the LNA device.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] 2 to 6 are schematic structural diagrams of respective steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Referring to FIG. 2 , a substrate 200 is provided.

[0041] In this embodiment, the substrate 200 includes an active region (not shown) and an isolation region (not shown) located between adjacent active regions. The isolation region has an isolation structure 301, and the active region has a well region 302. The isolation structure 301 is used to achieve electrical isolation between different devices.

[0042] In this embodiment, the conductivity type of the well region 302 is P-type, which is used to form an NMOS device. In another embodiment, the conductivity type of the well region is N-type, which is used to form a PMOS device.

[0043] In this embodiment, the substrate 200 is made of silicon.

[0044] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0045] Continuing to refer to FIG. 2 , an initial gate 201 is formed on a portion of the substrate 200 .

[0046] In this embodiment, the material of the initial gate 201 includes polysilicon.

[0047] The method for forming the initial gate 201 includes: forming a gate material layer (not shown in the figure) on the substrate 200; and patterning the gate material layer to form the initial gate 201.

[0048] Referring to FIG. 3 , an initial first spacer 202 is formed on the sidewall of the initial gate 201 .

[0049] Subsequently, a second sidewall spacer is formed on the sidewall of the initial first sidewall spacer 202 .

[0050] In this embodiment, after forming the initial first sidewall spacer 202 and before forming the second sidewall spacer, initial lightly doped regions 203 are formed in the substrate 200 on both sides of the initial gate 201 using the initial first sidewall spacer 202 as a mask. The initial lightly doped regions 203 are used to form lightly doped regions, which are used to improve the hot carrier injection (HCI) effect.

[0051] The conductivity type of the initial lightly doped region 203 is different from the conductivity type of the well region 302. In this embodiment, the conductivity type of the initial lightly doped region 203 is N-type. In another embodiment, the conductivity type of the initial lightly doped region 203 is P-type.

[0052] In this embodiment, after forming the initial first sidewall spacer 202 and before forming the second sidewall spacer, initial halo-doped regions (not shown) are formed in the substrate 200 on both sides of the initial gate 201 using the initial first sidewall spacer 202 as a mask. The ion implantation depth of the initial halo-doped regions is greater than the ion implantation depth of the initial lightly doped regions 203. The conductivity type of the initial halo-doped regions is the same as that of the well region 302. The initial halo-doped regions are used to form halo-doped regions, which are used to reduce the probability of source-drain punch-through. In another embodiment, the initial halo-doped regions may not be formed.

[0053] In this embodiment, the method for forming the initial first spacer 202 includes: forming a first spacer material layer (not shown) on the substrate 200; and etching back the first spacer material layer until the surface of the substrate 200 is exposed.

[0054] In this embodiment, the process of etching back the first spacer material layer includes a dry etching process.

[0055] The first spacer material layer includes a dielectric material, which includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the first spacer material layer includes silicon oxide. The first spacer material layer is used to form the initial first spacer 202, further forming the first spacer.

[0056] 4 , after the initial first sidewall spacer 202 is formed, a second sidewall spacer 204 is formed on the sidewall of the initial first sidewall spacer 202 . The second sidewall spacer 204 is made of a different material from the initial first sidewall spacer 202 , and the second sidewall spacer 204 exposes the top surface of the initial first sidewall spacer 202 .

[0057] In this embodiment, the method for forming the second spacer 204 includes: forming a second spacer material layer (not shown) on the substrate 200 after forming the initial first spacer 202; and etching back the second spacer material layer.

[0058] The material of the second spacer material layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.

[0059] In this embodiment, after forming the initial first side wall 202 and before forming the second side wall material layer, a third side wall material layer 205 is further formed on the substrate 200. The second side wall material layer is located on the third side wall material layer 205. The materials of the third side wall material layer 205 and the second side wall material layer are different.

[0060] Specifically, after forming the initial lightly doped region 203 , the third spacer material layer 205 is formed.

[0061] The material of the third spacer material layer 205 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0062] In this embodiment, the material of the third spacer material layer 205 includes silicon oxide, and the material of the second spacer material layer includes silicon nitride. In this embodiment, the second spacer material layer also serves as a buffer layer.

[0063] In this embodiment, the method for forming the second sidewall spacer 203 further includes: etching back the second sidewall spacer material layer until the third sidewall spacer material layer 205 is exposed. The third sidewall spacer material layer 205 acts as an etch stop layer in the etching back process for forming the second sidewall spacer 204, reducing etching damage to the substrate 200 and the surface of the initial gate 201 caused by the etching back process, thereby improving device performance. In addition, by controlling the etching back time, the height of the second sidewall spacer 204 can be controlled. During the process of forming the second sidewall spacer 204, the third sidewall spacer material layer 205 is partially etched. The presence of the third sidewall spacer material layer 205 facilitates precise control of the height of the second sidewall spacer 204, and further facilitates controlling the height of the subsequently exposed top sidewall of the initial gate 201.

[0064] 5 , the exposed initial first spacer 202 is etched so that a portion of the top sidewall surface of the initial gate 201 is exposed to form a first spacer 206 .

[0065] In this embodiment, the process of etching the exposed initial first sidewall spacer 202 includes a wet etching process.

[0066] In this embodiment, the initial gate 201 has a first height h1, and the exposed top sidewall of the initial gate 201 has a second height h2. The ratio of the second height h2 to the first height h1 is greater than or equal to 1 / 3. The first height h1 and the second height h2 both refer to dimensions perpendicular to the surface of the substrate 200.

[0067] In this embodiment, before forming the first spacer 206 , the third spacer material layer 205 is further etched to expose the top surface of the initial first spacer 202 , and the third spacer 207 is formed by the third spacer material layer 205 .

[0068] Subsequently, metal silicide treatment is performed on the exposed top surface and sidewall surfaces of the initial gate 201 to form a contact layer.

[0069] In this embodiment, after forming the second sidewall spacer 204 and before forming the contact layer, source and drain regions 208 are formed in the substrate 200 on both sides of the initial gate 201 using the first sidewall spacer 206 and the second sidewall spacer 204 as masks. The initial lightly doped region 203 outside the source and drain region 208 serves as a lightly doped region 209. Specifically, the source and drain regions 208 are formed after forming the first sidewall spacer 207.

[0070] In this embodiment, the initial halo-doped region outside the source / drain region 208 is also used as a halo-doped region (not shown in the figure).

[0071] 6 , the exposed top surface and sidewall surfaces of the initial gate 201 are subjected to metal silicide treatment to form a contact layer 210 , and a gate 211 is formed with the initial gate 201 under the contact layer 210 .

[0072] The exposed top surface and sidewall surfaces of the initial gate 201 are subjected to metal silicide treatment, so that the top surface and part of the top sidewall surface of the formed gate 211 have a contact layer 210, which increases the size of the contact layer 210, helps to reduce the contact resistance, and further promotes the low noise performance of the LNA device.

[0073] In this embodiment, a first distance d is defined between the top surface of the first sidewall spacer 206 and the top surface of the contact layer 210. The gate 211 has a first thickness L1. The ratio of the first distance d to the first thickness L1 is greater than or equal to 1 / 3. The first thickness L1 refers to a dimension perpendicular to the surface of the substrate 200.

[0074] In this embodiment, the contact layer 210 has a second thickness (not shown), and the ratio of the second thickness to the first thickness L1 of the gate 211 is greater than or equal to 1 / 4. The second thickness refers to the dimension perpendicular to the sidewall or top surface of the gate 211.

[0075] In this embodiment, the total height of the gate 211 and the contact layer 210 is a third height L3, the first sidewall spacer 206 has a fourth height L4, and the ratio of the third height L3 to the fourth height L4 is greater than or equal to 1.5. The third height L3 and the fourth height L4 both refer to dimensions perpendicular to the surface of the substrate 200.

[0076] In this embodiment, the metal silicide treatment is further performed on the surface of the source / drain region 208 , and the contact layer 210 is also located on the surface of the source / drain region 208 .

[0077] In this embodiment, the material of the contact layer 210 includes metal silicide, and the metal silicide may be TiSi 2 , CoSi 2 , or NiPtSi 2 .

[0078] Accordingly, an embodiment of the present invention also provides a semiconductor structure formed using the above method, please continue to refer to Figure 6, including: a substrate 200; a gate 211 located on a portion of the substrate 200; a contact layer 210 located on the top surface and a portion of the top sidewall surface of the gate 211, the material of the contact layer 210 including metal silicide; a first sidewall 206 located on the sidewall surface of the gate 211, the first sidewall 206 exposing a portion of the contact layer 210; a second sidewall 204 located on the sidewall of the first sidewall 206, the second sidewall 204 and the first sidewall 206 being made of different materials.

[0079] Here, the contact layer 210 is located on the top surface and part of the top sidewall surface of the gate 211, so that the size of the contact layer 210 is larger, which is beneficial to reducing the contact resistance and further contributing to the low noise performance of the LNA device.

[0080] In this embodiment, a first distance d is defined between the top surface of the first sidewall spacer 206 and the top surface of the contact layer 210. The gate 211 has a first thickness L1. The ratio of the first distance d to the first thickness L1 is greater than or equal to 1 / 3. The first thickness L1 refers to a dimension perpendicular to the surface of the substrate 200.

[0081] In this embodiment, the contact layer 210 has a second thickness (not shown), and the ratio of the second thickness to the first thickness L1 of the gate 211 is greater than or equal to 1 / 4. The second thickness refers to the dimension perpendicular to the sidewall or top surface of the gate 211.

[0082] In this embodiment, the total height of the gate 211 and the contact layer 210 is a third height L3, the first sidewall 206 has a fourth height L4, and the ratio of the third height L3 to the fourth height L4 is greater than or equal to 1.5. The third height L3 and the fourth height L4 both refer to the dimensions in the direction perpendicular to the surface of the substrate 200.

[0083] In this embodiment, the semiconductor structure further includes: source and drain regions 208 in the substrate 200 located on both sides of the gate 211 , the first sidewall 206 and the second sidewall 204 ; and a lightly doped region 209 in the substrate 200 located at the bottom of the second sidewall 204 .

[0084] The material of the first spacer 206 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the first spacer 206 includes silicon oxide.

[0085] The material of the second sidewall spacer 204 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon nitride oxynitride. In this embodiment, the material of the second sidewall spacer includes silicon nitride.

[0086] In this embodiment, the semiconductor structure further includes: a third sidewall 207 located between the first sidewall 206 and the second sidewall 204 , the material of the third sidewall 207 being different from that of the second sidewall 204 , and the third sidewall 207 being also located between the bottom of the second sidewall 204 and the substrate 200 .

[0087] The material of the third spacer 207 includes a dielectric material, and the dielectric material includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride. In this embodiment, the material of the third spacer includes silicon oxide.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate located on a part of the substrate; A contact layer located on the top surface and part of the top sidewall surface of the gate, the material of the contact layer comprising a metal silicide; A first sidewall located on the sidewall surface of the gate, the first sidewall exposing a part of the contact layer; A second sidewall located on the sidewall of the first sidewall, the second sidewall and the first sidewall being made of different materials.

2. The semiconductor structure according to claim 1, wherein The top surface of the first sidewall is at a first distance from the top surface of the contact layer, the gate has a first thickness, and the ratio of the first distance to the first thickness ranges from greater than or equal to 1 / 3.

3. The semiconductor structure according to claim 2, wherein, The contact layer has a second thickness, the ratio of the second thickness to the first thickness of the gate ranges from greater than or equal to 1 / 4; the total height of the gate and the contact layer is a third height, the first sidewall has a fourth height, and the ratio of the third height to the fourth height ranges from greater than or equal to 1.

5.

4. The semiconductor structure according to claim 1, wherein, Further comprising: Source / drain regions in the substrate on both sides of the gate, the first sidewall, and the second sidewall; A lightly doped region in the substrate at the bottom of the second sidewall.

5. The semiconductor structure according to claim 1, characterized in that, The material of the first sidewall comprises a dielectric material, the dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride; the material of the first sidewall comprises silicon oxide.

6. The semiconductor structure according to claim 1, wherein The material of the second sidewall comprises a dielectric material, the dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride; the material of the second sidewall comprises silicon nitride.

7. The semiconductor structure according to claim 1, wherein, Further comprising: A third sidewall located between the first sidewall and the second sidewall, the material of the third sidewall being different from the material of the second sidewall, and the third sidewall is also located between the bottom of the second sidewall and the substrate.

8. The semiconductor structure according to claim 7, wherein The material of the third sidewall comprises a dielectric material, the dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride; the material of the third sidewall comprises silicon oxide.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming an initial gate on a part of the substrate; Forming an initial first sidewall on the sidewall of the initial gate; After forming the initial first sidewall, forming a second sidewall on the sidewall of the initial first sidewall, the second sidewall and the initial first sidewall being made of different materials, and the second sidewall exposing the top surface of the initial first sidewall; Etching the exposed initial first sidewall so that part of the top sidewall surface of the initial gate is exposed to form a first sidewall; Performing a metal silicide treatment on the exposed top surface and sidewall surface of the initial gate to form a contact layer, and forming a gate with the initial gate under the contact layer.

10. The method for forming a semiconductor structure according to claim 9, wherein, The method for forming the second sidewall includes: after forming the initial first sidewall, forming a second sidewall material layer on the substrate; and back-etching the second sidewall material layer.

11. The method for forming a semiconductor structure according to claim 10, wherein After forming the initial first sidewall and before forming the second sidewall material layer, the method further includes: forming a third sidewall material layer on the substrate, where the second sidewall material layer is located on the third sidewall material layer, and the materials of the third sidewall material layer and the second sidewall material layer are different; the method for forming the second sidewall further includes: etching back the second sidewall material layer until the third sidewall material layer is exposed.

12. The method for forming a semiconductor structure according to claim 11, wherein, Before forming the first sidewall, the third sidewall material layer is etched to expose the top surface of the initial first sidewall, and the third sidewall is formed with the third sidewall material layer.

13. The method for forming a semiconductor structure according to claim 9, wherein, The process of etching the exposed initial first sidewall includes a wet etching process.

14. The method for forming a semiconductor structure according to claim 9, wherein, The method for forming the initial first sidewall includes: forming a first sidewall material layer on the substrate; etching back the first sidewall material layer until the substrate surface is exposed.

15. The method for forming a semiconductor structure according to claim 14, wherein, The process of etching back the first sidewall material layer includes a dry etching process.

16. The method for forming a semiconductor structure according to claim 9, wherein The method further includes: After forming the initial first sidewall and before forming the second sidewall, using the initial first sidewall as a mask, initial lightly doped regions are formed in the substrate on both sides of the initial gate; after forming the second sidewall and before forming the contact layer, using the first sidewall and the second sidewall as masks, source / drain regions are formed in the substrate on both sides of the initial gate, and the initial lightly doped regions outside the source / drain regions are used as the lightly doped regions.

17. The method for forming a semiconductor structure according to claim 9, wherein The initial gate has a first height, and the exposed top sidewall of the initial gate has a second height, and the ratio range of the second height to the first height is greater than or equal to 1 / 3.

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