Refilling data processing method and apparatus, and device, storage medium and program

Abstract

Provided in the present application are a refilling data processing method and apparatus, and an electronic device, a computer-readable storage medium and a computer program. The method comprises: when a memory access instruction of a processor is acquired by means of a first cache, acquiring a hit result of the memory access instruction in the first cache; if the hit result is that the memory access instruction is not hit, suspending the memory access instruction, and sending an acquisition request to a second cache by means of the first cache at the same time; and upon receiving, by means of the first cache, refilling data sent by the second cache in response to the acquisition request, determining a target data block from the first cache, releasing old data stored in the target data block, and writing the refilling data into the target data block. In the present application, after receiving refilling data, a first cache releases old data stored in a selected target data block, thereby ensuring the normal implementation of the process of reading the old data by a memory access instruction during this period.

Description

Method, device, equipment, storage medium and program for processing refill data

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on January 12, 2024, with application number 202410053386.6 and application name “Processing method, device, equipment and storage medium for refilling data”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of computer technology, and in particular to a method, device, electronic device, computer-readable storage medium, and computer program for processing refill data. Background Art

[0004] Modern processors generally have three levels of cache: L1 cache, L2 cache and L3 cache. When the processor's memory access instruction misses the L1 cache, L2 cache needs to refill the data requested by the memory access instruction into the L1 cache to ensure normal data access. Similarly, when the memory access instruction misses the L2 cache, L3 cache needs to refill the requested data into the L2 cache.

[0005] Currently, in the process of refilling data from the lower-level cache to the upper-level cache, the upper-level cache first selects a data block (data is used to represent the location where data is stored) and releases the old data in it, and then waits for the lower-level cache to send the refill data, and then writes the refill data into the data block to realize data refilling.

[0006] However, in the above process, it often takes a long time to send the refill data from the lower-level cache to the upper-level cache. During the waiting time for the refill data, the old data in the data block has been released, but the refill data has not yet been received, so there is no valid data in the data block, but the data block is still occupied, resulting in idle and wasted cache resources. Summary of the Invention

[0007] Embodiments of the present application provide a method, device, electronic device, computer-readable storage medium, and computer program for processing refill data to solve problems in related technologies.

[0008] In a first aspect, an embodiment of the present application provides a method for processing refilled data, the method comprising:

[0009] When a memory access instruction of the processor is obtained through the first cache, obtaining a hit result of the memory access instruction in the first cache;

[0010] If the hit result is a miss, the memory access instruction is suspended, and a fetch request is sent to a second cache through the first cache; the second cache is a lower-level cache of the first cache;

[0011] When the first cache receives the refill data sent by the second cache in response to the acquisition request, the target data block is determined from the first cache, the old data stored in the target data block is released, and the refill data is written into the target data block.

[0012] In a second aspect, an embodiment of the present application provides a device for processing refill data, the device comprising:

[0013] an acquiring module, configured to, when a memory access instruction of the processor is acquired through the first cache, acquire a hit result of the memory access instruction in the first cache;

[0014] a miss module, configured to suspend the memory access instruction if the hit result is a miss, and simultaneously send an acquisition request to a second cache through the first cache; the second cache is a lower-level cache of the first cache;

[0015] A write module is used to determine a target data block from the first cache, release old data stored in the target data block, and write the refill data into the target data block when receiving the refill data sent by the second cache in response to the acquisition request through the first cache.

[0016] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor;

[0017] a memory for storing instructions executable by the processor;

[0018] The processor is configured to execute the instructions to implement the method of the first aspect.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0020] In a fifth aspect, an embodiment of the present application provides a computer program, comprising a computer-readable code, which, when executed on a computing and processing device, causes the computing and processing device to execute the method of the first aspect.

[0021] In an embodiment of the present application, when a memory access instruction misses in the first cache, the data block is not selected for release first, but the lower-level second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block. In this way, during the period before the refill data arrives, the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally. In addition, after the first cache receives the refill data, the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.

[0022] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] FIG1 is an architecture diagram of an implementation scenario provided by an embodiment of the present application;

[0025] FIG2 is a flowchart of a method for processing refill data provided by an embodiment of the present application;

[0026] FIG3 is a schematic diagram of the architecture of a first cache provided by an embodiment of the present invention;

[0027] FIG4 is a flowchart showing the specific steps of a method for processing refilled data provided by an embodiment of the present application;

[0028] FIG5 is a schematic diagram of the architecture of another first cache provided by an embodiment of the present invention;

[0029] FIG6 is a block diagram of a device for processing refill data provided by an embodiment of the present application;

[0030] FIG7 schematically shows a block diagram of a computing and processing device for executing the method according to the present application;

[0031] FIG8 schematically illustrates a storage unit for holding or carrying program codes for implementing the method according to the present application;

[0032] FIG9 is a block diagram of an electronic device provided in an embodiment of the present application. Specific embodiments

[0033] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0034] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0035] Referring to Figure 1, Figure 1 is an architecture diagram of an implementation scenario provided by an embodiment of the present application. In order to improve execution efficiency and reduce the interaction between the processor and the memory, modern processors can integrate a multi-level cache architecture on the processor. The common architecture is the three-level cache structure of Figure 1, including: Level 1 cache L1, Level 2 cache L2 and Level 3 cache L3. Level 1 cache L1 is the cache closest to the processor, with the smallest capacity and the fastest speed; Level 2 cache L2 has a larger capacity but is slower than Level 1 cache L1. Level 2 cache L2 is the buffer of Level 1 cache L1. The function of Level 2 cache L2 is to store data that is needed for processor processing but cannot be stored by Level 1 cache L1; Level 3 cache L3 has the largest capacity and is also the slowest level. Level 3 cache L3 and memory can be regarded as buffers of Level 2 cache L2.

[0036] When the processor is running, it will first search the L1 cache for the required data according to the memory access instruction, then the L2 cache, and then the L3 cache. If the data is not found in the L3 cache, it will be retrieved from the main memory. The longer the search path, the longer it takes. Therefore, if certain data needs to be retrieved frequently, it is best to ensure that this data is in the L1 cache, so that the speed will be very fast. Among them, the memory access instruction is an instruction to obtain data from a specified address in the main memory, or to store data to a specified address in the main memory.

[0037] In the above process, if the memory access instruction does not hit in the first-level cache L1 (meaning that the first-level cache L1 does not store the data requested to be read by the memory access instruction), the memory access instruction will continue to search whether it hits in the second-level cache L2. If it hits in the second-level cache L2, the second-level cache L2 will refill the data requested to be read by the memory access instruction into the first-level cache L1; if it does not hit in the second-level cache L2, the memory access instruction will continue to search whether it hits in the third-level cache L3. If it hits in the third-level cache L3, the third-level cache L3 will refill the data requested to be read by the memory access instruction into the second-level cache L2, and then the second-level cache L2 will refill the data into the first-level cache L1.

[0038] However, due to the limited cache space, when a cache capacity conflict occurs (i.e., the cache space is full and insufficient to continue storing the refilled data), it is necessary to select a data block in the first cache waiting to be refilled to release the old data therein, thereby freeing up space to store the refilled data.

[0039] The related technology involves a first cache notifying a lower-level second cache to refill data while selecting a data block in the first cache to release the old data. The first cache then waits for the lower-level cache to send the refill data, then writes the refill data into the data block to refill the data. This results in the vacant data block being continuously occupied while waiting for the refill data. Furthermore, if the old data is needed during this process, it cannot be successfully accessed because the old data has been released.

[0040] In order to solve this problem, the embodiment of the present application may not select a data block for release when the memory access instruction does not hit in the first cache, but instead notify the lower-level second cache to obtain the refill data required for the memory access request, wait for the second cache to obtain the refill data and send the refill data to the first cache, and then determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data to the target data block. In this way, during the period before the refill data arrives, the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally. In addition, after the first cache receives the refill data, the present application releases the old data stored in the selected target data block and writes the refill data to the target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.

[0041] FIG2 is a flowchart of a method for processing refilled data provided by an embodiment of the present application. As shown in FIG2 , the method may include:

[0042] Step 101: When a memory access instruction of a processor is obtained through a first cache, a hit result of the memory access instruction in the first cache is obtained.

[0043] In an embodiment of the present application, after the memory access instruction enters the pipeline of the first cache, it is necessary to further check whether the first cache contains the data requested to be read by the memory access instruction. The process of determining whether the data exists can be understood as determining the hit result of the memory access instruction in the first cache. The hit result includes a hit or a miss. A hit represents that the first cache contains the data requested to be read by the memory access instruction; a miss represents that the first cache does not contain the data requested to be read by the memory access instruction.

[0044] Specifically, judging the hit result of the memory access instruction in the first cache requires traversing the cache directory of the first cache, so it takes a certain amount of time, which is fixed. Referring to Figure 3, it shows a schematic diagram of the architecture of the first cache. The first cache can adopt a 5-stage pipeline architecture, that is, it includes a pipeline queue with 5 sequentially arranged data bits, each data bit corresponds to a pipeline moment, and different data bits correspond to different pipeline moments. The instruction is used to enter the pipeline from the initial data bit S1 of the pipeline queue and change the data bit as time passes. The embodiment of the present application can obtain the hit result of the memory access instruction in the first cache (obtain the hit result at the moment corresponding to the S3 data bit) after the memory access instruction enters the pipeline from the starting data bit (S1) of the pipeline queue, after a fixed number of data bits (for example, 2 data bits are separated). Since a hit result is obtained, and the hit result includes a hit or a miss. Therefore, the embodiment of the present application can subsequently perform corresponding instruction control operations based on the hit result.

[0045] It should be noted that the interval of a fixed number of data bits (Figure 3 shows an interval of 2 data bits) refers to the time required to wait for the execution of the operation of determining the hit result of the memory access instruction in the first cache. Since the time is fixed, and the data bits in the pipeline queue of the first cache represent the moment, the time can be converted into a fixed number of data bits. Starting from the starting data bit (S1), a fixed number of data bits are spaced apart to represent the completion of the execution process of waiting for the determination of whether a hit is achieved after the memory access instruction enters the pipeline of the first cache, thereby obtaining the hit result of the memory access instruction in the first cache.

[0046] Step 102: If the hit result is a miss, the memory access instruction is suspended, and a fetch request is sent to a second cache through the first cache; the second cache is a lower-level cache of the first cache.

[0047] In an embodiment of the present application, the hit result of the memory access instruction in the first cache is a hit, indicating that the first cache has the data requested to be read by the memory access instruction. If the first cache also has a superior third cache, the first cache can refill the data requested to be read by the memory access instruction into the third cache; if the first cache does not have a superior third cache, the processor can read the data directly from the first cache through the memory access instruction.

[0048] In this step, the hit result of the memory access instruction in the first cache is a miss, indicating that the first cache does not store the data requested by the memory access instruction. At this time, it is necessary to check whether the second cache below the first cache has the data. If the data is stored in the second cache, the second cache is allowed to refill the data into the first cache. Therefore, when the hit result is a miss, the embodiment of the present application can suspend the memory access instruction and send a get request to the second cache through the first cache to request the second cache to find the refill data required by the memory access instruction and send it to the first cache. In addition, when the hit result is a miss, the embodiment of the present application does not need to immediately find the target data block in the first cache for release. In this way, during the period before the refill data arrives, the target data block storing the old data can operate normally and the old data can also be accessed normally. The second cache is a lower-level cache of the first cache. For example, for the three-level cache structure: first-level cache L1, second-level cache L2 and third-level cache L3, assuming that the first cache is first-level cache L1, then the second-level cache can be second-level cache L2; assuming that the first cache is second-level cache L2, then the second-level cache can be third-level cache L3.

[0049] It should be noted that, referring to Figure 3, when the hit result of the memory access instruction in the first cache is a miss, the memory access instruction is suspended, which means that the memory access instruction is removed from the pipeline queue of the first cache and enters an assigned miss status register (MSHR, Miss-status Handling Registers) for waiting. The miss status register is a register used to record each unfinished transaction. The recorded information includes the failed address, keyword information, and the incomplete execution instruction. Once the second cache completes the refill of the first cache, the memory access instruction in the miss status register can be re-executed. The re-executed memory access instruction can re-enter the pipeline queue of the first cache.

[0050] Step 103: When the first cache receives the refill data sent by the second cache in response to the acquisition request, determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data into the target data block.

[0051] In an embodiment of the present application, the process of the second cache responding to the acquisition request to find and obtain the refill data and sending it to the first cache usually takes a long time (it takes dozens to hundreds of data bits in the pipeline of the first cache). However, during the period when the first cache waits for the refill data to be sent, the embodiment of the present application does not release or occupy the data block containing the old data, thereby improving the utilization of cache resources while ensuring that the old data can be accessed normally.

[0052] Furthermore, in an embodiment of the present application, the target data block is selected only when the refill data sent by the second cache is received through the first cache. If the target data block stores old data, the old data is released and the refill data is written into the target data block. In this way, during the period before the refill data arrives, the data block storing the old data in the first cache can operate normally and is not vacant or occupied, and the old data can also be accessed normally. After the first cache receives the refill data, the old data stored in the selected target data block is released and the refill data is written into the target data block, which also ensures the normal implementation of the memory access instruction data reading process.

[0053] In summary, in the embodiment of the present application, when a memory access instruction does not hit in the first cache, the data block is not selected for release first, but the lower-level second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block. In this way, during the period before the arrival of the refill data, the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally. In addition, after the first cache receives the refill data, the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.

[0054] FIG4 is a flowchart of specific steps of a method for processing refilled data provided by an embodiment of the present application. As shown in FIG4 , the method may include:

[0055] Step 201: When a memory access instruction of a processor is obtained through a first cache, a hit result of the memory access instruction in the first cache is obtained.

[0056] This step may be specifically referred to the above step 101 and will not be described in detail here.

[0057] Step 202: If the hit result is a miss, the memory access instruction is controlled to leave the pipeline queue and enter the missing status register for suspended waiting, and at the same time, an acquisition request is sent to the second cache through the first cache; the second cache is a lower-level cache of the first cache.

[0058] In an embodiment of the present application, referring to Figure 3, the hit result of the memory access instruction in the first cache is a miss, indicating that the data requested to be read by the memory access instruction is not stored in the first cache. At this time, it is necessary to send a get request to the lower-level second cache through the first cache to check whether the lower-level second cache has the data. If the data is stored in the second cache, the second cache responds to the get request and refills the data into the first cache.

[0059] Specifically, when the hit result is a miss, the memory access instruction can be removed from the pipeline queue of the first cache and enter an allocated miss status register (MSHR) to wait. The miss status register is a register used to record each unfinished transaction. Once the second cache completes the refill of the first cache, the memory access instruction in the miss status register can be re-executed, and the re-executed memory access instruction can re-enter the pipeline queue of the first cache.

[0060] Among them, the memory access instruction is separated from the pipeline queue of the first cache because the data requested by the memory access instruction is not stored in the first cache, which causes the memory access instruction to currently fail to realize data reading. Therefore, the memory access instruction is first separated from the pipeline queue of the first cache and enters the missing status register to wait, so as to avoid interfering with the execution of other requests of the first cache. After waiting for the lower-level second cache to send the data requested by the memory access instruction to the first cache, the data requested by the memory access instruction has been obtained by the first cache, then the memory access instruction in the missing status register can enter the pipeline queue of the first cache again, so as to correctly read the data in the first cache.

[0061] Step 203: When the refill data sent by the second cache in response to the acquisition request is received through the first cache, the first cache directory is read starting from the starting data bit of the pipeline queue of the first cache, and after an interval of a first number of data bits, the target data block is determined from the first cache according to the first cache directory.

[0062] In an embodiment of the present application, referring to FIG5 , which shows another schematic diagram of the architecture of the first cache, FIG5 is a first cache processing process connected to FIG3 . When the first cache receives the refill data sent by the second cache in response to the acquisition request, the data requested by the memory access instruction has been obtained by the first cache, and the memory access instruction in the missing status register can enter the pipeline queue of the first cache again. Specifically, the memory access instruction can enter the pipeline from the starting data bit (S1 data bit) of the pipeline queue of the first cache, and read the first cache directory starting from the starting data bit (S1 data bit). The first cache directory is a data that represents the directory of data stored in the first cache. By reading the first cache directory, a target data block can be determined from the first cache to release and store the refill data.

[0063] Optionally, step 203 may specifically include sub-steps 2031-2032:

[0064] Sub-step 2031: According to the first cache directory, obtain the last access time of each data block in the first cache.

[0065] Sub-step 2032: Use the data block with the earliest last access time as the target data block.

[0066] In one implementation of an embodiment of the present application, for sub-steps 2031-2032, the first cache directory records the last access time of each data block in the first cache. Then, the embodiment of the present application can obtain the last access time of each data block in the first cache based on the first cache directory, and use the data block with the earliest last access time as the target data block. The data block with the earliest last access time indicates that the data stored in the data block is the least active. Therefore, using the data block with the earliest last access time as the target data block can minimize the impact on the more active data in other data blocks.

[0067] In another implementation of the embodiment of the present application, a data block may be randomly selected from the first cache as the target data block. The embodiment of the present application does not specifically limit the strategy for selecting the target data block.

[0068] Optionally, step 203 may further include sub-steps 2033-2034:

[0069] Sub-step 2033: When receiving the refill data sent by the second cache in response to the acquisition request through the first cache, detecting the storage status of the first cache.

[0070] Sub-step 2034: When it is determined that the storage status is: there is no free data block in the first cache that can store the refill data, determine a target data block from the first cache.

[0071] In an embodiment of the present application, for sub-steps 2033-2034, before determining the target data block in the first cache, the storage status of the first cache can be detected first. If the storage status is that there is a free data block in the first cache that can store the refill data, the free data block is directly used as the target data block. However, when a capacity conflict occurs in the first cache (there is no free data block in the first cache that can store the refill data), it is necessary to determine the target data block from the first cache through the method of the above embodiment, release the old data in the target data block to make it a free data block, and write the refill data into the free target data block.

[0072] Step 204: Write the refill data into the refill buffer area of ​​the first cache.

[0073] In an embodiment of the present application, referring to Figure 5, when the first cache just receives the refill data sent by the second cache of the lower level (the refill data has not yet been written to the target data block at this time), it is necessary to temporarily store the refill data before writing the refill data to the target data block. Therefore, an independent refill buffer area can be set up in the first cache, and the first cache can write the refill data into the refill buffer area for temporary storage.

[0074] Step 205: read the refill buffer area at the data bit following the starting data bit, and read the refill data after an interval of a second number of data bits, write the read refill data into the write buffer area of ​​the first cache, and read the old data in the target data block.

[0075] In an embodiment of the present application, referring to Figure 5, the operation of reading the refill buffer area is started at the next data bit (S2 data bit) after the starting data bit (S1 data bit) of the pipeline queue of the first cache. Since it takes a fixed time for the first cache to read the refill cache area from the beginning to read the refill data (corresponding to the pipeline, it takes a time corresponding to 1 data bit), the refill data can be read at the S3 data bit after the second number of data bits (1 data bit).

[0076] In the S3 data bit of the pipeline queue of the first cache, while the first cache reads the refill data from the refill buffer area, the first cache can also write the refill data into the write buffer area of ​​the first cache (not shown in the figure). The write buffer area is an independent storage area established in the first cache. Its function is to determine whether to write the refill data into the target data block based on whether a read operation is performed on the target data block, and to write the refill data into the target data block when it is determined to write.

[0077] Furthermore, in the S3 data bit of the pipeline queue of the first cache, the first cache also synchronously starts an operation of reading old data in the target data block.

[0078] Step 206: After a third number of data bits have passed, the old data obtained by reading is stored in the second cache, thereby completing the release of the target data block.

[0079] In an embodiment of the present application, referring to Figure 5, the first cache also synchronously starts the operation of reading the old data in the target data block in the S3 data bit of the pipeline queue of the first cache. Since it takes a fixed time for the first cache to read the target data block from the beginning to read the old data therein (corresponding to the pipeline, it takes a time corresponding to 2 data bits), after an interval of the third number of data bits (an interval of 2 data bits), the old data in the target data block can be read at the S5 data bit of the pipeline queue of the first cache. At this time, the old data is read out from the target data block.

[0080] Furthermore, the S5 data bit of the pipeline queue of the first cache can also send the read old data to the second cache to complete the release of the target data block.

[0081] It should be noted that after the old data in the target data block is released, if a read instruction for the old data is received subsequently, the first cache still needs to obtain data from the second cache and refill it into the first cache according to steps 201 to 207 to meet the requirements of the read instruction to read the old data.

[0082] Step 207: When it is detected that the operation of reading the target data block is completed, write the refill data in the write buffer area into the target data block.

[0083] In an embodiment of the present application, the function of the write buffer section is to determine whether to write the refill data to the target data block based on the determination of the read operation performed on the target data block. Specifically, in an embodiment of the present application, a higher priority is set for the operation of reading the target data block. Therefore, the write buffer section must wait until all read operations on the target data block are completed before it can begin the operation of writing the refill data in the write buffer section to the target data block. In other words, if the write buffer section determines that all read operations performed on the target data block are completed, the write buffer section executes the operation of writing the refill data in the write buffer section to the target data block, thereby completing the operation of storing the refill data in the first cache storage unit.

[0084] Optionally, the method may further include:

[0085] Step 208: When the first address carried in the read request received by the first cache matches the second address of the target refill data in the write buffer area, return the target refill data as a response to the read request.

[0086] In an embodiment of the present application, if a read request for the target refill data is received while the target refill data is in the write buffer area but has not yet been written to the target data block, the target refill data in the write buffer area can be directly returned as a response to the read request. Specifically, if the first address of the read request received by the first cache matches the second address of the target refill data in the write buffer area, the data requested by the read request is determined to be the target refill data in the refill buffer area.

[0087] It should be noted that, in summary, the missing status register can establish two tasks. The first task is used to implement the above-mentioned embodiment in which the first cache obtains the refill data from the second cache; the second task is used to implement the above-mentioned embodiment in which the target data block is determined, the target data block is released, the refill data is written into the target data block, and the refill data is continued to be refilled to the upper cache.

[0088] Optionally, the method may further include:

[0089] Step 209: After writing the refill data into the target data block, extract the memory access instruction from the missing status register, write the refill data into the third cache, and wake up the operation of reading data from the third cache through the memory access instruction.

[0090] The third cache is an upper-level cache of the first cache; and the memory access instruction misses in the third cache.

[0091] In an embodiment of the present application, if the first cache does not have a third cache at an upper level, a memory access instruction can directly obtain refill data from the first cache and feed it back to the processor. However, if the first cache has a third cache at an upper level, after writing the refill data to the target data block, the first cache also needs to extract the memory access instruction from the miss status register, write the refill data to the third cache, and wake up the operation of reading data from the third cache via the memory access instruction. That is, the memory access instruction first accesses the upper cache, and if the access to the upper cache does not hit, then accesses the data in the lower cache to access the data. Therefore, if the memory access instruction does not hit in the upper third cache, after the lower second cache writes the refill data to the first cache at the same level, the first cache also needs to refill the refill data into the upper third cache. If the third cache no longer has a higher cache at an upper level, the operation of reading data from the third cache via the memory access instruction can be woken up. After waking up, the memory access instruction can directly obtain the refill data from the third cache and feed it back to the processor. Similarly, if the third cache has a higher cache at an upper level, the third cache still needs to continue to refill the refill data into the higher cache.

[0092] Optionally, step 209 may specifically include sub-steps 2091-2092:

[0093] Sub-step 2091: Control the memory access instruction to enter the pipeline queue of the first cache from the starting data bit, and at the same time generate a wake-up instruction through the first cache and send it to the third cache through the wake-up queue.

[0094] Sub-step 2092: After spacing the second number of data bits in the pipeline queue, obtain refill data through the first cache, and send the memory access instruction as a refill instruction from the refill queue to the third cache.

[0095] The wake-up instruction is used to wake up the operation of reading data from the third cache through the memory access instruction; and the refill instruction is used to write the refill data into the third cache for reading by the memory access instruction.

[0096] In an embodiment of the present application, the hit result is a miss, indicating that the data requested to be read by the memory access instruction is not stored in the first cache. At this time, it is necessary to check whether the lower-level second cache has the data. If the data is stored in the second cache, the second cache will refill the data into the first cache for reading by the memory access instruction.

[0097] Specifically, referring to Figure 3, after waiting for the second cache to refill the first cache, the memory access instruction is controlled to re-enter the pipeline queue from the starting data bit, and at the same time, a wake-up instruction is generated through the first cache and issued by the wake-up queue to the upper-level third cache (the moment of entering the wake-up queue and issuing the wake-up instruction is the moment corresponding to the data bit S1); and after an interval of the second number of data bits (an interval of 2 data bits), the refill data is obtained through the first cache, and the memory access instruction is issued from the refill queue to the third cache as a refill instruction.

[0098] For example, referring to Figure 3, when the hit result is a miss, the actual sending time of the wake-up request is the moment corresponding to data bit S1. Since the refill request has to wait in the refill queue for the length of time represented by a data bit (ensuring that the refill request at the exit of the refill queue is issued in time to reduce the chance of congestion in the refill queue), the actual sending time of the refill request is the moment corresponding to data bit S4. It can be seen that the embodiment of the present application can ensure that for each refill request, a wake-up request is issued three data bits in advance.

[0099] The embodiment of the present application implements the management of memory access instructions through a concise and clear multi-level pipeline queue architecture of the first cache. Based on the pipeline queue, a method is designed to obtain the hit result of the memory access instruction and send a wake-up request at a fixed data bit, and to obtain refill data at another fixed data bit and send the refill request through the refill queue. Based on the pipeline queue architecture and the design of each processing timing of the instruction in the pipeline, it is possible to achieve accurate and stable control of the fixed advance amount of the wake-up request, ensuring the accuracy and coverage of the memory access instruction reading process. The entire process does not require reading the status of the requests at each level of the pipeline, and the real-time calculation of the advance issuance time based on the status of the refill queue request, so the complexity is extremely low, reducing the cost and power consumption of the circuit.

[0100] Optionally, the method may further include:

[0101] Step 210: If the hit result is a hit, read the data in the data block hit by the memory access instruction in the first cache and return it.

[0102] In an embodiment of the present application, the hit result of the memory access instruction in the first cache is a hit, indicating that the first cache has the data requested to be read by the memory access instruction. If the first cache also has a superior third cache, the first cache can refill the data requested to be read by the memory access instruction into the third cache; if the first cache does not have a superior third cache, the processor can read the data directly from the first cache through the memory access instruction.

[0103] In summary, in an embodiment of the present application, when a memory access instruction misses in the first cache, the data block is not selected for release first, but the lower-level second cache is notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block is determined from the first cache, and the old data stored in the target data block is released, and the refill data is written into the target data block. In this way, during the period before the refill data arrives, the data block storing the old data operates normally, is not vacant or occupied, and the old data can also be accessed normally. In addition, after the first cache receives the refill data, the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.

[0104] FIG6 is a block diagram of a device for processing refill data provided by an embodiment of the present application, the device comprising:

[0105] An acquisition module 301 is configured to, when a memory access instruction of a processor is acquired through a first cache, acquire a hit result of the memory access instruction in the first cache;

[0106] a miss module 302 configured to suspend the memory access instruction if the hit result is a miss, and simultaneously send a fetch request to a second cache through the first cache; the second cache is a lower-level cache of the first cache;

[0107] The writing module 303 is used to determine the target data block from the first cache, release the old data stored in the target data block, and write the refill data into the target data block when the refill data sent by the second cache in response to the acquisition request is received through the first cache.

[0108] Optionally, the writing module 303 includes:

[0109] The determination submodule is configured to read a first cache directory starting from a start data bit of the pipeline queue of the first cache, and determine the target data block from the first cache according to the first cache directory after an interval of a first number of data bits.

[0110] Optionally, the writing module 303 includes:

[0111] A first writing submodule, configured to write the refill data into a refill buffer area of ​​the first cache;

[0112] a processing submodule, configured to read the refill buffer area at a data bit following the start data bit, and read the refill data after an interval of a second number of data bits, write the read refill data into the write buffer area of ​​the first cache, and read old data in the target data block;

[0113] a releasing submodule, configured to store the read old data into the second cache after a third number of data bits have passed, thereby completing the release of the target data block;

[0114] The second writing submodule is configured to write the refill data in the write buffer area into the target data block upon detecting that the operation of reading the target data block is completed.

[0115] Optionally, the device further includes:

[0116] A return module is used to return the target refill data as a response to the read request when the first address carried by the read request received by the first cache matches the second address of the target refill data in the write buffer area.

[0117] Optionally, the determining submodule includes:

[0118] an acquiring unit, configured to acquire, according to the first cache directory, a last access time of each data block in the first cache;

[0119] The determining unit is configured to use the data block with the earliest last access time as the target data block.

[0120] Optionally, the miss module 302 includes:

[0121] The suspend submodule is used to control the memory access instruction to leave the pipeline queue and enter the missing status register to suspend and wait if the hit result is a miss.

[0122] Optionally, the device further includes:

[0123] a wake-up module, configured to extract the memory access instruction from the missing status register after writing the refill data into the target data block, write the refill data into the third cache, and wake up an operation of reading data from the third cache through the memory access instruction;

[0124] The third cache is an upper-level cache of the first cache; and the memory access instruction misses in the third cache.

[0125] Optionally, the wake-up module includes:

[0126] An entry submodule, configured to control the memory access instruction to enter the pipeline queue of the first cache from the starting data bit, and at the same time generate a wake-up instruction through the first cache and send it from the wake-up queue to the third cache;

[0127] a sending submodule, configured to obtain refill data through the first cache after the second number of data bits are spaced apart in the pipeline queue, and send the memory access instruction as a refill instruction from the refill queue to the third cache;

[0128] The wake-up instruction is used to wake up the operation of reading data from the third cache through the memory access instruction; and the refill instruction is used to write the refill data into the third cache for reading by the memory access instruction.

[0129] Optionally, the device further includes:

[0130] A hit module is configured to read the data in the data block hit by the memory access instruction in the first cache and return the data if the hit result is a hit.

[0131] Optionally, the writing module 303 includes:

[0132] a detection submodule, configured to detect a storage status of the first cache upon receiving, through the first cache, refill data sent by the second cache in response to the acquisition request;

[0133] The full-load submodule is configured to determine a target data block from the first cache when it is determined that the storage condition is that there is no free data block in the first cache that can store the refill data.

[0134] Optionally, the pipeline queue includes five data bits arranged in sequence.

[0135] Optionally, the first number is 1.

[0136] Optionally, the second number is 1.

[0137] Optionally, the third quantity is 2.

[0138] Optionally, the missing status register records the memory access instruction that has not been completed, the failure address of the memory access instruction that has not been completed, and the keyword information of the memory access instruction that has not been completed.

[0139] Optionally, the device further includes:

[0140] The data release module is used to release the old data in the target data block, so that the target data block becomes an idle data block.

[0141] In summary, in an embodiment of the present application, when a memory access instruction misses in the first cache, the data block may not be selected for release first, but the lower-level second cache may be notified to obtain the refill data required for the memory access request, and when the second cache obtains the refill data and sends the refill data to the first cache, the target data block may be determined from the first cache, and the old data stored in the target data block may be released, and the refill data may be written into the target data block. In this way, during the period before the refill data arrives, the data block storing the old data operates normally, is not vacant or occupied, and the old data may be accessed normally. In addition, after the first cache receives the refill data, the present application releases the old data stored in the selected target data block, which also ensures the normal implementation of the old data reading process of the memory access instruction during this period.

[0142] The various component embodiments of the present application can be implemented in hardware, or in a software module running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the computing processing equipment according to the embodiment of the present application. The application can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for performing a part or all of the methods described herein. Such a program implementing the present application can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0143] For example, FIG7 illustrates a computing device that can implement the methods according to the present application. The computing device typically includes a processor 1010 and a computer program product or computer-readable medium in the form of a memory 1020. Memory 1020 can be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, a hard disk, or ROM. Memory 1020 has storage space 1030 for program code 1031 for executing any of the method steps described above. For example, storage space 1030 for program code can include individual program codes 1031 for implementing various steps in the method described above. These program codes can be read from or written to one or more computer program products. These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards, or floppy disks. Such computer program products are typically portable or fixed storage units, as described with reference to FIG8 . This storage unit can have storage segments, storage space, and the like arranged similarly to memory 1020 in the computing device of FIG7 . The program code can, for example, be compressed in a suitable form. Typically, the storage unit includes computer-readable codes 1031 ′, ie, codes that can be read by a processor such as 1010 , which, when executed by a computing device, cause the computing device to perform the steps of the method described above.

[0144] Figure 9 is a block diagram of an electronic device according to an embodiment of the present invention. As shown in Figure 9 , the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions that cause the processor to execute the data refill processing method according to the aforementioned embodiment.

[0145] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0146] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, for example. The communication bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of illustration, FIG9 shows only one line, but this does not imply that there is only one bus or only one type of bus.

[0147] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0148] An embodiment of the present application also provides a computer program product, including a computer program, and a method for processing refill data implemented when the computer program is executed by a processor.

[0149] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0150] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0151] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0152] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

[0153] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0154] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

[0155] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

[0156] The above is a detailed introduction to the processing method, device, electronic device, computer-readable storage medium and computer program for refilling data provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for processing re-filled data, wherein, The method includes: When a memory access instruction of a processor is obtained through a first cache, obtaining a hit result of the memory access instruction in the first cache; If the hit result is a miss, suspending the memory access instruction and simultaneously sending a fetch request to a second cache through the first cache; the second cache is a lower-level cache of the first cache; When receiving refill data sent by the second cache in response to the fetch request through the first cache, determining a target data block from the first cache, releasing old data stored in the target data block, and writing the refill data into the target data block.

2. The processing method for refilled data according to claim 1, wherein, The determining the target data block from the first cache includes: Reading a first cache directory starting from the starting data bit of a pipeline queue of the first cache, and after skipping a first number of data bits, determining the target data block from the first cache according to the first cache directory.

3. The method for processing re-filled data according to claim 2, wherein, The releasing the old data stored in the target data block and writing the refill data into the target data block includes: Writing the refill data into a refill buffer area of the first cache; Reading the refill buffer area at the next data bit after the starting data bit, and after skipping a second number of data bits, reading the obtained refill data, writing the read refill data into a write buffer area of the first cache, and reading the old data in the target data block; After skipping a third number of data bits, storing the read old data into the second cache to complete the release of the target data block; When detecting that the operation of reading the target data block ends, writing the refill data in the write buffer area into the target data block.

4. The method for processing re-filled data according to claim 3, wherein, The method further includes: When a first address carried by a read request received by the first cache matches a second address of target refill data in the write buffer area, returning the target refill data as a response to the read request.

5. The method for processing refilled data according to claim 2, wherein, The determining the target data block from the first cache according to the first cache directory includes: According to the first cache directory, obtaining the last access time of each data block in the first cache; Taking the data block with the earliest last access time as the target data block.

6. The processing method for refilled data according to claim 1, wherein, The suspending the memory access instruction if the hit result is a miss includes: If the hit result is a miss, controlling the memory access instruction to break away from the pipeline queue and enter a miss status register for suspension waiting.

7. The method for processing refilled data according to claim 6, wherein, The method further includes: After writing the refill data into the target data block, extracting the memory access instruction from the miss status register, writing the refill data into a third cache, and waking up an operation of reading data from the third cache through the memory access instruction; wherein the third cache is a higher-level cache of the first cache; the memory access instruction misses in the third cache.

8. The method for processing refilled data according to claim 7, wherein, The writing the refill data into the third cache and waking up the operation of reading data from the third cache through the memory access instruction includes: Control the memory access instruction to enter the pipeline queue of the first cache from the starting data bit, and at the same time generate a wake-up instruction through the first cache and issue it to the third cache by the wake-up queue; After an interval of a second quantity of data bits in the pipeline queue, obtain refill data through the first cache, and issue the memory access instruction as a refill instruction to the third cache by the refill queue; Wherein, the wake-up instruction is used to wake up the operation of reading data from the third cache through the memory access instruction; the refill instruction is used to write the refill data into the third cache for the memory access instruction to read.

9. The method for processing refilled data according to claim 1, wherein The method further includes: If the hit result is a hit, read the data in the data block hit by the memory access instruction in the first cache and return it.

10. The method for processing refilled data according to claim 1, wherein, When receiving the refill data sent by the second cache in response to the acquisition request through the first cache, determining a target data block from the first cache includes: When receiving the refill data sent by the second cache in response to the acquisition request through the first cache, detecting the storage status of the first cache; When determining that the storage status is that there is no idle data block in the first cache that can store the refill data, determining a target data block from the first cache.

11. The method for processing refilled data according to claim 2, wherein, The pipeline queue includes five data bits arranged in sequence.

12. The method for processing refilled data according to claim 2, wherein, The first quantity is 1.

13. The method for processing refill data according to claim 3 or 8, wherein, The second quantity is 1.

14. The processing method for re-filled data according to claim 3, wherein, The third quantity is 2.

15. The processing method for re-filled data according to claim 6, wherein, The miss status register records the memory access instructions that have not been completed, the invalid addresses of the memory access instructions that have not been completed, and the key information of the memory access instructions that have not been completed.

16. The processing method for re-filled data according to claim 10, wherein, After determining the target data block from the first cache, it further includes: Release the old data in the target data block to make the target data block become an idle data block.

17. A processing device for re-filling data, wherein, The device includes: An acquisition module, configured to acquire the hit result of the memory access instruction in the first cache when the memory access instruction of the processor is acquired through the first cache; A miss module, configured to suspend the memory access instruction if the hit result is a miss, and at the same time send an acquisition request to the second cache through the first cache; the second cache is a lower-level cache of the first cache; A writing module, configured to determine a target data block from the first cache when receiving the refill data sent by the second cache in response to the acquisition request through the first cache, release the old data stored in the target data block, and write the refill data into the target data block.

18. An electronic device, wherein, Includes: A processor; A memory for storing executable instructions of the processor; Wherein, the processor is configured to execute the instructions to implement the method according to any one of claims 1 to 16.

19. A computer-readable storage medium, wherein, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device can execute the method according to any one of claims 1 to 16.

20. A computer program comprising computer-readable code which, when run on a computing processing device, causes the computing processing device to perform the method according to any one of claims 1 - 16.

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