Control method for pixel circuit, display panel, and display apparatus

Abstract

A control method for a pixel circuit. The pixel circuit comprises a drive transistor, a compensation transistor, and a bias transistor. A control electrode of the drive transistor is electrically connected to a first node, a first electrode thereof is electrically connected to a second node, and a second electrode thereof is electrically connected to a third node. A control electrode of the compensation transistor is electrically connected to a first scanning signal line, a first electrode thereof is electrically connected to the third node, and a second electrode thereof is electrically connected to the first node. A control electrode of the bias transistor is electrically connected to a second scanning signal line, a first electrode thereof is electrically connected to a bias voltage signal line, and a second electrode thereof is electrically connected to the second node. The control method comprises: in a bias stage, the bias transistor transmits a first bias voltage to the first node at least twice sequentially by means of the drive transistor and the compensation transistor, and there is a first time interval between two adjacent transmissions of the first bias voltage performed by the bias transistor. The polarity of the first bias voltage is opposite to the polarity of the voltage of the first node.

Description

Pixel circuit control method, display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410052298.4, filed on January 12, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a control method for a pixel circuit, a display panel, and a display device. Background Art

[0003] With the continuous development of display technology, organic light-emitting diode (OLED) display panels have gradually become a mainstream product in the display field due to their excellent performance, such as self-luminescence, lack of backlight, high contrast, thinness, wide viewing angle, fast response time, flexibility, wide operating temperature range, and simple structure and manufacturing process. OLED display panels are widely used in end products such as smartphones, tablets, TVs, and wearable devices (such as watches). However, improving the short-term image retention of OLED display panels is a technical issue that needs to be addressed. Summary of the Invention

[0004] In one aspect, a method for controlling a pixel circuit is provided. The pixel circuit includes a driving transistor, a compensation transistor, and a bias transistor. The driving transistor has a control electrode electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node. The compensation transistor has a control electrode electrically connected to a first scanning signal line, a first electrode electrically connected to the third node, and a second electrode electrically connected to the first node. The bias transistor has a control electrode electrically connected to a second scanning signal line, a first electrode electrically connected to a bias voltage signal line, and a second electrode electrically connected to the second node. A frame period includes a bias phase. The control method includes: during the bias phase, the bias transistor sequentially transmits a first bias voltage to the first node at least twice through the driving transistor and the compensation transistor, with a first time interval between two adjacent transmissions of the first bias voltage by the bias transistor; the first bias voltage has an electrical property opposite to that of the voltage at the first node.

[0005] In some embodiments, the pixel circuit further includes a first reset transistor, wherein a control electrode of the first reset transistor is electrically connected to the third scan signal line, a first electrode is electrically connected to the first reset voltage signal line, and a second electrode is electrically connected to the first node. The control method further includes: during the bias phase and within the first time interval, the first reset transistor transmits a first reset voltage to the first node, wherein the electrical property of the first reset voltage is opposite to that of the first bias voltage.

[0006] In some embodiments, during the first time interval, the compensation transistor is turned on under the control of a first scan signal from the first scan signal line.

[0007] In some embodiments, the first time interval is greater than a turn-on time of the first reset transistor.

[0008] In some embodiments, the bias phase includes at least two first time periods and at least one second time period, with a second time period between two adjacent first time periods. The control method includes: during the first time period, the second scan signal line transmits a second scan signal, and the bias transistor is turned on under the control of the second scan signal. During the second time period, the third scan signal line transmits a third scan signal, and the first reset transistor is turned on under the control of the third scan signal. There is a second time interval between adjacent first and second time periods.

[0009] In some embodiments, the first time period is greater than 1 hour, and / or the second time period is greater than 1 hour, and / or the second time interval is greater than 1 hour.

[0010] In some embodiments, the pixel circuit further includes a data write transistor, a second reset transistor, a first emission control transistor, and a second emission control transistor. The data write transistor has a control electrode electrically connected to the fourth scan signal line, a first electrode electrically connected to the data signal line, and a second electrode electrically connected to the second node. The second reset transistor has a control electrode electrically connected to the second scan signal line, a first electrode electrically connected to the second reset voltage signal line, and a second electrode electrically connected to the fourth node. The first emission control transistor has a control electrode electrically connected to the emission control signal line, a first electrode electrically connected to the first voltage signal line, and a second electrode electrically connected to the second node. The second emission control transistor has a control electrode electrically connected to the emission control signal line, a first electrode electrically connected to the third node, and a second electrode electrically connected to the fourth node. A frame period further includes a first reset phase, a data write phase, and a second reset phase, sequentially provided after the bias phase. The control method further includes: in the first reset phase, the first reset transistor transmits the first reset voltage to the first node, and the compensation transistor is first turned off and then turned on, whereupon the compensation transistor transmits the first reset voltage from the first node to the third node. In the data writing phase, the data writing transistor transmits a data signal from the data signal line to the second node, and the data signal is sequentially transmitted to the first node via the driving transistor and the compensation transistor. In the second reset phase, the bias transistor transmits a second bias voltage to the second node.

[0011] On the other hand, a display panel is provided, comprising a plurality of pixel circuits and a plurality of light-emitting devices, wherein one light-emitting device is electrically connected to one pixel circuit, and the pixel circuit is controlled by the control method of the pixel circuit described in any of the above embodiments.

[0012] On the other hand, a display device is provided, comprising the above-mentioned display panel and a driving circuit board, wherein the driving circuit board is electrically connected to the display panel and configured to transmit a control signal to the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0014] FIG1 is a structural diagram of a display device according to some embodiments;

[0015] FIG2 is a block diagram of a display device according to some embodiments;

[0016] FIG3 is a grayscale change diagram of a sub-pixel having an afterimage;

[0017] FIG4 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0018] FIG5 is a control timing diagram of a pixel circuit according to some embodiments;

[0019] FIG6 is a control timing diagram of a pixel circuit according to some embodiments;

[0020] FIG. 7 is a control timing diagram of a pixel circuit according to some embodiments. DETAILED DESCRIPTION

[0021] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0022] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0023] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0024] When describing some embodiments, the terms "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0025] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0026] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0027] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0028] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0029] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0030] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0031] The transistors used in the pixel circuits provided in the embodiments of the present disclosure may be thin film transistors (TFTs), metal oxide semiconductors (MOSs), or other switching devices with the same characteristics. The transistors in the embodiments of the present disclosure are described using thin film transistors as an example. The thin film transistors may be P-type transistors or N-type transistors. P-type transistors are turned on by a low voltage level and turned off by a high voltage level; N-type transistors are turned on by a high voltage level and turned off by a low voltage level.

[0032] The control electrode of each thin-film transistor used in the pixel circuit is the gate of the thin-film transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally the same. In other words, the first electrode and the second electrode of the thin-film transistor in the embodiments of the present disclosure can be structurally the same. For example, the first electrode of the thin-film transistor is the source, and the second electrode is the drain.

[0033] The various circuit nodes in the pixel circuit, such as the first node, the second node, etc., do not represent actual components, but represent the confluence points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the confluence points of related electrical connections in the circuit diagram.

[0034] 1 , an embodiment of the present disclosure provides a display device 1000 , which is a product having an image display function. For example, the display device 1000 can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0035] For example, the display device 1000 may be a mobile phone, a wireless device, a personal digital assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, an automotive display (e.g., an odometer display), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, packaging, and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. For example, as shown in FIG1 , the display device 1000 may be a mobile phone.

[0036] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an organic light-emitting diode display device or a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED), etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. The following takes an organic light-emitting diode display device that is rectangular and flat as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display devices may also be considered as long as the same technical ideas are applied.

[0037] Referring to Figure 2, in some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor voltage divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed one by one in the embodiments of the present disclosure. The driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not specifically limited here.

[0038] Continuing with FIG. 2 , the display panel 1100 includes a display area AA and a peripheral area BB. The peripheral area BB is located on at least one side of the display area AA. For example, the peripheral area BB surrounds the display area AA. The display area AA is the area on the display panel 1100 used to display images. The display area AA is provided with a plurality of sub-pixels P, which are the smallest light-emitting units on the display panel 1100 and are used to display images. The peripheral area BB can be used, for example, to configure a gate driver on array (GOA) circuit and control signal lines (such as clock signal lines and power supply voltage signal lines). Of course, the functions of the peripheral area BB are not limited thereto, and non-disclosed embodiments will not be described in detail here.

[0039] The multiple sub-pixels P can emit light of different colors. For example, the multiple sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, so that the display panel can achieve color display. Of course, the embodiments of the present disclosure are not limited to this, as long as the same technical concept is adopted.

[0040] Each sub-pixel P includes a pixel circuit 100 and a light-emitting device 200. The multiple pixel circuits 100 included in the multiple sub-pixels P can be arranged into multiple rows and columns. The multiple rows of pixel circuits 100 are arranged along a first direction Y, and the multiple rows of pixel circuits 100 each include multiple pixel circuits 100 arranged along a second direction X, where the first direction Y intersects with the second direction X. The multiple columns of pixel circuits 100 are arranged along the second direction X, and the multiple columns of pixel circuits 100 each include multiple pixel circuits 100 arranged along the first direction Y. A row of pixel circuits 100 may include multiple pixel circuits 100 arranged along the second direction X, and a column of pixel circuits 100 may include multiple pixel circuits arranged along the first direction Y. The first direction X is the row direction in which the multiple pixel circuits 100 are arranged, and the second direction Y is the column direction in which the multiple pixel circuits 100 are arranged. The first direction Y intersects with the second direction X. Exemplarily, the first direction Y is perpendicular to the second direction X.

[0041] The pixel circuit 100 includes a plurality of thin film transistors (TFT) and at least one capacitor Cst, and the plurality of thin film transistors include at least a driving transistor. The pixel circuit 100 can be used to drive the light-emitting device 200 to emit light. For example, the pixel circuit 100 can be a "7T2C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits can also be considered as long as the same technical ideas are applied. Among them, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0042] After the pixel circuit 100 has been working for a period of time, the characteristics of the driving transistor will shift, that is, the driving transistor will exhibit hysteresis after working for a certain period of time. When the driving transistor is a low-temperature polysilicon thin-film transistor (LTPS-TFT), the hysteresis phenomenon of the driving transistor refers to the capture and release of carriers by the insulating layer and the P-Si interface traps and the influence of the back-channel induced charge, resulting in a difference in the current of the driving transistor. When the gate of the driving transistor receives a voltage, the defects of the insulating layer will capture carriers, causing the driving transistor to have different characteristic curves during forward scanning and reverse scanning, thereby causing hysteresis, and the hysteresis phenomenon of the driving transistor will cause problems such as short-term afterimages (afterimages).

[0043] Among them, afterimage refers to the phenomenon that after a sub-pixel P experiences high grayscale and low grayscale display, and then changes from high grayscale to low grayscale or from low grayscale to high grayscale, the sub-pixel displays the same grayscale but the luminous brightness is inconsistent. As shown in Figure 3, taking the sub-pixel P that can display 256 grayscales (0 to 255) as an example, after multiple sub-pixels P all display 31 grayscales for a period of time, some sub-pixels P begin to display 255 grayscales, and some sub-pixels P display 0 grayscale, and after a period of time, when the sub-pixel P displays 31 grayscale again, the problem of inconsistent display brightness is shown. Specifically, it can be manifested as the actual brightness of the sub-pixel P is brighter when displaying from 0 grayscale to 31 grayscale, and the actual brightness of the sub-pixel P is darker when displaying from 255 grayscale to 31 grayscale. Since all sub-pixels P display 31 grayscales, the above brightness difference will cause the display panel to have a display boundary phenomenon, that is, an afterimage occurs.

[0044] To address the aforementioned technical issues, referring to FIG4 , an embodiment of the present disclosure provides an "8T1C" pixel circuit 100, i.e., the pixel circuit 100 includes eight thin-film transistors and one capacitor. Specifically, the pixel circuit 100 may include a drive transistor DT, a compensation transistor T1, a bias transistor T2, a first reset transistor T3, a second reset transistor T4, a data write transistor T5, a first emission control transistor T6, a second emission control transistor T7, and a storage capacitor C.

[0045] The control electrode of the driving transistor DT is electrically connected to the first node N1, the first electrode (e.g., source electrode) is electrically connected to the second node N2, and the second electrode (e.g., drain electrode) is electrically connected to the third node N3. The driving transistor DT is configured to generate a driving current under the control of a voltage difference Vgs between the gate and source electrodes of the driving transistor DT. When the driving transistor DT is a P-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the second node N2. In this case, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the second node N2, and drives the light-emitting device 200 to emit light according to the driving current. Of course, when the driving transistor DT is an N-type transistor, the voltage difference Vgs between the gate and source electrodes of the driving transistor DT is equal to the voltage of the first node N1 minus the voltage of the third node N3. In other words, the driving transistor DT generates a driving current under the control of the voltage difference (Vgs) between the first node N1 and the third node N3, and drives the light-emitting device 200 to emit light according to the driving current.

[0046] The compensation transistor T1 has a control electrode electrically connected to the first scan signal line GL1, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the first node N1. The compensation transistor T1 is configured to be turned on under control of a first scan signal from the first scan signal line GL1, thereby conducting a connection between the first node N1 and the third node N3. If the compensation transistor T1 is an N-type transistor, a "valid" voltage signal of the first scan signal can be a high-level signal, and an "invalid" voltage signal of the first scan signal can be a low-level signal. A "valid" first scan signal refers to a voltage signal that can turn on the compensation transistor T1, and an "invalid" first scan signal refers to a voltage signal that cannot turn on the compensation transistor T1.

[0047] The bias transistor T2 has a control electrode electrically connected to the second scan signal line GL2, a first electrode electrically connected to the bias voltage signal line VOBS, and a second electrode electrically connected to the second node N2. The bias transistor T2 is configured to transmit a bias voltage signal from the bias voltage signal line VOBS to the second node N2 under the control of a second scan signal from the second scan signal line GL2. If the bias transistor T2 is a P-type transistor, the "valid" voltage signal of the second scan signal can be a low-level signal, and the "invalid" voltage signal of the second scan signal can be a high-level signal. The "valid" second scan signal refers to a voltage signal that can turn on the bias transistor T2, while the "invalid" second scan signal refers to a voltage signal that cannot turn on the bias transistor T2. In the following embodiments, unless otherwise specified, the second scan signal refers to a valid voltage signal that can turn on the bias transistor T2.

[0048] The first reset transistor T3 has a control electrode electrically connected to the third scan signal line GL3, a first electrode electrically connected to the first reset voltage signal line Vinit1, and a second electrode electrically connected to the first node N1. The first reset transistor T3 is configured to transmit a first reset voltage from the first reset voltage signal line Vinit1 to the first node N1 under control of a third scan signal from the third scan signal line GL3. If the first reset transistor T3 is an N-type transistor, the "valid" voltage signal of the third scan signal can be a high-level signal, and the "invalid" voltage signal of the third scan signal can be a low-level signal. A "valid" third scan signal refers to a voltage signal that can turn on the first reset transistor T3, and an "invalid" third scan signal refers to a voltage signal that cannot turn on the first reset transistor T3.

[0049] The data write transistor T5 has a control electrode electrically connected to the fourth scan signal line GL4, a first electrode electrically connected to the data signal line DL, and a second electrode electrically connected to the second node N2. The data write transistor T5 is configured to be turned on under the control of the fourth scan signal from the fourth scan signal line GL4, and transmit the data signal Data from the data signal line DL to the second node N2. When the data write transistor T5 is a P-type transistor, the "valid" voltage signal of the fourth scan signal can be a low-level signal, and the "invalid" voltage signal of the fourth scan signal can be a high-level signal, wherein the "valid" fourth scan signal refers to a voltage signal that can turn on the data write transistor T5, and the "invalid" fourth scan signal refers to a voltage signal that cannot turn on the data write transistor T5.

[0050] The first emission control transistor T6 has a control electrode electrically connected to the emission control signal line EM, a first electrode electrically connected to the first voltage signal line VDD, and a second electrode electrically connected to the second node N2. The first emission control transistor T6 is configured to be turned on under the control of the emission control signal from the emission control signal line EM and transmit the first voltage signal from the first voltage signal line VDD to the second node N2. The second emission control transistor T7 has a control electrode electrically connected to the emission control signal line EM, a first electrode electrically connected to the third node N3, and a second electrode electrically connected to the fourth node N4. The fourth node N4 is also configured to be electrically connected to the light-emitting device 200. The second emission control transistor T7 is configured to be turned on under the control of the emission control signal from the emission control signal line EM and connect the third node N3 to the fourth node N4. Furthermore, the first and second emission control transistors T6 and T7 are also configured to be turned on during the display phase to transmit the drive current generated by the drive transistor DT to the light-emitting device 200, thereby driving the light-emitting device 200 to emit light. When the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are P-type transistors, the "valid" voltage signal of the light-emitting control signal can be a low-level signal, and the "invalid" voltage signal of the light-emitting control signal can be a high-level signal, wherein the "valid" fourth scanning signal refers to a voltage signal that can turn on the data writing transistor T5, and the "invalid" fourth scanning signal refers to a voltage signal that cannot turn on the data writing transistor T5.

[0051] The control electrode of the second reset transistor T4 is electrically connected to the second scan signal line GL2, the first electrode is electrically connected to the second reset voltage signal line Vinit2, and the second electrode is electrically connected to the fourth node N4. The second reset transistor T4 is configured to transmit the second initialization voltage signal from the second initialization voltage signal line Vinit2 to the fourth node N4 under the control of the second scan signal from the second scan signal line GL2, thereby resetting the voltage of the fourth node N2. When the second reset transistor T4 is a P-type transistor, the "valid" voltage signal of the second scan signal can be a low-level signal, and the "invalid" voltage signal of the second scan signal can be a high-level signal, where the "valid" second scan signal refers to a voltage signal that can turn on the second reset transistor T4, and the "invalid" second scan signal refers to a voltage signal that cannot turn on the second reset transistor T4.

[0052] One plate of the storage capacitor Cst is electrically connected to the first node N1, and the other plate is electrically connected to a constant voltage signal line (eg, the first voltage signal line VDD). The storage capacitor Cst is configured to maintain the voltage of the first node N1.

[0053] Continuing with FIG. 4 , in some embodiments, the compensation transistor T1 and the first reset transistor T3 may be N-type transistors, and the compensation transistor T1 and the first reset transistor T3 may be oxide thin-film transistors. In other words, the compensation transistor T1 and the first reset transistor T3 may be N-type oxide thin-film transistors. N-type oxide thin-film transistors have low leakage current, thereby reducing leakage current from the first node N1 through the compensation transistor T1 and the first reset transistor T3 during the light-emitting phase, thereby reducing leakage current from the first node N1. Meanwhile, the drive transistor DT, the bias transistor T2, the second reset transistor T4, the data write transistor T5, the first emission control transistor T6, and the second emission control transistor T7 may all be P-type transistors. Furthermore, the drive transistor DT, the bias transistor T2, the second reset transistor T4, the data write transistor T5, the first emission control transistor T6, and the second emission control transistor T7 may all be low-temperature polysilicon thin-film transistors. In other words, the drive transistor DT, the bias transistor T2, the second reset transistor T4, the data write transistor T5, the first emission control transistor T6, and the second emission control transistor T7 may all be P-type low-temperature polysilicon thin-film transistors. The P-type low-temperature polysilicon thin film transistor has a high carrier mobility, which is conducive to realizing a display panel 1100 with high resolution, high response speed and high aperture ratio.

[0054] An embodiment of the present disclosure further provides a method for controlling a pixel circuit, which is used to control the pixel circuit shown in FIG4 , and can reduce the hysteresis phenomenon of the driving transistor DT, thereby reducing the afterimage problem of the display panel.

[0055] 5 and 7 , a display frame period includes a bias phase D1 , a first reset phase D2 , a data writing phase D3 , a second reset phase D4 and a light emitting phase D5 , which are sequentially arranged.

[0056] Referring to Figures 4 and 5 , during bias phase D1, bias transistor T2 sequentially transmits a first bias voltage to first node N1 at least twice via driver transistor DT and compensation transistor T1. That is, during bias phase D1, bias transistor T2 is turned on at least twice. Thus, bias voltage signal line VOBS sequentially transmits the first bias voltage to first node N1 at least twice via bias transistor T2, driver transistor DT, and compensation transistor T1. The first bias voltage has an electrical property opposite to that of the voltage at first node N1. Consequently, each time the control electrode (first node / gate) of driver transistor DT receives the first bias voltage, it is reverse biased (compared to the bias direction of the control electrode of driver transistor DT during the previous light-emitting phase). This can desensitize dangling bonds in the gate insulation layer and channel layer, thereby improving hysteresis in driver transistor DT. The driving transistor DT receives the first bias voltage at least twice during the bias phase D1, that is, the control electrode of the driving transistor DT is reverse biased at least twice, which is beneficial for further eliminating the hysteresis phenomenon of the driving transistor DT in the previous frame. In addition, there is a first time interval D11 between the two adjacent transmissions of the first bias voltage by the bias transistor T2. The control electrode of the driving transistor DT is not biased during the first time interval D11, and can be reset and repaired during the first time interval, which can prevent the driving transistor DT from generating new hysteresis under the at least two first bias voltages. For example, if the output duration of the first bias voltage is increased or the absolute value of the first bias voltage is increased, the driving transistor DT may generate new hysteresis under the action of the first bias voltage after eliminating the hysteresis phenomenon of the previous frame. In the embodiment of the present disclosure, the first time interval D11 is set between the two adjacent transmissions of the first bias voltage by the bias transistor T2, which can prevent the driving transistor DT from generating new hysteresis under the at least two first bias voltages.

[0057] In the embodiments of the present disclosure, the electrical property of the first bias voltage is opposite to the electrical property of the voltage of the first node N1, which means that the electrical property of the first bias voltage is opposite to the electrical property of the data signal written to the first node N1 in the previous frame. For example, taking the driving transistor DT as a P-type transistor as an example, the voltage of the data signal written to the driving transistor DT in each frame is a negative value (negative voltage), in which case the first bias voltage can be a positive value (positive voltage). Conversely, in the case where the driving transistor DT is an N-type transistor, the voltage of the data signal written to the driving transistor DT in each frame is a positive value (positive voltage), in which case the first bias voltage can be a negative value (negative voltage).

[0058] The bias direction of the control electrode of the driving transistor DT refers to the electrical property of the voltage applied to the control electrode of the driving transistor DT. In the embodiment of the present disclosure, the control electrode of the driving transistor DT is forward biased by the data signal written to the control electrode of the driving transistor DT in the previous frame, and the first bias voltage written to the control electrode of the driving transistor DT is reverse biased. In other words, the electrical property of the control electrode of the driving transistor DT in the display phase of the previous frame is opposite to the electrical property of the first bias voltage.

[0059] For example, during the bias phase D1, the bias transistor T2 may be turned on two, three, four, or more times. This is not detailed in the embodiments of the present disclosure. That is, the bias transistor T2 may transmit the first bias voltage to the first node N1 two, three, four, or more times. FIG. 5 illustrates the embodiments of the present disclosure by taking the example of the bias transistor T2 being turned on twice and transmitting the first bias voltage to the first node N1 twice as an example.

[0060] In some embodiments, as shown in FIG5 , during a bias phase D1, the second scan signal line GL2 may intermittently transmit a second scan signal at least twice. Each time the second scan signal line GL2 transmits the second scan signal, the bias transistor T2 is turned on under the control of the second scan signal. The first scan signal line GL1 transmits a first scan signal, and the compensation transistor T1 is turned on under the control of the first scan signal. The bias transistor T2 first transmits a first bias voltage from the bias voltage signal line VOBS to the second node N2. The drive transistor DT then transmits the first bias voltage from the second node N2 to the third node N3. The compensation transistor T1 then transmits the first bias voltage from the third node N3 to the first node N1.

[0061] For example, as shown in FIG5 , within the first time interval D11, the first scanning signal line GL1 can continuously output the first scanning signal. In this way, the compensation transistor T1 can remain in the on state within the first time interval D11, which can simplify the transmission difficulty of the first scanning signal and thereby simplify the control method of the pixel circuit.

[0062] In some embodiments, as shown in FIG5 , during the bias phase D1, the bias transistor T2 transmits the first bias voltage to the first node N1 twice. That is, the second scan signal line GL2 transmits a "valid" second scan signal twice at intervals. This helps shorten the total duration of the bias phase D1 and improves the refresh rate of the pixel circuit.

[0063] In some embodiments, referring to Figures 4 and 6 , during bias phase D1 and within a first time interval D11, the first reset transistor T3 transmits a first reset voltage to the first node N1. The first reset voltage has an electrical property opposite to that of the first bias voltage. That is, in the interval between transmitting the first bias voltage twice to the first node N1, the first reset voltage is transmitted once to the first node via the first reset transistor T3. The electrical property of the first reset voltage is opposite to that of the first bias voltage. The first reset voltage can reset and reverse bias the previous first bias voltage, thereby increasing the number of times the drive transistor DT is reset during bias phase D1. Furthermore, the control electrode of the drive transistor DT is alternately reset by voltages of opposite electrical property, further facilitating the elimination of hysteresis in the drive transistor DT.

[0064] For example, when the driving transistor DT is a P-type transistor, the first bias voltage can be a positive voltage, and the first reset voltage can be a negative voltage. In this way, the driving transistor DT can be in different bias states under the action of the first bias voltage and the first reset voltage, which is conducive to eliminating the hysteresis phenomenon of the driving transistor DT.

[0065] For example, as shown in FIG6 , during a first time interval D11, the second scan signal line GL2 transmits a cutoff voltage signal. If the bias transistor T2 is a P-type transistor, the cutoff voltage signal transmitted by the second scan signal line GL2 can be a high-level signal. The bias transistor T2 is turned off by the inactive voltage signal. The bias transistor T2 stops transmitting the first bias voltage to the first node. The third scan signal line GL3 transmits a third scan signal. The first reset transistor T3 is turned on under control of the third scan signal and transmits the first reset voltage from the first reset voltage signal line Vinit to the first node N1.

[0066] In some embodiments, as shown in FIG6 , the first time interval D11 is greater than the on-time duration of the first reset transistor T3. In other words, the first time interval D11 is greater than the time duration during which the third scan signal line GL3 transmits the third scan signal. In this way, the on-time period of the first reset transistor T3 can be completely within the first time interval D11, preventing the first reset transistor T3 and the bias transistor T2 from being turned on at the same time.

[0067] 6 , the bias phase D1 includes at least two first time periods D12 and at least one second time period D13 , and a second time period D13 is included between two adjacent first time periods D12 . The control method of the pixel circuit includes:

[0068] In the first period D12 , the second scan signal line GL2 transmits a second scan signal, and the bias transistor T2 is turned on under the control of the second scan signal.

[0069] In the second period D13 , the third scan signal line GL3 transmits a third scan signal, and the first reset transistor T3 is turned on under the control of the third scan signal.

[0070] There is a second time interval D14 between the adjacent first period D12 and second period D13. That is, there is a second time interval D14 between the bias transistor T2 transmitting the first bias voltage to the first node N1 and the first reset transistor T3 transmitting the first reset voltage to the first node N1. This prevents the first reset transistor T3 and the bias transistor T2 from being turned on at the same time, thereby preventing the voltage of the first node N1 from being interfered with by different voltage signals at the same time.

[0071] In some embodiments, the first time period D12 is greater than 1H. This helps increase the length of time that the bias transistor T2 is turned on once, helps ensure that the first bias voltage is fully written to the first node N1, and thus improves the effect of the first bias voltage in improving the hysteresis problem of the driving transistor DT. 1H is the row scan time (charging time) of the display panel, and 1H is determined by the refresh rate and resolution of the display panel. Specifically, 1H = 1 second / refresh rate of the display panel / total number of rows of pixel circuits. Exemplarily, the first time period D12 can be 1H, 2H, 3H, or 4H, etc., and the embodiments of the present disclosure are not listed one by one. Among them, as the length of the first time period D12 increases and / or the number of first time periods D12 increases, the length of time that the bias voltage signal line VOBS transmits the first bias voltage to the first node N1 can be increased, that is, the length of time that the current flowing through the driving transistor DT (the current transmitted from the second node N2 to the third node N3) is increased, which helps improve the effect of improving the hysteresis problem of the driving transistor, and thus helps improve the afterimage problem of the display panel.

[0072] The second time period D13 is also greater than 1 hour, which helps to increase the duration of time the first reset transistor T3 is on, and helps the first reset voltage to be fully written to the first node N1. For example, the second time period D13 can be 1 hour, 2 hours, 3 hours, or 4 hours, etc., which are not listed one by one in the embodiments of the present disclosure.

[0073] The second time interval D14 is also greater than 1 hour, which helps completely stagger the on-time of the first reset transistor T3 and the on-time of the bias transistor T2, thereby preventing the voltage of the first node N1 from being simultaneously interfered with by different voltage signals. For example, the second time interval D14 can be 1 hour, 2 hours, 3 hours, or 4 hours, etc., which are not listed in detail in the embodiments of the present disclosure.

[0074] In some embodiments, the first time period D12 and the second time period D13 may be equal in length. In other embodiments, the first time period D12 and the second time period D13 may be unequal in length.

[0075] In some embodiments, as shown in FIG6 , during the bias phase D1, the compensation transistor T1 turns on before the bias transistor T2. That is, the first scan signal line GL1 transmits the first scan signal first, and then the second scan signal line GL2 begins transmitting the second scan signal. Exemplarily, there is a third time interval D15 between the time when the first scan signal line GL1 begins transmitting the first scan signal and the time when the second scan signal line GL2 first begins transmitting the second scan signal. Furthermore, the compensation transistor T1 turns off later than the bias transistor T2. That is, the second scan signal line GL2 stops transmitting the second scan signal first, and then the first scan signal line GL1 stops transmitting the first scan signal. Exemplarily, there is a fourth time interval D16 between the time when the second scan signal line GL2 stops transmitting the second scan signal for the last time and the time when the first scan signal line GL1 stops transmitting the first scan signal. The third time interval D15 and the fourth time interval D16 can be equal in length, or they can be different in length.

[0076] In some embodiments, referring to FIG. 7 , the method for controlling the pixel circuit further includes:

[0077] In the first reset stage D2, the first reset transistor T3 transmits the first reset voltage to the first node N1, and the compensation transistor T1 is first turned off and then turned on. After the compensation transistor T1 is turned on, the first reset voltage of the first node N1 is transmitted to the third node N3, thereby resetting the voltages of the first node N1 and the third node N3.

[0078] As shown in Figure 7, during the first reset phase D2, the third scan signal line GL3 transmits a third scan signal. For example, if the first reset transistor T3 is an N-type transistor, the third scan signal is a high-level signal, that is, the third scan signal line GL3 transmits a high-level signal. Under the control of the third scan signal, the first reset transistor T3 turns on and transmits the first reset voltage of the first reset voltage signal line to the first node N1. Furthermore, during the first reset phase D2, the first scan signal line GL1 first transmits a cutoff voltage signal and then the first scan signal. For example, if the compensation transistor T1 is an N-type transistor, the cutoff voltage signal is a low-level signal and the third scan signal is a high-level signal. In other words, during the first reset phase D2, the first scan signal line GL1 first transmits a low-level signal and then a high-level signal. In this way, the compensation transistor T1 can be turned off first and then turned on, transmitting the first reset voltage of the first node N1 to the third node N3, thereby initializing the voltage of the third node N3.

[0079] In the data writing phase D3, the data writing transistor T5 transmits the data signal Data from the data signal line DL to the second node N2. The data signal is then transmitted to the first node N1 via the driving transistor DT and the compensation transistor T1. The data signal at the second node N2 is compensated by the driving transistor DT and then transmitted to the third node N3. The voltage at the third node N3 and the first node N1 after compensation is Data + the threshold voltage Vth of the driving transistor.

[0080] As shown in FIG7 , during the data writing phase D3, the fourth scanning signal line GL4 transmits a fourth scanning signal. When the data writing transistor T5 is a P-type transistor, the fourth scanning signal is a low-level signal. That is, the fourth scanning signal line GL4 transmits a low-level signal. The data writing transistor T5 is turned on under the control of the fourth scanning signal and transmits the data signal from the data signal line DL to the second node N2. The driving transistor DT is turned on by the voltage difference Vgs between the gate and the source. Vgs of the driving transistor DT = the voltage of the first node N1 (the first reset voltage) - the voltage of the second node N2 (the voltage of the data signal) ≤ Vth. The driving transistor DT is turned on and transmits the data signal of the second node N2 after compensation (Data + Vth) to the third node N3, and then transmits it to the first node N1 through the compensation transistor T1.

[0081] In the second reset phase D4, the bias transistor T2 transmits a second bias voltage to the second node N2 to reset the voltage at the second node N2. Furthermore, the second reset transistor T4 transmits a second reset voltage to the fourth node N4 to reset the voltage at the fourth node N4. The magnitude of the second bias voltage may be the same as or different from the magnitude of the first bias voltage, and is not specifically limited herein.

[0082] Illustratively, in the second reset stage D4, the second scan signal GL2 transmits the second scan signal, the bias transistor T2 and the second reset transistor T4 are turned on under the control of the second scan signal, the bias transistor T2 transmits the bias voltage from the bias voltage signal line VOBS to the second node N2, the second reset transistor T4 transmits the second reset voltage from the second reset voltage signal line Vinit2 to the fourth node N4, and resets the voltage of the fourth node N4.

[0083] During the light-emitting phase D5, the light-emitting control signal line EM transmits a light-emitting control signal. The first light-emitting control transistor T6 and the second light-emitting control transistor T7 are turned on under the control of the light-emitting control signal line. The first light-emitting control transistor T6 transmits the first voltage signal from the first voltage signal line VDD to the second node N2. At this time, the driving transistor DT generates a driving current under the control of the voltage difference between the first node N1 and the second node N2, and transmits the driving current to the third node N3. The second light-emitting control transistor T7 is turned on to transmit the driving current at the third node N3 to the fourth node N4, and further to the light-emitting device 200. The light-emitting device 200 emits light under the control of the driving current.

[0084] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A control method for a pixel circuit, wherein, the pixel circuit includes a driving transistor, a compensating transistor, and a biasing transistor; a control electrode of the driving transistor is electrically connected to a first node, a first pole is electrically connected to a second node, and a second pole is electrically connected to a third node; a control electrode of the compensating transistor is electrically connected to a first scanning signal line, a first pole is electrically connected to the third node, and a second pole is electrically connected to the first node; a control electrode of the biasing transistor is electrically connected to a second scanning signal line, a first pole is electrically connected to a biasing voltage signal line, and a second pole is electrically connected to the second node; a frame period includes a biasing stage; the control method includes: in the biasing stage, the biasing transistor sequentially transmits at least two first biasing voltages to the first node through the driving transistor and the compensating transistor, and there is a first time interval between two adjacent transmissions of the first biasing voltage on the biasing voltage signal line; an electric property of the first biasing voltage is opposite to an electric property of a voltage of the first node.

2. The control method according to claim 1, wherein the pixel circuit further includes a first reset transistor, a control electrode of the first reset transistor is electrically connected to a third scanning signal line, a first pole is electrically connected to a first reset voltage signal line, and a second pole is electrically connected to the first node; the control method further includes: in the biasing stage and within the first time interval, the first reset transistor transmits a first reset voltage to the first node, and an electric property of the first reset voltage is opposite to an electric property of the first biasing voltage.

3. The control method according to claim 2, wherein within the first time interval, the compensating transistor is turned on under the control of a first scanning signal from the first scanning signal line.

4. The control method according to claim 3, the first time interval is greater than a conduction duration of the first reset transistor.

5. The control method according to any one of claims 2 to 4, wherein, the biasing stage includes at least two first time periods and at least one second time period, and there is a second time period between two adjacent first time periods; the control method includes: in the first time period, the second scanning signal line transmits a second scanning signal, and the biasing transistor is turned on under the control of the second scanning signal; in the second time period, the third scanning signal line transmits a third scanning signal, and the first reset transistor is turned on under the control of the third scanning signal; wherein, there is a second time interval between an adjacent first time period and second time period.

6. The control method according to claim 5, wherein, the first time period is greater than 1H; and / or, the second time period is greater than 1H; and / or, the second time interval is greater than 1H.

7. The control method according to any one of claims 2 to 6, wherein The pixel circuit further includes a data writing transistor, a second reset transistor, a first light-emitting control transistor, and a second light-emitting control transistor; a control electrode of the data writing transistor is electrically connected to a fourth scan signal line, a first electrode is electrically connected to a data signal line, and a second electrode is electrically connected to the second node; a control electrode of the second reset transistor is electrically connected to the second scan signal line, a first electrode is electrically connected to a second reset voltage signal line, and a second electrode is electrically connected to a fourth node; a control electrode of the first light-emitting control transistor is electrically connected to a light-emitting control signal line, a first electrode is electrically connected to a first voltage signal line, and a second electrode is electrically connected to the second node; a control electrode of the second light-emitting control transistor is electrically connected to the light-emitting control signal line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to the fourth node; A frame period further includes a first reset stage, a data writing stage, and a second reset stage sequentially arranged after the bias stage; the control method further includes: In the first reset stage, the first reset transistor transmits the first reset voltage to the first node, and the compensation transistor is first cut off and then turned on. After the compensation transistor is turned on, it transmits the first reset voltage of the first node to the third node; In the data writing stage, the data writing transistor transmits a data signal from the data signal line to the second node, and the data signal is sequentially transmitted to the first node through the driving transistor and the compensation transistor; In the second reset stage, the bias transistor transmits a second bias voltage to the second node.

8. The control method according to any one of claims 1 to 7, wherein In the bias stage, the bias transistor transmits the first bias voltage to the first node twice.

9. A display panel, comprising: A plurality of pixel circuits, the pixel circuits adopting the control method according to any one of claims 1 to 8; A plurality of light-emitting devices, one light-emitting device being electrically connected to one pixel circuit.

10. A display device, comprising: The display panel according to claim 9; A driving circuit board, electrically connected to the display panel and configured to transmit control signals to the display panel.

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