Dynamic random access memory array structure and manufacturing method therefor

Abstract

Provided in the present disclosure are a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, and a manufacturing method therefor. The DRAM array structure comprises a plurality of DRAM unit structures, which are arranged in an array. The DRAM array structure according to the present disclosure comprises: a substrate; first storage capacitors of DRAM unit structures in odd-numbered columns or even-numbered columns, which first storage capacitors are arranged on the substrate; first bit lines of DRAM unit structures in even-numbered columns or odd-numbered columns, which first bit lines are arranged above the first storage capacitors; gating transistors of the DRAM unit structures, which gating transistors are arranged on the first storage capacitors and the first bit lines, wherein the gating transistors of DRAM unit structures in adjacent rows share a first layer of word lines and a second layer of word lines; second bit lines of the DRAM unit structures in the odd-numbered columns or the even-numbered columns, which second bit lines are arranged on the gating transistors; and second storage capacitors of the DRAM unit structures in the even-numbered columns or the odd-numbered columns, which second storage capacitors are arranged above the second bit lines. By means of the DRAM array structure and the manufacturing method therefor according to the present disclosure, further size scaling can be realized.

Description

Dynamic random access memory array structure and manufacturing method thereof Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a dynamic random access memory (DRAM) array structure and a method for manufacturing the same. Background Art

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a transistor for enabling the device and a capacitor for storing charge (a 1T1C structure). In a DRAM cell structure that uses a conventional planar horizontal transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the enabling transistor, the transistor's source, gate, and drain are arranged horizontally parallel to the substrate surface. Because the transistor's source, gate, and drain each occupy independent areas in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by gate length and contact size, making it impossible to meet the continued scaling requirements of DRAM devices. This, in turn, limits further increases in the integration density and bandwidth of DRAM devices.

[0004] Therefore, a vertical DRAM cell structure has been proposed in recent years, in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the miniaturization of the DRAM array structure.

[0005] However, in existing DRAM cell circuit structures based on vertical channel transistors (VCTs), the metal gate wraps the entire channel, requiring additional area for isolation between word lines formed by the metal gate connection. This limits the scaling of VCT transistors used as gate transistors in DRAM cell circuits. Furthermore, the resistance of metal deposited by atomic layer deposition (ALD) increases significantly as its thickness decreases. This, combined with the additional area required by the metal and gate oxide thickness compared to planar structures, limits further reductions in word line spacing.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel dynamic random access memory (DRAM) array structure and a manufacturing method thereof.

[0008] According to one aspect of the present disclosure, a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: a substrate; a first storage capacitor of the DRAM cell structure of the odd or even columns, arranged on the substrate; a first bit line of the DRAM cell structure of the even or odd columns, arranged above the first storage capacitor; a selection transistor of each DRAM cell structure, arranged on the first storage capacitor and the first bit line, wherein the selection transistors of the DRAM cell structures of adjacent rows share the first and second layer word lines; a second bit line of the DRAM cell structure of the odd or even columns, arranged on the selection transistor; and a second storage capacitor of the DRAM cell structure of the even or odd columns, arranged above the second bit line.

[0009] According to another aspect of the present disclosure, a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: a substrate; a storage capacitor of each DRAM cell structure, disposed on the substrate; a selection transistor of each DRAM cell structure, disposed on the storage capacitor, wherein the selection transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and a bit line, disposed on the selection transistor.

[0010] According to another aspect of the present disclosure, a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: a substrate; a bit line disposed on the substrate; a selection transistor of each DRAM cell structure disposed on the bit line, wherein the selection transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and a storage capacitor of each DRAM cell structure disposed on the selection transistor.

[0011] According to another aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, the method comprising: providing a substrate; forming a first storage capacitor of the DRAM cell structure of odd columns or even columns above the substrate; forming a first bit line of the DRAM cell structure of even columns or odd columns above the first storage capacitor; forming a selection transistor for each DRAM cell structure, wherein the selection transistors of the DRAM cell structures of adjacent rows share the first layer word line and the second layer word line; forming a second bit line of the DRAM cell structure of odd columns or even columns above the selection transistor; and forming a second storage capacitor of the DRAM cell structure of even columns or odd columns above the second bit line.

[0012] According to another aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, the method comprising: providing a substrate; forming a storage capacitor for each DRAM cell structure above the substrate; forming a selection transistor for each DRAM cell structure above the storage capacitor, wherein the selection transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and forming a bit line above the selection transistor.

[0013] According to another aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, the method comprising: providing a substrate; forming a bit line of each DRAM cell structure above the substrate; forming a selection transistor of each DRAM cell structure above a storage capacitor, wherein the selection transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and forming a storage capacitor above the selection transistor.

[0014] According to the DRAM array structure and manufacturing method disclosed herein, a vertical DRAM cell structure with a double-layer word line is manufactured by using a double-sided layout method, and the DRAM cell structures in adjacent rows share the word line in the column direction, thereby eliminating the inherent spacing area between the word lines in the traditional DRAM array structure based on ring-gate transistors, increasing the area of ​​the storage capacitor, and thus achieving further size reduction.

[0015] According to one aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, the method comprising: providing a stop layer and an active layer on a base layer; forming a plurality of bit line isolation grooves extending along a column direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in a row direction; forming a plurality of word line grooves extending along a row direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in a column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a first storage capacitor at one end of the active area of ​​the DRAM cell structure of an odd column or an even column; forming a first bit line at one end of the active area of ​​the DRAM cell structure of an even column or an odd column; flipping the DRAM array structure and removing the base layer and the stop layer; forming a second bit line at the other end of the active area of ​​the DRAM cell structure of an odd column or an even column; and forming a second storage capacitor at the other end of the active area of ​​the DRAM cell structure of an even column or an odd column.

[0016] According to the method for manufacturing a DRAM array structure disclosed in the present invention, a vertical DRAM cell structure with a double-layer word line is manufactured through double-sided processing using a double-sided layout method, and adjacent DRAM cell structures share the word line in the column direction, thereby eliminating the inherent spacing area between the word lines in the traditional DRAM array structure based on ring-gate transistors, and increasing the size of the storage capacitor of each DRAM cell structure in the word line direction, thereby achieving further size miniaturization.

[0017] According to one aspect of the present disclosure, a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: a substrate; a first storage capacitor of the DRAM cell structure of odd columns or even columns, arranged on the substrate; a first bit line of the DRAM cell structure of even columns or odd columns, arranged above the first storage capacitor; a selection transistor of each DRAM cell structure, arranged on the first storage capacitor and the first bit line, wherein the selection transistors of the DRAM cell structures of adjacent rows share the first layer word line and the second layer word line; a second bit line of the DRAM cell structure of odd columns or even columns, arranged on the selection transistor; and a second storage capacitor of the DRAM cell structure of even columns or odd columns, arranged above the second bit line, wherein the first storage capacitor and the second storage capacitor are arranged into a first storage capacitor array and a second storage capacitor array, respectively.

[0018] According to the DRAM array structure disclosed in the present invention, a DRAM array structure is constructed by using a double-sided layout method using a DRAM cell structure with a double-layer word line, and adjacent DRAM cell structures share word lines in the column direction, thereby eliminating the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors and increasing the size of the storage capacitor of each DRAM cell structure, thereby achieving further size miniaturization.

[0019] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0021] FIG. 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0022] FIG. 2 is a perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0023] FIG. 3 is a top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0024] FIG. 4 is a vertical cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0025] FIG. 5 is a schematic diagram illustrating an operating method of a DRAM cell structure according to an embodiment of the present disclosure.

[0026] FIG. 6 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to an embodiment of the present disclosure.

[0027] 7A and 7B are top views of a DRAM array structure respectively illustrating a DRAM cell structure including a VCT transistor according to the related art and a transistor having four gate structures sharing a word line according to an embodiment of the present disclosure.

[0028] FIG. 8 is a schematic diagram illustrating an operating method of a DRAM array structure according to an embodiment of the present disclosure.

[0029] 9A to 9D are schematic cross-sectional views respectively illustrating steps of a method for manufacturing a DRAM array structure according to the first embodiment of the present disclosure.

[0030] FIG. 10A is a schematic cross-sectional view taken along line BB′ of FIG. 9D .

[0031] FIG. 10B is a schematic cross-sectional view taken along line CC′ of FIG. 9D .

[0032] 11A to 11D are schematic cross-sectional views respectively illustrating steps of a method for manufacturing a DRAM array structure according to a second embodiment of the present disclosure.

[0033] FIG. 12A is a schematic cross-sectional view taken along line DD′ of FIG. 11D .

[0034] FIG. 12B is a schematic cross-sectional view taken along line EE′ of FIG. 11D .

[0035] FIG. 13 is a schematic top view showing a DRAM array structure manufactured by the method according to the first and second embodiments of the present disclosure.

[0036] 14A is a schematic cross-sectional view showing a DRAM array structure manufactured by a method according to a third embodiment of the present disclosure.

[0037] FIG. 14B is a schematic top view showing a DRAM array structure manufactured by the method according to the third embodiment of the present disclosure.

[0038] FIG. 14C is a schematic bottom view showing a DRAM array structure manufactured by the method according to the third embodiment of the present disclosure.

[0039] FIG. 15 is an equivalent circuit diagram illustrating a DRAM array structure manufactured by a method according to a third embodiment of the present disclosure.

[0040] 16 to 30B are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure.

[0041] FIG. 31 is a schematic cross-sectional view illustrating a DRAM array structure manufactured by a method according to an embodiment of the present disclosure.

[0042] FIG. 32A is a schematic top view illustrating a DRAM array structure manufactured by a method according to an embodiment of the present disclosure.

[0043] FIG. 32B is a schematic bottom view illustrating a DRAM array structure manufactured by a method according to an embodiment of the present disclosure.

[0044] FIG. 33 is an equivalent circuit diagram illustrating a DRAM array structure manufactured by a method according to an embodiment of the present disclosure.

[0045] 34A and 34B are schematic top views each illustrating a DRAM array structure according to an embodiment of the present disclosure.

[0046] 35A and 35B are schematic top views each illustrating a DRAM array structure according to another embodiment of the present disclosure.

[0047] 36A and 36B are schematic top views each illustrating a DRAM array structure according to another embodiment of the present disclosure.

[0048] FIG. 37 is a schematic cross-sectional view illustrating a DRAM array structure taken along line DD′ in FIG. 35A and FIG. 36A according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0050] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0051] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0052] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0053] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0055] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same elements. Furthermore, in the accompanying drawings, for clarity of illustration, the various components are not necessarily drawn to ratio, and the ratios and sizes of the various components may be exaggerated.

[0056] FIG1 shows an equivalent circuit diagram of a dynamic random access memory (DRAM) cell structure 100 according to an embodiment of the present disclosure. FIG2 also shows a schematic perspective view of the DRAM cell structure 100 according to an embodiment of the present disclosure, FIG3 shows a schematic top view of the DRAM cell structure 100 according to an embodiment of the present disclosure, and FIG4 shows a schematic vertical cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure. It should be noted that FIG4 is a schematic vertical cross-sectional view taken along line AA′ in FIG3 .

[0057] As shown in FIG1 , a DRAM cell structure 100 according to an embodiment of the present disclosure may include a storage capacitor C and a gate transistor T (as shown in a dotted box). As shown in FIG1 to FIG4 , according to an embodiment of the present disclosure, the gate transistor T may include a vertically extending active region 101, which includes a first source / drain region 102, a channel region 103, and a second source / drain region 104 arranged in sequence from bottom to top along the vertical direction, wherein the first source / drain region 102 may be connected to a bit line BL, and the second source / drain region may be connected to one electrode (lower electrode) CP1 of the storage capacitor C. According to an embodiment of the present disclosure, the other electrode (upper electrode) CP2 of the storage capacitor C may be connected to a source line SL.

[0058] Although FIG1 shows that the bit line BL, the gate transistor T, the storage capacitor C, and the source line SL are arranged in a vertical direction from bottom to top, the configuration of the DRAM cell structure 100 is not limited thereto. According to an alternative embodiment of the present disclosure, the source line SL, the storage capacitor C, the gate transistor T, and the bit line may also be arranged in a vertical direction from bottom to top. In this embodiment, the second source / drain region 102 may be connected to the bit line BL, the first source / drain region 102 may be connected to the upper electrode CP2 of the storage capacitor C, and the lower electrode CP1 of the storage capacitor C may be connected to the source line SL.

[0059] As shown in Figures 1 to 4, according to an embodiment of the present disclosure, the selection transistor T may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107 and a fourth gate structure G4 108, wherein the first gate structure G1 105 and the second gate structure G2 106 may be arranged from bottom to top along a vertical direction on a first side of the channel region 103, and the third gate structure G3 107 and the fourth gate structure G4 108 may be arranged from bottom to top along a vertical direction on a second side of the channel region 103 opposite to the first side.

[0060] As shown in Figure 4, according to an embodiment of the present disclosure, the selection transistor T can be a junction-less device, that is, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with the same type. For example, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with a first doping type. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. However, the present disclosure is not limited to this. According to an alternative embodiment of the present disclosure, the first doping type can be P-type doping, and the second doping type can be N-type doping. According to an embodiment of the present disclosure, the doping concentration of the first source / drain region 102 and the second source / drain region 104 can be higher than the doping concentration of the channel region 103.

[0061] In addition, according to an embodiment of the present disclosure, the gate transistor T may also be a junction type device, that is, different types of doping may be performed on the first source / drain region 102, the channel region 103, and the second source / drain region 104. For example, the first source / drain region 102 and the second source / drain region 104 may be doped with a first doping type, and the channel region 103 may be doped with a second doping type.

[0062] As shown in FIG1 , according to an embodiment of the present disclosure, the first source / drain region 102 can be connected to a bit line BL, and the second source / drain region 104 can be connected to one electrode or lower electrode CP1 of the storage capacitor C. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is in a write period, the bit line BL can be connected to a voltage representing data 0 (e.g., ground voltage VSS) or a voltage representing data 1 (e.g., power supply voltage VDD) to store the voltage representing the corresponding data in the storage capacitor C. When the DRAM cell structure 100 is not in a write period, the bit line BL can be connected to an equalization voltage VBLQ. According to an embodiment of the present disclosure, the equalization voltage VBLQ can be, for example, a voltage at the intersection of a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 0 (e.g., ground voltage VSS) and a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 1 (e.g., power supply voltage VDD) (e.g., typically approximately (VDD+VSS) / 2).

[0063] Furthermore, as shown in FIG1 , according to an embodiment of the present disclosure, the other electrode or upper electrode CP2 of the storage capacitor C can be connected to a source line SL. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, the source line SL can be connected to a fixed voltage VFF. For example, according to an embodiment of the present disclosure, the fixed voltage VFF can be used as a reference voltage, which is typically half of the power supply voltage VDD, i.e., VFF = 1 / 2 VDD.

[0064] For clarity, the storage capacitor C, the bit line BL, and the source line SL are not shown in FIG. 2 to FIG. 4 .

[0065] Furthermore, as described above, with reference to Figures 1 to 4 , according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107, and a fourth gate structure G4 108. According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 are vertically arranged from bottom to top on a first side of the channel region 103 (e.g., the left side as shown in Figures 2 and 4 ), and the third gate structure G3 107 and the fourth gate structure G4 108 are vertically arranged from bottom to top on a second side of the channel region 103 opposite the first side (e.g., the right side as shown in Figures 2 and 4 ). Herein, the first gate structure G1 105 and the third gate structure G3 107 may also be referred to as a lower gate structure, and the second gate structure G2 106 and the fourth gate structure G4 108 may also be referred to as an upper gate structure.

[0066] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed of the same conductive material. According to an embodiment of the present disclosure, examples of conductive materials used to form the first to fourth gate structures G1 105 to G4 108 may include: metals or alloys, such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the above metals; metal nitrides, such as titanium nitride (TiN); or polysilicon. In addition, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may include a high work function material, a low work function material, or a combination thereof. The low work function material may have a low work function of approximately 4.5 eV or less, and the high work function material may have a high work function of approximately 4.5 eV or more. For example, the low work function material may include N-type doped polysilicon, and the high work function material may include tungsten, titanium nitride, or a combination thereof. According to an alternative embodiment of the present invention, the first to fourth gate structures G1 105 to G4 108 may have a dual work function structure in which a low work function material and a high work function material are combined.

[0067] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 can be formed of different conductive materials. For example, the lower gate structure, namely the first gate structure G1 105 and the third gate structure G3 107, can be formed of a metal-based material such as titanium nitride or tungsten, while the upper gate structure, namely the second gate structure G2 106 and the fourth gate structure G4 108, can be formed of polysilicon. According to an embodiment of the present disclosure, by forming the first to fourth gate structures G1 105 to G4 108 with different conductive materials, the work function can be adjusted, thereby adjusting the threshold voltage of the gate transistor T.

[0068] In addition, as more clearly shown in Figures 3 and 4, according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a gate dielectric 109 disposed between the first gate structure G1 105 to the fourth gate structure G4 108 and the channel region 103. According to an embodiment of the present disclosure, the gate dielectric 109 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide may have a dielectric constant of approximately 3.9, and the gate dielectric 109 may include a high-k material having a dielectric constant of approximately 4 or greater. As the gate dielectric 109, the high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to an alternative embodiment of the present invention, the gate dielectric 109 may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0069] Furthermore, as shown in Figures 2 to 4 , according to embodiments of the present disclosure, the first gate structure G1 105 to the fourth gate structure G4 108 may be separated from each other by an isolation dielectric 110. As shown in Figure 3 , according to embodiments of the present disclosure, the two upper gate structures, namely, the second gate structure G2 106 and the fourth gate structure G4 108, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110. Similarly, although not shown, according to embodiments of the present disclosure, the two lower gate structures, namely, the first gate structure 105 and the third gate structure 107, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110.

[0070] 4 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 disposed on the first side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. Furthermore, the third gate structure G3 107 and the fourth gate structure G4 108 disposed on the second side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. According to an embodiment of the present disclosure, the isolation dielectric 110 may be formed of the same material as or a different material from the gate dielectric 109.

[0071] According to an embodiment of the present disclosure, the first gate structure G1 105, the second gate structure G2 106, the third gate structure G3 107, and the fourth gate structure G4 108 may have the same size and structure. In addition, as shown in Figures 2 and 4, according to an embodiment of the present disclosure, the first gate structure G1 105 and the third gate structure G3 107 may be aligned with each other in the vertical direction, and the second gate structure G2 106 and the fourth gate structure G4 108 may be aligned with each other in the vertical direction.

[0072] As shown in FIG4 , according to an embodiment of the present disclosure, the vertical distance d1 between the upper end of the first gate structure G1 105 and the lower end of the second gate structure G2 106 may be equal to the vertical distance d2 between the upper end of the third gate structure G3 107 and the lower end of the fourth gate structure G4 108, i.e., d1 = d2. According to an embodiment of the present disclosure, the distances d1 and d2 may be greater than the horizontal thickness d3 of the gate dielectric 109 between the first to fourth gate structures G1 105 to G4 108 and the channel region 103, and preferably greater than twice the horizontal thickness d3 of the gate dielectric 109 between the first to fourth gate structures G1 105 to G4 108 and the channel region 103, to reduce the impact of parasitic capacitance formed between the first gate structure G1 105 and the second gate structure G2 106, and between the third gate structure G3 107 and the fourth gate structure G4 108.

[0073] In addition, according to an embodiment of the present disclosure, although not shown, a work function adjustment layer may be formed between the gate dielectric 109 and the first to fourth gate structures G1 105 to G4 108 to further adjust the threshold voltage of the gate transistor T.

[0074] Furthermore, according to an embodiment of the present disclosure, although not shown, a doping concentration adjustment layer may be formed at the surface of the channel region 103 overlapping the first to fourth gate structures G1 105 to G4 108 to reduce fluctuations in the threshold voltage of the gate transistor T.

[0075] As shown in FIG. 3 , according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed to have a “[”-shaped cross-section in a horizontal direction to obtain a larger control area between the gate structure and the channel region 103 .

[0076] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, the gate transistor T can be equivalent to two dual-gate transistors connected in series, wherein the lower dual-gate transistor (hereinafter referred to as the “lower dual-gate transistor”) uses the first gate structure G1 105 and the third gate structure G3 107 as gates, and the upper dual-gate transistor (hereinafter referred to as the “upper dual-gate transistor”) uses the second gate structure G2 106 and the fourth gate structure G4 108 as gates. Therefore, according to an embodiment of the present disclosure, the gate transistor T is turned on only when both the upper dual-gate transistor and the lower dual-gate transistor are turned on. In addition, according to an embodiment of the present disclosure, the gate transistor T is turned off when at least one of the upper dual-gate transistor and the lower dual-gate transistor is turned off.

[0077] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, by controlling the voltage applied to the first gate structure G1 105 to the fourth gate structure G4 108, the conduction and shutoff of the selection transistor T can be controlled, thereby realizing the read, write and refresh operations of the DRAM cell structure, which will be described in more detail below in conjunction with FIG5 .

[0078] FIG. 5 is a schematic diagram illustrating an operating method of the DRAM cell structure 100 according to an embodiment of the present disclosure.

[0079] In a traditional 1T1C DRAM cell structure, a single transistor is used as a gate transistor to control the formation of a conduction path between the bit line and the storage capacitor. According to an embodiment of the present disclosure, the gate transistor T can be equivalent to two NMOS depletion-type dual-gate transistors (i.e., a lower dual-gate transistor and an upper dual-gate transistor) connected in series to form a logic AND unit. In other words, only when the upper and lower dual-gate transistors are turned on at the same time, a conduction path is formed between the storage capacitor C and the bit line BL, thereby performing read, write and refresh operations on the DRAM cell structure. According to an embodiment of the present disclosure, when one of the upper and lower dual-gate transistors of the gate transistor T is turned on, a conduction path is not formed. In other words, when at least one of the upper and lower dual-gate transistors of the gate transistor T is turned off, a conduction path is not formed. In addition, according to an embodiment of the present disclosure, when the upper and lower dual-gate transistors of the gate transistor T are turned off at the same time, leakage is minimized, and data is continuously retained in the storage capacitor C in the form of charge.

[0080] As shown in FIG2 to FIG4, when the gate transistor T is a junction-less device, that is, the active region 101 is entirely formed of the first doping type semiconductor, when no voltage is applied to the first gate structure G1 105 to the fourth gate structure G4 108, the gate transistor T is in the on state.

[0081] As shown in FIG. 5 , according to an embodiment of the present disclosure, the gate transistor T may be turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107 .

[0082] Specifically, as shown in FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is not selected, low voltages VGL1 to VGL4 may be applied to the first to fourth gate structures G1 105 to G4 108 of the gate transistor T, respectively, to ensure that the gate transistor T is turned off. According to an embodiment of the present disclosure, each of the low voltages VGL1 to VGL4 may be a negative voltage, so that the portion of the channel region 103 between the first gate structure G1 105 and the third gate structure G3 107, as well as the portion of the channel region 103 between the second gate structure G2 106 and the fourth gate structure G4 108, are completely pinched off. This ensures that the gate transistor T is turned off while reducing or eliminating leakage current in the off state of the gate transistor T. According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 applied to the first to fourth gate structures G1 105 to G4 108 may be the same as or different from each other.

[0083] 5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T can be applied with high voltages VGH2 and VGH3, respectively, and the first gate structure G1 105 and the fourth gate structure G4 108 can remain connected to low voltages VGL1 and VGL4, respectively. According to an embodiment of the present disclosure, each of the high voltages VGH2 and VGH3 can be the ground voltage VSS or a positive voltage, so that the channel region 103 forms a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107. That is, as shown in FIG5 , according to an embodiment of the present disclosure, by applying high voltages VGH2 and VGH3, respectively, to the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T, an "S"-shaped conduction path can be formed near the surface of the channel region 103 overlapping with the second gate structure G2 106 and the third gate structure G3 107, as shown by arrows in FIG5 , thereby turning on the gate transistor T. According to an embodiment of the present disclosure, the high voltages VGH2 and VGH3, respectively applied to the second gate structure G2 106 and the third gate structure G3 107, can be the same as or different from each other.

[0084] According to an embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, the first gate structure G1 105 and the fourth gate structure G4 108 can be constantly connected to the low voltages VGL1 and VGL4, respectively. In addition, according to an embodiment of the present disclosure, the first gate structure G1 105 and the fourth gate structure G4 108 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the first gate structure G1 105 and the fourth gate structure G4 108, or the first gate structure G1 105 and the fourth gate structure G4 108 can be individually or collectively floated.

[0085] Although FIG5 describes an embodiment of the present disclosure by taking the example of turning on or off the selection transistor T by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, those skilled in the art should recognize that the selection transistor T may also be turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, which can also achieve the technical effects of the present disclosure.

[0086] Specifically, according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the first gate structure G1 105 and the fourth gate structure G4 108 of the gate transistor T can be applied with high voltages VGH1 and VGH4, respectively, and the second gate structure G2 106 and the third gate structure G3 107 can remain connected to low voltages VGL2 and VGL3, respectively. At this time, an "S"-shaped conduction path can be formed near the surface of the channel region 103 that overlaps with the first gate structure G1 105 and the fourth gate structure G4 108. This "S"-shaped conduction path is mirror-symmetrical to the conduction path indicated by the arrow in FIG. 5 .

[0087] According to an alternative embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, the second gate structure G2 106 and the third gate structure G3 107 can be constantly connected to the low voltages VGL2 and VGL3, respectively. In addition, according to an embodiment of the present disclosure, the second gate structure G2 106 and the third gate structure G3 107 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107, or the second gate structure G2 106 and the third gate structure G3 107 can be individually or collectively floated.

[0088] According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 may be the same as each other and are collectively denoted as VGL, and the high voltages VGH1 to VGH4 may be the same as each other and are collectively denoted as VGH.

[0089] FIG. 6 shows an equivalent circuit diagram of a DRAM array structure 200 formed by the DRAM cell structure 100 shown in FIG. 1 according to an embodiment of the present disclosure. As shown in FIG. 6, according to an embodiment of the present disclosure, the DRAM array structure 200 may include a plurality of DRAM cell structures 100 shown in FIG. 1, and some reference numerals inside each DRAM cell structure 100 are omitted for clarity.

[0090] According to an embodiment of the present disclosure, the plurality of DRAM cell structures included in the DRAM array structure 200 may be arranged in an array of M rows and N columns, where M and N are natural numbers greater than 1. According to an embodiment of the present disclosure, the row selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 may be performed by M + 1 first word lines or M + 1 second word lines, and the column selection operation may be performed by N bit lines.

[0091] It should be noted that for ease of description, FIG. 6 only shows the nth column DRAM cell structure of the DRAM array structure 200 that can be selected by the nth bit line BLn (n is a positive integer, and 0 < n ≤ N). As shown in FIG. 6, according to an embodiment of the present disclosure, the nth column DRAM cell structure of the DRAM array structure 200 may include M DRAM cell structures CELL1n to CELLMn, where each DRAM cell CELLmn includes a storage capacitor Cmn and a select transistor Tmn (m is a positive integer, and 0 < m ≤ M; n is a positive integer, and 0 < n ≤ N).

[0092] According to an embodiment of the present disclosure, a row selection operation of the M DRAM cell structures CELL1n through CELLMn of the nth column of DRAM cell structures can be performed via M+1 first word lines WL1m (m is an integer, and 0≤m≤M). As shown in FIG6 , according to an embodiment of the present disclosure, the M+1 first word lines WL10 through WL1M are respectively connected to the second gate structure G2 and the third gate structure G3 of the nth column of DRAM cell structures. Specifically, as shown in Figure 6, the first word line WL10 is connected to the second gate structure G2 of the selection transistor T1n of the DRAM cell structure CELL1n, the first word line WL11 is connected to the third gate structure G3 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the first word line WL12 is connected to the second gate structure G2 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The first word line WL1M is connected to the second gate structure G2 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0093] Alternatively, according to an embodiment of the present disclosure, the row selection operation of the M DRAM cell structures CELL1n to CELLMn in the nth column of the DRAM cell structure can also be performed through M+1 second word lines WL2m (m is an integer, and 0≤m≤M). As shown in Figure 6, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M are respectively connected to the first gate structure G1 and the fourth gate structure G4 of the nth column of the DRAM cell structure. Specifically, as shown in Figure 6, the second word line WL20 is connected to the first gate structure G1 of the selection transistor T1n of the DRAM cell structure CELL1n, the second word line WL21 is connected to the fourth gate structure G4 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the second word line WL22 is connected to the first gate structure G1 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The second word line WL2M is connected to the first gate structure G1 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0094] According to an embodiment of the present disclosure, N columns of DRAM cell structures can be connected together through M+1 first word lines WL10 to WL1M and M+1 second word lines WL20 to WL2M, thereby forming a DRAM array structure 200 including M rows and N columns, i.e., M×N DRAM cell structures.

[0095] As shown in FIG6 , according to an embodiment of the present disclosure, the M×N DRAM cell structures included in the DRAM array structure 200 can be arranged in mirror-symmetry along the column direction. That is, as shown in FIG6 , each DRAM cell structure is mirror-symmetric relative to its adjacent DRAM cell structure in the column direction. Taking the DRAM cell structure CELL2n shown in FIG6 as an example, its gate transistor T2n is mirror-symmetric with the gate transistor T1n of the adjacent DRAM cell structure CELL1n. That is, the third gate structure G3 of the gate transistor T2n is adjacent to the third gate structure G3 of the gate transistor T1n, and the fourth gate structure G4 of the gate transistor T2n is adjacent to the fourth gate structure G4 of the gate transistor T1n. In addition, the gate transistor T2n of the DRAM cell structure CELL2n is also mirror-symmetrical with the gate transistor T3n of the adjacent DRAM cell structure CELL3n, that is, the first gate structure G1 of the gate transistor T2n is adjacent to the first gate structure G1 of the gate transistor T3n, and the second gate structure G2 of the gate transistor T2n is adjacent to the second gate structure G2 of the gate transistor T3n.

[0096] According to an embodiment of the present disclosure, DRAM cell structures in adjacent rows are configured such that they share a first word line WL1m and a second word line WL2m in the column direction. For example, as shown in FIG6 , in the column direction, a DRAM cell structure CELL2n shares a first word line WL11 and a second word line WL21 with an adjacent DRAM cell structure CELL1n, and shares a first word line WL12 and a second word line WL22 with an adjacent DRAM cell structure CELL3n. In other words, as shown in FIG6 , according to an embodiment of the present disclosure, in the column direction, the first gate structure of the first side of the gate transistor of the DRAM cell structure shares a second word line with the first gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the second gate structure of the first side of the gate transistor of the DRAM cell structure shares a first word line with the second gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the third gate structure of the second side of the gate transistor of the DRAM cell structure shares a first word line with the third gate structure of the second side of the gate transistor of its adjacent DRAM cell structure, and the fourth gate structure of the second side of the gate transistor of the DRAM cell structure shares a second word line with the fourth gate structure of the second side of the gate transistor of its adjacent DRAM cell structure. In particular, according to an embodiment of the present disclosure, each DRAM cell structure of the DRAM cell array 200 is connected to two first word lines and two second word lines.

[0097] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share word lines (first word lines and second word lines), the isolation between word lines formed by the gate structures connecting adjacent DRAM cell structures can be omitted. Therefore, compared with the vertical channel transistor (VCT) of the prior art, the size miniaturization of the DRAM array structure can be further improved.

[0098] 7A and 7B respectively illustrate top views of a DRAM array structure including a VCT transistor according to the prior art and a DRAM cell structure of a transistor having four gate structures sharing a bit line according to an embodiment of the present disclosure.

[0099] As shown in FIG7A , in the column direction, word lines formed by connecting gate structures of VCT transistors according to the prior art require isolation via an isolation dielectric, which occupies additional area. In contrast, as shown in FIG7B , in the column direction, transistors having four gate structures according to an embodiment of the present disclosure share word lines with adjacent transistors having four gate structures, thereby eliminating isolation between word lines. Consequently, the DRAM array structure shown in FIG7B achieves further size reduction compared to the DRAM array structure shown in FIG7A .

[0100] In fact, according to the embodiment of the present disclosure, compared with the DRAM array structure implemented by the VCT transistor according to the prior art, the DRAM array structure implemented by the transistor with four gate structures according to the embodiment of the present disclosure changes the word line isolation in the horizontal direction to the word line isolation in the vertical direction, thereby achieving further size reduction.

[0101] The following describes the operating method of the DRAM array structure 200 according to an embodiment of the present disclosure based on Figure 6 in combination with Figure 5 and Figure 8. Figure 8 shows a schematic diagram of the operating method of the DRAM array structure 200 according to an embodiment of the present disclosure.

[0102] According to an embodiment of the present disclosure, the gate transistor in each DRAM cell structure in the DRAM array structure 200 is a transistor having four gate structures, which, as described above, can be equivalent to two dual-gate transistors connected in series. As described above with reference to FIG5 , by controlling the voltages applied to the four gate structures of the gate transistor, the gate transistor can be controlled to be turned on and off, thereby connecting or disconnecting the conductive path from the bit line of the corresponding DRAM cell structure to the storage capacitor.

[0103] 5 , 6 and 8 , according to an embodiment of the present disclosure, for each DRAM cell structure in the DRAM array structure 200, as described above, the conduction and shutoff of the selection transistor can be controlled by controlling the voltage applied to the second gate structure and the third gate structure of the selection transistor in the DRAM cell structure, that is, the voltage applied to the two first word lines connected thereto.

[0104] 5 , 6 and 8 , taking the case where the DRAM cell structure CELL2n in the 2nd row and nth column shown in FIG6 is selected as an example, when the DRAM cell structure CELL2n is selected, a high voltage VGH is applied to the first word lines WL12 and WL11 of the second gate structure G2 and the third gate structure G3 respectively connected to the selection transistor T2n in the DRAM cell structure CELL2n, so that the selection transistor T2n is turned on (as indicated by the arrow in the DRAM cell structure CELL2n in FIG6 ).

[0105] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the third gate structure G3 of the gate transistor T1n of the DRAM cell structure CELL1n in the 1st row and nth column, which is also connected to the first word line WL11, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T1n of the DRAM cell structure CELL1n, which is close to the third gate structure G3 (as indicated by the arrow in the DRAM cell structure CELL1n in FIG6 ). However, as shown in FIG8 , according to an embodiment of the present disclosure, since the first word line WL10 and the second word line WL21, which are respectively connected to the second gate structure G2 and the fourth gate structure G4 of the DRAM cell structure CELL1n, are applied with a low voltage VGL, the upper dual-gate transistor of the gate transistor T1n is turned off, and the gate transistor T1n of the DRAM cell structure CELL1n as a whole remains turned off.

[0106] Similarly, according to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the second gate structure G2 of the gate transistor T3n of the DRAM cell structure CELL3n in the 3rd row and nth column, which is also connected to the first word line WL12, is also applied with the high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T3n of the DRAM cell structure CELL3n, which is close to the second gate structure G2 (as indicated by the arrow in the DRAM cell structure CELL3n in FIG6 ). However, as shown in FIG8 , according to an embodiment of the present disclosure, since the second word line WL22 and the first word line WL13, which are respectively connected to the first gate structure G1 and the third gate structure G3 of the DRAM cell structure CELL3n, are applied with the low voltage VGL, the lower dual-gate transistor of the gate transistor T3n is turned off, and thus the gate transistor T3n of the DRAM cell structure CELL3n as a whole remains turned off.

[0107] 6 and 8 , according to an embodiment of the present disclosure, by controlling the voltages applied to the first word lines WL11 and WL12 , the DRAM cell structure CELL2 n can be turned on and off without affecting the operations of other DRAM cell structures.

[0108] Therefore, as shown in Figures 6 and 8, according to the embodiments of the present disclosure, the conduction and shutoff of the gate transistor in the DRAM cell structure can be controlled by the voltage applied to the first word line. Specifically, according to the embodiments of the present disclosure, for each DRAM cell structure in the DRAM array structure 200, the conduction and shutoff of the gate transistor of the DRAM cell structure can be controlled by controlling the voltages applied to its second gate structure and third gate structure via the two first word lines.

[0109] According to an embodiment of the present disclosure, in order to ensure that the selection transistors of adjacent DRAM cell structures in the column direction will not be erroneously turned on, in the selection transistors of each DRAM cell structure in the DRAM array structure 200, the gate structures arranged on the same side of the channel region (for example, the first gate structure and the second gate structure arranged on the first side or the third gate structure and the fourth gate structure arranged on the second side) will never be applied with a high voltage VGH at the same time.

[0110] In addition, as shown in FIG. 6 and FIG. 8 , according to an embodiment of the present disclosure, M+1 second word lines WL20 to WL2M may be commonly connected to the low voltage VGL.

[0111] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M may be commonly connected to a bias voltage different from VGL or floated to adjust switching characteristics of gate transistors of all DRAM cell structures.

[0112] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M can also be connected to corresponding bias voltages or floated in groups (for example, by storage area (Bank)) or individually, so as to adjust the switching characteristics of the selection transistors of the corresponding DRAM cell structures in groups or individually.

[0113] Specifically, according to the embodiments of the present disclosure, by setting the bias voltage at a lower voltage, the gate transistor including the gate structure connected to the second word line (i.e., the first gate structure and the fourth gate structure) can have a lower leakage current, thereby reducing the power consumption of the corresponding DRAM cell structure. In addition, by setting the bias voltage at a higher voltage, the gate transistor including the gate structure connected to the second word line can have a higher on-state current, thereby improving the read and write speed of the corresponding DRAM cell structure.

[0114] According to the embodiments of the present disclosure, adjusting the bias voltage can provide a greater degree of adjustment than adjusting the switching characteristics of the gate transistor by adjusting the work function of the gate structure alone. Furthermore, according to the embodiments of the present disclosure, adjusting the bias voltage can enable the DRAM array structure to operate in different operating modes, such as a high-performance operating mode and a low-power operating mode.

[0115] Those skilled in the art will appreciate that the operating method of the DRAM array structure according to the present disclosure is not limited to the embodiments described above with reference to FIG. 6 and FIG. 8 .

[0116] For example, according to another embodiment of the present disclosure, the on / off state of the gate transistor in the DRAM cell structure can be controlled by applying voltages to the M+1 second word lines, that is, by controlling the voltages applied to the first gate structure and the fourth gate structure. Accordingly, according to this embodiment of the present disclosure, bias voltages can be applied to the M+1 first word lines collectively, in groups, and / or individually, or they can be left floating.

[0117] The following describes a method for manufacturing a DRAM array structure according to the first embodiment of the present disclosure in conjunction with Figures 9A to 10B. Figures 9A to 9D are schematic cross-sectional views of the various steps of the method for manufacturing a DRAM array structure according to the first embodiment of the present disclosure. Figures 9A to 9D are cross-sectional views taken in the column direction, i.e., the bit line direction, of the DRAM array structure. In other words, in Figures 9A to 9D, the direction perpendicular to the paper is the row direction, and the direction parallel to the paper is the column direction.

[0118] As shown in FIG9A , according to an embodiment of the present disclosure, a substrate 901 may be provided. According to an embodiment of the present disclosure, the substrate 901 may include, for example, a P-type semiconductor, an N-type semiconductor, or an intrinsic semiconductor. Furthermore, according to an embodiment of the present disclosure, the substrate 901 may also be a substrate of other forms, including but not limited to a bulk semiconductor material substrate such as a bulk silicon substrate, a compound semiconductor substrate such as a silicon germanium (SiGe) substrate, and the like.

[0119] 9A , according to an embodiment of the present disclosure, a bit line 902 may be formed in a substrate 901. According to an embodiment of the present disclosure, the bit line 902 may include a metal, such as copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), tungsten (W), manganese (Mn), platinum (Pt), palladium (Pd), tantalum nitride, titanium nitride, or other low-resistance metals.

[0120] Subsequently, as shown in FIG9B , according to an embodiment of the present disclosure, a plurality of semiconductor pillars 903 may be formed above the bit lines 902. According to an embodiment of the present disclosure, the semiconductor pillars 903 may be used to form the active area 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to FIG2 to FIG4 in a subsequent process step, and are therefore also referred to as “active area pillars” hereinafter, which may include a first source / drain region and a second source / drain region and a channel region therebetween in the vertical direction. According to an embodiment of the present disclosure, the active area pillars 903 may be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the row direction and the column direction.

[0121] Subsequently, as shown in Figure 9C, according to the embodiment of the present disclosure, the first gate dielectric 904 and the first layer word line 905 and the second gate dielectric 906 and the second layer word line 907 can be formed in sequence between each row of active area pillars 903 along the row direction (i.e., the direction perpendicular to the paper surface).

[0122] According to an embodiment of the present disclosure, the first gate dielectric 904 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 2 to 4. According to an embodiment of the present disclosure, the first layer word line 905 may not only serve as the first word line and the second word line connected to the lower gate structure (i.e., the first gate structure G1 105 and the third gate structure G3 107) of the gate transistor T described above in conjunction with Figure 6, but may also serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4.

[0123] Furthermore, according to an embodiment of the present disclosure, the second gate dielectric 906 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 2 to 4 . According to an embodiment of the present disclosure, the dielectric material and thickness of the first gate dielectric 904 and the second gate dielectric 906 may be the same or different. According to an embodiment of the present disclosure, the second layer word line 907 may not only serve as the first word line and the second word line connected to the upper gate structure (i.e., the second gate structure G2 106 and the fourth gate structure G4 108) of the gate transistor T described above in conjunction with Figure 6 , but may also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4 .

[0124] 9D , according to an embodiment of the present disclosure, storage capacitors 909 may be formed over each row of active region pillars 903. Since the process steps for forming storage capacitors are well known to those skilled in the art, they will not be described in further detail herein for the sake of brevity.

[0125] Although not shown, according to an embodiment of the present disclosure, contacts may be formed at both ends of the active region pillar 903 through, for example, ion implantation and annealing processes to achieve better electrical connection with the storage capacitor and the bit line.

[0126] 9C and 9D , according to an embodiment of the present disclosure, an isolation dielectric 908 may be filled between the bit line 902 and the first gate dielectric 904 and the first-layer word line 905, between the first gate dielectric 904 and the first-layer word line 905 and the second gate dielectric 906 and the second-layer word line 907, and between the second gate dielectric 906 and the second-layer word line 907 and the storage capacitor 909. According to an embodiment of the present disclosure, the isolation dielectric 908 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination thereof.

[0127] FIG10A shows a schematic cross-sectional view taken along line BB' in FIG9D , and FIG10B shows a schematic cross-sectional view taken along line CC' in FIG9D . Both FIG10A and FIG10B are cross-sectional views taken along the row direction, i.e., the word line direction, of the DRAM array structure. In other words, in FIG10A and FIG10B , the direction perpendicular to the paper is the column direction, and the direction parallel to the paper is the row direction.

[0128] The method for manufacturing a DRAM array structure according to the second embodiment of the present disclosure will be described below in conjunction with Figures 11A to 12B. Figures 11A to 11D are schematic cross-sectional views of the various steps of the method for manufacturing a DRAM array structure according to the second embodiment of the present disclosure. Figures 11A to 11D are cross-sectional views taken in the column direction, i.e., the bit line direction, of the DRAM array structure. In other words, in Figures 11A to 11D, the direction perpendicular to the paper is the row direction, and the direction parallel to the paper is the column direction.

[0129] For the sake of brevity, the components in FIG. 11A to FIG. 11D that are identical to those in FIG. 9A to FIG. 9D are denoted by the same reference numerals, and the corresponding descriptions are omitted.

[0130] The difference between the method for manufacturing a DRAM array structure shown in Figures 11A to 11D and the method for manufacturing a DRAM array structure shown in Figures 9A to 9D is that in Figures 9A to 9D, the bit lines, selection transistors and storage capacitors of the DRAM cell structure are formed sequentially in the vertical direction, while in Figures 11A to 11D, the storage capacitors, selection transistors and bit lines of the DRAM cell structure are formed sequentially in the vertical direction.

[0131] 11A , according to an embodiment of the present disclosure, a substrate 901 may be provided. Furthermore, as shown in FIG11A , according to an embodiment of the present disclosure, a storage capacitor 909 may be formed over the substrate 901.

[0132] Subsequently, as shown in FIG11B , according to an embodiment of the present disclosure, a plurality of semiconductor pillars 903 may be formed above the storage capacitor 909. According to an embodiment of the present disclosure, the semiconductor pillars 903 may be used to form the active area 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to FIG2 to FIG4 in a subsequent process step, and are therefore also referred to as “active area pillars” hereinafter, which may include a first source / drain region and a second source / drain region and a channel region therebetween in the vertical direction. According to an embodiment of the present disclosure, the active area pillars 903 may be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the row direction and the column direction.

[0133] According to an embodiment of the present disclosure, the semiconductor pillar (active region pillar) 903 may include a bulk semiconductor material such as a P-type semiconductor, an N-type semiconductor, or an intrinsic semiconductor. In addition, according to an embodiment of the present disclosure, the semiconductor pillar 903 may also include other types of materials. For example, the semiconductor pillar 903 may include, but is not limited to, a compound semiconductor material such as silicon germanium (SiGe), an oxide semiconductor material such as zinc oxide (ZnO), indium zinc oxide (IZO), and / or indium gallium zinc oxide (IGZO), or a two-dimensional semiconductor material such as graphene, molybdenum sulfide, and the like.

[0134] Subsequently, as shown in Figure 9C, according to the embodiment of the present disclosure, the first gate dielectric 904 and the first layer word line 905 and the second gate dielectric 906 and the second layer word line 907 can be formed in sequence between each row of active area pillars 903 along the row direction (i.e., the direction perpendicular to the paper surface).

[0135] According to an embodiment of the present disclosure, the first gate dielectric 904 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 2 to 4. According to an embodiment of the present disclosure, the first layer word line 905 may not only serve as the first word line and the second word line connected to the upper gate structure (i.e., the second gate structure G2 106 and the fourth gate structure G4 108) of the gate transistor T described above in conjunction with Figure 6, but may also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4.

[0136] Furthermore, according to an embodiment of the present disclosure, the second gate dielectric 906 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 2 to 4 . According to an embodiment of the present disclosure, the dielectric material and thickness of the first gate dielectric 904 and the second gate dielectric 906 may be the same or different. According to an embodiment of the present disclosure, the second layer word line 907 may not only serve as the first word line and the second word line connected to the lower gate structure (i.e., the first gate structure G1 105 and the third gate structure G3 107) of the gate transistor T described above in conjunction with Figure 6 , but may also serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4 .

[0137] 9D , according to an embodiment of the present disclosure, a bit line 902 may be formed over each row of active region pillars 903. According to an embodiment of the present disclosure, the bit line 902 may include a metal, such as copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), tungsten (W), manganese (Mn), platinum (Pt), palladium (Pd), tantalum nitride, titanium nitride, or other low-resistance metals.

[0138] Although not shown, according to an embodiment of the present disclosure, contacts may be formed at both ends of the active region pillar 903 through, for example, ion implantation and annealing processes to achieve better electrical connection with the storage capacitor and the bit line.

[0139] FIG12A shows a schematic cross-sectional view taken along line DD′ in FIG11D , and FIG12B shows a schematic cross-sectional view taken along line EE′ in FIG11D . Both FIG12A and FIG12B are cross-sectional views taken along the row direction, i.e., the word line direction, of the DRAM array structure. In other words, in FIG12A and FIG12B , the direction perpendicular to the paper is the column direction, and the direction parallel to the paper is the row direction.

[0140] FIG13 is a schematic top view illustrating a DRAM array structure manufactured according to the methods of the first and second embodiments of the present disclosure. In FIG13 , for clarity, the bit lines 902 and the second word lines 907 (and the second gate dielectric 906) are moderately extended. Furthermore, in FIG13 , a dotted-line box represents a storage capacitor 909.

[0141] Although the active region pillar 903 is shown as having a square cross-section in the horizontal direction in FIG13 , the present disclosure is not limited thereto. According to the teachings of the present disclosure, those skilled in the art may also envision that the active region pillar 903 has other shapes in the horizontal direction, such as a rectangle, a circle, an ellipse, a diamond, etc., and all such variations should be included within the scope of the present disclosure.

[0142] In addition, although the storage capacitor 909 is shown as having a square cross-section in the horizontal direction in FIG13 , the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision that the storage capacitor 909 has other shapes in the horizontal direction, such as a rectangle, a circle, an ellipse, and all such variations are intended to fall within the scope of the present disclosure.

[0143] The method for manufacturing a DRAM array structure according to the third embodiment of the present disclosure will be described below with reference to Figures 14A to 14C. Figure 14A shows a schematic cross-sectional view of a DRAM array structure manufactured by the method according to the third embodiment of the present disclosure, Figure 14B shows a schematic top view of the DRAM array structure manufactured by the method according to the third embodiment of the present disclosure, and Figure 14C shows a schematic bottom view of the DRAM array structure manufactured by the method according to the third embodiment of the present disclosure.

[0144] Figure 14A is a schematic cross-sectional view taken in the row direction, i.e., the word line direction, of a DRAM array structure. In other words, in Figure 14A, the direction perpendicular to the paper is the column direction, and the direction parallel to the paper is the row direction.

[0145] For the sake of brevity, the components in FIG. 14A to FIG. 14C that are identical to those in FIG. 9A to FIG. 13 are denoted by the same reference numerals, and the corresponding descriptions are omitted.

[0146] The method for manufacturing a DRAM array structure shown in Figures 14A to 14C is different from the method for manufacturing a DRAM array structure shown in Figures 9A to 13 in that, in Figures 9A to 13, bit lines, selection transistors and storage capacitors are formed sequentially in the vertical direction, or storage capacitors, selection transistors and bit lines are formed sequentially in the vertical direction, whereas in Figures 14A to 14C, storage capacitors of the DRAM cell structure of odd columns (or even columns), bit lines of the DRAM cell structure of even columns (or odd columns), selection transistors of the DRAM cell structure, bit lines of the DRAM cell structure of odd columns (or even columns) and storage capacitors of the DRAM cell structure of even columns (or odd columns) are formed sequentially in the vertical direction.

[0147] In this specification, for the sake of clarity, the storage capacitor located vertically below is referred to as the first storage capacitor and is denoted by reference numeral 909a, while the storage capacitor located vertically above is referred to as the second storage capacitor and is denoted by reference numeral 909b. Furthermore, the bit line located vertically below is referred to as the first bit line and is denoted by reference numeral 902a, while the bit line located vertically above is referred to as the second bit line and is denoted by reference numeral 902b.

[0148] 14A , the method for manufacturing a DRAM array structure according to the third embodiment of the present disclosure may include the following steps.

[0149] First, a substrate 901 may be provided, and then a first storage capacitor 909a may be formed over the substrate 901. According to an embodiment of the present disclosure, the first storage capacitor 909a may be a storage capacitor of a DRAM cell structure of odd columns or a storage capacitor of a DRAM cell structure of even columns.

[0150] Subsequently, a first bit line 902a may be formed. Preferably, the first bit line 902a is located vertically above the first storage capacitor 909a. When the first storage capacitor 909a is a storage capacitor for an odd-numbered column DRAM cell structure, the first bit line 902a may be a bit line for an even-numbered column DRAM cell structure, and when the first storage capacitor 909a is a storage capacitor for an even-numbered column DRAM cell structure, the first bit line 902a may be a bit line for an odd-numbered column DRAM cell structure.

[0151] Subsequently, similar to the steps described above with reference to Figures 9C and 11C, active area pillars 903 are formed, and a first gate dielectric 904 and a first layer of word line 905 as well as a second gate dielectric 906 and a second layer of word line 907 are sequentially formed between each row of active area pillars 903 along the row direction (i.e., the direction perpendicular to the paper surface).

[0152] Subsequently, a second bit line 902b may be formed over a portion of the active region pillar 903. When the first bit line 902a is a bit line of the DRAM cell structure of an even column, the second bit line 902b may be a bit line of the DRAM cell structure of an odd column, and when the first bit line 902a is a bit line of the DRAM cell structure of an odd column, the second bit line 902b may be a bit line of the DRAM cell structure of an even column.

[0153] Subsequently, a second storage capacitor 909b may be formed above the remaining portion of the active region pillar 903. Preferably, the second storage capacitor 909b is located vertically above the second bit line 902b. When the first storage capacitor 909a is a storage capacitor for an odd-numbered column DRAM cell structure, the second storage capacitor 909b may be a storage capacitor for an even-numbered column DRAM cell structure, and when the first storage capacitor 909a is a storage capacitor for an even-numbered column DRAM cell structure, the second storage capacitor 909b may be a storage capacitor for an odd-numbered column DRAM cell structure.

[0154] As shown in Figures 14B and 14C, according to an embodiment of the present disclosure, by arranging the storage capacitors and bit lines of adjacent columns on the upper and lower sides of the gate transistor, respectively, the size of the storage capacitor can be expanded in the row direction. As shown in Figures 14A to 14C, since the storage capacitor of the DRAM cell structure connected to the first bit line 902a (i.e., the second storage capacitor 909b) is arranged above the gate transistor, and the storage capacitor of the DRAM cell structure connected to the second bit line 902b (i.e., the first storage capacitor 909a) is arranged below the gate transistor, the storage capacitors of the DRAM cell structures in adjacent columns will not occupy each other's space. Referring to Figures 14B and 14C, compared with the first and second embodiments, the size of the storage capacitor of the DRAM cell structure manufactured according to the third embodiment of the present disclosure can be expanded by up to twice in the row direction, thereby further achieving the size reduction of the DRAM array structure.

[0155] FIG15 shows an equivalent circuit diagram of a DRAM array structure manufactured according to the method of the third embodiment of the present disclosure. For the sake of brevity, the components in FIG15 that are identical to those in FIG6 are represented by the same reference numerals, and the corresponding descriptions are omitted. FIG15 shows the n-th column DRAM cell structure and the n+1-th column DRAM cell structure of the DRAM array structure manufactured according to the method of the third embodiment of the present disclosure, which can be selected by the n-th bit line BLn and the n+1-th bit line, respectively. The n-th column DRAM cell structure can be a DRAM cell structure of an odd column (or even column), and the n+1-th column DRAM cell structure can be a DRAM cell structure of an even column (or technology column).

[0156] Referring to Figure 15 in combination with Figure 14A, according to an embodiment of the present disclosure, the storage capacitors C1n to CMn in the n-th column DRAM cell structure may correspond to the first storage capacitor 909a shown in Figure 14A, the n+1-th bit line BLn+1 commonly connected to the n+1-th column DRAM cell structure may correspond to the first bit line 902a shown in Figure 14A, the n-th bit line BLn commonly connected to the n-th column DRAM cell structure may correspond to the second bit line 902b shown in Figure 14A, and the storage capacitors C1n+1 to CMn+1 in the n+1-th column DRAM cell structure may correspond to the second storage capacitor 909b shown in Figure 14A.

[0157] Those skilled in the art will recognize that although a cylinder capacitor is used as the storage capacitor in the embodiments described above, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision using capacitors with other structures as storage capacitors, such as pillar capacitors. All of the above variations are intended to be within the scope of the present disclosure.

[0158] According to the DRAM array structure and manufacturing method disclosed herein, a vertical DRAM cell structure with a double-layer word line is manufactured by using a double-sided layout method, and the DRAM cell structures in adjacent rows share the word line in the column direction, thereby eliminating the inherent spacing area between the word lines in the traditional DRAM array structure based on ring-gate transistors, increasing the area of ​​the storage capacitor, and thus achieving further size reduction.

[0159] The method for manufacturing a DRAM array structure according to an embodiment of the present disclosure will be described below in conjunction with Figures 16 to 30B. Figures 16 to 30B respectively show schematic cross-sectional views of various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. It should be noted that Figures 16 to 18 are cross-sectional views taken in the row direction of the DRAM array structure, i.e., the word line direction, wherein the bit line direction is perpendicular to the paper plane, while Figures 19 to 30B are cross-sectional views taken in the column direction of the DRAM array structure, i.e., the bit line direction, wherein the word line direction is perpendicular to the paper plane. In addition, Figures 25A to 30A respectively show cross-sectional views of the DRAM cell structure of an odd column (or even column) at various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure, while Figures 25B to 30B respectively show cross-sectional views of the DRAM cell structure of an even column (or odd column) at various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure.

[0160] In the following description, the materials for each layer are exemplified. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description of "selectively etching B (relative to A)" indicates that the etching recipe used can primarily affect B, with little or no effect on A or other material layers exposed to the etching recipe when etching B (in the absence of explicit mention of A or only a portion of such material layers). Based on this description, those skilled in the art will understand how to select the materials for each layer, and are not limited to the materials exemplified herein.

[0161] As shown in FIG16 , according to an embodiment of the present disclosure, a substrate may be provided. As shown in FIG16 , according to an embodiment of the present disclosure, the substrate may include a base layer 1601 , a stop layer 1602 disposed on the base layer 1601 , and an active layer 1603 disposed on the stop layer 1602 .

[0162] According to an embodiment of the present disclosure, the base layer 1601 may include, for example, silicon. In addition, according to an embodiment of the present disclosure, as will be further described below, the stop layer 1602 may be used to stop, for example, an etching or grinding process at this layer in a subsequent process step. According to an embodiment of the present disclosure, the stop layer 1602 may be formed by an epitaxial or implantation process and may include, for example, silicon germanium. In addition, according to an embodiment of the present disclosure, the active layer 1603 may be used to form, in a subsequent process step, the active region 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to Figures 2 to 4, which may include a first source / drain region and a second source / drain region and a channel region therebetween. According to an embodiment of the present disclosure, the active layer 1603 may include, for example, a P-type semiconductor, an N-type semiconductor, or an intrinsic semiconductor, and have an etching selectivity relative to the stop layer 1602. In addition, according to an embodiment of the present disclosure, the active layer 1603 may also include other types of materials. For example, the active layer 1603 may include but is not limited to compound semiconductor materials, such as silicon germanium (SiGe), oxide semiconductor materials, such as zinc oxide (ZnO), indium zinc oxide (IZO) and / or indium gallium zinc oxide (IGZO), or two-dimensional semiconductor materials, such as graphene, molybdenum sulfide, and the like.

[0163] Alternatively, according to an embodiment of the present disclosure, a semiconductor-on-insulator (SOI) substrate may be provided, which includes an insulating layer sandwiched between silicon layers, wherein the insulating layer typically includes silicon oxide. In an embodiment of the present disclosure, the lower silicon layer of the SOI substrate may serve as the base layer 1601, the insulating layer may serve as the stop layer 1602, and the upper silicon layer may serve as the active layer 1603. As known to those skilled in the art, the SOI substrate may be manufactured by, for example, oxygen implantation isolation, wafer bonding, or smart lift-off processes.

[0164] Subsequently, as shown in FIG17 , according to an embodiment of the present disclosure, the active layer 1603 can be etched by, for example, a photolithography and etching process to form a first groove G1 extending to the stop layer 1602. It should be noted that according to an embodiment of the present disclosure, the first groove G1 extends along the column direction (i.e., the direction perpendicular to the paper), i.e., the bit line direction. According to an embodiment of the present disclosure, the first groove G1 is used to isolate the bit lines connected to each column of the DRAM cell structure, and is therefore also referred to as a "bit line isolation groove" hereinafter. According to an embodiment of the present disclosure, the bit line isolation groove G1 can be used to limit the size of the active area of ​​the selection transistor of the DRAM cell structure in the row direction.

[0165] 18 , according to an embodiment of the present disclosure, a first isolation dielectric 1604 may be filled in the first trench G1 by, for example, a deposition process. According to an embodiment of the present disclosure, the first isolation dielectric 1604 may include oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof.

[0166] It should be noted that Figures 19 to 24 illustrate cross-sectional views of the DRAM array structure taken along lines BB' and CC' of Figure 18 , i.e., cross-sectional views in the row direction, i.e., the wordline direction, of the DRAM array structure. Furthermore, Figures 25A to 30A illustrate cross-sectional views of the DRAM cell structure of an odd-numbered column of the DRAM array structure taken along line BB' of Figure 18 , while Figures 25B to 30B illustrate cross-sectional views of the DRAM cell structure of an even-numbered column of the DRAM array structure taken along line CC' of Figure 18 . Those skilled in the art should recognize that the terms even column and odd column mentioned herein are relative terms and may be used interchangeably herein. For example, Figures 25A to 30A may also illustrate cross-sectional views of the DRAM cell structure of an even-numbered column of the DRAM array structure taken along line BB' of Figure 18 , and Figures 25B to 30B may also illustrate cross-sectional views of the DRAM cell structure of an odd-numbered column of the DRAM array structure taken along line CC' of Figure 18 .

[0167] Based on the cross-sectional view of the DRAM array structure in the row direction, i.e., the word line direction, shown in FIG19 , according to an embodiment of the present disclosure, the upper surface of the active layer 1603 can be flattened and exposed by, for example, a grinding process or an etching process, as shown in FIG20 .

[0168] Furthermore, as shown in FIG20 , according to an embodiment of the present disclosure, the active layer 1603 can be etched by photolithography or etching to form a second trench G2 extending to the stop layer 1602. According to an embodiment of the present disclosure, the second trench G2 is used to define the position of the word line in subsequent process steps, and therefore may also be referred to herein as a "word line trench." The second trench G2 is horizontally perpendicular to the first trench (bit line isolation trench) G1. According to an embodiment of the present disclosure, the word line trench G2 can be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the column direction.

[0169] Subsequently, as shown in FIG21 , according to an embodiment of the present disclosure, a sacrificial dielectric 1605 can be formed in the second trench G2, for example, by a deposition process. According to an embodiment of the present disclosure, the sacrificial dielectric 1605 can be formed from a material having an etch selectivity, such as silicon oxide, silicon nitride, polyimide, amorphous silicon, polysilicon, silicon germanium, or germanium. According to an embodiment of the present disclosure, the sacrificial dielectric 1605 can be used to form a gate dielectric and first and second word lines in subsequent process steps.

[0170] 22 , according to an embodiment of the present disclosure, a portion of the sacrificial dielectric 1605 can be self-alignedly etched using the active layer 1603 as a mask, for example, through an etching process. Preferably, according to an embodiment of the present disclosure, the etching depth of the sacrificial dielectric 1605 can be controlled so that half of the thickness of the sacrificial dielectric 1605 in the vertical direction is removed.

[0171] 22 , according to an embodiment of the present disclosure, a first gate dielectric 1606 may be conformally formed, for example, by a deposition process, along the surface of the second groove G2 and the upper surface of the active layer 1603. According to an embodiment of the present disclosure, the first gate dielectric 1606 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG. 2 to FIG. 4 .

[0172] Subsequently, as shown in FIG23 , according to an embodiment of the present disclosure, a first conductor line 1607 (also referred to herein as a “first layer word line”) serving as both a word line and a gate structure can be formed in the second trench G2 by, for example, a deposition process and an etching process, wherein the first conductor line 1607 is separated from the active layer 1603 by a first gate dielectric 1606. According to an embodiment of the present disclosure, the first conductor line 1607 can simultaneously serve as the gate structure (the first gate structure and the third gate structure or the second gate structure and the fourth gate structure) of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the gate structure of the gate transistor T described above in conjunction with FIG6 .

[0173] Subsequently, as shown in Figure 24, according to an embodiment of the present disclosure, a contact portion can be formed at one end of the active layer 1603 (the upper end shown in Figure 23), namely the capacitor contact portion 1608 of the odd-numbered column DRAM cell structure or the bit line contact portion 1614 of the even-numbered column DRAM cell structure described below.

[0174] Subsequently, as shown in FIG25A , according to an embodiment of the present disclosure, the second trench G2 may be filled with a second isolation dielectric 1609, and a first storage capacitor 1610 a may be formed on the capacitor contact 1608 in the odd-numbered columns of the DRAM cell structure. Furthermore, as shown in FIG25B , according to an embodiment of the present disclosure, the second trench G2 may be filled with a second isolation dielectric 1609, and a first bit line 1616 a may be formed on the bit line contact 1614 in the even-numbered columns of the DRAM cell structure. According to an embodiment of the present disclosure, the first bit line 1616 a may include a metal, such as copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), tungsten (W), manganese (Mn), platinum (Pt), palladium (Pd), tantalum nitride, titanium nitride, or other low-resistance metal.

[0175] According to an embodiment of the present disclosure, the second isolation dielectric 1609 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination thereof. According to an embodiment of the present disclosure, the second isolation dielectric 1609 may be formed of the same material as the first isolation dielectric 1604, or may be formed of a different material from the first isolation dielectric 1604.

[0176] Since the process steps for forming the storage capacitor are well known to those skilled in the art, they are not described in further detail herein for the sake of brevity.

[0177] According to an embodiment of the present disclosure, in order to increase the size of the first storage capacitor 1610a in the row direction (i.e., the word line direction), in Figures 25A and 25B, the first bit line 1616a can be arranged below the first storage capacitor 1610a in the vertical direction (as further described below with reference to Figures 31, 32A, and 32B). Therefore, as shown in Figures 25A and 25B, according to an embodiment of the present disclosure, the capacitor contact 1608 and the bit line contact 1614 can be formed to have different lengths in the vertical direction. For example, according to an embodiment of the present disclosure, the length of the capacitor contact 1608 in the vertical direction is at least greater than the length of the bit line contact 1614 in the vertical direction by the length of the first bit line 1616a in the vertical direction, so that the first storage capacitor 1610a in the odd-numbered columns of the DRAM cell structure is arranged in the vertical direction above the first bit line 1616a in the even-numbered columns. Therefore, according to an embodiment of the present disclosure, the first bit line 1616a shown in FIG. 25B may be formed before the first storage capacitor 1610a shown in FIG. 25A to ensure that the first storage capacitor 1610a is disposed vertically above the first bit line 1616a.

[0178] Subsequently, as shown in Figures 26A and 26B, according to an embodiment of the present disclosure, the entire DRAM array structure can be flipped, and a support layer 1611 is bonded to one side of the first storage capacitor 1610a and the first bit line 1616a through, for example, a wafer bonding process to support the flipped DRAM array structure. According to an embodiment of the present disclosure, the support layer 1611 can include, for example, inorganic polymers such as silicon, oxides, nitrides, and glass, organic polymers such as polyimide, or combinations thereof.

[0179] 26A and 26B , according to an embodiment of the present disclosure, the base layer 1601 and the stop layer 1602 may be sequentially removed by etching or grinding processes to expose the other end (the upper end shown in FIG. 24 ) of the active layer 1603 .

[0180] Subsequently, as shown in FIG. 27A and FIG. 27B , according to an embodiment of the present disclosure, the remaining portion of the sacrificial dielectric 1605 in the second groove G2 may be self-alignedly etched using the active layer 1603 as a mask, for example, through an etching process to expose the first gate dielectric 1606 .

[0181] Subsequently, as shown in Figures 28A and 28B, according to an embodiment of the present disclosure, a second gate dielectric 1612 and a second conductor line 1613 (also referred to herein as a "second-layer word line") can be sequentially formed above the first gate dielectric 1606 by repeating the steps described above with reference to Figures 22 and 23, wherein the second conductor line 1613 is separated from the active layer 1603 by the second gate dielectric 1612. According to an embodiment of the present disclosure, the second conductor line 1613 can simultaneously serve as the gate structure (the second gate structure and the fourth gate structure or the first gate structure and the third gate structure) of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4, as well as the first and second word lines connected to the lower gate structure of the gate transistor T described above in conjunction with Figure 6. According to an embodiment of the present disclosure, the dielectric material and thickness of the first gate dielectric 1606 and the second gate dielectric 1612 can be the same or different. According to an embodiment of the present disclosure, the first conductor line 1607 and the second conductor line 1613 can respectively form the two-layer word lines of the DRAM array structure according to an embodiment of the present disclosure.

[0182] Subsequently, as shown in FIG29A , according to an embodiment of the present disclosure, a bit line contact 1614 may be formed at the other end (the lower end shown in FIG24 , corresponding to the upper end shown in FIG28A and FIG28B ) of the active layer 1603 of the DRAM cell structure of the odd columns by repeating the steps described above with reference to FIG24 . Furthermore, as shown in FIG29B , according to an embodiment of the present disclosure, a capacitor contact 1608 may be formed at the other end (the lower end shown in FIG24 , corresponding to the upper end shown in FIG28A and FIG28B ) of the active layer 1603 of the DRAM cell structure of the even columns by repeating the steps described above with reference to FIG24 .

[0183] Subsequently, as shown in FIG30A , according to an embodiment of the present disclosure, the second trench G2 may be filled with a third isolation dielectric 1615, and a second bit line 1616b may be formed on the bit line contact 1614 in the DRAM cell structure of the odd columns, thereby forming a DRAM array structure of the odd columns. According to an embodiment of the present disclosure, the second bit line 1616b may include a metal such as copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), molybdenum (Mo), tungsten (W), manganese (Mn), platinum (Pt), palladium (Pd), tantalum nitride, titanium nitride, or other low-resistance metal. Furthermore, as shown in FIG30B , according to an embodiment of the present disclosure, the second trench G2 may be filled with a third isolation dielectric 1615, and a second storage capacitor 1610b may be formed on the capacitor contact 1608 in the DRAM cell structure of the even columns, thereby forming a DRAM array structure of the even columns. The DRAM array structure of the odd columns and the DRAM array structure of the even columns together constitute a DRAM array structure according to an embodiment of the present disclosure.

[0184] That is, according to an embodiment of the present disclosure, the storage capacitors and bit lines of adjacent columns of DRAM cell structures may be arranged differently in the vertical direction, and the storage capacitors and bit lines of alternate columns of DRAM cell structures may be arranged identically in the vertical direction.

[0185] Similar to the description above with reference to Figures 25A and 25B, in order to increase the size of the second storage capacitor 1610b in the row direction (i.e., the word line direction), in Figures 30A and 30B, the second bit line 1616b can be arranged below the second storage capacitor 1610b in the vertical direction (as further described below with reference to Figures 31, 32A, 32B, and 34A, 34B). Therefore, as shown in Figures 30A and 30B, according to an embodiment of the present disclosure, the length of the capacitor contact 1608 in the vertical direction is also greater than the length of the bit line contact 1614 in the vertical direction by at least the length of the second bit line 1616b in the vertical direction, so that the second storage capacitor 1610b in the DRAM cell structure of even columns is arranged vertically above the second bit line 1616b in odd columns. Therefore, the length of the capacitor contact 1608 in the vertical direction is greater than the length of the bit line contact 1614 in the vertical direction by at least the greater of the lengths of the first and second bit lines 1616a and 1616b in the vertical direction.

[0186] Therefore, according to an embodiment of the present disclosure, the second bit line 1616b shown in FIG. 30A may be formed before the second storage capacitor 1610b shown in FIG. 30B to ensure that the second storage capacitor 1610b is disposed vertically above the second bit line 1616b.

[0187] According to an embodiment of the present disclosure, the third isolation dielectric 1615 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination thereof. According to an embodiment of the present disclosure, the third isolation dielectric 1615 may be formed of the same material as the first isolation dielectric 1604 and / or the second isolation dielectric 1609, or may be formed of a different material than the first isolation dielectric 1604 and / or the second isolation dielectric 1609.

[0188] FIG31 shows a schematic cross-sectional view of a DRAM array structure manufactured according to a method according to an embodiment of the present disclosure. FIG31 is a schematic cross-sectional view taken along the row direction, i.e., the word line direction, of the DRAM array structure. In other words, in FIG31 , the direction perpendicular to the paper is the column direction, and the direction parallel to the paper is the row direction.

[0189] FIG32A shows a schematic top view of a DRAM array structure manufactured according to a method according to an embodiment of the present disclosure, and FIG32B shows a schematic bottom view of a DRAM array structure manufactured according to a method according to an embodiment of the present disclosure. In FIG32A and FIG32B , for clarity, first bit line 1616 a, second bit line 1616 b, and second conductor line 1613 (and second gate dielectric 1612) are moderately extended.

[0190] For the sake of brevity, the same components in Figures 31, 32A, and 32B as those in Figures 16 to 30B are represented by the same reference numerals, and the corresponding descriptions are omitted.

[0191] As shown in Figure 31, through the double-sided processing process for manufacturing the DRAM array structure described above with reference to Figures 16 to 30B, the first storage capacitor 1610a of the DRAM cell structure of odd columns (or even columns), the first bit line 1616a of the DRAM cell structure of even columns (or odd columns), the selection transistor of the DRAM cell structure, the second bit line 1616b of the DRAM cell structure of odd columns (or even columns) and the second storage capacitor 1610b of the DRAM cell structure of even columns (or odd columns) are arranged in sequence in the vertical direction.

[0192] As shown in Figure 31, according to an embodiment of the present disclosure, the first bit line 1616a is staggered with the first storage capacitor 1610a in the vertical direction, and the second bit line 1616b is staggered with the second storage capacitor 1610b in the vertical direction, so that the bit line does not occupy the space of the storage capacitor in the row direction.

[0193] According to an embodiment of the present disclosure, as shown in FIG31 , since the first bit line 1616a can be set above the first storage capacitor 1610a, and the second bit line 1616b can be set below the second storage capacitor 1610b, as shown in FIG32A and FIG32B , the storage capacitors of adjacent columns of DRAM cell structures will not occupy each other's space, so that the size of the storage capacitors (first storage capacitor and second storage capacitor) can be expanded by up to twice in the row direction, thereby further realizing the size miniaturization of the DRAM array structure.

[0194] Figure 33 shows an equivalent circuit diagram of a DRAM array structure manufactured by a method according to an embodiment of the present disclosure. For the sake of brevity, the components in Figure 33 that are identical to those in Figure 6 are represented by the same reference numerals, and the corresponding descriptions are omitted. Figure 33 shows the n-th column DRAM cell structure and the n+1-th column DRAM cell structure of the DRAM array structure manufactured by a method according to an embodiment of the present disclosure, which can be selected by the n-th bit line BLn and the n+1-th bit line, respectively. The n-th column DRAM cell structure can be a DRAM cell structure of an odd column (or even column), and the n+1-th column DRAM cell structure can be a DRAM cell structure of an even column (or technology column).

[0195] Referring to Figure 33 in combination with Figure 31, according to an embodiment of the present disclosure, the storage capacitors C1n to CMn in the nth column DRAM cell structure may correspond to the first storage capacitor 1610a shown in Figure 31, the n+1th bit line BLn+1 commonly connected to the n+1th column DRAM cell structure may correspond to the first bit line 1616a shown in Figure 31, the nth bit line BLn commonly connected to the nth column DRAM cell structure may correspond to the second bit line 1616b shown in Figure 31, and the storage capacitors C1n+1 to CMn+1 in the n+1th column DRAM cell structure may correspond to the second storage capacitor 1610b shown in Figure 31.

[0196] Those skilled in the art will recognize that, although in the embodiments described above, a stop layer is provided so that the etching or grinding process after flipping can stop at the stop layer, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also conceive of using the dielectric filled in the first trench (i.e., the bit line isolation trench) and / or the second trench (i.e., the word line trench) as a stop layer or providing a stop layer at the bottom of the first trench (i.e., the bit line isolation trench) and / or the second trench (i.e., the word line trench).

[0197] Those skilled in the art will recognize that although the DRAM array structure is manufactured using a double-sided processing method in which the first layer of word lines (e.g., first conductor lines 1607) are manufactured on one side and the second layer of word lines (e.g., second conductor lines 1613) are manufactured on the other side in the embodiment described above, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision manufacturing both layers of word lines on one side before or after flipping.

[0198] In addition, those skilled in the art will recognize that although a cylinder capacitor is used as a storage capacitor in the embodiments described above, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also conceive of using capacitors of other structures as storage capacitors, such as a pillar capacitor.

[0199] All of the above variations are intended to fall within the scope of this disclosure.

[0200] According to the method for manufacturing a DRAM array structure disclosed in the present invention, a vertical DRAM cell structure with a double-layer word line is manufactured through double-sided processing using a double-sided layout method, and adjacent DRAM cell structures share the word line in the column direction, thereby eliminating the inherent spacing area between the word lines in the traditional DRAM array structure based on ring-gate transistors, and increasing the size of the storage capacitor of each DRAM cell structure in the word line direction, thereby achieving further size miniaturization.

[0201] Figures 34A and 34B are schematic top views of a DRAM array structure according to an embodiment of the present disclosure. In Figures 34A and 34B , the DRAM array structure is appropriately expanded for clarity, and the first bit line 1616a, the second bit line 1616b, and the second conductor line 1613 (and the second gate dielectric 1612) are appropriately extended.

[0202] For the sake of brevity, the same components in Figures 31, 34A, and 34B as those in Figures 9 to 23B are represented by the same reference numerals, and the corresponding descriptions are omitted.

[0203] As shown in Figure 31, the DRAM structure manufactured by the double-sided processing process described above with reference to Figures 9 to 23B is vertically arranged in sequence with the first storage capacitor 1610a of the DRAM cell structure of odd columns (or even columns), the first bit line 1616a of the DRAM cell structure of even columns (or odd columns), the selection transistor of the DRAM cell structure, the second bit line 1616b of the DRAM cell structure of odd columns (or even columns), and the second storage capacitor 1610b of the DRAM cell structure of even columns (or odd columns).

[0204] As shown in Figure 31, according to an embodiment of the present disclosure, the first bit line 1616a is staggered with the first storage capacitor 1610a in the vertical direction, and the second bit line 1616b is staggered with the second storage capacitor 1610b in the vertical direction, so that the bit line does not occupy the space of the storage capacitor in the row direction.

[0205] According to an embodiment of the present disclosure, as shown in Figure 31, since the first bit line 1616a (for example, the bit lines BLn-1 and BLn+1 shown in Figures 34A and 34B) can be set above the first storage capacitor 1610a, and the second bit line 1616b (for example, the bit lines BLn-2, ​​BLn and BLn+2 shown in Figures 34A and 34B) can be set below the second storage capacitor 1610b, as shown in Figures 34A and 34B, the storage capacitors of the DRAM cell structures in adjacent columns will not occupy each other's space, so that the size of the storage capacitors (the first storage capacitor and the second storage capacitor) can be expanded by up to twice in the row direction, thereby further realizing the size miniaturization of the DRAM array structure.

[0206] As shown in Figures 34A and 34B, according to an embodiment of the present disclosure, the first storage capacitor 1610a can form a first storage capacitor array, and the second storage capacitor 1610b can form a second storage capacitor array. In addition, as shown in Figure 31, according to an embodiment of the present disclosure, the first storage capacitor array and the second storage capacitor array are respectively located on both sides of the DRAM array structure in the vertical direction.

[0207] As shown in Figures 34A and 34B, according to an embodiment of the present disclosure, the arrangement direction of the first storage capacitor array and the second storage capacitor array can be the same as the arrangement direction of the multiple DRAM cell structures in the DRAM array structure. That is, the row direction and column direction of the first storage capacitor array and the second storage capacitor array are respectively the same as the word line direction and bit line direction of the DRAM array structure. Therefore, in Figures 34A and 34B, the center of each storage capacitor of the first storage capacitor array and the second storage capacitor array substantially coincides with the center of each DRAM cell structure in the DRAM array structure. In this case, the first storage capacitor 1610a and the second storage capacitor 1610b can have a rectangular shape in the horizontal direction (as shown in Figure 34A) or an elliptical shape (as shown in Figure 34B), but the present disclosure is not limited to this. According to the teachings of the present disclosure, those skilled in the art can envision that the first storage capacitor 1610a and the second storage capacitor 1610b adopt any shape that is axisymmetric in the horizontal direction, such as a trapezoid.

[0208] In addition, according to other embodiments of the present disclosure, the first storage capacitor 1610a and the second storage capacitor 1610b may also have a shape that is centrally symmetrical in the horizontal direction. Figures 35A and 35B respectively show schematic top views of a DRAM array structure according to another embodiment of the present disclosure, wherein the first storage capacitor 1610a and the second storage capacitor 1610b have a square shape in the horizontal direction. In addition, Figures 36A and 36B respectively show schematic top views of a DRAM array structure according to another embodiment of the present disclosure, wherein the first storage capacitor 1610a and the second storage capacitor 1610b have a circular shape in the horizontal direction.

[0209] For the sake of brevity, the same components in Figures 35A to 36B as those in Figures 34A and 34B are represented by the same reference numerals, and the corresponding descriptions are omitted.

[0210] As shown in FIG35A , according to an embodiment of the present disclosure, in order to ensure that the first storage capacitor 1610a and the second storage capacitor 1610b have a centrally symmetrical shape in the horizontal direction, the arrangement direction of the first storage capacitor array (not shown) formed by the first storage capacitor 1610a and the second storage capacitor array formed by the second storage capacitor 1610b can be different from the arrangement direction of the multiple DRAM cell structures in the DRAM array structure. In other words, the row and column directions of the first storage capacitor array and the second storage capacitor array are rotated at a specific angle, such as 45 degrees, relative to the word line direction and bit line direction of the DRAM array structure. Therefore, in FIG35A , the centers of the storage capacitors in the first storage capacitor array and the second storage capacitor array are offset from the centers of the DRAM cell structures in the DRAM array structure. In this case, the first storage capacitor 1610a and the second storage capacitor 1610b can have a square shape (as shown in FIG35A and FIG35B ) or a circular shape (as shown in FIG36A and FIG36B ) in the horizontal direction, but the present disclosure is not limited to this. According to the teachings of this disclosure, those skilled in the art can envision that the first storage capacitor 1610a and the second storage capacitor 1610b may adopt any shape that is centrally symmetrical in the horizontal direction, such as a hexagon. In this case, the arrangement direction of the first storage capacitor array and the second storage capacitor array may form a 60-degree angle with the arrangement direction of the plurality of DRAM cell structures in the DRAM array structure.

[0211] Similar to the DRAM array structure shown in Figures 34A and 34B, in the DRAM array structure shown in Figures 35A to 36B, the storage capacitors of adjacent columns of DRAM cell structures will not occupy each other's space, so that the size of the storage capacitors (first storage capacitors and second storage capacitors) can be expanded by up to twice, thereby further realizing the size miniaturization of the DRAM array structure.

[0212] In the DRAM array structure shown in Figures 35A to 36B , because the arrangement direction of the first storage capacitor array (not shown) and the second storage capacitor array forms a specific angle (45 degrees) with the arrangement direction of the multiple DRAM cell structures in the DRAM array structure, the center of the active area of ​​each DRAM cell structure and the center of the storage capacitor (first storage capacitor 1610a and second storage capacitor 1610b) are horizontally offset. Therefore, as shown in Figures 35B and 36B , a lateral contact portion 1617 is provided above the capacitor contact portion 1608 of the DRAM cell structure that contacts the storage capacitor to achieve connection between the selection transistor of each DRAM cell structure and the storage capacitor.

[0213] In particular, to clearly illustrate lateral contact portion 1617, FIG35B is a schematic cross-sectional view obtained by removing a portion of second storage capacitor 1610b (i.e., the storage capacitor of a column of DRAM cell structures connected to bit line BLn-1) from FIG35A, and FIG36B is a schematic cross-sectional view obtained by removing a portion of second storage capacitor 1610b (i.e., the storage capacitor of a column of DRAM cell structures connected to bit line BLn-1) from FIG36A. Furthermore, FIG37 is a schematic cross-sectional view of a DRAM array structure taken along line DD' in FIG35A and FIG36A according to an embodiment of the present disclosure.

[0214] As shown in Figures 35B, 36B and 37, by using the lateral contact portion 1617, even if the arrangement direction of the first storage capacitor array and / or the second storage capacitor array is different from the DRAM cell structure of the DRAM array structure, resulting in the center of the active area of ​​each DRAM cell structure and the center of the storage capacitor being offset in the horizontal direction, the storage capacitor can still be connected to the selection transistor of the corresponding DRAM cell structure.

[0215] According to the DRAM array structure disclosed in the present invention, a DRAM array structure is constructed by using a double-sided layout method using a DRAM cell structure with a double-layer word line, and adjacent DRAM cell structures share word lines in the column direction, thereby eliminating the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors and increasing the size of the storage capacitor of each DRAM cell structure, thereby achieving further size miniaturization.

[0216] Those skilled in the art will recognize that although in the embodiments described above, the first storage capacitor array and the second storage capacitor array have the same arrangement, that is, have the same shape and the same arrangement direction in the horizontal direction, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision that the first storage capacitor array and the second storage capacitor array have different arrangements, for example, the first storage capacitor array may have the same arrangement direction as the DRAM cell structure of the DRAM array structure, while the second storage capacitor array may have a different arrangement direction from the DRAM cell structure of the DRAM array structure, or the first storage capacitor may have a different shape in the horizontal direction from the second storage capacitor.

[0217] In addition, those skilled in the art will recognize that although a cylinder capacitor is used as a storage capacitor in the embodiments described above, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also conceive of using capacitors of other structures as storage capacitors, such as a pillar capacitor.

[0218] All of the above variations are intended to fall within the scope of this disclosure.

[0219] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0220] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A vertical dynamic random access memory (DRAM) array structure with double-layer word lines, wherein, The DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: A substrate; A first storage capacitor of the DRAM cell structures in an odd-numbered column or an even-numbered column, disposed on the substrate; A first bit line of the DRAM cell structures in an even-numbered column or an odd-numbered column, disposed above the first storage capacitor; A select transistor of each DRAM cell structure, disposed between the first storage capacitor and the first bit line, wherein the select transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; A second bit line of the DRAM cell structures in an odd-numbered column or an even-numbered column, disposed on the select transistor; and A second storage capacitor of the DRAM cell structures in an even-numbered column or an odd-numbered column, disposed above the second bit line.

2. A vertical dynamic random access memory (DRAM) array structure with double-layer word lines, wherein, The DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: A substrate; A storage capacitor of each DRAM cell structure, disposed on the substrate; A select transistor of each DRAM cell structure, disposed on the storage capacitor, wherein the select transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and A bit line, disposed on the select transistor.

3. A vertical dynamic random access memory (DRAM) array structure with double-layer word lines, wherein, The DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: A substrate; A bit line, disposed on the substrate; A select transistor of each DRAM cell structure, disposed on the bit line, wherein the select transistors of the DRAM cell structures in adjacent rows share a first layer of word lines and a second layer of word lines; and A storage capacitor of each DRAM cell structure, disposed on the select transistor.

4. The DRAM array structure according to any one of claims 1 to 3, wherein, The select transistor includes: An active region extending vertically, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the storage capacitor; and First to fourth gate structures, wherein the first gate structure and the second gate structure are disposed on a first side of the channel region from bottom to top in the vertical direction, and the third gate structure and the fourth gate structure are disposed on a second side of the channel region opposite to the first side from bottom to top in the vertical direction, wherein one of the first layer of word lines and the second layer of word lines forms the first gate structure and the third gate structure of the select transistor, and the other of the first layer of word lines and the second layer of word lines forms the second gate structure and the fourth gate structure of the select transistor.

5. The DRAM array structure according to claim 4, wherein, The first layer of word lines is isolated from the active region by a first gate dielectric, and the second layer of word lines is isolated from the active region by a second gate dielectric.

6. The DRAM array structure according to claim 5, wherein The first gate dielectric and the second gate dielectric have the same or different materials or thicknesses from each other.

7. The DRAM array structure according to claim 5, wherein, The first layer of word lines and the second layer of word lines are separated from each other by the first gate dielectric and the second gate dielectric.

8. The DRAM array structure according to claim 4 further includes: Contact portions formed at both ends of the active region of each DRAM cell structure to contact the storage capacitor and the bit line.

9. The DRAM array structure according to claim 4, wherein the active region includes bulk semiconductor material, compound semiconductor material, oxide semiconductor material, and / or two-dimensional semiconductor material.

10. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, and includes: Providing a substrate; Forming a first storage capacitor of DRAM cell structures in odd or even columns above the substrate; Forming a first bit line of DRAM cell structures in even or odd columns above the first storage capacitor; Forming a select transistor for each DRAM cell structure, wherein the select transistors of DRAM cell structures in adjacent rows share a first layer of word line and a second layer of word line; Forming a second bit line of DRAM cell structures in odd or even columns above the select transistor; And Forming a second storage capacitor of DRAM cell structures in even or odd columns above the second bit line.

11. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, and includes: Providing a substrate; Forming a storage capacitor for each DRAM cell structure above the substrate; Forming a select transistor for each DRAM cell structure above the storage capacitor, wherein the select transistors of DRAM cell structures in adjacent rows share a first layer of word line and a second layer of word line; And Forming a bit line above the select transistor.

12. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, and includes: Providing a substrate; Forming a bit line for each DRAM cell structure above the substrate; Forming a select transistor for each DRAM cell structure above the storage capacitor, wherein the select transistors of DRAM cell structures in adjacent rows share a first layer of word line and a second layer of word line; And Forming a storage capacitor above the select transistor.

13. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, and includes: Providing a stop layer and an active layer on a base layer; Forming a plurality of bit line isolation grooves extending in the column direction in the active layer to define the size of the active region of each DRAM cell structure in the row direction; Forming a plurality of word line grooves extending in the row direction in the active layer to define the size of the active region of each DRAM cell structure in the column direction, wherein a first layer of word line and a second layer of word line are formed in the plurality of word line grooves; A first storage capacitor is formed at one end of the active region of the DRAM cell structure in an odd-numbered or even-numbered column. A first bit line is formed at one end of the active region of the DRAM cell structure in an even-numbered or odd-numbered column. Flip the DRAM array structure and remove the base layer and the stop layer. A second bit line is formed at the other end of the active region of the DRAM cell structure in an odd-numbered or even-numbered column; and A second storage capacitor is formed at the other end of the active region of the DRAM cell structure in an even-numbered or odd-numbered column.

14. The method according to claim 13, further comprising: Forming a first gate dielectric and the first layer of word lines in the plurality of word line grooves; And After flipping the DRAM array structure and removing the base layer and the stop layer, forming a second gate dielectric and the second layer of word lines in the plurality of word line grooves.

15. The method according to claim 13, further comprising: Before or after flipping the DRAM array structure, forming a first gate dielectric and the first layer of word lines and a second gate dielectric and the second layer of word lines in the plurality of word line grooves.

16. The method according to claim 13, further comprising: Filling the bit line isolation grooves with a first isolation medium; Filling one end of the word line grooves with a second isolation medium to isolate the first layer of word lines from one of the storage capacitors and the bit lines; And Filling the other end of the word line grooves with a third isolation medium to isolate the second layer of word lines from the other of the storage capacitors and the bit lines.

17. The method according to claim 16, wherein The first isolation medium, the second isolation medium, and the third isolation medium include the same or different materials from each other.

18. The method according to claim 14 or 15, wherein The first gate dielectric and the second gate dielectric have the same or different materials or thicknesses from each other.

19. The method according to claim 14 or 15, wherein, The first layer of word lines and the second layer of word lines are separated from each other by the first gate dielectric and the second gate dielectric.

20. The method according to claim 13, further comprising: Forming capacitor contacts at one end of the active region of each DRAM cell structure to contact the storage capacitor, and Forming bit line contacts at the other end of the active region of each DRAM cell structure to contact the bit lines.

21. The method according to claim 20, further comprising: Making the length of the capacitor contacts in the vertical direction greater than the length of the bit line contacts in the vertical direction, such that the first bit line is staggered from the first storage capacitor in the vertical direction, and the second bit line is staggered from the second storage capacitor in the vertical direction.

22. The method according to claim 13, wherein The DRAM array structure includes: A plurality of DRAM cell structures arranged in M rows and N columns, where M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: A storage capacitor including a first electrode and a second electrode, wherein the second electrode is connected to the source line; and A select transistor including: A vertically-extended active region, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a first electrode of the storage capacitor; and First to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side; N bit lines, respectively connected to the other of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; M + 1 first word lines, respectively connected to the second gate structure and the third gate structure of M rows of DRAM cell structures; and M + 1 second word lines, respectively connected to the first gate structure and the fourth gate structure of M rows of DRAM cell structures, wherein one of the first layer word line and the second layer word line forms the first gate structure and the third gate structure of the M rows of DRAM cell structures, and the other of the first layer word line and the second layer word line forms the second gate structure and the fourth gate structure of the M rows of DRAM cell structures.

23. A vertical dynamic random access memory (DRAM) array structure with double-layer word lines, wherein, The DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: A substrate; A first storage capacitor of the DRAM cell structures in odd or even columns, disposed on the substrate; A first bit line of the DRAM cell structures in even or odd columns, disposed above the first storage capacitor; A select transistor of each DRAM cell structure, disposed on the first storage capacitor and the first bit line, wherein the select transistors of the DRAM cell structures in adjacent rows share the first layer word line and the second layer word line; A second bit line of the DRAM cell structures in odd or even columns, disposed on the select transistor; and A second storage capacitor of the DRAM cell structures in even or odd columns, disposed above the second bit line, wherein the first storage capacitor and the second storage capacitor are respectively arranged into a first storage capacitor array and a second storage capacitor array.

24. The DRAM array structure according to claim 23, wherein, The arrangement directions of the first storage capacitor array and the second storage capacitor array are the same as the arrangement direction of the plurality of DRAM cell structures.

25. The DRAM array structure according to claim 24, wherein, The first storage capacitor and the second storage capacitor have a rectangular and / or elliptical shape in the horizontal direction, and wherein the long side of the rectangle and / or the major axis of the ellipse extend along the row direction of the DRAM array structure.

26. The DRAM array structure according to claim 23, wherein, The arrangement directions of the first storage capacitor array and the second storage capacitor array are different from the arrangement direction of the plurality of DRAM cell structures.

27. The DRAM array structure according to claim 26, wherein, The arrangement directions of the first storage capacitor array and the second storage capacitor array form a 45-degree angle with the arrangement direction of the plurality of DRAM cell structures, and wherein the first storage capacitor and the second storage capacitor have a square and / or circular shape in the horizontal direction.

28. The DRAM array structure according to claim 26, wherein, Each of the plurality of DRAM cell structures includes a lateral contact portion for connecting a select transistor to a corresponding storage capacitor.

29. The DRAM array structure according to claim 23, wherein The select transistor includes: a vertically extending active region including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the storage capacitor; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side, wherein one of the first layer word line and the second layer word line forms the first gate structure and the third gate structure of the M row DRAM cell structures, and the other of the first layer word line and the second layer word line forms the second gate structure and the fourth gate structure of the M row DRAM cell structures.

30. The DRAM array structure according to claim 29, wherein, the first layer word line is isolated from the active region by a first gate dielectric, and the second layer word line is isolated from the active region by a second gate dielectric.

31. The DRAM array structure according to claim 30, wherein the first gate dielectric and the second gate dielectric have the same or different materials or thicknesses from each other.

32. The DRAM array structure according to claim 30, wherein, the first layer word line and the second layer word line are separated from each other by the first gate dielectric and the second gate dielectric.

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