Method for manufacturing dynamic random access memory array structure

Abstract

The present disclosure provides a method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines. The DRAM array structure comprises a plurality of DRAM cell structures arranged in an array. The method for manufacturing the DRAM array structure according to the present disclosure comprises: providing a stop layer and an active layer on a base layer; forming in the active layer a plurality of bit line isolation grooves extending along a column direction to limit the size of an active region of each DRAM cell structure in a row direction; forming in the active layer a plurality of word line grooves extending in the row direction to limit the size of the active region of each DRAM cell structure in the column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a storage capacitor or a bit line at one end of the active region of each DRAM cell structure; turning over the DRAM array structure and removing the base layer and the stop layer; and forming a bit line or a storage capacitor at the other end of the active region of each DRAM cell structure.

Description

Method for manufacturing a dynamic random access memory array structure Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a method for fabricating a dynamic random access memory (DRAM) array structure. Background Art

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a transistor for enabling the device and a capacitor for storing charge (a 1T1C structure). In a DRAM cell structure that uses a conventional planar horizontal transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the enabling transistor, the transistor's source, gate, and drain are arranged horizontally parallel to the substrate surface. Because the transistor's source, gate, and drain each occupy independent areas in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by gate length and contact size, making it impossible to meet the continued scaling requirements of DRAM devices. This, in turn, limits further increases in the integration density and bandwidth of DRAM devices.

[0004] Therefore, a vertical DRAM cell structure has been proposed in recent years, in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the miniaturization of the DRAM array structure.

[0005] However, in existing DRAM cell circuit structures based on vertical channel transistors (VCTs), the metal gate wraps the entire channel, requiring additional area for isolation between word lines formed by the metal gate connection. This limits the scaling of VCT transistors used as gate transistors in DRAM cell circuits. Furthermore, the resistance of metal deposited by atomic layer deposition (ALD) increases significantly as its thickness decreases. This, combined with the additional area required by the metal and gate oxide thickness compared to planar structures, limits further reductions in word line spacing.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel method for manufacturing a dynamic random access memory array structure.

[0008] According to one aspect of the present disclosure, a method for manufacturing a vertical dynamic random access memory (DRAM) array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a stop layer and an active layer on a base layer; forming a plurality of bit line isolation grooves extending along the column direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in the row direction; forming a plurality of word line grooves extending along the row direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in the column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a storage capacitor at one end of the active area of ​​each DRAM cell structure; flipping the DRAM array structure and removing the base layer and the stop layer; and forming a bit line at the other end of the active area of ​​each DRAM cell structure.

[0009] According to another aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a stop layer and an active layer on a base layer; forming a plurality of bit line isolation grooves extending along a column direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in a row direction; forming a plurality of word line grooves extending along a row direction in the active layer to limit the size of the active area of ​​each DRAM cell structure in a column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a bit line at one end of the active area of ​​each DRAM cell structure; flipping the DRAM array structure and removing the base layer and the stop layer; and forming a storage capacitor at the other end of the active area of ​​each DRAM cell structure.

[0010] According to another aspect of the present disclosure, a method for manufacturing a vertical dynamic random access memory (DRAM) array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a substrate; forming a plurality of bit line isolation grooves extending along a column direction and a plurality of word line grooves extending along a row direction in the substrate to form active area pillars of the plurality of DRAM cell structures, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a storage capacitor at one end of the active area pillar of each DRAM cell structure; flipping the DRAM array structure and removing the substrate; and forming a bit line at the other end of the active area pillar of each DRAM cell structure.

[0011] According to another aspect of the present disclosure, a method for manufacturing a vertical DRAM array structure with a double-layer word line is provided, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a substrate; forming a plurality of bit line isolation grooves extending along a column direction and a plurality of word line grooves extending along a row direction in the substrate to form active area pillars of the plurality of DRAM cell structures, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a bit line at one end of the active area pillar of each DRAM cell structure; flipping the DRAM array structure and removing the substrate; and forming a storage capacitor at the other end of the active area pillar of each DRAM cell structure.

[0012] The method for manufacturing a DRAM array structure according to the present disclosure can reduce gate length fluctuation and alignment deviation when forming multi-layer word lines by using a double-sided processing process, and avoid using a complex bottom bit line formation process, thereby reducing the parasitic capacitance of the bit line.

[0013] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0015] FIG. 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0016] FIG. 2 is a perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0017] FIG. 3 is a top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0018] FIG. 4 is a vertical cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0019] FIG. 5 is a schematic diagram illustrating an operating method of a DRAM cell structure according to an embodiment of the present disclosure.

[0020] FIG. 6 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to an embodiment of the present disclosure.

[0021] 7A and 7B are top views of a DRAM array structure respectively illustrating a DRAM cell structure including a VCT transistor according to the related art and a transistor having four gate structures sharing a word line according to an embodiment of the present disclosure.

[0022] FIG. 8 is a schematic diagram illustrating an operating method of a DRAM array structure according to an embodiment of the present disclosure.

[0023] 9A to 9O are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure.

[0024] 10A to 10F are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0025] 11A to 11P are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0026] 12A to 12F are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0028] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0029] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0030] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0031] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0033] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, the same reference numerals represent the same elements. Furthermore, in the accompanying drawings, for clarity of illustration, the various components are not necessarily drawn to ratio, and the ratios and sizes of the various components may be exaggerated.

[0034] FIG1 shows an equivalent circuit diagram of a dynamic random access memory (DRAM) cell structure 100 according to an embodiment of the present disclosure. FIG2 also shows a schematic perspective view of the DRAM cell structure 100 according to an embodiment of the present disclosure, FIG3 shows a schematic top view of the DRAM cell structure 100 according to an embodiment of the present disclosure, and FIG4 shows a schematic vertical cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure. It should be noted that FIG4 is a schematic vertical cross-sectional view taken along line AA′ in FIG3 .

[0035] As shown in FIG1 , a DRAM cell structure 100 according to an embodiment of the present disclosure may include a storage capacitor C and a gate transistor T (as shown in a dotted box). As shown in FIG1 to FIG4 , according to an embodiment of the present disclosure, the gate transistor T may include a vertically extending active region 101, which includes a first source / drain region 102, a channel region 103, and a second source / drain region 104 arranged in sequence from bottom to top along the vertical direction, wherein the first source / drain region 102 may be connected to a bit line BL, and the second source / drain region may be connected to one electrode (lower electrode) CP1 of the storage capacitor C. According to an embodiment of the present disclosure, the other electrode (upper electrode) CP2 of the storage capacitor C may be connected to a source line SL.

[0036] Although FIG1 shows that the bit line BL, the gate transistor T, the storage capacitor C, and the source line SL are arranged in a vertical direction from bottom to top, the configuration of the DRAM cell structure 100 is not limited thereto. According to an alternative embodiment of the present disclosure, the source line SL, the storage capacitor C, the gate transistor T, and the bit line may also be arranged in a vertical direction from bottom to top. In this embodiment, the second source / drain region 102 may be connected to the bit line BL, the first source / drain region 102 may be connected to the upper electrode CP2 of the storage capacitor C, and the lower electrode CP1 of the storage capacitor C may be connected to the source line SL.

[0037] As shown in Figures 1 to 4, according to an embodiment of the present disclosure, the selection transistor T may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107 and a fourth gate structure G4 108, wherein the first gate structure G1 105 and the second gate structure G2 106 may be arranged from bottom to top along a vertical direction on a first side of the channel region 103, and the third gate structure G3 107 and the fourth gate structure G4 108 may be arranged from bottom to top along a vertical direction on a second side of the channel region 103 opposite to the first side.

[0038] As shown in Figure 4, according to an embodiment of the present disclosure, the selection transistor T can be a junction-less device, that is, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with the same type. For example, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with a first doping type. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. However, the present disclosure is not limited to this. According to an alternative embodiment of the present disclosure, the first doping type can be P-type doping, and the second doping type can be N-type doping. According to an embodiment of the present disclosure, the doping concentration of the first source / drain region 102 and the second source / drain region 104 can be higher than the doping concentration of the channel region 103.

[0039] In addition, according to an embodiment of the present disclosure, the gate transistor T may also be a junction type device, that is, different types of doping may be performed on the first source / drain region 102, the channel region 103, and the second source / drain region 104. For example, the first source / drain region 102 and the second source / drain region 104 may be doped with a first doping type, and the channel region 103 may be doped with a second doping type.

[0040] As shown in FIG1 , according to an embodiment of the present disclosure, the first source / drain region 102 can be connected to a bit line BL, and the second source / drain region 104 can be connected to one electrode or lower electrode CP1 of the storage capacitor C. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is in a write period, the bit line BL can be connected to a voltage representing data 0 (e.g., ground voltage VSS) or a voltage representing data 1 (e.g., power supply voltage VDD) to store the voltage representing the corresponding data in the storage capacitor C. When the DRAM cell structure 100 is not in a write period, the bit line BL can be connected to an equalization voltage VBLQ. According to an embodiment of the present disclosure, the equalization voltage VBLQ can be, for example, a voltage at the intersection of a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 0 (e.g., ground voltage VSS) and a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 1 (e.g., power supply voltage VDD) (e.g., typically approximately (VDD+VSS) / 2).

[0041] Furthermore, as shown in FIG1 , according to an embodiment of the present disclosure, the other electrode or upper electrode CP2 of the storage capacitor C can be connected to a source line SL. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, the source line SL can be connected to a fixed voltage VFF. For example, according to an embodiment of the present disclosure, the fixed voltage VFF can be used as a reference voltage, which is typically half of the power supply voltage VDD, i.e., VFF = 1 / 2 VDD.

[0042] For clarity, the storage capacitor C, the bit line BL, and the source line SL are not shown in FIG. 2 to FIG. 4 .

[0043] Furthermore, as described above, with reference to Figures 1 to 4 , according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a first gate structure G1 105, a second gate structure G2 106, a third gate structure G3 107, and a fourth gate structure G4 108. According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 are vertically arranged from bottom to top on a first side of the channel region 103 (e.g., the left side as shown in Figures 2 and 4 ), and the third gate structure G3 107 and the fourth gate structure G4 108 are vertically arranged from bottom to top on a second side of the channel region 103 opposite the first side (e.g., the right side as shown in Figures 2 and 4 ). Herein, the first gate structure G1 105 and the third gate structure G3 107 may also be referred to as a lower gate structure, and the second gate structure G2 106 and the fourth gate structure G4 108 may also be referred to as an upper gate structure.

[0044] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed of the same conductive material. According to an embodiment of the present disclosure, examples of conductive materials used to form the first to fourth gate structures G1 105 to G4 108 may include: metals or alloys, such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the above metals; metal nitrides, such as titanium nitride (TiN); or polysilicon. In addition, according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may include a high work function material, a low work function material, or a combination thereof. The low work function material may have a low work function of approximately 4.5 eV or less, and the high work function material may have a high work function of approximately 4.5 eV or more. For example, the low work function material may include N-type doped polysilicon, and the high work function material may include tungsten, titanium nitride, or a combination thereof. According to an alternative embodiment of the present invention, the first to fourth gate structures G1 105 to G4 108 may have a dual work function structure in which a low work function material and a high work function material are combined.

[0045] According to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 can be formed of different conductive materials. For example, the lower gate structure, namely the first gate structure G1 105 and the third gate structure G3 107, can be formed of a metal-based material such as titanium nitride or tungsten, while the upper gate structure, namely the second gate structure G2 106 and the fourth gate structure G4 108, can be formed of polysilicon. According to an embodiment of the present disclosure, by forming the first to fourth gate structures G1 105 to G4 108 with different conductive materials, the work function can be adjusted, thereby adjusting the threshold voltage of the gate transistor T.

[0046] In addition, as more clearly shown in Figures 3 and 4, according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a gate dielectric 109 disposed between the first gate structure G1105 to the fourth gate structure G4 108 and the channel region 103. According to an embodiment of the present disclosure, the gate dielectric 109 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide may have a dielectric constant of approximately 3.9, and the gate dielectric 109 may include a high-k material having a dielectric constant of approximately 4 or greater. As the gate dielectric 109, the high-k material may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to an alternative embodiment of the present invention, the gate dielectric 109 may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0047] Furthermore, as shown in Figures 2 to 4 , according to embodiments of the present disclosure, the first gate structure G1 105 to the fourth gate structure G4 108 may be separated from each other by an isolation dielectric 110. As shown in Figure 3 , according to embodiments of the present disclosure, the two upper gate structures, namely, the second gate structure G2 106 and the fourth gate structure G4 108, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110. Similarly, although not shown, according to embodiments of the present disclosure, the two lower gate structures, namely, the first gate structure 105 and the third gate structure 107, may be separated from each other in the horizontal direction using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as the isolation dielectric 110.

[0048] 4 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 disposed on the first side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. Furthermore, the third gate structure G3 107 and the fourth gate structure G4 108 disposed on the second side of the channel region 103 may be vertically separated from each other using, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof as an isolation dielectric 110. According to an embodiment of the present disclosure, the isolation dielectric 110 may be formed of the same material as or a different material from the gate dielectric 109.

[0049] According to an embodiment of the present disclosure, the first gate structure G1 105, the second gate structure G2 106, the third gate structure G3 107, and the fourth gate structure G4 108 may have the same size and structure. In addition, as shown in Figures 2 and 4, according to an embodiment of the present disclosure, the first gate structure G1 105 and the third gate structure G3 107 may be aligned with each other in the vertical direction, and the second gate structure G2 106 and the fourth gate structure G4 108 may be aligned with each other in the vertical direction.

[0050] As shown in FIG4 , according to an embodiment of the present disclosure, the vertical distance d1 between the upper end of the first gate structure G1 105 and the lower end of the second gate structure G2 106 can be equal to the vertical distance d2 between the upper end of the third gate structure G3 107 and the lower end of the fourth gate structure G4 108, i.e., d1 = d2. According to an embodiment of the present disclosure, the distances d1 and d2 can be greater than the horizontal thickness d3 of the gate dielectric 109 between the first gate structure G1 105 to the fourth gate structure G4 108 and the channel region 103, and preferably greater than twice the horizontal thickness d3 of the gate dielectric 109 between the first gate structure G1 105 to the fourth gate structure G4 108 and the channel region 103, to reduce the impact of parasitic capacitance formed between the first gate structure G1 105 and the second gate structure G2 106, and between the third gate structure G3 107 and the fourth gate structure G4 108.

[0051] In addition, according to an embodiment of the present disclosure, although not shown, a work function adjustment layer may be formed between the gate dielectric 109 and the first to fourth gate structures G1 105 to G4 108 to further adjust the threshold voltage of the gate transistor T.

[0052] Furthermore, according to an embodiment of the present disclosure, although not shown, a doping concentration adjustment layer may be formed at the surface of the channel region 103 overlapping the first to fourth gate structures G1 105 to G4 108 to reduce fluctuations in the threshold voltage of the gate transistor T.

[0053] As shown in FIG. 3 , according to an embodiment of the present disclosure, the first to fourth gate structures G1 105 to G4 108 may be formed to have a “[”-shaped cross-section in a horizontal direction to obtain a larger control area between the gate structure and the channel region 103 .

[0054] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, the gate transistor T can be equivalent to two dual-gate transistors connected in series, wherein the lower dual-gate transistor (hereinafter referred to as the “lower dual-gate transistor”) uses the first gate structure G1 105 and the third gate structure G3 107 as gates, and the upper dual-gate transistor (hereinafter referred to as the “upper dual-gate transistor”) uses the second gate structure G2 106 and the fourth gate structure G4 108 as gates. Therefore, according to an embodiment of the present disclosure, the gate transistor T is turned on only when both the upper dual-gate transistor and the lower dual-gate transistor are turned on. In addition, according to an embodiment of the present disclosure, the gate transistor T is turned off when at least one of the upper dual-gate transistor and the lower dual-gate transistor is turned off.

[0055] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, by controlling the voltage applied to the first gate structure G1 105 to the fourth gate structure G4 108, the conduction and shutoff of the selection transistor T can be controlled, thereby realizing the read, write and refresh operations of the DRAM cell structure, which will be described in more detail below in conjunction with FIG5 .

[0056] FIG. 5 is a schematic diagram illustrating an operating method of the DRAM cell structure 100 according to an embodiment of the present disclosure.

[0057] In a traditional 1T1C DRAM cell structure, a single transistor is used as a gate transistor to control the formation of a conduction path between the bit line and the storage capacitor. According to an embodiment of the present disclosure, the gate transistor T can be equivalent to two NMOS depletion-type dual-gate transistors (i.e., a lower dual-gate transistor and an upper dual-gate transistor) connected in series to form a logic AND unit. In other words, only when the upper and lower dual-gate transistors are turned on at the same time, a conduction path is formed between the storage capacitor C and the bit line BL, thereby performing read, write and refresh operations on the DRAM cell structure. According to an embodiment of the present disclosure, when one of the upper and lower dual-gate transistors of the gate transistor T is turned on, a conduction path is not formed. In other words, when at least one of the upper and lower dual-gate transistors of the gate transistor T is turned off, a conduction path is not formed. In addition, according to an embodiment of the present disclosure, when the upper and lower dual-gate transistors of the gate transistor T are turned off at the same time, leakage is minimized, and data is continuously retained in the storage capacitor C in the form of charge.

[0058] As shown in FIG2 to FIG4, when the gate transistor T is a junction-less device, that is, the active region 101 is entirely formed of the first doping type semiconductor, when no voltage is applied to the first gate structure G1 105 to the fourth gate structure G4 108, the gate transistor T is in the on state.

[0059] As shown in FIG. 5 , according to an embodiment of the present disclosure, the gate transistor T may be turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107 .

[0060] Specifically, as shown in FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is not selected, low voltages VGL1 to VGL4 may be applied to the first to fourth gate structures G1 105 to G4 108 of the gate transistor T, respectively, to ensure that the gate transistor T is turned off. According to an embodiment of the present disclosure, each of the low voltages VGL1 to VGL4 may be a negative voltage, so that the portion of the channel region 103 between the first gate structure G1 105 and the third gate structure G3 107, as well as the portion of the channel region 103 between the second gate structure G2 106 and the fourth gate structure G4 108, are completely pinched off. This ensures that the gate transistor T is turned off while reducing or eliminating leakage current in the off state of the gate transistor T. According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 applied to the first to fourth gate structures G1 105 to G4 108 may be the same as or different from each other.

[0061] 5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T can be applied with high voltages VGH2 and VGH3, respectively, and the first gate structure G1 105 and the fourth gate structure G4 108 can remain connected to low voltages VGL1 and VGL4, respectively. According to an embodiment of the present disclosure, each of the high voltages VGH2 and VGH3 can be the ground voltage VSS or a positive voltage, so that the channel region 103 forms a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107. That is, as shown in FIG5 , according to an embodiment of the present disclosure, by applying high voltages VGH2 and VGH3, respectively, to the second gate structure G2 106 and the third gate structure G3 107 of the gate transistor T, an "S"-shaped conduction path can be formed near the surface of the channel region 103 overlapping with the second gate structure G2 106 and the third gate structure G3 107, as shown by arrows in FIG5 , thereby turning on the gate transistor T. According to an embodiment of the present disclosure, the high voltages VGH2 and VGH3, respectively applied to the second gate structure G2 106 and the third gate structure G3 107, can be the same as or different from each other.

[0062] According to an embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, the first gate structure G1 105 and the fourth gate structure G4 108 can be constantly connected to the low voltages VGL1 and VGL4, respectively. In addition, according to an embodiment of the present disclosure, the first gate structure G1 105 and the fourth gate structure G4 108 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the first gate structure G1 105 and the fourth gate structure G4 108, or the first gate structure G1 105 and the fourth gate structure G4 108 can be individually or collectively floated.

[0063] Although FIG5 describes an embodiment of the present disclosure by taking the example of turning on or off the selection transistor T by controlling the voltage applied to the second gate structure G2 106 and the third gate structure G3 107, those skilled in the art should recognize that the selection transistor T may also be turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, which can also achieve the technical effects of the present disclosure.

[0064] Specifically, according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, the first gate structure G1 105 and the fourth gate structure G4 108 of the gate transistor T can be applied with high voltages VGH1 and VGH4, respectively, and the second gate structure G2 106 and the third gate structure G3 107 can remain connected to low voltages VGL2 and VGL3, respectively. At this time, an "S"-shaped conduction path can be formed near the surface of the channel region 103 that overlaps with the first gate structure G1 105 and the fourth gate structure G4 108. This "S"-shaped conduction path is mirror-symmetrical to the conduction path indicated by the arrow in FIG. 5 .

[0065] According to an alternative embodiment of the present disclosure, when the gate transistor T is turned on or off by controlling the voltage applied to the first gate structure G1 105 and the fourth gate structure G4 108, the second gate structure G2 106 and the third gate structure G3 107 can be constantly connected to the low voltages VGL2 and VGL3, respectively. In addition, according to an embodiment of the present disclosure, the second gate structure G2 106 and the third gate structure G3 107 can also be connected individually or collectively to a bias voltage that prevents the channel region 103 from forming a conductive path near the surface overlapping with the second gate structure G2 106 and the third gate structure G3 107, or the second gate structure G2 106 and the third gate structure G3 107 can be individually or collectively floated.

[0066] According to an embodiment of the present disclosure, the low voltages VGL1 to VGL4 may be the same as each other and are collectively represented as VGL, and the high voltages VGH1 to VGH4 may be the same as each other and are collectively represented as VGH.

[0067] FIG. 6 shows an equivalent circuit diagram of a DRAM array structure 200 formed by the DRAM cell structure 100 shown in FIG. 1 according to an embodiment of the present disclosure. As shown in FIG. 6, according to an embodiment of the present disclosure, the DRAM array structure 200 may include a plurality of DRAM cell structures 100 shown in FIG. 1, where some reference numerals inside each DRAM cell structure 100 are omitted for clarity.

[0068] According to an embodiment of the present disclosure, the plurality of DRAM cell structures included in the DRAM array structure 200 may be arranged in an array of M rows and N columns, where M and N are natural numbers greater than 1. According to an embodiment of the present disclosure, the row selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 may be performed by M + 1 word lines, and the column selection operation may be performed by N bit lines.

[0069] It should be noted that for ease of description, FIG. 6 only shows the nth column DRAM cell structure of the DRAM array structure 200 that can be selected through the nth bit line BLn (n is a positive integer, and 0 < n ≤ N). As shown in FIG. 6, according to an embodiment of the present disclosure, the nth column DRAM cell structure of the DRAM array structure 200 may include M DRAM cell structures CELL1n to CELLMn, where each DRAM cell CELLmn includes a storage capacitor Cmn and a select transistor Tmn (m is a positive integer, and 0 < m ≤ M; n is a positive integer, and 0 < n ≤ N).

[0070] According to an embodiment of the present disclosure, a row selection operation of the M DRAM cell structures CELL1n through CELLMn of the nth column of DRAM cell structures can be performed via M+1 first word lines WL1m (m is an integer, and 0≤m≤M). As shown in FIG6 , according to an embodiment of the present disclosure, the M+1 first word lines WL10 through WL1M are respectively connected to the second gate structure G2 and the third gate structure G3 of the nth column of DRAM cell structures. Specifically, as shown in Figure 6, the first word line WL10 is connected to the second gate structure G2 of the selection transistor T1n of the DRAM cell structure CELL1n, the first word line WL11 is connected to the third gate structure G3 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the first word line WL12 is connected to the second gate structure G2 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The first word line WL1M is connected to the second gate structure G2 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0071] Alternatively, according to an embodiment of the present disclosure, the row selection operation of the M DRAM cell structures CELL1n to CELLMn in the nth column of the DRAM cell structure can also be performed through M+1 second word lines WL2m (m is an integer, and 0≤m≤M). As shown in Figure 6, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M are respectively connected to the first gate structure G1 and the fourth gate structure G4 of the nth column of the DRAM cell structure. Specifically, as shown in Figure 6, the second word line WL20 is connected to the first gate structure G1 of the selection transistor T1n of the DRAM cell structure CELL1n, the second word line WL21 is connected to the fourth gate structure G4 of the selection transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and the second word line WL22 is connected to the first gate structure G1 of the selection transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n, and so on. The second word line WL2M is connected to the first gate structure G1 of the selection transistor TMn of the DRAM cell structure CELLMn.

[0072] According to an embodiment of the present disclosure, N columns of DRAM cell structures can be connected together through M+1 first word lines WL10 to WL1M and M+1 second word lines WL20 to WL2M, thereby forming a DRAM array structure 200 including M rows and N columns, i.e., M×N DRAM cell structures.

[0073] As shown in FIG6 , according to an embodiment of the present disclosure, the M×N DRAM cell structures included in the DRAM array structure 200 can be arranged in mirror-symmetry along the column direction. That is, as shown in FIG6 , each DRAM cell structure is mirror-symmetric relative to its adjacent DRAM cell structure in the column direction. Taking the DRAM cell structure CELL2n shown in FIG6 as an example, its gate transistor T2n is mirror-symmetric with the gate transistor T1n of the adjacent DRAM cell structure CELL1n. That is, the third gate structure G3 of the gate transistor T2n is adjacent to the third gate structure G3 of the gate transistor T1n, and the fourth gate structure G4 of the gate transistor T2n is adjacent to the fourth gate structure G4 of the gate transistor T1n. In addition, the gate transistor T2n of the DRAM cell structure CELL2n is also mirror-symmetrical with the gate transistor T3n of the adjacent DRAM cell structure CELL3n, that is, the first gate structure G1 of the gate transistor T2n is adjacent to the first gate structure G1 of the gate transistor T3n, and the second gate structure G2 of the gate transistor T2n is adjacent to the second gate structure G2 of the gate transistor T3n.

[0074] According to an embodiment of the present disclosure, DRAM cell structures in adjacent rows are configured such that they share a first word line WL1m and a second word line WL2m in the column direction. For example, as shown in FIG6 , in the column direction, a DRAM cell structure CELL2n shares a first word line WL11 and a second word line WL21 with an adjacent DRAM cell structure CELL1n, and shares a first word line WL12 and a second word line WL22 with an adjacent DRAM cell structure CELL3n. In other words, as shown in FIG6 , according to an embodiment of the present disclosure, in the column direction, the first gate structure of the first side of the gate transistor of the DRAM cell structure shares a second word line with the first gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the second gate structure of the first side of the gate transistor of the DRAM cell structure shares a first word line with the second gate structure of the first side of the gate transistor of its adjacent DRAM cell structure, the third gate structure of the second side of the gate transistor of the DRAM cell structure shares a first word line with the third gate structure of the second side of the gate transistor of its adjacent DRAM cell structure, and the fourth gate structure of the second side of the gate transistor of the DRAM cell structure shares a second word line with the fourth gate structure of the second side of the gate transistor of its adjacent DRAM cell structure. In particular, according to an embodiment of the present disclosure, each DRAM cell structure of the DRAM cell array 200 is connected to two first word lines and two second word lines.

[0075] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share word lines (first word lines and second word lines), the isolation between word lines formed by the gate structures connecting adjacent DRAM cell structures can be omitted. Therefore, compared with the vertical channel transistor (VCT) of the prior art, the size miniaturization of the DRAM array structure can be further improved.

[0076] 7A and 7B respectively illustrate top views of a DRAM array structure including a VCT transistor according to the prior art and a DRAM cell structure of a transistor having four gate structures sharing a bit line according to an embodiment of the present disclosure.

[0077] As shown in FIG7A , in the column direction, word lines formed by connecting gate structures of VCT transistors according to the prior art require isolation via an isolation dielectric, which occupies additional area. In contrast, as shown in FIG7B , in the column direction, transistors having four gate structures according to an embodiment of the present disclosure share word lines with adjacent transistors having four gate structures, thereby eliminating isolation between word lines. Consequently, the DRAM array structure shown in FIG7B achieves further size reduction compared to the DRAM array structure shown in FIG7A .

[0078] In fact, according to the embodiment of the present disclosure, compared with the DRAM array structure implemented by the VCT transistor according to the prior art, the DRAM array structure implemented by the transistor with four gate structures according to the embodiment of the present disclosure changes the word line isolation in the horizontal direction to the word line isolation in the vertical direction, thereby achieving further size reduction.

[0079] The following describes the operating method of the DRAM array structure 200 according to an embodiment of the present disclosure based on Figure 6 in combination with Figure 5 and Figure 8. Figure 8 shows a schematic diagram of the operating method of the DRAM array structure 200 according to an embodiment of the present disclosure.

[0080] According to an embodiment of the present disclosure, the gate transistor in each DRAM cell structure in the DRAM array structure 200 is a transistor having four gate structures, which, as described above, can be equivalent to two dual-gate transistors connected in series. As described above with reference to FIG5 , by controlling the voltages applied to the four gate structures of the gate transistor, the gate transistor can be controlled to be turned on and off, thereby connecting or disconnecting the conductive path from the bit line of the corresponding DRAM cell structure to the storage capacitor.

[0081] 5 , 6 and 8 , according to an embodiment of the present disclosure, for each DRAM cell structure in the DRAM array structure 200, as described above, the conduction and shutoff of the selection transistor can be controlled by controlling the voltage applied to the second gate structure and the third gate structure of the selection transistor in the DRAM cell structure, that is, the voltage applied to the two first word lines connected thereto.

[0082] 5 , 6 and 8 , taking the case where the DRAM cell structure CELL2n in the 2nd row and nth column shown in FIG6 is selected as an example, when the DRAM cell structure CELL2n is selected, a high voltage VGH is applied to the first word lines WL12 and WL11 of the second gate structure G2 and the third gate structure G3 respectively connected to the selection transistor T2n in the DRAM cell structure CELL2n, so that the selection transistor T2n is turned on (as indicated by the arrow in the DRAM cell structure CELL2n in FIG6 ).

[0083] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the third gate structure G3 of the gate transistor T1n of the DRAM cell structure CELL1n in the 1st row and nth column, which is also connected to the first word line WL11, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T1n of the DRAM cell structure CELL1n, which is close to the third gate structure G3 (as indicated by the arrow in the DRAM cell structure CELL1n in FIG6 ). However, as shown in FIG8 , according to an embodiment of the present disclosure, since the first word line WL10 and the second word line WL21, which are respectively connected to the second gate structure G2 and the fourth gate structure G4 of the DRAM cell structure CELL1n, are applied with a low voltage VGL, the upper dual-gate transistor of the gate transistor T1n is turned off, and the gate transistor T1n of the DRAM cell structure CELL1n as a whole remains turned off.

[0084] Similarly, according to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share the first and second word lines, the second gate structure G2 of the gate transistor T3n of the DRAM cell structure CELL3n in the 3rd row and nth column, which is also connected to the first word line WL12, is also applied with the high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T3n of the DRAM cell structure CELL3n, which is close to the second gate structure G2 (as indicated by the arrow in the DRAM cell structure CELL3n in FIG6 ). However, as shown in FIG8 , according to an embodiment of the present disclosure, since the second word line WL22 and the first word line WL13, which are respectively connected to the first gate structure G1 and the third gate structure G3 of the DRAM cell structure CELL3n, are still applied with the low voltage VGL, the lower dual-gate transistor of the gate transistor T3n is turned off, and thus the gate transistor T3n of the DRAM cell structure CELL3n as a whole remains turned off.

[0085] 6 and 8 , according to an embodiment of the present disclosure, by controlling the voltages applied to the first word lines WL11 and WL12 , the DRAM cell structure CELL2 n can be turned on and off without affecting the operations of other DRAM cell structures.

[0086] Therefore, as shown in Figures 6 and 8, according to the embodiments of the present disclosure, the conduction and shutoff of the gate transistor in the DRAM cell structure can be controlled by the voltage applied to the first word line. Specifically, according to the embodiments of the present disclosure, for each DRAM cell structure in the DRAM array structure 200, the conduction and shutoff of the gate transistor of the DRAM cell structure can be controlled by controlling the voltages applied to its second gate structure and third gate structure via the two first word lines.

[0087] According to an embodiment of the present disclosure, in order to ensure that the selection transistors of adjacent DRAM cell structures in the column direction will not be erroneously turned on, in the selection transistors of each DRAM cell structure in the DRAM array structure 200, the gate structures arranged on the same side of the channel region (for example, the first gate structure and the second gate structure arranged on the first side or the third gate structure and the fourth gate structure arranged on the second side) will never be applied with a high voltage VGH at the same time.

[0088] In addition, as shown in FIG. 6 and FIG. 8 , according to an embodiment of the present disclosure, M+1 second word lines WL20 to WL2M may be commonly connected to the low voltage VGL.

[0089] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M may be commonly connected to a bias voltage different from VGL or floated to adjust switching characteristics of gate transistors of all DRAM cell structures.

[0090] Alternatively, according to an embodiment of the present disclosure, the M+1 second word lines WL20 to WL2M can also be connected to corresponding bias voltages or floated in groups (for example, by storage area (Bank)) or individually, so as to adjust the switching characteristics of the selection transistors of the corresponding DRAM cell structures in groups or individually.

[0091] Specifically, according to the embodiments of the present disclosure, by setting the bias voltage at a lower voltage, the gate transistor including the gate structure connected to the second word line (i.e., the first gate structure and the fourth gate structure) can have a lower leakage current, thereby reducing the power consumption of the corresponding DRAM cell structure. In addition, by setting the bias voltage at a higher voltage, the gate transistor including the gate structure connected to the second word line can have a higher on-state current, thereby improving the read and write speed of the corresponding DRAM cell structure.

[0092] According to the embodiments of the present disclosure, adjusting the bias voltage can provide a greater degree of adjustment than adjusting the switching characteristics of the gate transistor by adjusting the work function of the gate structure alone. Furthermore, according to the embodiments of the present disclosure, adjusting the bias voltage can enable the DRAM array structure to operate in different operating modes, such as a high-performance operating mode and a low-power operating mode.

[0093] Those skilled in the art will appreciate that the operating method of the DRAM array structure according to the present disclosure is not limited to the embodiments described above with reference to FIG. 6 and FIG. 8 .

[0094] For example, according to another embodiment of the present disclosure, the on / off state of the gate transistor in the DRAM cell structure can be controlled by applying voltages to the M+1 second word lines, that is, by controlling the voltages applied to the first gate structure and the fourth gate structure. Accordingly, according to this embodiment of the present disclosure, bias voltages can be applied to the M+1 first word lines collectively, in groups, and / or individually, or they can be left floating.

[0095] The following describes a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure in conjunction with Figures 9A to 9O. Figures 9A to 9O are schematic cross-sectional views of various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. It should be noted that Figures 9A to 9C are cross-sectional views taken along the row direction of the DRAM array structure, i.e., the word line direction, while Figures 9D to 9O are cross-sectional views taken along the column direction of the DRAM array structure, i.e., the bit line direction.

[0096] In the following description, the materials for each layer are exemplified. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description of "selectively etching B (relative to A)" indicates that the etching recipe used can primarily affect B, with little or no effect on A or other material layers exposed to the etching recipe when etching B (in the absence of explicit mention of A or only a portion of such material layers). Based on this description, those skilled in the art will understand how to select the materials for each layer, and are not limited to the materials exemplified herein.

[0097] As shown in FIG9A , according to an embodiment of the present disclosure, a substrate may be provided. As shown in FIG9A , according to an embodiment of the present disclosure, the substrate may include a base layer 901 , a stop layer 902 disposed on the base layer 901 , and an active layer 903 disposed on the stop layer 902 .

[0098] According to an embodiment of the present disclosure, the base layer 901 may include, for example, silicon. In addition, according to an embodiment of the present disclosure, as will be further described below, the stop layer 902 may be used to stop, for example, an etching or grinding process at this layer in a subsequent process step. According to an embodiment of the present disclosure, the stop layer 902 may be formed by an epitaxial or implantation process and may include, for example, silicon germanium. In addition, according to an embodiment of the present disclosure, the active layer 903 may be used to form, in a subsequent process step, an active region 101 of the selection transistor T of the DRAM cell structure 100 described above with reference to Figures 2 to 4, which may include a first source / drain region and a second source / drain region and a channel region therebetween. According to an embodiment of the present disclosure, the active layer 903 may include, for example, a P-type semiconductor, an N-type semiconductor, or an intrinsic semiconductor, and have an etching selectivity relative to the stop layer 902.

[0099] Alternatively, according to an embodiment of the present disclosure, a semiconductor-on-insulator (SOI) substrate may be provided, which includes an insulating layer sandwiched between silicon layers, wherein the insulating layer typically includes silicon oxide. In an embodiment of the present disclosure, the lower silicon layer of the SOI substrate may serve as the base layer 901, the insulating layer may serve as the stop layer 902, and the upper silicon layer may serve as the active layer 903. As known to those skilled in the art, the SOI substrate may be manufactured by, for example, oxygen implantation isolation, wafer bonding, or smart lift-off processes.

[0100] Subsequently, as shown in FIG9B , according to an embodiment of the present disclosure, the active layer 903 can be etched by, for example, a photolithography and etching process to form a first groove G1 extending to the stop layer 902. It should be noted that according to an embodiment of the present disclosure, the first groove G1 extends along the column direction (i.e., the direction perpendicular to the paper), i.e., the bit line direction. According to an embodiment of the present disclosure, the first groove G1 is used to isolate the bit lines connected to each column of the DRAM cell structure, and is therefore also referred to as a "bit line isolation groove" hereinafter. According to an embodiment of the present disclosure, the bit line isolation groove G1 can be used to limit the size of the active area of ​​the selection transistor of the DRAM cell structure in the row direction.

[0101] 9C , according to an embodiment of the present disclosure, a first isolation dielectric 904 may be filled in the first trench G1 by, for example, a deposition process. According to an embodiment of the present disclosure, the first isolation dielectric 904 may include oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof.

[0102] It should be noted that FIG. 9D to FIG. 9O illustrate cross-sectional views of the DRAM array structure taken along line BB′ of FIG. 9C , ie, cross-sectional views in the row direction of the DRAM array structure, ie, in the word line direction.

[0103] Based on the cross-sectional view of the DRAM array structure in the row direction, i.e., the word line direction, shown in FIG9D , according to an embodiment of the present disclosure, the upper surface of the active layer 903 can be planarized and exposed by, for example, a grinding process or an etching process, as shown in FIG9E .

[0104] Subsequently, as shown in FIG9E , according to an embodiment of the present disclosure, the active layer 903 can be etched by photolithography or etching to form a second trench G2 extending to the stop layer 902. According to an embodiment of the present disclosure, the second trench G2 is used to define the position of the word line in subsequent process steps, and therefore may also be referred to as a "word line trench" herein. It is horizontally perpendicular to the first trench (bit line isolation trench) G1. According to an embodiment of the present disclosure, the word line trench G2 can be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the column direction.

[0105] Subsequently, as shown in FIG9F , according to an embodiment of the present disclosure, a sacrificial dielectric 905 may be formed in the second trench G2, for example, by a deposition process. According to an embodiment of the present disclosure, the sacrificial dielectric 905 may be formed from a material having an etch selectivity, such as silicon oxide, silicon nitride, polyimide, amorphous silicon, polycrystalline silicon, silicon germanium, or germanium. According to an embodiment of the present disclosure, the sacrificial dielectric 905 may be used to form a gate dielectric and first and second word lines in subsequent process steps.

[0106] 9G , according to an embodiment of the present disclosure, a portion of the sacrificial dielectric 905 can be self-alignedly etched using the active layer 903 as a mask, for example, through an etching process. Preferably, according to an embodiment of the present disclosure, the etching depth of the sacrificial dielectric 905 can be controlled so that half of the thickness of the sacrificial dielectric 905 in the vertical direction is removed.

[0107] 9G , according to an embodiment of the present disclosure, a first gate dielectric 906 may be conformally formed along the surface of the second groove G2 and the upper surface of the active layer 903, for example, by a deposition process. According to an embodiment of the present disclosure, the first gate dielectric 906 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG. 2 to FIG. 4 .

[0108] Subsequently, as shown in FIG9H , according to an embodiment of the present disclosure, a first conductor line 907 serving as both a word line and a gate structure can be formed in the second trench G2 by, for example, a deposition process and an etching process, wherein the first conductor line 907 is separated from the active layer 903 by a first gate dielectric 906. According to an embodiment of the present disclosure, the first conductor line 907 can also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the upper gate structure of the gate transistor T described above in conjunction with FIG6 .

[0109] Subsequently, as shown in FIG. 9I , according to an embodiment of the present disclosure, a first contact portion 908 may be formed at one end (the upper end shown in FIG. 9H ) of the active layer 903 by, for example, ion implantation and annealing processes.

[0110] Subsequently, as shown in FIG9J , according to an embodiment of the present disclosure, a second isolation dielectric 909 may be used to fill the second trench G2, and a storage capacitor 910 may be formed on the first contact portion 908. According to an embodiment of the present disclosure, the second isolation dielectric 909 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof. According to an embodiment of the present disclosure, the second isolation dielectric 909 may be formed of the same material as the first isolation dielectric 904, or may be formed of a material different from the first isolation dielectric 904. In addition, since the process steps for forming the storage capacitor are known to those skilled in the art, for the sake of brevity, they are not described in further detail herein.

[0111] Subsequently, as shown in FIG9K , according to an embodiment of the present disclosure, the entire DRAM array structure can be flipped over, and a support layer 911 can be bonded to one side of the storage capacitor 910, for example, by a wafer bonding process, to support the flipped DRAM array structure. According to an embodiment of the present disclosure, the support layer 911 can include, for example, inorganic polymers such as silicon, oxides, nitrides, and glass, organic polymers such as polyimide, or a combination of the foregoing materials.

[0112] 9K , according to an embodiment of the present disclosure, the base layer 901 and the stop layer 902 may be sequentially removed by etching or grinding processes to expose the other end (the upper end shown in FIG. 9K ) of the active layer 903 .

[0113] Subsequently, as shown in FIG. 9L , according to an embodiment of the present disclosure, the remaining portion of the sacrificial dielectric 905 in the second groove G2 may be self-alignedly etched using the active layer 903 as a mask, for example, through an etching process to expose the first gate dielectric 906 .

[0114] Subsequently, as shown in FIG9M , according to an embodiment of the present disclosure, a second gate dielectric 912 and a second conductor line 913 can be sequentially formed above the first gate dielectric 906 by repeating the steps described above with reference to FIG9G and FIG9H , wherein the second conductor line 913 is separated from the active layer 903 by the second gate dielectric 912. According to an embodiment of the present disclosure, the second conductor line 913 can also serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the lower gate structure of the gate transistor T described above in conjunction with FIG6 . According to an embodiment of the present disclosure, the dielectric material and thickness of the first gate dielectric 906 and the second gate dielectric 912 can be the same or different.

[0115] 9N , according to an embodiment of the present disclosure, a second contact portion 914 may be formed at the other end of the active layer 903 (the lower end shown in FIG. 9H , corresponding to the upper end shown in FIG. 9M ) by repeating the steps described above with reference to FIG. 9I .

[0116] Subsequently, as shown in FIG9O , according to an embodiment of the present disclosure, a third isolation dielectric 915 may be used to fill the second trench G2, and a bit line 916 may be formed on the second contact portion 914, thereby forming a DRAM array structure. According to an embodiment of the present disclosure, the third isolation dielectric 915 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof. According to an embodiment of the present disclosure, the third isolation dielectric 915 may be formed of the same material as the first isolation dielectric 904 and / or the second isolation dielectric 909, or may be formed of a different material than the first isolation dielectric 904 and / or the second isolation dielectric 909.

[0117] 10A to 10F are schematic cross-sectional views showing various process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0118] For the sake of brevity, the components in FIGS. 10A to 10F that are identical to those in FIGS. 9A to 9O are denoted by the same reference numerals, and the corresponding descriptions are omitted.

[0119] FIG10A may be continued from FIG9I , that is, the process steps prior to the process steps shown in FIG10A may be the same as the process steps described above with reference to FIG9A through FIG9H . Furthermore, similar to FIG9H through FIG9O , FIG10A through FIG10F are cross-sectional views taken along the column direction, i.e., the bit line direction, of the DRAM array structure.

[0120] The method for manufacturing a DRAM array structure shown in Figures 10A to 10F is similar to the method for manufacturing a DRAM array structure shown in Figures 9A to 9O in that both use a double-sided processing method. However, the difference is that in Figures 9A to 9O, storage capacitors are first manufactured on one side and then bit lines are manufactured on the other side. In contrast, in Figures 10A to 10F, bit lines are first manufactured on one side and then storage capacitors are manufactured on the other side.

[0121] 10A , according to an embodiment of the present disclosure, the second trench G2 may be filled with a second isolation dielectric 909, and a bit line 916 may be formed on the first contact 908. In this embodiment shown in FIG10A , the first conductor line 907 may simultaneously serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the lower gate structure of the gate transistor T described above in conjunction with FIG6 .

[0122] Subsequently, as shown in FIG10B , according to an embodiment of the present disclosure, the entire DRAM array structure can be flipped over, and a support layer 911 can be bonded to one side of the bit line 916, for example, by a wafer bonding process, to support the flipped DRAM array structure. Furthermore, as shown in FIG10B , according to an embodiment of the present disclosure, the base layer 901 and the stop layer 902 can be sequentially removed by etching or grinding to expose the other end of the active layer 903.

[0123] Subsequently, as shown in FIG. 10C , according to an embodiment of the present disclosure, the remaining portion of the sacrificial dielectric 905 in the second groove G2 may be self-alignedly etched using the active layer 903 as a mask, for example, through an etching process to expose the first gate dielectric 906 .

[0124] Subsequently, as shown in FIG10D , according to an embodiment of the present disclosure, a second gate dielectric 912 and a second conductor line 913 can be sequentially formed over the first gate dielectric 906 by repeating the steps described above with reference to FIG9G and FIG9H , wherein the second conductor line 913 is separated from the active layer 903 by the second gate dielectric 912. According to an embodiment of the present disclosure, the second conductor line 913 can also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the upper gate structure of the gate transistor T described above in conjunction with FIG6 .

[0125] Subsequently, as shown in FIG. 10E , according to an embodiment of the present disclosure, a second contact portion 914 may be formed at the other end of the active layer 903 by repeating the steps described above with reference to FIG. 9I .

[0126] Subsequently, as shown in FIG. 10F , according to an embodiment of the present disclosure, the second trench G2 may be filled with a third isolation dielectric 915 , and a storage capacitor 910 may be formed on the second contact portion 914 , thereby forming a DRAM array structure.

[0127] Those skilled in the art will recognize that although the DRAM array structure is manufactured using a double-sided processing method in the above-described embodiment, where the first layer of word lines (e.g., word lines connected to the upper gate structure or the lower gate structure) is manufactured on one side and the second layer of word lines (e.g., word lines connected to the lower gate structure or the upper gate structure) is manufactured on the other side, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision manufacturing both layers of word lines on one side before or after flipping.

[0128] The method for manufacturing a DRAM array structure according to an embodiment of the present disclosure will be described below in conjunction with Figures 11A to 11P. Figures 11A to 11P respectively show schematic cross-sectional views of various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. It should be noted that Figures 11A to 11C are cross-sectional views taken in the row direction of the DRAM array structure, that is, in the word line direction, Figures 11D to 11F and Figures 11H to 11P are cross-sectional views taken in the column direction of the DRAM array structure, that is, in the bit line direction, and Figure 11G is a top view taken in the horizontal direction of the DRAM array structure.

[0129] In the following description, the materials for each layer are exemplified. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description of "selectively etching B (relative to A)" indicates that the etching recipe used can primarily affect B, with little or no effect on A or other material layers exposed to the etching recipe when etching B (in the absence of explicit mention of A or only a portion of such material layers). Based on this description, those skilled in the art will understand how to select the materials for each layer, and are not limited to the materials exemplified herein.

[0130] As shown in FIG11A , according to an embodiment of the present disclosure, a substrate 1101 may be provided. According to an embodiment of the present disclosure, the substrate 1101 may include, for example, a P-type semiconductor, an N-type semiconductor, or an intrinsic semiconductor. Furthermore, according to an embodiment of the present disclosure, the substrate 1101 may also be a substrate of other forms, including but not limited to a bulk semiconductor material substrate such as a bulk silicon substrate, a compound semiconductor substrate such as a silicon germanium (SiGe) substrate, and the like.

[0131] Subsequently, as shown in FIG11B , according to an embodiment of the present disclosure, the substrate 1101 can be etched by, for example, a photolithography and etching process to form a first groove G1 having a first depth dp1. It should be noted that according to an embodiment of the present disclosure, the first groove G1 extends along the column direction (i.e., the direction perpendicular to the paper), i.e., the bit line direction. According to an embodiment of the present disclosure, the first groove G1 is used to isolate the bit lines connected to each column of the DRAM cell structure, and is therefore also referred to as a "bit line isolation groove" hereinafter. According to an embodiment of the present disclosure, the bit line isolation groove G1 can be used to limit the size of the active area of ​​the gate transistor of the DRAM cell structure in the row direction.

[0132] 11C , according to an embodiment of the present disclosure, a first isolation dielectric 1104 may be filled in the first trench G1 by, for example, a deposition process. According to an embodiment of the present disclosure, the first isolation dielectric 1104 may include oxide (e.g., silicon oxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof.

[0133] 11D to 11F and 11H to 11P show cross-sectional views of the DRAM array structure taken along line BB' of FIG. 11C , ie, cross-sectional views in the row direction of the DRAM array structure, ie, the word line direction.

[0134] Based on the cross-sectional view of the DRAM array structure in the row direction, i.e., the word line direction, shown in FIG11D , according to an embodiment of the present disclosure, the upper surface of the active layer 1103 can be planarized and exposed by, for example, a grinding process or an etching process, as shown in FIG11E .

[0135] Subsequently, as shown in FIG11E , according to an embodiment of the present disclosure, the substrate 1101 can be etched by photolithography or etching to form a second trench G2 having a second depth dp2. According to an embodiment of the present disclosure, the second trench G2 is used to define the position of the word line in subsequent process steps, and therefore may also be referred to herein as a "word line trench." It is horizontally perpendicular to the first trench (bit line isolation trench) G1. According to an embodiment of the present disclosure, the word line trench G2 can be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the column direction.

[0136] Subsequently, as shown in FIG11F , according to an embodiment of the present disclosure, a sacrificial dielectric 1105 may be formed in the second trench G2, for example, by a deposition process. According to an embodiment of the present disclosure, the sacrificial dielectric 1105 may be formed from a material having an etch selectivity, such as silicon oxide, silicon nitride, polyimide, amorphous silicon, polycrystalline silicon, silicon germanium, or germanium. According to an embodiment of the present disclosure, the sacrificial dielectric 1105 may be used to form a gate dielectric and first and second word lines in subsequent process steps.

[0137] In addition, Figure 11G shows a top view of the DRAM array structure taken along line CC' of Figure 11F in the horizontal direction. As shown in Figure 11G, a plurality of semiconductor pillars 1103 can be formed on the substrate 1101 by forming a first groove G1 (i.e., a bit line isolation groove) in the column direction and a second groove G2 (i.e., a word line groove) in the row direction in the substrate 1101. According to an embodiment of the present disclosure, the semiconductor pillar 1103 can be used to form the active area 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to Figures 2 to 4 in subsequent process steps, and is therefore also referred to as an "active area pillar" hereinafter, which may include a first source / drain region and a second source / drain region and a channel region therebetween in the vertical direction. Although the active area pillar 1103 is shown in Figure 11G as having a rectangular cross-section in the horizontal direction, the present disclosure is not limited thereto. According to the teachings of the present disclosure, those skilled in the art may also envision that the active region pillar 1103 has other shapes in the horizontal direction, such as square, circle, ellipse, diamond, etc., and all these variations should be included in the scope of the present disclosure.

[0138] 11H , according to an embodiment of the present disclosure, a portion of the sacrificial dielectric 1105 can be self-alignedly etched using the active region pillars 1103 as a mask, for example, through an etching process. Preferably, according to an embodiment of the present disclosure, the etching depth of the sacrificial dielectric 1105 can be controlled so that half of the thickness of the sacrificial dielectric 1105 in the vertical direction is removed.

[0139] 11H , according to an embodiment of the present disclosure, a first gate dielectric 1106 may be conformally formed along the surface of the second groove G2 and the upper surface of the active region pillar 1103, for example, by a deposition process. According to an embodiment of the present disclosure, the first gate dielectric 1106 may correspond to the gate dielectric 1011 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG. 2 to FIG. 4 .

[0140] Subsequently, as shown in FIG11I , according to an embodiment of the present disclosure, a first conductor line 1107 serving as both a word line and a gate structure can be formed in the second trench G2 by, for example, a deposition process and an etching process, wherein the first conductor line 1107 is separated from the active region pillar 1103 by a first gate dielectric 1106. According to an embodiment of the present disclosure, the first conductor line 1107 can simultaneously serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the upper gate structure of the gate transistor T described above in conjunction with FIG6 .

[0141] Subsequently, as shown in FIG. 11J , according to an embodiment of the present disclosure, a first contact portion 1108 may be formed at one end (the upper end shown in FIG. 11I ) of the active region pillar 1103 by, for example, ion implantation and annealing processes.

[0142] Subsequently, as shown in FIG11K , according to an embodiment of the present disclosure, the second trench G2 may be filled with a second isolation dielectric 1109, and a storage capacitor 1110 may be formed on the first contact portion 1108. According to an embodiment of the present disclosure, the second isolation dielectric 1109 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof. According to an embodiment of the present disclosure, the second isolation dielectric 1109 may be formed of the same material as the first isolation dielectric 1104, or may be formed of a material different from the first isolation dielectric 1104. In addition, since the process steps for forming the storage capacitor are known to those skilled in the art, for the sake of brevity, they are not described in further detail herein.

[0143] Subsequently, as shown in FIG11L , according to an embodiment of the present disclosure, the entire DRAM array structure can be flipped over, and a support layer 1111 can be bonded to one side of the storage capacitor 1110, for example, by a wafer bonding process, to support the flipped DRAM array structure. According to an embodiment of the present disclosure, the support layer 1111 can include, for example, inorganic polymers such as silicon, oxides, nitrides, and glass, organic polymers such as polyimide, or combinations thereof.

[0144] In addition, as shown in FIG11L , according to an embodiment of the present disclosure, after flipping the DRAM array structure, an etching or grinding process can be performed on the substrate 1101 to expose the sacrificial dielectric 1105, so that the gate dielectric and conductor lines can be formed from the other side. In other words, the bottom surface of the sacrificial dielectric 1105 shown in FIG11K can be used as a stop surface for the etching or grinding process. In addition, in order to avoid short circuiting of the active area pillars 1103 of adjacent columns, that is, to avoid short circuiting of the bit lines of adjacent columns, according to an embodiment of the present disclosure, the depth dp1 of the first groove G1 (i.e., the bit line isolation groove) should be greater than or equal to the depth dp2 of the second groove G2.

[0145] Alternatively, according to another embodiment of the present disclosure, after flipping the DRAM array structure, an etching or grinding process can be performed on substrate 1101 to expose the first isolation dielectric 1104 in the first trench G1 (i.e., the bitline isolation trench). In other words, as shown in FIG11C , the bottom surface of the first isolation dielectric 1104 can serve as a stop surface for the etching or grinding process. In this case, the depth dp1 of the first trench G1 can be less than the depth dp2 of the second trench G2.

[0146] Subsequently, as shown in FIG. 11M , according to an embodiment of the present disclosure, the remaining portion of the sacrificial dielectric 1105 in the second groove G2 may be self-alignedly etched using the active region pillar 1103 as a mask, for example, through an etching process to expose the first gate dielectric 1106 .

[0147] Subsequently, as shown in FIG11N , according to an embodiment of the present disclosure, a second gate dielectric 1112 and a second conductor line 1113 can be sequentially formed above the first gate dielectric 1106 by repeating the steps described above with reference to FIG11H and FIG11I , wherein the second conductor line 1113 is separated from the active region pillar 1103 by the second gate dielectric 1112. According to an embodiment of the present disclosure, the second conductor line 1113 can also serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the lower gate structure of the gate transistor T described above in conjunction with FIG6 . According to an embodiment of the present disclosure, the dielectric material and thickness of the first gate dielectric 1106 and the second gate dielectric 1112 can be the same or different.

[0148] Subsequently, as shown in Figure 11O, according to an embodiment of the present disclosure, a second contact portion 1114 can be formed at the other end of the active area column 1103 (the lower end shown in Figure 11I, corresponding to the upper end shown in Figure 11N) by repeating the steps described above with reference to Figure 11J.

[0149] Subsequently, as shown in FIG11P , according to an embodiment of the present disclosure, a third isolation dielectric 1115 may be used to fill the second trench G2, and a bit line 1116 may be formed on the second contact portion 1114, thereby forming a DRAM array structure. According to an embodiment of the present disclosure, the third isolation dielectric 1115 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the third isolation dielectric 1115 may be formed of the same material as the first isolation dielectric 1104 and / or the second isolation dielectric 1109, or may be formed of a different material from the first isolation dielectric 1104 and / or the second isolation dielectric 1109.

[0150] 12A to 12F illustrate schematic cross-sectional views of various process steps of a method for manufacturing a DRAM array structure according to another embodiment of the present disclosure.

[0151] For the sake of brevity, the components in FIGS. 12A to 12F that are identical to those in FIGS. 11A to 11P are denoted by the same reference numerals, and the corresponding descriptions are omitted.

[0152] FIG12A may be continued from FIG11J , that is, the process steps preceding the process steps shown in FIG12A may be the same as the process steps described above with reference to FIG11A through FIG11I . Furthermore, similar to FIG11J through FIG11P , FIG12A through FIG12F are cross-sectional views taken along the column direction, i.e., the bit line direction, of the DRAM array structure.

[0153] The method for manufacturing a DRAM array structure shown in Figures 12A to 12F is similar to the method for manufacturing a DRAM array structure shown in Figures 11A to 11P in that both use a double-sided processing method. However, the difference is that in Figures 11A to 11P, storage capacitors are first manufactured on one side and then bit lines are manufactured on the other side. In contrast, in Figures 12A to 12F, bit lines are first manufactured on one side and then storage capacitors are manufactured on the other side.

[0154] Specifically, as shown in FIG12A , according to an embodiment of the present disclosure, the second trench G2 may be filled with a second isolation dielectric 1109, and a bit line 1116 may be formed on the first contact 1108. In this embodiment as shown in FIG12A , the first conductor line 1107 may simultaneously serve as the lower gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the lower gate structure of the gate transistor T described above in conjunction with FIG6 .

[0155] Subsequently, as shown in FIG. 12B , according to an embodiment of the present disclosure, the entire DRAM array structure may be flipped, and a support layer 1111 may be bonded to one side of the bit line 1116 through, for example, a wafer bonding process to support the flipped DRAM array structure.

[0156] In addition, as shown in FIG12B , according to an embodiment of the present disclosure, after flipping the DRAM array structure, an etching or grinding process can be performed on the substrate 1101 to expose the sacrificial dielectric 1105, so that the gate dielectric and conductor lines can be formed from the other side. In other words, the bottom surface of the sacrificial dielectric 1105 shown in FIG11K can be used as a stop surface for the etching or grinding process. In addition, in order to avoid short circuiting of the active area pillars 1103 of adjacent columns, that is, to avoid short circuiting of the storage capacitors of adjacent columns, according to an embodiment of the present disclosure, the depth dp1 of the first groove G1 (i.e., the bit line isolation groove) should be greater than or equal to the depth dp2 of the second groove G2.

[0157] Alternatively, according to another embodiment of the present disclosure, after flipping the DRAM array structure, an etching or grinding process can be performed on substrate 1101 to expose the first isolation dielectric 1104 in the first trench G1 (i.e., the bitline isolation trench). In other words, as shown in FIG11C , the bottom surface of the first isolation dielectric 1104 can serve as a stop surface for the etching or grinding process. In this case, the depth dp1 of the first trench G1 can be less than the depth dp2 of the second trench G2.

[0158] Subsequently, as shown in FIG. 12C , according to an embodiment of the present disclosure, the remaining portion of the sacrificial dielectric 1105 in the second groove G2 may be self-alignedly etched using the active region pillar 1103 as a mask to expose the first gate dielectric 1106 , for example, through an etching process.

[0159] Subsequently, as shown in FIG12D , according to an embodiment of the present disclosure, a second gate dielectric 1112 and a second conductor line 1113 can be sequentially formed over the first gate dielectric 1106 by repeating the steps described above with reference to FIG11H and FIG11I , wherein the second conductor line 1113 is separated from the active region pillar 1103 by the second gate dielectric 1112. According to an embodiment of the present disclosure, the second conductor line 1113 can also serve as the upper gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , as well as the first word line and the second word line connected to the upper gate structure of the gate transistor T described above in conjunction with FIG6 .

[0160] Subsequently, as shown in FIG. 12E , according to an embodiment of the present disclosure, a second contact portion 1114 may be formed at the other end of the active region pillar 1103 by repeating the steps described above with reference to FIG. 11J .

[0161] Subsequently, as shown in FIG. 12F , according to an embodiment of the present disclosure, the second trench G2 may be filled with a third isolation dielectric 1115 , and a storage capacitor 1110 may be formed on the second contact portion 1114 , thereby forming a DRAM array structure.

[0162] Those skilled in the art will recognize that although the DRAM array structure is manufactured using a double-sided processing method in the above-described embodiment, where the first layer of word lines (e.g., word lines connected to the upper gate structure or the lower gate structure) is manufactured on one side and the second layer of word lines (e.g., word lines connected to the lower gate structure or the upper gate structure) is manufactured on the other side, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also envision manufacturing both layers of word lines on one side before or after flipping.

[0163] In particular, referring to Figures 11A to 11P , according to an embodiment of the present disclosure, when both word lines are formed in the second trench G2 (i.e., the word line trench) before flipping, because the depth dp1 of the first trench G1 (i.e., the bit line isolation trench) is greater than or equal to the depth dp2 of the second trench G2 and the DRAM cell structures in the same column are connected to the same bit line, the etching or grinding process performed after flipping can also stop at the bottom surface of the first isolation dielectric 1104, i.e., the bottom surface of the first trench G1. In other words, the bottom surface of the first isolation dielectric 1104, as shown in Figure 11C , can serve as a stop surface for the etching or grinding process.

[0164] Furthermore, those skilled in the art will recognize that, although in the embodiments described above, the bottom surface of the first isolation dielectric and / or sacrificial dielectric is used as a stop surface for the etching or grinding process after flipping, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may envision providing a dedicated stop layer at the bottom of the first trench (i.e., the bit line isolation trench) and / or the second trench (i.e., the word line trench) so that the etching or grinding process after flipping can stop at this stop layer.

[0165] In addition, those skilled in the art will recognize that although a cylinder capacitor is used as a storage capacitor in the embodiments described above, the present disclosure is not limited thereto. Based on the teachings of the present disclosure, those skilled in the art may also conceive of using capacitors of other structures as storage capacitors, such as a pillar capacitor.

[0166] All of the above variations are intended to fall within the scope of this disclosure.

[0167] According to the method for manufacturing a DRAM array structure disclosed herein, a vertical transistor with a four-gate structure is manufactured using a double-sided processing process to serve as the gate transistor of the DRAM cell structure. Adjacent DRAM cell structures in the column direction share word lines, eliminating the inherent spacing between word lines in a conventional DRAM array structure based on gate-all-around transistors, thereby achieving further size reduction. Furthermore, the method for manufacturing a DRAM array structure disclosed herein can reduce gate length fluctuations and alignment deviations when forming multi-layer word lines by using a double-sided processing process, and avoid the use of a complex bottom bit line formation process, thereby reducing the parasitic capacitance of the bit lines.

[0168] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0169] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, comprising: Providing a stop layer and an active layer on a base layer; Forming a plurality of bit line isolation trenches extending in a column direction in the active layer to define the size of the active region of each DRAM cell structure in a row direction; Forming a plurality of word line trenches extending in a row direction in the active layer to define the size of the active region of each DRAM cell structure in a column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line trenches; Forming a storage capacitor at one end of the active region of each DRAM cell structure; Flipping the DRAM array structure and removing the base layer and the stop layer; and Forming a bit line at the other end of the active region of each DRAM cell structure.

2. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, comprising: Providing a stop layer and an active layer on a base layer; Forming a plurality of bit line isolation trenches extending in a column direction in the active layer to define the size of the active region of each DRAM cell structure in a row direction; Forming a plurality of word line trenches extending in a row direction in the active layer to define the size of the active region of each DRAM cell structure in a column direction, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line trenches; Forming a bit line at one end of the active region of each DRAM cell structure; Flipping the DRAM array structure and removing the base layer and the stop layer; and Forming a storage capacitor at the other end of the active region of each DRAM cell structure.

3. The method according to claim 1 or 2, further comprising: Forming a first gate dielectric and the first layer of word lines in the plurality of word line trenches; And After flipping the DRAM array structure and removing the base layer and the stop layer, forming a second gate dielectric and the second layer of word lines in the plurality of word line trenches.

4. The method according to claim 1 or 2, further comprising: Before or after flipping the DRAM array structure, forming a first gate dielectric and the first layer of word lines and a second gate dielectric and the second layer of word lines in the plurality of word line trenches.

5. The method according to claim 3 or 4, further comprising: Filling the bit line isolation trenches with a first isolation medium; Filling one end of the word line trenches with a second isolation medium to isolate the first layer of word lines from one of the storage capacitor and the bit line; And Filling the other end of the word line trenches with a third isolation medium to isolate the second layer of word lines from the other of the storage capacitor and the bit line.

6. The method according to claim 5, wherein The first isolation medium, the second isolation medium, and the third isolation medium include the same or different materials from each other.

7. The method according to claim 3 or 4, wherein The first gate dielectric and the second gate dielectric have the same or different materials or thicknesses from each other.

8. The method according to claim 3 or 4, wherein the first layer of word lines and the second layer of word lines are separated from each other by the first gate dielectric and the second gate dielectric.

9. The method according to claim 1 or 2, further comprising: forming a first contact at one end of the active region of each DRAM cell structure to contact one of the storage capacitor and the bit line, and forming a second contact at the other end of the active region of each DRAM cell structure to contact the other of the storage capacitor and the bit line.

10. The method according to claim 1 or 2, wherein, The DRAM array structure includes: a plurality of DRAM cell structures arranged in M rows and N columns, where M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: a storage capacitor including a first electrode and a second electrode, wherein the second electrode is connected to the source line; and a select transistor including: an active region extending vertically, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on the first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on the second side of the channel region opposite to the first side; N bit lines respectively connected to the other of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; M + 1 first word lines respectively connected to the second gate structure and the third gate structure of the DRAM cell structures in M rows; and M + 1 second word lines respectively connected to the first gate structure and the fourth gate structure of the DRAM cell structures in M rows, wherein one of the first layer of word lines and the second layer of word lines forms the first gate structure and the third gate structure of the DRAM cell structures in M rows, and the other of the first layer of word lines and the second layer of word lines forms the second gate structure and the fourth gate structure of the DRAM cell structures in M rows.

11. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a substrate; forming a plurality of bit line isolation grooves extending in the column direction and a plurality of word line grooves extending in the row direction in the substrate to form active region columns of a plurality of DRAM cell structures, wherein a first layer of word lines and a second layer of word lines are formed in the plurality of word line grooves; forming a storage capacitor at one end of the active region column of each DRAM cell structure; flipping the DRAM array structure and removing the substrate; and forming a bit line at the other end of the active region column of each DRAM cell structure.

12. A method for manufacturing a vertical dynamic random access memory (DRAM) array structure having double-layer word lines, wherein the DRAM array structure includes a plurality of DRAM cell structures arranged in an array, including: providing a substrate; Form a plurality of bit line isolation grooves extending in the column direction and a plurality of word line grooves extending in the row direction in the substrate to form active region columns of a plurality of DRAM cell structures, wherein a first word line and a second word line are formed in the plurality of word line grooves; Form a bit line at one end of the active region column of each DRAM cell structure; Flip the DRAM array structure and remove the substrate; And Form a storage capacitor at the other end of the active region column of each DRAM cell structure.

13. The method according to claim 11 or 12, wherein, The plurality of bit line isolation grooves are used to define the size of the active region column of each DRAM cell structure in the row direction, and The plurality of word line grooves are used to define the size of the active region column of each DRAM cell structure in the column direction.

14. The method according to claim 11 or 12, further comprising: Form a first gate dielectric and the first word line in the plurality of word line grooves; And After flipping the DRAM array structure and removing the substrate, form a second gate dielectric and the second word line in the plurality of word line grooves.

15. The method according to claim 11 or 12, further comprising: Before or after flipping the DRAM array structure, form a first gate dielectric and the first word line and a second gate dielectric and the second word line in the plurality of word line grooves.

16. The method according to claim 11 or 12, wherein, The depth of the bit line isolation groove in the vertical direction is greater than or equal to the depth of the word line groove, and After flipping the DRAM array structure, the step of removing the substrate stops at the bottom surface of the word line groove.

17. The method according to claim 11 or 12, wherein The depth of the bit line isolation groove in the vertical direction is less than the depth of the word line groove, and After flipping the DRAM array structure, the step of removing the substrate stops at the bottom surface of the bit line isolation groove.

18. The method according to claim 11, further comprising: Before flipping the DRAM array structure, form a first gate dielectric and the first word line and a second gate dielectric and the second word line in the plurality of word line grooves, wherein the depth of the bit line isolation groove in the vertical direction is greater than or equal to the depth of the word line groove; and After flipping the DRAM array structure, the step of removing the substrate stops at the bottom surface of the bit line isolation groove.

19. The method according to claim 11 or 12, further comprising: Form a stop layer at the bottom of the bit line isolation groove and / or the word line groove; And After flipping the DRAM array structure, the step of removing the substrate stops at the stop layer.

20. The method according to claim 14 or 15, further comprising: Fill the bit line isolation groove with a first isolation medium; Fill one end of the word line groove with a second isolation medium to isolate the first word line from one of the storage capacitor and the bit line; And Fill the other end of the word line groove with a third isolation medium to isolate the second word line from the other of the storage capacitor and the bit line.

21. The method according to claim 20, wherein The first isolation medium, the second isolation medium, and the third isolation medium include the same or different materials from each other.

22. The method according to claim 14 or 15, wherein the first gate dielectric and the second gate dielectric have the same or different materials or thicknesses from each other.

23. The method according to claim 14 or 15, wherein the first layer of word lines and the second layer of word lines are separated from each other by the first gate dielectric and the second gate dielectric.

24. The method according to claim 11 or 12, further comprising: forming a first contact portion at one end of the active region of each DRAM cell structure to contact one of the storage capacitor and the bit line, and forming a second contact portion at the other end of the active region of each DRAM cell structure to contact the other of the storage capacitor and the bit line.

25. The method according to claim 11 or 12, wherein The DRAM array structure includes: a plurality of DRAM cell structures arranged in M rows and N columns, where M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: a storage capacitor including a first electrode and a second electrode, wherein the second electrode is connected to the source line; and a select transistor including: a vertically extending active region including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and first to fourth gate structures, wherein the first gate structure and the second gate structure are arranged from bottom to top in the vertical direction on a first side of the channel region, and the third gate structure and the fourth gate structure are arranged from bottom to top in the vertical direction on a second side of the channel region opposite to the first side; N bit lines respectively connected to the other of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; M + 1 first word lines respectively connected to the second gate structure and the third gate structure of the DRAM cell structures in M rows; and M + 1 second word lines respectively connected to the first gate structure and the fourth gate structure of the DRAM cell structures in M rows, wherein one of the first layer of word lines and the second layer of word lines forms the first gate structure and the third gate structure of the DRAM cell structures in M rows, and the other of the first layer of word lines and the second layer of word lines forms the second gate structure and the fourth gate structure of the DRAM cell structures in M rows.

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