Dram unit structure and operation method therefor, and dram array structure and operation method and manufacturing method therefor

Abstract

Provided in the present disclosure are a dynamic random access memory (DRAM) unit structure and an operation method therefor, and a DRAM array structure and an operation method and manufacturing method therefor. The DRAM unit structure according to the present disclosure comprises: a storage capacitor, which comprises a first electrode, and a second electrode connected to a source line; and a gating transistor, which comprises: a vertically extending active region, comprising a first source / drain region, a channel region and a second source / drain region, which are sequentially arranged from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a bit line, and the other one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and a first gate structure and a second gate structure, wherein the first gate structure is arranged in the vertical direction on a first side of the channel region, and the second gate structure is arranged in the vertical direction on a second side of the channel region, which second side is opposite the first side, and the first gate structure and the second gate structure are staggered from each other in the vertical direction and have no overlapping region. By means of the DRAM unit structure and the operation method therefor according to the present disclosure, a leakage current of a gating transistor can be reduced, thereby improving the switching characteristics.

Description

DRAM cell structure and operation method thereof, DRAM array structure, operation method and manufacturing method Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a dynamic random access memory (DRAM) cell structure and an operating method thereof, as well as a DRAM array structure and an operating method and a manufacturing method thereof. Background Art

[0002] Since Intel Corporation invented Dynamic Random Access Memory (DRAM) in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit typically consists of a selection transistor and a storage capacitor (1T1C structure) for storing charge. In a DRAM cell structure that uses a conventional planar horizontal transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the selection transistor, the transistor's source, gate, and drain are arranged horizontally parallel to the substrate surface. Because the transistor's source, gate, and drain each occupy independent areas in the horizontal direction, the scaling of the DRAM cell circuit structure is limited by gate length and contact size, making it impossible to meet the continued scaling requirements of DRAM devices. This in turn limits the integration density and bandwidth of DRAM devices.

[0004] Therefore, a vertical DRAM cell structure has been proposed in recent years, in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the miniaturization of the DRAM array structure.

[0005] However, in existing DRAM cell circuit structures based on vertical channel transistors (VCTs), the metal gate wraps the entire channel, requiring additional area for isolation between word lines formed by the metal gate connection. This limits the scaling of VCT transistors used as gate transistors in DRAM cell circuits. Furthermore, the resistance of metal deposited by atomic layer deposition (ALD) increases significantly as its thickness decreases. This, combined with the additional area required by the metal and gate oxide thickness compared to planar structures, limits further reductions in word line spacing.

[0006] The above information disclosed in this Background section is only for understanding the background of the present inventive concept and therefore it may contain information that does not constitute prior art. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel dynamic random access memory (DRAM) cell structure and an operating method thereof.

[0008] According to one aspect of the present disclosure, a DRAM cell structure is provided, comprising: a storage capacitor, comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a selection transistor, comprising: a vertically extending active region, comprising a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a bit line, and the other of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and a first gate structure and a second gate structure, wherein the first gate structure is arranged on a first side of the channel region in the vertical direction, and the second gate structure is arranged on a second side of the channel region opposite to the first side in the vertical direction, and wherein the first gate structure and the second gate structure are staggered from each other in the vertical direction and have no overlapping area.

[0009] According to another aspect of the present disclosure, there is provided an operating method for the above-mentioned DRAM cell structure, comprising: turning on or off a gate transistor by controlling voltages applied to a first gate structure and a second gate structure.

[0010] The DRAM cell structure and operating method disclosed herein provide gate structures on either side of the vertical channel region and control the voltages applied to the two gate structures to turn the gate transistor on or off, thereby reducing leakage current in the gate transistor and improving switching characteristics. Consequently, the DRAM cell structure and operating method disclosed herein extend data storage time, reduce the frequency of interruptions due to refresh operations, and thus reduce power consumption.

[0011] According to one aspect of the present disclosure, a DRAM array structure is provided, comprising: a plurality of DRAM cell structures arranged in M ​​rows and N columns, wherein M and N are natural numbers greater than 1, each of the plurality of DRAM cell structures comprising: a storage capacitor comprising a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a selection transistor comprising: a vertically extending active region comprising a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in a vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and a first gate structure and a second gate structure, wherein the first gate structure is arranged on a first side of the channel region in the vertical direction, and the second gate structure is arranged on a second side of the channel region opposite to the first side in the vertical direction, and wherein the first gate structure and the second gate structure are staggered from each other in the vertical direction and have no overlapping area; N bit lines, respectively connected to the other of the first source / drain region and the second source / drain region of the selection transistor in the N columns of DRAM cell structures; and M+1 word lines, respectively connected to the first gate structure and the second gate structure of the M rows of DRAM cell structures.

[0012] According to another aspect of the present disclosure, a method for operating the above-mentioned DRAM array structure is provided, comprising: controlling the turning on and off of the gate transistors in the plurality of DRAM cell structures by applying a voltage to the word line.

[0013] According to another aspect of the present disclosure, a method for manufacturing the above-mentioned DRAM array structure is provided, comprising: providing a sacrificial layer and an active layer on a substrate; forming a plurality of bit line grooves extending in a column direction in the active layer to define the size of the active area of ​​each DRAM cell structure in a row direction; removing the sacrificial layer through the plurality of bit line grooves and filling a conductive material to form bit lines below the active area of ​​each DRAM cell structure; forming a plurality of alternating first word line grooves and second word line grooves extending in a row direction in the active layer to define the size of the active area of ​​each DRAM cell structure in the row direction; forming a gate dielectric, a word line connected to the first gate structure, and an isolation dielectric in the first word line groove; forming a gate dielectric, a word line connected to the second gate structure, and an isolation dielectric in the second word line groove; and sequentially forming a contact portion and a storage capacitor above the active area of ​​each DRAM cell structure.

[0014] According to the DRAM array structure and its operation method and manufacturing method disclosed in the present invention, by using vertical transistors with two gate structures offset from each other in the vertical direction as selection transistors of the DRAM cell structure, and making adjacent DRAM cell structures share word lines in the column direction, the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors is eliminated, thereby achieving further size reduction.

[0015] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0017] FIG. 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0018] FIG. 2 is a schematic perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0019] FIG. 3 is a schematic top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0020] FIG. 4 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to an embodiment of the present disclosure.

[0021] FIG. 5 is a schematic diagram illustrating an operating method of a DRAM cell structure according to an embodiment of the present disclosure.

[0022] FIG. 6 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0023] FIG. 7 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0024] FIG. 8 is a schematic cross-sectional view in a vertical direction showing a DRAM cell structure according to another embodiment of the present disclosure.

[0025] FIG. 9 is a schematic top view illustrating a DRAM cell structure according to another embodiment of the present disclosure.

[0026] 10A and 10B are schematic top views illustrating DRAM cell structures according to other embodiments of the present disclosure.

[0027] FIG. 11 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in FIG. 1 according to an embodiment of the present disclosure.

[0028] 12A and 12B are top views of a DRAM array structure respectively illustrating a DRAM cell structure including a VCT transistor according to the related art and a transistor having two gate structures sharing a word line according to an embodiment of the present disclosure.

[0029] FIG. 13 is a schematic diagram illustrating an operating method of a DRAM array structure according to an embodiment of the present disclosure.

[0030] 14A to 14R are schematic cross-sectional views respectively illustrating respective process steps of a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment of the present disclosure. As used herein, an "embodiment" is a non-limiting example of a device or method using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be implemented without these specific details or with one or more equivalent configurations. In addition, each exemplary embodiment can be different, but does not have to be exclusive. For example, without departing from the present invention, the specific features of other exemplary embodiments can be used or implemented in some exemplary embodiments.

[0032] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, regions and / or aspects of the various embodiments (hereinafter individually or collectively referred to as "elements") may be combined, separated, interchanged and / or reconfigured without departing from the inventive concept.

[0033] For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0034] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0035] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "a" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "comprise" and / or "comprising" mean that there are stated features, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to account for the inherent deviations in the values ​​measured, calculated and / or provided that are recognized by those of ordinary skill in the art.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0037] The various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be detailed and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the text, the same reference numerals represent the same components. Furthermore, in the drawings, for clarity of illustration, the components are not necessarily drawn to ratio, and the ratios and sizes of the components may be exaggerated.

[0038] FIG1 shows an equivalent circuit diagram of a dynamic random access memory (DRAM) cell structure 100 according to an embodiment of the present disclosure. FIG2 also shows a schematic perspective view of the DRAM cell structure 100 according to an embodiment of the present disclosure, FIG3 shows a schematic top view of the DRAM cell structure 100 according to an embodiment of the present disclosure, and FIG4 shows a schematic vertical cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure. It should be noted that FIG4 is a schematic vertical cross-sectional view taken along line AA′ in FIG3 .

[0039] As shown in FIG1 , a DRAM cell structure 100 according to an embodiment of the present disclosure may include a storage capacitor C and a gate transistor T (as shown in a dotted box). As shown in FIG1 to FIG4 , according to an embodiment of the present disclosure, the gate transistor T may include a vertically extending active region 101, which includes a first source / drain region 102, a channel region 103, and a second source / drain region 104 arranged in sequence from bottom to top along the vertical direction, wherein the first source / drain region 102 may be connected to a bit line BL, and the second source / drain region may be connected to one electrode (lower electrode) CP1 of the storage capacitor C. According to an embodiment of the present disclosure, the other electrode (upper electrode) CP2 of the storage capacitor C may be connected to a source line SL.

[0040] Although FIG1 shows that the bit line BL, the gate transistor T, the storage capacitor C, and the source line SL are arranged in a vertical direction from bottom to top, the configuration of the DRAM cell structure 100 is not limited thereto. According to an alternative embodiment of the present disclosure, the source line SL, the storage capacitor C, the gate transistor T, and the bit line may also be arranged in a vertical direction from bottom to top. In this embodiment, the second source / drain region 102 may be connected to the bit line BL, the first source / drain region 102 may be connected to the upper electrode CP2 of the storage capacitor C, and the lower electrode CP1 of the storage capacitor C may be connected to the source line SL.

[0041] As shown in Figures 1 to 4, according to an embodiment of the present disclosure, the selection transistor T may further include a first gate structure G1 105 and a second gate structure G2 106, wherein the first gate structure G1 105 may be arranged on a first side of the channel region 103 along the vertical direction, and the second gate structure G2 106 may be arranged on a second side of the channel region 103 opposite to the first side along the vertical direction.

[0042] As shown in Figure 4, according to an embodiment of the present disclosure, the selection transistor T can be a junction-less device, that is, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with the same type. For example, the first source / drain region 102, the channel region 103, and the second source / drain region 104 can be doped with a first doping type. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. However, the present disclosure is not limited to this. According to an alternative embodiment of the present disclosure, the first doping type can be P-type doping, and the second doping type can be N-type doping. According to an embodiment of the present disclosure, the doping concentration of the first source / drain region 102 and the second source / drain region 104 can be higher than the doping concentration of the channel region 103.

[0043] Furthermore, according to an embodiment of the present disclosure, the gate transistor T may also be a junction-type device. That is, different types of doping may be performed on the first source / drain region 102, the channel region 103, and the second source / drain region 104. For example, the first source / drain region 102 and the second source / drain region 104 may be doped with a first doping type, and the channel region 103 may be doped with a second doping type. This will be described in more detail below with reference to FIG. 6 and FIG. 7 .

[0044] As shown in FIG1 , according to an embodiment of the present disclosure, the first source / drain region 102 can be connected to a bit line BL, and the second source / drain region 104 can be connected to one electrode or lower electrode CP1 of the storage capacitor C. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is in a write period, the bit line BL can be connected to a voltage representing data 0 (e.g., ground voltage VSS) or a voltage representing data 1 (e.g., power supply voltage VDD) to store the voltage representing the corresponding data in the storage capacitor C. When the DRAM cell structure 100 is not in a write period, the bit line BL can be connected to an equalization voltage VBLQ. According to an embodiment of the present disclosure, the equalization voltage VBLQ can be, for example, a voltage at the intersection of a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 0 (e.g., ground voltage VSS) and a time-degraded voltage curve when the storage capacitor C stores a voltage representing data 1 (e.g., power supply voltage VDD) (e.g., typically approximately (VDD+VSS) / 2).

[0045] Furthermore, as shown in FIG1 , according to an embodiment of the present disclosure, the other electrode or upper electrode CP2 of the storage capacitor C can be connected to a source line SL. As further described below in conjunction with FIG5 , according to an embodiment of the present disclosure, the source line SL can be connected to a fixed voltage VFF. For example, according to an embodiment of the present disclosure, the fixed voltage VFF can be used as a reference voltage, which is typically half of the power supply voltage VDD, i.e., VFF = 1 / 2 VDD.

[0046] For clarity, the storage capacitor C, the bit line BL, and the source line SL are not shown in FIG. 2 to FIG. 4 .

[0047] In addition, as described above, with reference to Figures 1 to 4, according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a first gate structure G1 105 and a second gate structure G2 106. According to an embodiment of the present disclosure, the first gate structure G1 105 is disposed on a first side of the channel region 103 along a vertical direction (e.g., the left side as shown in Figures 2 and 4), and the second gate structure G2 106 is disposed on a second side of the channel region 103 opposite to the first side along a vertical direction (e.g., the right side as shown in Figures 2 and 4).

[0048] According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 can be formed from the same conductive material. According to an embodiment of the present disclosure, examples of conductive materials used to form the first gate structure G1 105 and the second gate structure G2 106 may include: metals or alloys such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the foregoing metals; metal nitrides such as titanium nitride (TiN); or polysilicon. In addition, according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may include high work function materials, low work function materials, or a combination thereof. The low work function material may have a low work function of approximately 4.5 eV or less, and the high work function material may have a high work function of approximately 4.5 eV or more. For example, the low work function material may include N-type doped polysilicon, and the high work function material may include tungsten, titanium nitride, or a combination thereof. According to an alternative embodiment of the present invention, the first gate structure G1 105 and the second gate structure G2 106 may have a dual work function structure in which a low work function material and a high work function material are combined.

[0049] According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 can be formed of different conductive materials. For example, the first gate structure G1 105 can be formed of a metal-based material such as titanium nitride or tungsten, while the second gate structure G2 106 can be formed of polysilicon. According to an embodiment of the present disclosure, by forming the first gate structure G1 105 and the second gate structure G2 106 with different conductive materials, the work function can be adjusted, thereby adjusting the threshold voltage of the gate transistor T.

[0050] Furthermore, as more clearly shown in Figures 3 and 4 , according to an embodiment of the present disclosure, the gate transistor T of the DRAM cell structure 100 may further include a gate dielectric 109 disposed between the first gate structure G1 105, the second gate structure G2 106, and the channel region 103. In Figure 3 , the first gate structure G1 105 and the adjacent gate dielectric 109 are represented by dashed lines. Furthermore, in Figure 4 , the thickness of the gate dielectric 109 may be represented by d1. According to an embodiment of the present disclosure, the gate dielectric 109 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide may have a dielectric constant of approximately 3.9, and the gate dielectric 109 may include a high-k material having a dielectric constant of approximately 4 or greater. The high-k material used as the gate dielectric 109 may have a dielectric constant of approximately 20 or greater. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to an alternative embodiment of the present invention, the gate dielectric 109 may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0051] Furthermore, as shown in Figures 2 to 4 , according to embodiments of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may be separated from each other by an isolation dielectric 110. As shown in Figures 2 to 4 , according to embodiments of the present disclosure, the isolation dielectric 110 may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, to isolate the first gate structure G1 105 and the second gate structure G2 106 from each other. According to embodiments of the present disclosure, the isolation dielectric 110 may be formed of the same material as or a different material from the gate dielectric 109.

[0052] According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 can have the same size and structure. Furthermore, as shown in Figures 2 and 4 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 can be vertically offset from each other and have no overlapping regions. That is, as shown in Figure 4 , the vertical distance d2 between the upper end of the first gate structure G1 105 and the lower end of the second gate structure G2 106 is greater than zero.

[0053] According to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may have different sizes in the vertical direction. In addition, according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may also have different sizes in the horizontal direction.

[0054] In addition, according to an embodiment of the present disclosure, although not shown, a work function adjustment layer may be formed between the gate dielectric 109 and the first gate structure G1 105 and the second gate structure G2 106 to further adjust the threshold voltage of the gate transistor T.

[0055] Furthermore, according to an embodiment of the present disclosure, although not shown, a doping concentration adjustment layer may be formed at a surface of the channel region 103 overlapping the first gate structure G1 105 and the second gate structure G2 106 to reduce fluctuations in the threshold voltage of the gate transistor T.

[0056] As shown in FIG. 3 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may be formed to have a “[”-shaped cross section in the horizontal direction to obtain a larger control area between the gate structure and the channel region 103 .

[0057] 3 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may have an overhanging portion extending to a third side of the channel region 103 adjacent to the first side (e.g., an upper side of the channel region 103 shown in FIG3 ) and a fourth side opposite to the third side (e.g., a lower side of the channel region 103 shown in FIG3 ).

[0058] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, the gating transistor T can be equivalent to two transistors connected in series, wherein the lower transistor (hereinafter referred to as the “lower transistor”) uses the first gate structure G1 105 as the gate, and the upper transistor (hereinafter referred to as the “upper transistor”) uses the second gate structure G2 106 as the gate. Therefore, according to an embodiment of the present disclosure, the gating transistor T is turned on only when both the upper transistor and the lower transistor are turned on. In addition, according to an embodiment of the present disclosure, the gating transistor T is turned off when at least one of the upper transistor and the lower transistor is turned off.

[0059] Therefore, as shown in FIG1 , according to an embodiment of the present disclosure, by controlling the voltages applied to the first gate structure G1 105 and the second gate structure G2 106, the on and off of the selection transistor T can be controlled, thereby realizing the read, write, and refresh operations of the DRAM cell structure, which will be described in more detail below in conjunction with FIG5 .

[0060] FIG. 5 is a schematic diagram illustrating an operating method of the DRAM cell structure 100 according to an embodiment of the present disclosure.

[0061] In a traditional 1T1C DRAM cell structure, a single transistor is used as a gate transistor to control the formation of a conduction path between the bit line and the storage capacitor. According to an embodiment of the present disclosure, the gate transistor T can be equivalent to two NMOS depletion-mode transistors (i.e., a lower transistor and an upper transistor) connected in series to form a logic AND unit. In other words, only when the upper and lower transistors are turned on at the same time, a conduction path is formed between the storage capacitor C and the bit line BL, thereby performing read, write and refresh operations on the DRAM cell structure. According to an embodiment of the present disclosure, when one of the upper and lower transistors of the gate transistor T is turned on, a conduction path is not formed. In other words, when at least one of the upper and lower transistors of the gate transistor T is turned off, a conduction path is not formed. In addition, according to an embodiment of the present disclosure, when the upper and lower transistors of the gate transistor T are turned off at the same time, leakage is minimized, and data is continuously retained in the storage capacitor C in the form of charge.

[0062] As shown in FIG2 to FIG4, when the gate transistor T is a junction-less device, that is, the active region 101 is entirely formed of the first doping type semiconductor, when no voltage is applied to the first gate structure G1 105 and the second gate structure G2 106, the gate transistor T is in the on state.

[0063] As shown in FIG. 5 , according to an embodiment of the present disclosure, the gate transistor T may be turned on or off by controlling the voltage applied to the first gate structure G1 105 and the second gate structure G2 106 .

[0064] Specifically, as shown in FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is not selected, the first gate structure G1 105 and the second gate structure G2 106 of the gate transistor T may be applied with low voltages VGL1 and VGL2, respectively, to ensure that the gate transistor T is turned off. According to an embodiment of the present disclosure, both low voltages VGL1 and VGL2 may be negative voltages, so that the portion of the channel region 103 between the first gate structure G1 105 and the portion of the channel region 103 between the second gate structure G2 106 are completely pinched off, thereby ensuring that the gate transistor T is turned off while reducing or eliminating leakage current in the off state of the gate transistor T. According to an embodiment of the present disclosure, the low voltages VGL1 and VGL2 applied to the first gate structure G1 105 and the second gate structure G2 106, respectively, may be the same or different.

[0065] Furthermore, as shown in FIG5 , according to an embodiment of the present disclosure, when the DRAM cell structure 100 is selected, high voltages VGH1 and VGH2 can be applied to the first gate structure G1 105 and the second gate structure G2 106 of the gate transistor T, respectively. According to an embodiment of the present disclosure, each of the high voltages VGH1 and VGH2 can be the ground voltage VSS or a positive voltage, so that a conductive path is formed in the channel region 103 near the surface overlapping with the first gate structure G1 105 and the second gate structure G2 106. That is, as shown in FIG5 , according to an embodiment of the present disclosure, by applying the high voltages VGH1 and VGH2 to the first gate structure G1 105 and the second gate structure G2 106 of the gate transistor T, respectively, an "S"-shaped conductive path can be formed near the surface overlapping with the first gate structure G1 105 and the second gate structure G2 106 of the channel region 103, as indicated by arrows in FIG5 , thereby turning on the gate transistor T. According to an embodiment of the present disclosure, the high voltages VGH1 and VGH2 respectively applied to the first gate structure G1 105 and the second gate structure G2 106 may be the same as or different from each other.

[0066] FIG6 shows a schematic vertical cross-sectional view of a DRAM cell structure 200 according to another embodiment of the present disclosure. Components in FIG6 identical to those shown in FIG4 are denoted by the same reference numerals. The DRAM cell structure 200 shown in FIG6 differs from the DRAM cell structure 100 shown in FIG4 in that, in FIG6 , the gate transistor T is a junction device.

[0067] As shown in FIG6 , according to an embodiment of the present disclosure, the first source / drain region 102 and the second source / drain region 104 of the active region 101 of the gate transistor T of the DRAM cell structure 200 are formed of a first doping type semiconductor, and the channel region 103 can be formed of a second doping type semiconductor. According to an embodiment of the present disclosure, the first doping type can be N-type doping, and the second doping type can be P-type doping. In this case, the gate transistor T can be an NMOS enhancement-mode transistor.

[0068] The operating method of the DRAM cell structure 100 described above with reference to FIG5 can also be applied to the DRAM cell structure 200 shown in FIG6 , that is, the high voltages VGH1 and VGH2 can be applied to the first gate structure G1 105 and the second gate structure G2 106 respectively, so that the gate transistor T is turned on (as shown by the arrow in FIG6 ).

[0069] Unlike the DRAM cell structure 100 shown in FIG4 , the gate transistor T in the DRAM cell structure 200 of FIG6 is a junction-type device. Therefore, when no voltage is applied to the first gate structure G1 105 and the second gate structure G2 106, the gate transistor T is in an off state. Therefore, in the DRAM cell structure 200 shown in FIG6 , the low voltages VGL1 and VGL2 can both be, for example, the ground voltage VSS, and the high voltages VGH1 and VGH2 can both be positive voltages greater than the threshold voltage.

[0070] In addition, as shown in Figure 6, according to an embodiment of the present disclosure, in order to ensure that the inversion zone formed near the lower end of the second gate structure G2 106 in the channel region 103 overlaps with the inversion zone formed near the upper end of the first gate structure G1 105 (as shown in the shaded area in Figure 6), thereby forming a conductive path in the region corresponding to the spacing d2 in the channel region 103, at least one of the following conditions should be met: the spacing d2 is sufficiently small, the high voltages VGH1 and VGH2 applied to the first gate structure G1 105 and the second gate structure G2 106, respectively, are sufficiently large, and the size w of the channel region 103 in the horizontal direction is sufficiently small.

[0071] FIG7 shows a schematic vertical cross-sectional view of a DRAM cell structure 300 according to another embodiment of the present disclosure. Components in FIG7 identical to those shown in FIG6 are denoted by the same reference numerals. As shown in FIG7 , the DRAM cell structure 300 shown in FIG7 is identical to the DRAM cell structure 200 shown in FIG6 , except that a third source / drain region 111 formed of a semiconductor of the first doping type is provided at a position corresponding to the spacing d2 in the channel region 103 of the gate transistor T. In this case, the active region 101 includes a first source / drain region 102, a second source / drain region 104, a third source / drain region 111 provided between the first source / drain region 102 and the second source / drain region 104, and a channel region 103. According to an embodiment of the present disclosure, the first doping type may be N-type doping, and the second doping type may be P-type doping. In this case, as shown in FIG7 , the gate transistor T can be considered to be composed of two NMOS enhancement-mode transistors connected in series, one above the other.

[0072] The operating method of the DRAM cell structure 100 described above with reference to FIG5 can also be applied to the DRAM cell structure 300 shown in FIG7 , that is, the high voltages VGH1 and VGH2 can be applied to the first gate structure G1 105 and the second gate structure G2 106 respectively, so that the gate transistor T is turned on (as shown by the arrows in FIG7 ).

[0073] Unlike the DRAM cell structure 100 shown in FIG4 , the gate transistor T in the DRAM cell structure 300 of FIG7 is a junction-type device. Therefore, when no voltage is applied to the first gate structure G1 105 and the second gate structure G2 106, the gate transistor T is in an off state. Therefore, in the DRAM cell structure 300 shown in FIG7 , the low voltages VGL1 and VGL2 can both be, for example, the ground voltage VSS, and the high voltages VGH1 and VGH2 can both be a positive voltage greater than the threshold voltage.

[0074] In addition, as shown in Figure 7, according to an embodiment of the present disclosure, since an N-type doped third source / drain region 111 is provided at a position corresponding to the spacing d2 in the channel region 103, even if the conditional restrictions for forming a conductive path described above in conjunction with Figure 6 are not met, a conductive path can be formed in the channel region 103 via the third source / drain region 111 (as shown by the arrow in Figure 7).

[0075] Furthermore, according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 of the gate transistor T of the DRAM cell structure 100 may have different structures from each other.

[0076] FIG8 illustrates a schematic vertical cross-sectional view of a DRAM cell structure 400 according to another embodiment of the present disclosure. Components in FIG8 identical to those shown in FIG4 are denoted by the same reference numerals. As shown in FIG8 , the DRAM cell structure 400 shown in FIG8 is identical to the DRAM cell structure 100 shown in FIG4 , except for the structure of the first gate structure G1 105.

[0077] As shown in FIG8 , according to an embodiment of the present disclosure, in the gate transistor T of the DRAM cell structure 400, the second gate structure G2 106 can have a uniform structure, i.e., all formed from the same material, such as polysilicon, while the first gate structure G1 105 can have a stacked structure. As shown in FIG10 , according to an embodiment of the present disclosure, the first gate structure G1 105 can include upper and lower layers of gate material, for example, the lower gate material can be formed from polysilicon, and the upper gate material can be formed from titanium nitride. This arrangement allows the work function to be adjusted, thereby adjusting the threshold voltage of the gate transistor T.

[0078] Furthermore, those skilled in the art will recognize that, although not shown in FIG10 , according to embodiments of the present disclosure, the first gate structure G1 105 may be formed to have a uniform structure, and the second gate structure G2 106 may be formed to have a stacked structure. All of these variations are intended to fall within the scope of the present disclosure.

[0079] FIG. 9 is a schematic top view illustrating a DRAM cell structure according to another embodiment of the present disclosure.

[0080] As shown in FIG9 , similar to FIG3 , according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may also have protruding portions extending to a third side of the channel region 103 adjacent to the first side (e.g., the upper side of the channel region 103 shown in FIG3 ) and a fourth side opposite the third side (e.g., the lower side of the channel region 103 shown in FIG3 ). Unlike FIG3 , in FIG9 , according to an embodiment of the present disclosure, since the first gate structure G1 105 and the second gate structure G2 106 do not have an overlapping region in the vertical direction, the protruding portions of the first gate structure G1 105 and the protruding portions of the second gate structure G2 106 may have an overlapping region in the horizontal direction. As shown in FIG9 , the length d3 of the horizontal overlapping region of the protruding portions of the first gate structure G1 105 and the second gate structure G2 106 may be greater than zero.

[0081] 10A and 10B illustrate schematic top views of DRAM cell structures according to other embodiments of the present disclosure. Components in FIG. 10A and FIG. 10B identical to those shown in FIG. 3 are denoted by the same reference numerals. As shown in FIG. 10A and FIG. 10B , the DRAM cell structure shown in FIG. 10A and FIG. 10B is identical to the DRAM cell structure 100 shown in FIG. 3 , except that the horizontal cross-sectional shapes of the first gate structure G1 105 and the second gate structure G2 106 are different.

[0082] 10A , unlike the first gate structure G1 105 and the second gate structure G2 106 shown in FIG3 , which are formed to have a “[”-shaped cross section in the horizontal direction, the first gate structure G1 105 and the second gate structure G2 106 in FIG10A are formed to have a “|”-shaped cross section in the horizontal direction.

[0083] Specifically, unlike Figure 3, as shown in Figure 10A, according to an embodiment of the present disclosure, the first gate structure G1 105 and the second gate structure G2 106 may not have an overhanging portion extending to the third side of the channel region 103 adjacent to the first side (for example, the upper side of the channel region 103 shown in Figure 3) and the fourth side opposite to the third side (for example, the lower side of the channel region 103 shown in Figure 3).

[0084] 10B , unlike the first gate structure G1 105 and the second gate structure G2 106 shown in FIG3 , which are formed to have a “[”-shaped cross section in the horizontal direction, the first gate structure G1 105 and the second gate structure G2 106 in FIG10B are formed to have an “L”-shaped cross section in the horizontal direction.

[0085] Specifically, different from FIG. 3, as shown in FIG. 10B, according to an embodiment of the present disclosure, the first gate structure G1 105 may have an overhanging portion extending to the fourth side adjacent to the first side of the channel region 103 (e.g., the lower side of the channel region 103 shown in FIG. 3), and the second gate structure G2 106 may have an overhanging portion extending to the third side adjacent to the second side of the channel region 103 and opposite to the fourth side (e.g., the upper side of the channel region 103 shown in FIG. 3). In addition, although not shown in FIG. 10B, according to an embodiment of the present disclosure, since the first gate structure G1 105 and the second gate structure G2 106 do not have an overlapping region in the vertical direction, the overhanging portion of the first gate structure G1 105 and the second gate structure G2 106 may have an overlapping region in the horizontal direction, and the overhanging portion of the second gate structure G2 106 and the first gate structure G1 105 may have an overlapping region in the horizontal direction.

[0086] According to the DRAM cell structure and its operation method of the present disclosure, the leakage current of the select transistor can be reduced, thereby improving the switching characteristics.

[0087] FIG. 11 shows an equivalent circuit diagram of a DRAM array structure 500 formed by the DRAM cell structure 100 shown in FIG. 1 according to an embodiment of the present disclosure. As shown in FIG. 11, according to an embodiment of the present disclosure, the DRAM array structure 500 may include a plurality of DRAM cell structures 100 shown in FIG. 1, where some reference numerals inside each DRAM cell structure 100 are omitted for clarity.

[0088] According to an embodiment of the present disclosure, the plurality of DRAM cell structures included in the DRAM array structure 500 may be arranged in an array of M rows and N columns, where M and N are natural numbers greater than 1. According to an embodiment of the present disclosure, the row selection operation of the plurality of DRAM cell structures included in the DRAM array structure 500 may be performed by M + 1 word lines WL0 to WLM, and the column selection operation may be performed by N bit lines.

[0089] It should be noted that for ease of description, FIG. 11 only shows the nth column DRAM cell structure of the DRAM array structure 500 that can be selected by the nth bit line BLn (n is a positive integer, and 0 < n ≤ N). As shown in FIG. 11, according to an embodiment of the present disclosure, the nth column DRAM cell structure of the DRAM array structure 500 may include M DRAM cell structures CELL1n to CELLMn, where each DRAM cell CELLmn includes a storage capacitor Cmn and a select transistor Tmn (m is a positive integer, and 0 < m ≤ M; n is a positive integer, and 0 < n ≤ N).

[0090] According to an embodiment of the present disclosure, a row selection operation of M DRAM cell structures CELL1n to CELLMn in the nth column of the DRAM cell structure can be performed via M+1 word lines WLm (m is an integer, and 0≤m≤M). As shown in FIG11 , according to an embodiment of the present disclosure, the M+1 word lines WL0 to WLM are respectively connected to the first gate structure G1 and the second gate structure G2 of the nth column of the DRAM cell structure. Specifically, as shown in FIG11 , word line WL0 is connected to the second gate structure G2 of the gate transistor T1n of the DRAM cell structure CELL1n, word line WL1 is connected to the first gate structure G1 of the gate transistors T1n and T2n of the DRAM cell structures CELL1n and CELL2n, and word line WL2 is connected to the second gate structure G2 of the gate transistors T2n and T3n of the DRAM cell structures CELL2n and CELL3n. Similarly, word line WLM is connected to the first gate structure G1 of the gate transistor TMn of the DRAM cell structure CELLMn.

[0091] According to an embodiment of the present disclosure, N columns of DRAM cell structures may be connected together through M+1 word lines WL0 to WLM, thereby forming a DRAM array structure 500 including M rows and N columns, ie, M×N DRAM cell structures.

[0092] As shown in FIG11 , according to an embodiment of the present disclosure, the M×N DRAM cell structures included in the DRAM array structure 500 can be arranged in mirror-symmetry along the column direction. That is, as shown in FIG11 , each DRAM cell structure is mirror-symmetric relative to its adjacent DRAM cell structures in the column direction. Taking the DRAM cell structure CELL2n shown in FIG11 as an example, its gate transistor T2n is mirror-symmetric with the gate transistor T1n of the adjacent DRAM cell structure CELL1n, i.e., the first gate structure G1 of the gate transistor T2n is adjacent to the first gate structure G1 of the gate transistor T1n. Furthermore, the gate transistor T2n of the DRAM cell structure CELL2n is also mirror-symmetric with the gate transistor T3n of the adjacent DRAM cell structure CELL3n, i.e., the second gate structure G2 of the gate transistor T2n is adjacent to the second gate structure G2 of the gate transistor T3n.

[0093] According to an embodiment of the present disclosure, such a configuration is adopted so that DRAM cell structures in adjacent rows share a word line WLm in the column direction. For example, as shown in FIG11 , in the column direction, the DRAM cell structure CELL2n shares a word line WL1 with the adjacent DRAM cell structure CELL1n, and shares a word line WL2 with the adjacent DRAM cell structure CELL3n. In other words, as shown in FIG11 , according to an embodiment of the present disclosure, in the column direction, the first gate structure of the first side of the gating transistor of the DRAM cell structure shares a word line with the first gate structure of the first side of the gating transistor of its adjacent DRAM cell structure, and the second gate structure of the second side of the gating transistor of the DRAM cell structure shares a word line with the second gate structure of the second side of the gating transistor of its adjacent DRAM cell structure. In particular, according to an embodiment of the present disclosure, each DRAM cell structure of the DRAM cell array 500 is connected to two word lines arranged on both sides thereof.

[0094] According to the embodiments of the present disclosure, since adjacent DRAM cell structures in the column direction share word lines, the isolation between word lines formed by connecting the gate structures of adjacent DRAM cell structures can be omitted, thereby further improving the size miniaturization of the DRAM array structure compared to the vertical channel transistor (VCT) of the prior art.

[0095] 12A and 12B respectively illustrate top views of a DRAM array structure including a VCT transistor according to the prior art and a DRAM cell structure of a transistor having two gate structures sharing a bit line according to an embodiment of the present disclosure.

[0096] As shown in FIG12A , in the column direction, word lines formed by connecting gate structures of VCT transistors according to the prior art require isolation via an isolation dielectric, which occupies additional area. In contrast, as shown in FIG12B , in the column direction, transistors having two vertically offset gate structures according to an embodiment of the present disclosure share word lines with adjacent transistors having the same gate structure, thereby eliminating isolation between word lines. Consequently, the DRAM array structure shown in FIG12B achieves further size reduction compared to the DRAM array structure shown in FIG12A .

[0097] In fact, according to the embodiment of the present disclosure, compared with the DRAM array structure implemented by the VCT transistor according to the prior art, the DRAM array structure implemented by the transistor with two gate structures offset from each other in the vertical direction according to the embodiment of the present disclosure changes the word line isolation in the horizontal direction to the word line isolation in the vertical direction, thereby achieving further size reduction.

[0098] The following describes the operating method of the DRAM array structure 500 according to an embodiment of the present disclosure based on Figure 11 in combination with Figure 5 and Figure 13. Figure 13 shows a schematic diagram of the operating method of the DRAM array structure 500 according to an embodiment of the present disclosure.

[0099] According to an embodiment of the present disclosure, the gate transistor in each DRAM cell structure in the DRAM array structure 500 is a transistor having two gate structures, which, as described above, can be equivalent to two upper and lower transistors connected in series. As described above with reference to FIG5 , by controlling the voltage applied to the two gate structures of the gate transistor, the gate transistor can be controlled to be turned on and off, thereby connecting or disconnecting the conductive path from the bit line of the corresponding DRAM cell structure to the storage capacitor.

[0100] 5 , 11 and 13 , according to an embodiment of the present disclosure, for each DRAM cell structure in the DRAM array structure 500 , as described above, the conduction and shutoff of the selection transistor can be controlled by controlling the voltage applied to the first gate structure and the second gate structure of the selection transistor in the DRAM cell structure, that is, the voltage applied to the two word lines connected thereto.

[0101] 5 , 11 and 13 , taking the case where the DRAM cell structure CELL2n in the 2nd row and nth column shown in FIG11 is selected as an example, when the DRAM cell structure CELL2n is selected, a high voltage VGH is applied to the word lines WL1 and WL2 of the first gate structure G1 and the second gate structure G2 of the selection transistor T2n in the DRAM cell structure CELL2n, respectively, so that the selection transistor T2n is turned on (as indicated by the arrow in the DRAM cell structure CELL2n in FIG11 ).

[0102] According to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share a word line, the first gate structure G1 of the gate transistor T1n of the DRAM cell structure CELL1n in the 1st row and nth column, which is also connected to the word line WL1, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T1n of the DRAM cell structure CELL1n, which is close to the first gate structure G1 (as indicated by the arrow in the DRAM cell structure CELL1n in FIG11 ). However, as shown in FIG13 , according to an embodiment of the present disclosure, since the word line WL0 connected to the second gate structure G2 of the DRAM cell structure CELL1n is applied with a low voltage VGL, the upper transistor of the gate transistor T1n is turned off, and thus the gate transistor T1n of the DRAM cell structure CELL1n as a whole remains turned off.

[0103] Similarly, according to an embodiment of the present disclosure, since adjacent DRAM cell structures in the column direction share a word line, the second gate structure G2 of the gate transistor T3n of the DRAM cell structure CELL3n in the 3rd row and nth column, which is also connected to the word line WL2, is also applied with a high voltage VGH, thereby forming a conductive path near the surface of the channel region of the gate transistor T3n of the DRAM cell structure CELL3n, which is close to the second gate structure G2 (as indicated by the arrow in the DRAM cell structure CELL3n in FIG11). However, as shown in FIG13, according to an embodiment of the present disclosure, since the word line WL3 connected to the first gate structure G1 of the DRAM cell structure CELL3n is applied with a low voltage VGL, the lower transistor of the gate transistor T3n is turned off, and thus the gate transistor T3n of the DRAM cell structure CELL3n as a whole remains turned off.

[0104] 11 and 13 , according to an embodiment of the present disclosure, by controlling the voltages applied to the word lines WL1 and WL2 , the DRAM cell structure CELL2 n can be turned on and off without affecting the operations of other DRAM cell structures.

[0105] Therefore, as shown in Figures 11 and 13, according to the embodiments of the present disclosure, the conduction and shutoff of the gate transistor in the DRAM cell structure can be controlled by the voltage applied to the word line. Specifically, according to the embodiments of the present disclosure, for each DRAM cell structure in the DRAM array structure 500, the conduction and shutoff of the gate transistor of the DRAM cell structure can be controlled by controlling the voltage applied to its first gate structure and second gate structure via two word lines.

[0106] The following will describe a method for manufacturing a DRAM array structure according to an embodiment of the present disclosure in conjunction with Figures 14A to 14R. Figures 14A to 14R respectively show schematic cross-sectional views of various process steps of the method for manufacturing a DRAM array structure according to an embodiment of the present disclosure. It should be noted that Figures 14A to 14G are cross-sectional views taken in the row direction of the DRAM array structure, that is, the word line direction, wherein the bit line direction is perpendicular to the paper plane and the word line direction is parallel to the paper plane, while Figures 14H to 14R are cross-sectional views taken in the column direction of the DRAM array structure, that is, the bit line direction, wherein the word line direction is perpendicular to the paper plane and the bit line direction is parallel to the paper plane.

[0107] In the following description, the materials for each layer are exemplified. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description of "selectively etching B (relative to A)" indicates that the etching recipe used can primarily affect B, with little or no effect on A or other material layers exposed to the etching recipe when etching B (in the absence of explicit mention of A or only a portion of such material layers). Based on this description, those skilled in the art will understand how to select the materials for each layer, and are not limited to the materials exemplified herein.

[0108] As shown in FIG14A , according to an embodiment of the present disclosure, a substrate 1401 may be provided, and a well region 1402 may be formed on the substrate 1401 by, for example, an ion implantation process. According to an embodiment of the present disclosure, the substrate 1401 may be a P-type silicon substrate, and the well region 1402 may be an N-type well region. However, according to an embodiment of the present disclosure, the substrate 1401 may also be a substrate of other forms, including but not limited to a bulk semiconductor material substrate such as a bulk silicon substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a silicon-germanium (SiGe) substrate, etc. Alternatively, the substrate 401 may also be an N-type silicon substrate, and the well region 402 may be a P-type well region.

[0109] Subsequently, as shown in FIG14B , according to an embodiment of the present disclosure, a sacrificial layer 1403 and an active layer 1404 may be sequentially grown on the well region 1402 by, for example, an epitaxial process. According to an embodiment of the present disclosure, the sacrificial layer 1403 may be formed of a silicon germanium material having an etch selectivity, such as silicon germanium (SiGe) or germanium (Ge). According to an embodiment of the present disclosure, the sacrificial layer 1403 may be used to form a conductor line serving as a bit line in a subsequent process step. According to an embodiment of the present disclosure, the active layer 1404 may include a semiconductor material, such as silicon (Si).

[0110] According to an embodiment of the present disclosure, the active layer 1404 may be in-situ doped when grown, for example, by an epitaxial process. It should be noted that according to an embodiment of the present disclosure, the active layer 1404 may be used to form, in subsequent process steps, the active region 101 of the gate transistor T of the DRAM cell structure 100 described above with reference to FIG. 2 to FIG. 4 , which may include the first source / drain region, the second source / drain region, and a channel region therebetween.

[0111] As described above, according to embodiments of the present disclosure, the gating transistor T may be a junctionless device, in which case the active layer 1404 may be doped with the same type of doping, such as N-type doping. Furthermore, according to embodiments of the present disclosure, the gating transistor T may also be a junction-type device, in which case the active layer 1404 may be doped with different types of doping. For example, the lower and upper portions of the active layer 1404 may be doped with N-type to form first and second source / drain regions of the gating transistor T, respectively, and the middle portion of the active layer 1404 may be doped with P-type to form a channel region. For clarity, this description is based on the example of a junctionless gating transistor T.

[0112] Alternatively, although not shown, the active layer 1404 may also include a plurality of semiconductor material layers sequentially disposed on the sacrificial layer 1404, such as a first semiconductor layer for forming a first source / drain region of the gate transistor T, a second semiconductor layer for forming a channel region of the gate transistor T, and a third semiconductor layer for forming a second source / drain region of the gate transistor T. These semiconductor layers may be doped with different types or concentrations as needed.

[0113] Subsequently, as shown in FIG14C , according to an embodiment of the present disclosure, a hard mask layer may be formed on the active layer 1404 by, for example, a deposition process, and then patterned and etched to form a first hard mask stopper 1407. According to an embodiment of the present disclosure, the first hard mask stopper 1407 may include, for example, silicon oxide, silicon nitride, silicon glass, polysilicon, amorphous silicon, or a combination thereof. It should be noted that the first hard mask stopper 1407 shown in FIG14C extends along the column direction (i.e., perpendicular to the paper), i.e., the bit line direction.

[0114] Subsequently, according to an embodiment of the present disclosure, a first spacer 1405 can be formed on both sides of the first hard mask barrier 1407 through a spacer process to expose a portion of the upper surface of the active layer 1404. It should be noted that, similar to the first hard mask barrier 1407, the first spacer 1405 also extends in the column direction (i.e., perpendicular to the paper), i.e., the bit line direction. According to an embodiment of the present disclosure, the first spacer 1405, which serves as a mask for self-aligned etching in subsequent process steps, can be used to define the size of the active area of ​​the gate transistor of the DRAM cell structure in the row direction.

[0115] Subsequently, according to an embodiment of the present disclosure, the active layer 1404, the sacrificial layer 1403, the well region 1402, and / or a portion of the substrate 1401 may be sequentially self-alignedly etched using, for example, the first hard mask barrier 1407 and the first spacer 1405 as masks through an etching process to form a first trench G1 extending into the substrate 1401. According to an embodiment of the present disclosure, the first trench G1 may extend vertically into the substrate 1401. It should be noted that, according to an embodiment of the present disclosure, the first trench G1 also extends along the column direction (i.e., a direction perpendicular to the paper), i.e., the bit line direction.

[0116] 14D , according to an embodiment of the present disclosure, a first isolation dielectric 1406 may be filled in the first trench G1 by, for example, a deposition process, and the upper surfaces of the first hard mask barrier 1407, the first isolation dielectric 1406, and the first spacer 1405 may be planarized by, for example, a grinding process or an etching process. According to an embodiment of the present disclosure, the first isolation dielectric 1406 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof.

[0117] Subsequently, as shown in FIG14E , according to an embodiment of the present disclosure, the first hard mask stopper 1407 can be removed by, for example, an etching process, and the active layer 1404 can be self-alignedly etched using the first spacer 1405 as a mask to form a second trench G2 that exposes the sacrificial layer 1403. It should be noted that according to an embodiment of the present disclosure, similar to the first trench G1, the second trench G2 also extends along the column direction (i.e., perpendicular to the paper), i.e., the bit line direction. In other words, the first trench G1 is parallel to the second trench G2.

[0118] According to an embodiment of the present disclosure, although not shown, after forming the second groove G2, a protective layer may be formed along the inner surface of the second groove G2 to protect the active area of ​​the gate transistor of the DRAM cell structure in subsequent process steps. According to an embodiment of the present disclosure, the protective layer may include an oxide, such as silicon oxide.

[0119] According to an embodiment of the present disclosure, the first groove G1 and the second groove G2 may be formed respectively by performing two self-aligned etching steps using the first spacer 1405 as a mask.

[0120] Subsequently, according to an embodiment of the present disclosure, the sacrificial layer 1403 may be removed through the second groove G2 by, for example, an etching process.

[0121] Subsequently, as shown in FIG14F , according to an embodiment of the present disclosure, a conductive material layer can be conformally formed along the inner surface of the second groove G2 and the upper surface of the entire semiconductor structure (i.e., the DRAM array structure) by, for example, a deposition process (e.g., atomic layer deposition (ALD)). According to an embodiment of the present disclosure, the conductive material layer can include a metal or alloy, such as cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), palladium (Pd), or alloys of the above metals. In particular, according to an embodiment of the present disclosure, the conductive material layer can include, for example, titanium nitride (TiN).

[0122] Subsequently, according to an embodiment of the present disclosure, a portion of the conductive material layer may be removed by, for example, an etching process to bury a conductor line 1409 in the space left by removing the sacrificial layer 1403 below the active layer 1404. As shown in FIG14F , according to an embodiment of the present disclosure, the conductor line 1409 may be formed into a structure having a mirrored “[”-shaped cross-section. According to an embodiment of the present disclosure, as shown in FIG14F , the opening of the “[”-shaped cross-section of the conductor line formed using the second groove G2 faces the second groove G2, that is, the openings of the “[”-shaped cross-section of the conductor line formed using the same second groove G2 face each other. However, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the conductor line 1409 may also be formed into a structure having a solid rectangular cross-section.

[0123] According to an alternative embodiment of the present disclosure, when the conductive material layer includes metal, silicidation can be performed by, for example, an annealing process, so that metal silicide is formed below the active layer 1404 in the space left by removing the sacrificial layer 1403 through the second groove G2, so that these metal silicides can form conductor lines used as, for example, bit lines.

[0124] According to an embodiment of the present disclosure, the first spacer 1405 used as a mask for self-aligned etching may further define a dimension of a conductor line 1409 used as a bit line in a row direction.

[0125] Subsequently, as shown in FIG14G , according to an embodiment of the present disclosure, the well region 1402 and / or a portion of the substrate 1401 can be etched downward through the second trench G2, for example, by an etching process, so that the second trench G2 extends into the substrate 1401, and the second trench G2 is filled with a second isolation dielectric 1410, for example, by a deposition process. According to an embodiment of the present disclosure, since the first trench G1 and the second trench G2 are formed in different etching process steps, the bottom ends of the first trench G1 and the second trench G2 may or may not be aligned in the vertical direction. According to an embodiment of the present disclosure, the second isolation dielectric 1410 can fill the concave portion of the conductor line 1409 having a "["-shaped cross-section formed by the second trench G2. According to an embodiment of the present disclosure, the second isolation dielectric 1410 can include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the second isolation medium 1410 may be formed of the same material as the first isolation medium 1406 , or may be formed of a different material from the first isolation medium 1406 .

[0126] According to an embodiment of the present disclosure, first trench G1 and second trench G2 extend into substrate 1401 and are respectively filled with non-conductive first isolation dielectric 1406 and second isolation dielectric 1410. Furthermore, a PN junction formed between N-type well region 1402 and P-type substrate 1401 below conductor lines 1409 can isolate conductor lines 1409 from one another from below, reducing the effects of parasitic capacitance between conductor lines 1409. In an embodiment of the present disclosure, buried conductor lines 1409 serving as bit lines are formed by first trench G1 and second trench G2. Therefore, first trench G1 and second trench G2 may also be collectively referred to herein as bit line trenches.

[0127] Through the process steps shown in Figures 14A to 14G, a first groove G1 and a second groove G2 can be formed by two self-aligned etchings using the first sidewall 1405 (and the first hard mask blocking portion 1407) as a mask, so that a buried conductor line 1409 serving as a bit line extending along the column direction (i.e., the direction perpendicular to the paper surface of Figures 14A to 14G) is formed in the DRAM array structure composed of vertical DRAM cell structures, and the size of the active area of ​​the selection transistor of each DRAM cell structure of the DRAM array structure in the row direction is also limited.

[0128] It should be noted that FIG. 14H to FIG. 14R illustrate cross-sectional views of the DRAM array structure taken along line BB′ of FIG. 14G , ie, cross-sectional views in the row direction of the DRAM array structure, ie, in the word line direction.

[0129] Subsequently, as shown in FIG14H , according to an embodiment of the present disclosure, a second hard mask stopper 1418 and a second spacer 1417 are formed on the first spacer 1405, the first isolation dielectric 1406, and the second isolation dielectric 1410 (not shown in FIG14H ), extending in the row direction (i.e., perpendicular to the paper), i.e., the word line direction. According to an embodiment of the present disclosure, the second hard mask stopper 1418 may include, for example, silicon oxide, silicon nitride, silicon glass, polycrystalline silicon, amorphous silicon, or a combination of the foregoing materials. According to an embodiment of the present disclosure, the second hard mask stopper 1418 may have a different etch selectivity than the first spacer 1405 and the second spacer 1417 below it. According to an embodiment of the present disclosure, the second spacer 1417 may have a different etch selectivity than the first spacer 1405. According to an embodiment of the present disclosure, the second spacer 1417 is used to define the size of the active area 101 in the column direction described above with reference to FIG2 to FIG4 .

[0130] Subsequently, as shown in FIG14I , according to an embodiment of the present disclosure, the first spacer 1405 and the active layer 1404 can be etched using, for example, an etching process with the second spacer 1417 as a mask to form a third trench G3. According to an embodiment of the present disclosure, the third trench G3 is used to subsequently form a portion of the word line of the DRAM array structure (e.g., a word line of the first gate structure of the gate transistor of each DRAM cell structure connected to the DRAM array structure). Therefore, the third trench G3 can also be referred to as the first word line trench in this document, which is horizontally perpendicular to the bit line trench. According to an embodiment of the present disclosure, the etching depth of the third trench G3 can be controlled so that its lower end does not extend into the metal bit line 1409 below.

[0131] Subsequently, as shown in FIG. 14J , according to an embodiment of the present disclosure, a third isolation dielectric 1412 a may be formed at the bottom of the third trench G3 by, for example, a deposition process.

[0132] Subsequently, as shown in FIG14K , according to an embodiment of the present disclosure, a gate dielectric 1413 may be formed, for example, by a deposition process, along the surface of the third trench G3 and the upper surfaces of the second hard mask barrier 1418 and the second spacer 1417. According to an embodiment of the present disclosure, the gate dielectric 1413 may correspond to the gate dielectric 109 of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG2 to FIG4 .

[0133] Subsequently, as shown in FIG14L , according to an embodiment of the present disclosure, a conductor line 1414 serving as both a word line and a first gate structure may be formed in the third trench G3 by, for example, a deposition process and an etching process, wherein the conductor line 1414 is separated from the active layer 1404 by a gate dielectric 1413. According to an embodiment of the present disclosure, the conductor line 1414 may simultaneously serve as the first gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with FIG1 to FIG4 , and as a word line connected to the first gate structure described above in conjunction with FIG11 .

[0134] Subsequently, as shown in FIG. 14M , according to embodiments of the present disclosure, a third isolation dielectric 1412 b may be filled in the third trench G3 (i.e., above the gate dielectric 1413 and the conductor line 1414) through, for example, a deposition process to isolate the conductor line 1414. According to embodiments of the present disclosure, the third isolation dielectrics 1412 a and 1412 b may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polycrystalline silicon, or a combination thereof. The third isolation dielectrics 1412 a and 1412 b may be formed of the same material as the first isolation dielectric 1406 and / or the second isolation dielectric 1410, or may be formed of a different material than the first isolation dielectric 1406 and / or the second isolation dielectric 1410. Although collectively referred to as the third isolation dielectric, the dielectric material and thickness of the third isolation dielectrics 1412 a and 1412 b may be the same or different.

[0135] Subsequently, as shown in Figure 14N, according to an embodiment of the present disclosure, the third isolation medium 1412b above can be removed by, for example, a grinding process to expose the second hard mask blocking portion 1418, and the second hard mask blocking portion 1418 and the first side wall 1405 thereunder can be removed by, for example, an etching process using the second side wall 1417 as a mask to expose the active layer 1404.

[0136] Subsequently, as shown in FIG14O , according to an embodiment of the present disclosure, the active layer 1404 exposed by the process step shown in FIG14N can be etched using, for example, an etching process with the second sidewall 1417 as a mask to form a fourth trench G4. According to an embodiment of the present disclosure, the fourth trench G4 is used to subsequently form the remaining word lines of the DRAM array structure (e.g., the word lines of the second gate structure of the gate transistor of each DRAM cell structure of the DRAM array structure). Therefore, the fourth trench G4 can also be referred to as the second word line trench herein, which is parallel to the first word line trench in the horizontal direction and perpendicular to the bit line trench. According to an embodiment of the present disclosure, the etching depth of the fourth trench G4 can be controlled so that its lower end does not extend into the metal bit line 1409 below. In addition, according to an embodiment of the present disclosure, the depth of the fourth trench G4 in the vertical direction can be the same as or different from the depth of the third trench G3. In particular, as shown in FIG14O , the depth of the fourth trench G4 can be less than that of the third trench G3. According to an embodiment of the present disclosure, in order to fully function the first gate structure, the bottom surface of the fourth trench G4 may be located vertically below the bottom surface of the conductor line 1414 formed in the third trench G3 .

[0137] Subsequently, as shown in FIG14P , according to an embodiment of the present disclosure, a fourth isolation dielectric 1421a, a gate dielectric 1415, and a conductor line 1416 can be sequentially formed from bottom to top in the fourth trench G4, for example, by the processes described above with reference to FIG14J to FIG14L . In other words, the second gate structure and word line on the other side of each DRAM cell structure are formed in the fourth trench G4.

[0138] According to an embodiment of the present disclosure, the conductor line 1416 is separated from the active layer 1404 by the gate dielectric 1415. According to an embodiment of the present disclosure, the materials of the fourth isolation dielectric 1421a, the gate dielectric 1415, and the conductor line 1416 can be the same as or different from the materials of the third isolation dielectric 1412a, the gate dielectric 1413, and the conductor line 1414. According to an embodiment of the present disclosure, the conductor line 1416 can also serve as the second gate structure of the gate transistor T of the DRAM cell structure 100 described above in conjunction with Figures 1 to 4, and as a word line connected to the second gate structure as described above in conjunction with Figure 11.

[0139] According to an embodiment of the present disclosure, by adjusting the depth of the third groove G3 and the fourth groove G4 and the thickness in the vertical direction of the third isolation dielectric 1412a formed at the bottom of the third groove G3 and the fourth isolation dielectric 1421a formed at the bottom of the fourth groove G4, the first gate structure (i.e., the word line formed in the first word line groove G3) and the second gate structure (i.e., the word line formed in the second word line groove G4) can be staggered in the vertical direction and have no overlapping parts.

[0140] Subsequently, as shown in FIG14Q , according to an embodiment of the present disclosure, the fourth trench G4 may be filled with a fourth isolation dielectric 1421b, for example, by a deposition process. According to an embodiment of the present disclosure, the fourth isolation dielectrics 1421a and 1421b may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), amorphous silicon, polysilicon, or a combination thereof. The fourth isolation dielectrics 1421a and 1412b may be formed of the same material as the third isolation dielectrics 1412a and 1412b, or may be formed of a material different from the third isolation dielectrics 1412a and 1412b. Although collectively referred to as the fourth isolation dielectric, the dielectric material and thickness of the fourth isolation dielectrics 1421a and 1421b may be the same or different.

[0141] Through the process steps shown in Figures 14H to 14Q, a DRAM array structure is formed, which has a conductor line 1414 extending along the row direction (i.e., a direction perpendicular to the paper surface of Figures 14H to 14Q) and serving as both a word line and a first gate structure, and a conductor line 1416 serving as both a word line and a second gate structure, and the size of the active area of ​​the selection transistor of each DRAM unit structure of the DRAM array structure in the column direction is limited by the second sidewall 1417.

[0142] Subsequently, as shown in FIG. 14R , according to an embodiment of the present disclosure, the second spacer 1417 and the remaining first spacer 1405 may be removed by, for example, an etching process to expose the active layer 1404 .

[0143] Furthermore, as shown in FIG14R , according to an embodiment of the present disclosure, a contact 1419 may be formed on the active layer 1404, and a storage capacitor 1420 may be formed on the contact 1419, thereby forming a DRAM array structure. Since the process steps for forming the storage capacitor are well known to those skilled in the art, they will not be described in further detail herein for the sake of brevity.

[0144] As shown in FIG14R , since adjacent DRAM cell structures in the column direction share word lines, the area overhead for isolating the word lines can be omitted, thereby further achieving size reduction of the DRAM array structure.

[0145] According to the embodiment of the present disclosure, since the gate structures and word lines on both sides of each DRAM cell structure are respectively formed in different grooves (i.e., the third groove G3 (first word line groove) and the fourth groove G4 (second word line groove)), their sizes and positions can be controlled, so that the DRAM cell structure that can be finally formed can have a first gate structure and a second gate structure on both sides that are staggered in the vertical direction and have no overlapping area.

[0146] According to the DRAM array structure and its operation method and manufacturing method disclosed in the present invention, by using vertical transistors with two gate structures offset from each other in the vertical direction as selection transistors of the DRAM cell structure, and making adjacent DRAM cell structures share word lines in the column direction, the inherent spacing area between word lines in the traditional DRAM array structure based on ring-gate transistors is eliminated, thereby achieving further size reduction.

[0147] For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to the embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0148] Although this document contains many details, these details should not be construed as limitations on the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated as such, in some cases one or more features in a combination may be deleted from the claimed combination, and the claimed combination may involve subcombinations or variations of subcombinations.

Claims

1. A dynamic random access memory (DRAM) cell structure, comprising: A storage capacitor, including a first electrode and a second electrode, wherein the second electrode is connected to a source line; and A select transistor, including: An active region extending vertically, including a first source / drain region, a channel region, and a second source / drain region arranged in sequence from bottom to top in the vertical direction, wherein one of the first source / drain region and the second source / drain region is connected to a bit line, and the other of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and A first gate structure and a second gate structure, wherein the first gate structure is arranged on a first side of the channel region in the vertical direction, and the second gate structure is arranged on a second side of the channel region opposite to the first side in the vertical direction, and wherein the first gate structure and the second gate structure are staggered from each other in the vertical direction and do not have an overlapping region.

2. The DRAM cell structure according to claim 1, Among them, The first gate structure and the second gate structure are formed of the same or different materials.

3. The DRAM cell structure according to claim 1, Among them, The first gate structure and the second gate structure have the same or different dimensions.

4. The DRAM cell structure according to claim 1, Among them, The active region is formed of a semiconductor of a first doping type, and wherein the doping concentrations of the first source / drain region and the second source / drain region are greater than or equal to the doping concentration of the channel region.

5. The DRAM cell structure according to claim 1, Among them, The first and second source / drain regions are formed of a semiconductor of a first doping type, and the channel region is formed of a semiconductor of a second doping type.

6. The DRAM cell structure according to claim 7, Among them, The active region further includes a third source / drain region located between the first source / drain region and the second source / drain region in the vertical direction, and the third source / drain region is formed of a semiconductor of a first doping type.

7. The DRAM cell structure according to claim 1, wherein, The first gate structure has extending portions extending to a third side and a fourth side of the channel region adjacent to the first side, and the third side and the fourth side of the channel region are opposite to each other, The second gate structure has extending portions extending to a third side and a fourth side of the channel region adjacent to the second side.

8. The DRAM cell structure according to claim 7, wherein, The extending portions of the first gate structure and the extending portions of the second gate structure overlap each other in the horizontal direction.

9. The DRAM cell structure according to claim 1, wherein, The first gate structure does not have extending portions extending to a third side and a fourth side of the channel region adjacent to the first side, and the third side and the fourth side of the channel region are opposite to each other, and The second gate structure does not have extending portions extending to a third side and a fourth side of the channel region adjacent to the second side.

10. The DRAM cell structure according to claim 1, wherein, The first gate structure has an overhanging portion extending to the third side or the fourth side of the channel region adjacent to the first side, where the third side and the fourth side of the channel region are opposite to each other. The second gate structure has an overhanging portion extending to the fourth side or the third side of the channel region adjacent to the second side.

11. The DRAM cell structure according to claim 10, wherein, the overhanging portion of the first gate structure overlaps with the second gate structure in the horizontal direction, and / or the overhanging portion of the second gate structure overlaps with the first gate structure in the horizontal direction.

12. An operation method for the DRAM cell structure according to any one of claims 1 to 11, comprising: turning on or off the select transistor by controlling the voltages applied to the first gate structure and the second gate structure.

13. A dynamic random access memory DRAM array structure, comprising: a plurality of DRAM cell structures arranged in M rows and N columns, where M and N are natural numbers greater than 1, and each of the plurality of DRAM cell structures includes: a storage capacitor including a first electrode and a second electrode, wherein the second electrode is connected to a source line; and a select transistor, including: an active region extending vertically, including a first source / drain region, a channel region, and a second source / drain region sequentially arranged from bottom to top in the vertical direction, where one of the first source / drain region and the second source / drain region is connected to the first electrode of the storage capacitor; and a first gate structure and a second gate structure, wherein the first gate structure is arranged on the first side of the channel region in the vertical direction, and the second gate structure is arranged on the second side of the channel region opposite to the first side in the vertical direction, and wherein the first gate structure and the second gate structure are staggered from each other in the vertical direction and do not have an overlapping region; N bit lines respectively connected to the other one of the first source / drain region and the second source / drain region of the select transistors in N columns of DRAM cell structures; and M + 1 word lines respectively connected to the first gate structures and the second gate structures of M rows of DRAM cell structures.

14. The DRAM array structure according to claim 13, Among them, the M rows of DRAM cell structures are arranged in mirror symmetry in the column direction such that the DRAM cell structures in adjacent rows share a word line in the column direction.

15. The DRAM array structure according to claim 13, Among them, in each of the plurality of DRAM cell structures, the active region is formed of a semiconductor of a first doping type, and the doping concentrations of the first source / drain region and the second source / drain region are greater than or equal to the doping concentration of the channel region.

16. The DRAM array structure according to claim 13, Among them, in the active region of each of the plurality of DRAM cell structures, the first and second source / drain regions are formed of a semiconductor of a first doping type, and the channel region is formed of a semiconductor of a second doping type.

17. A method for operating the DRAM array structure according to any one of claims 13 to 16, comprising: The conduction and cutoff of the select transistors in the plurality of DRAM cell structures are controlled by the voltage applied to the word lines.

18. A method for manufacturing a DRAM array structure according to any one of claims 13 to 16, comprising: providing a sacrificial layer and an active layer on a substrate; forming a plurality of bit line grooves extending in a column direction in the active layer to define the size of the active region of each DRAM cell structure in a row direction; removing the sacrificial layer through the plurality of bit line grooves and filling with a conductive material to form the bit lines under the active regions of the respective DRAM cell structures; forming a plurality of alternately arranged first word line grooves and second word line grooves extending in a row direction in the active layer to define the size of the active region of each DRAM cell structure in a row direction; forming a gate dielectric, a word line connected to the first gate structure, and an isolation dielectric in the first word line groove; forming a gate dielectric, a word line connected to the second gate structure, and an isolation dielectric in the second word line groove; and forming a contact portion and the storage capacitor in sequence above the active region of each DRAM cell structure.

19. The method according to claim 18, wherein The first word line groove and the second word line groove have different depths in the vertical direction.

20. The method according to claim 18, wherein The isolation dielectric formed at the bottom of the first word line groove and the isolation dielectric formed at the bottom of the second word line groove have different thicknesses.

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