Switch node resonant frequency

Abstract

Provided is an arrangement for determining a switch node resonant frequency of a synchronous converter (i.e. a high frequency buck or boost converter). The arrangement comprises a comparator configured to determine the difference between a peak voltage on a switch node and a voltage on a bus node. A controller is also provided, which, based on the determined difference, adjusts the peak voltage on the switch node to be equal to the voltage on the bus node. This is achieved by controlling a low side gate drive and a high side gate drive to adjust a switching regime of a high side switch and a low side switch of the synchronous converter. In some cases, the switch node resonant frequency may be determined based on the switching frequency of the low side switch when the magnitude of the peak voltage on the switch node just reaches the bus voltage during one switching cycle. By determining the switch node resonant frequency, a feedforward control scheme of the synchronous controller may be implemented with improved efficiency.

Description

[0001] SWITCH NODE RESONANT FREQUENCY

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to the field of synchronous converters, and in particular to determining the switch node resonant frequency of a synchronous converter.

[0004] BACKGROUND OF THE INVENTION

[0005] There are various methods of control of high frequency synchronous converters (e.g., high frequency buck or boost converters). Conventional control schemes operate on a cycle-by-cycle (i.e., event driven) basis in which an output of the converter is compared to thresholds to determine required changes in the switching pattern (e.g. the switching frequency and duty cycle). However, the efficacy of event driven control schemes at high switching frequencies is dependent on delays related to signal propagation, gate driving, inverter transition and comparator operation. Such delays must be reduced as the switching frequency increases.

[0006] For example, microcontroller units (MCUs) are increasingly used for power management, and are often provided with built-in comparators. The built-in comparators may not be capable of computing the comparison in an adequate amount of time to enable effective event driven control schemes. As a result, it is increasingly the case that dedicated and expensive comparators are required to implement cycle-by-cycle control schemes.

[0007] One solution is to use a feedforward (or average) control scheme to operate synchronous converters. Feedforward control schemes rely on time-averaged measurements, and therefore do not require comparators capable of calculating comparison results with sufficient delay within cycles. Feedforward control schemes have been shown to operate high frequency synchronous converters at a minimum loss.

[0008] Feedforward control schemes run most efficiently if parameters of the high frequency synchronous converter are known with a high degree of accuracy. Such parameters are dependent on each individual component of the converter. However, these parameters are the subject of tolerances. One parameter of importance is the resonant frequency of the switch node. If the resonant frequency is known, the switching pattern may be optimized and inverter, inductor, and filter loses may be reduced. Therefore, there exists a need for a means for determining the switch node resonant frequency of a synchronous converter with a high degree of accuracy.

[0009] SUMMARY OF THE INVENTION

[0010] The invention is defined by the claims.

[0011] According to an aspect of the invention, there is provided an arrangement for determining a switch node resonant frequency of a synchronous converter.

[0012] The synchronous converter comprises a high side switch connected between a bus node and a switch node, a low side switch connected between the switch node and ground, a low side gate drive connected to a low voltage power supply and adapted to drive a gate of the low side switch, a high side gate drive connected to the low voltage power supply and adapted to drive a gate of the high side switch, an output inductor connected between the switch node and an output node, and an output capacitor connected between the output node and ground.

[0013] The arrangement comprises: a comparator configured to determine a difference between a peak voltage on the switch node and a voltage on the bus node; a controller configured to adjust the peak voltage on the switch node to be equal to the voltage on the bus node based on the difference by controlling the low side gate drive and the high side gate drive.

[0014] Provided is an arrangement for determining a switch node resonant frequency of a synchronous converter (i.e. a high frequency buck or boost converter). The arrangement comprises a comparator configured to determine the difference between a peak voltage on a switch node and a voltage on a bus node. A controller is also provided, which, based on the determined difference, adjusts the peak voltage on the switch node to be equal to the voltage on the bus node. This is achieved by controlling a low side gate drive and a high side gate drive to adjust a switching regime of a high side switch and a low side switch of the synchronous converter. In some cases, the switch node resonant frequency may be determined based on the switching frequency of the low side switch when the magnitude of the peak voltage on the switch node just reaches the bus voltage during one switching cycle. By determining the switch node resonant frequency, a feedforward control scheme of the synchronous controller may be implemented with improved efficiency.

[0015] In other words, the arrangement provides a comparison of the peak voltage on the switch node, with the voltage on the bus node. From this comparison, the peak voltage on the switch node may be adjusted / controlled by controlling the low side gate drive and the high side gate drive. Controlling the low side gate drive and the high side gate drive results in a control of the switching frequency and / or duty cycle of the low side switch and high side switch respectively, thereby adjusting the peak voltage on the switch node.

[0016] To be clear, the switch node is a node of the synchronous converter that is connected between the high side switch and the low side switch. Thus, if either the high side switch or the low side switch is conducting, the switch node voltage is pulled to a rail (i.e., is either pulled to the bus voltage or ground). If neither switch is conducting (i.e. neither turned on, nor conducting in diode mode), the switch node voltage experiences an oscillation of the resonant circuit formed by the output inductor and the switch node capacitance (i.e., the capacitance formed from the output capacitances of the high side switch and the low side switch). The instantaneous voltage then depends on the capacitance and inductance, the time elapsed since either switch has ended conducting, and the switch node voltage and current at the time either switch ended conducting.

[0017] The voltage on the switch node depends on the switching frequency and duty cycle of both the high side switch and the low side switch, which both determine the initial conditions for the oscillation of the switch node voltage. The switching frequency is the rate at which a switch is alternated from an on-state to an off-state, and back to an on-state. The duty cycle is the percentage of the time during a switching cycle that the switch is in an on- state.

[0018] The controller controls or adjusts the high side gate drive and low side gate drive based on a result of the comparison of the switch node peak voltage and the bus node voltage. That is, the controller generates a control signal for the high side gate drive and the low side gate drive so that a switching regime of the high side switch and low side switch may be altered.

[0019] This may be considered a feedback loop with the aim of causing the peak voltage on the switch node to be equal to the voltage on the bus node, with the adjusting / manipulating value being the switching frequency of the high side switch and the low side switch. Once, the difference is minimized (so that the peak voltage on the switch node and the voltage on the bus node are substantially equal at one instant in a switching cycle), the switching frequency may be used to derive the switch node resonant frequency.

[0020] Once the switch node resonant frequency is known, a feedforward control scheme of the synchronous converter may be implemented in an efficient manner. While the switch node resonant frequency may be derived from various known parameters of the synchronous converter, the parameters of each element of the synchronous converter are subject to tolerances and may also depend on the operation conditions. Therefore, the degree of accuracy by which the switch node resonant frequency may be calculated is reduced if merely based on specifications provided by the manufacturer. In contrast, embodiments of the invention enable the switch node resonant frequency to be directly measured without dependence on various tolerances. Further, embodiments of the invention implicitly account for the dependence of the parameters on the operation conditions.

[0021] In some embodiments, the controller may be configured to operate in a second control mode in which the controller is configured to control the high side gate drive to cause the high side switch to remain in an off-state; and control the low side gate drive to adjust a switching frequency of the low side switch based on the difference.

[0022] Put another way, the high side switch is kept in an off-state while only the low side switch continues switching. In this case, the manipulating value to reduce the difference (i.e. to cause the peak voltage on the switch node to be equal to the voltage on the bus node) is the switching frequency of the low side switch.

[0023] When the controller is in the second control mode, the high side switch, low side switch, output inductor and output capacitor essentially act as a boost converter. That is, the inductor is charged when the low side switch is in an on-state, and when the low side switch is in an off-state, the voltage on the switch node is equal to the voltage across the inductor added to the voltage across the capacitor. Accordingly, if the switching frequency is controlled correctly, the voltage on the switch node when the low side switch is in an off- state may increase to the same magnitude as the bus voltage.

[0024] An initial switching frequency of the low side gate drive may be based on a rated resonant frequency value of the synchronous converter.

[0025] That is, initially when in the second control mode the controller controls the low side gate drive to drive the low side switch at an initial switching frequency based on the rated resonant frequency value. This acts as an approximation for the real value, such that adjustments to the switching frequency may not need to be large for the difference to be minimized. Accordingly, the switching frequency at which the difference is small may be determined quickly.

[0026] The controller may be further configured, responsive to the difference during at least one cycle of the low side switch falling below a predetermined threshold amount and the difference during the at least one cycle being zero for a predetermined maximum amount of time, to output the switching frequency of the low side switch. In other words, the switching frequency is output when (i) the peak voltage on the switch node is not saturated (e.g., equal to the bus node); and (ii) the difference falls below a predetermined threshold. This means that the voltage on the switch node only peaks instantaneously, but also peaks within a small margin (i.e. the predetermined threshold amount), for example a few volts.

[0027] In some embodiments, the arrangement may further comprise a processor configured to determine the switch node resonant frequency based, at least in part, on the output switching frequency.

[0028] Accordingly, the switch node resonant frequency may be directly determined by the arrangement based on the switching frequency when the above criteria are satisfied.

[0029] The processor may be configured to determine the switch node resonant frequency further based on a voltage on the output node and the voltage on the bus node.

[0030] The actual resonant frequency of the switch node, in some cases, can be accurately derived from said output switching frequency, the voltage on the output node, and the voltage on the bus node.

[0031] In some embodiments, the controller may be configured to operate in the second control mode responsive to a voltage across the output capacitor satisfying a predetermined condition.

[0032] That is, the controller may only operate in the second control mode when the output capacitor is charged adequately. For example, the predetermined condition may be satisfied when the voltage across the output capacitor reaches 10-20% of the voltage on the bus node.

[0033] According to some embodiments, the controller may be configured to operate in a first control mode in which the controller is configured to control a load connected to the output so that no current flows into the load; and control the high side gate drive and the low side gate drive to increase a voltage on the output node to a target voltage.

[0034] The controller operating in the first control mode enables charging of the output capacitor. This may fulfil the predetermined condition outlined above. In other words, the controller controls the high side gate drive and the low side gate drive in such a way (i.e. control the gate drives to drive the switches) that the high side switch and the low side switch provide a voltage for charging the output capacitor.

[0035] As no current flows into the load (e.g., because the voltage is less than the voltage required by the load, such as an LED load), the load is not driven. Accordingly, the control modes of the controller disclosed herein may be implemented during use of the synchronous converter. That is, the disclosed means for determining the switch node resonant frequency may be employed even when the synchronous converter is deployed rather than requiring factory testing and reconfiguration.

[0036] Of course, factory testing may still be employed. In this case, a large capacitor may be provided in place of a deployed load to relax timing requirements for the second control mode. Alternatively, a voltage source may be provided in place of a deployed load to relax timing requirements and negate the need to charge an output capacitor.

[0037] In one example implementation, the comparator may comprise a PNP transistor having a base connected to the bus node; a diode and a resistor connected in series between the switch node and an emitter of the PNP transistor; and an output node connected to a collector of the PNP transistor.

[0038] One implementation of the comparator is the use of a transistor, diode and resistor arranged so as to sense a difference between the bus node and the peak voltage on the switch node. The sensed difference is provided on the output node of the comparator.

[0039] Furthermore, the comparator may also comprise a capacitor connected between the base of the PNP transistor and the emitter of the PNP transistor.

[0040] Also, the comparator may further comprise a level shifter configured to attenuate a voltage on the output node of the comparator. The level shifter converts the voltage on the output node, originally referenced to the bus voltage, to be referenced to ground. In some cases, the PNP transistor may be considered to be part of the level shifter.

[0041] The voltage outputted by the level shifter may be of a magnitude that can be processed with typical control circuitry.

[0042] Specifically, the level shifter may comprise a high side resistor connected between the output node of the comparator and a voltage sensing output node; and a low side resistor connected between the voltage sensing output node and ground.

[0043] In some embodiments, the high side gate drive may be connected to the low voltage power supply via a bootstrap circuit. In this case, the comparator may be connected to the switch node via the bootstrap circuit. In particular, the bootstrap circuit may comprise a diode connecting the low voltage power supply to a bootstrap node, the high side gate drive connected to the bootstrap node, and a bootstrap capacitor connecting the bootstrap node to the switch node, and wherein the comparator is connected to the switch node via the bootstrap node.

[0044] Advantageously, by providing the bootstrap circuit, the voltage on the bus node will be compared to a slightly reduced switch node voltage. The reduction may only be, for example, a few volts and is dependent on the voltage across the bootstrap capacitor minus the voltage across the transistor and resistor of the comparator. This allows detection of the switch node voltage approaching the bus voltage by a few volts, which may prevent the circuit entering a boost mode too early (e.g., while the control is settling) avoiding a rapid discharge of the output capacitor.

[0045] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment s) described hereinafter.

[0046] BRIEF DESCRIPTION OF THE DRAWINGS

[0047] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0048] Fig. l is a circuit diagram of a synchronous converter with a comparator according to an aspect of the invention;

[0049] Fig. 2 is a graph depicting a relationship between a voltage on the switch node, and an output inductor current over time responsive to the low side switch switching to an off-state during the second control mode of the controller;

[0050] Fig. 3 is a simplified block diagram of a control loop for a switching regime of high and low switches of a synchronous converter according to another aspect of the invention;

[0051] Fig. 4 is a simplified block diagram of the operation of a switching frequency control and pulse width modulation element of the control loop depicted in Fig. 3;

[0052] Fig. 5 presents graphs depicting waveforms of different aspects of the synchronous converter when the controller is in a second operation mode according to an aspect of the invention;

[0053] Fig. 6 also presents graphs depicting waveforms of different aspects of the synchronous converter when the controller is in a second operation mode according to another aspect of the invention; and

[0054] Fig. 7 presents graphs depicting waveforms of different aspects of the synchronous converter when the controller is in a second operation mode, and when the peak voltage on the switch node just reaches the voltage on the bus node.

[0055] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] The invention will be described with reference to the Figures. It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims, and accompanying drawings. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts.

[0057] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. If the term "adapted to" is used in the claims or description, it is noted the term "adapted to" is intended to be equivalent to the term "configured to".

[0058] According to proposed concepts, a number of possible solutions may be implemented separately or jointly. That is, although these possible solutions may be described below separately, two or more of these possible solutions may be implemented in one combination or another.

[0059] Provided is an arrangement for determining a switch node resonant frequency of a synchronous converter (i.e. a high frequency buck or boost converter). The arrangement comprises a comparator configured to determine the difference between a peak voltage on a switch node and a voltage on a bus node. A controller is also provided, which, based on the determined difference, adjusts the peak voltage on the switch node to be equal to the voltage on the bus node. This is achieved by controlling a low side gate drive and a high side gate drive to adjust a switching regime of a high side switch and a low side switch of the synchronous converter. In some cases, the switch node resonant frequency may be determined based on the switching frequency of the low side switch when the magnitude of the peak voltage on the switch node just reaches the bus voltage during one switching cycle. By determining the switch node resonant frequency, a feedforward control scheme of the synchronous controller may be implemented with improved efficiency.

[0060] Disclosed concepts provide a measurement circuit that extends the synchronous converter, and two operation modes by which the synchronous converter may be driven. Firstly, a comparator is provided that enables the determination of a difference between a peak voltage on the switch node, and a voltage on the bus node. This difference signal can be used to determine switching parameters according to which the high gate drive and low gate drive control / drive high and low side switches respectively.

[0061] Furthermore, a first control mode is provided by which an output capacitor connected to an output node of the synchronous converter may be charged. Responsive to the capacitor being charged (by operation in the first control mode or otherwise), the controller may operate in a second control mode in which the high side switch is kept in an off-state, and the low side switch is driven at a switching frequency. The switching frequency can then be adjusted until the difference (measured by the comparator) just reaches zero. That is, the switching frequency is adjusted until the peak voltage on the switch node is equal (or substantially equal, for example within a few volts) to the bus voltage during a switching cycle of the low side switch. In other words, the control parameter settles in a steady state characterized by a switching frequency and a peak voltage of the switch node. The switching frequency when this occurs may be used to derive the resonant frequency of the switch node.

[0062] Recently, deficiencies in cycle-by-cycle (i.e. event driven) control schemes have become more apparent. Various delays in signal propagation, gate driving, and inverter transition reduce the efficacy of event driven control schemes at high switching frequencies. Furthermore, increasingly fast comparators are required in order to determine the result of the comparison in adequate time. Indeed, typical comparators often cannot compute fast enough for high switching frequencies, and therefore increasingly complex and expensive dedicated circuitry is required.

[0063] Alternatively, all signals controlling the switches of the synchronous converter can be generated by a modulator based on a model and quantities that vary relatively slowly in time. That is, the quantities can be acquired in a more straightforward manner because their values can be averaged over a number of switching cycles.

[0064] Specifically, feedforward (or average) control schemes rely on time-averaged measurements. Such schemes have been shown to run synchronous converters with minimum loss in terms of rms losses and such related to the diode conduction mode.

[0065] Feedforward control schemes can only be run efficiently if certain parameters of the synchronous converter circuit are known with a high degree of accuracy. Specifically, the nominal switch node resonant frequency (mnom) must be known, which is related to the nominal value of the boost or buck inductance (Lnom) and the total switch node capacitance (Cxnom) according to the following:

[0066] This can be as high as 2K*20 MHZ in synchronous converters designed for a switching frequency range of up to 1MHz.

[0067] LnOm and Cxnomare the subject of tolerances and are non-linear as they depend on current and voltage respectively. Accordingly, calculation of the switch node resonant frequency based on rated values of inductance and capacitance may be inaccurate and lead to inefficient implementation of a feedforward control scheme.

[0068] Indeed, only if the switch node resonant frequency is known accurately, can the gate driving pattern of the synchronous converter be optimized in terms of always keeping zero voltage switching (ZVS) while minimizing the reactive current needed for ZVS and thus minimizing inverter, inductor, and filter losses, as well as minimizing the dead times to avoid ‘diode mode’ conduction of the transistors, which can be lossy (particularly for SiC or GaN inverters).

[0069] It has been realized that sensing of the switch node resonant frequency can be performed without a cumbersome data acquisition process or requiring a time consuming factory configuration. Indeed, disclosed embodiments enable the determination of the switch node resonant frequency in the actual application context of the synchronous converter (e.g., as used as an LED driver).

[0070] The sensing of the switch node resonant frequency according to some disclosed embodiments is characterized by two distinct operation modes (used during charging or discharging the output capacitor) and further, by a measurement circuit that extends the synchronous converter. Specifically:

[0071] (i) A sensing hardware (i.e. a comparator) to compare the peak of the switch node voltage (Vx) to the bus voltage (HVin). This may be implemented by a peak voltage comparator with integrated level shifter, to make the high voltage detection result available by a low voltage signal (Vsens). Alternatively, this may be implemented using a diode mode conduction detector.

[0072] (ii) A controller configured to be operable in a first control mode, in which the high side gate drive and low side gate drive are controlled so that the voltage on the output node is controlled and ramped up to a predetermined level below a load voltage.

[0073] For example, if the synchronous converter is to be used as an LED driving circuit, the voltage on the output node may be below the minimum LED voltage (e.g., 10- 20% of the voltage on the bus node). Accordingly, no current flows into the load, and the output capacitor is charged. In this mode there is bidirectional power flow between input and output filter capacitors.

[0074] Other aspects for configuring / selecting the voltage on the output node include the fact that the output voltage should stay below 50% of the voltage on the bus node so that the operation of high side switch and the low side switch do not have to be reversed. This reversed operation works in principle, but may be more difficult to implement in practice. Furthermore, the lower the voltage on the output node, the lower the switching frequency with respect to the switch node resonant frequency, which allows detecting high resonant frequencies (e.g. several MHz) using hardware limited to a relatively low frequency (e.g. 1MHz). Nevertheless, should the voltage on the output node become too low, the energy in the output capacitor may be discharged before the control has settled (i.e. before the peak voltage on the output node just becomes equal to the voltage on the bus node). Finally, in some applications, the tuning may be run while a load (e.g., an LED load) is connected. Thus the voltage must stay below a minimum voltage, above which the load commences drawing current.

[0075] (iii) A controller configured to be operable in a second control mode, in which the high side gate drive keeps the high side switch (e.g., the upper switch of an inverter half bridge of the synchronous controller) in an off-state, while the low side gate drive causes the low side switch to continue switching / alternating between an on-state and an off-state. The above described sensing hardware output voltage is controlled to a pre-set value by manipulating the frequency of the switching of the low side switch. Then, the frequency settles at an operation point at which the peak switch node voltage just reaches the bus voltage (or comes close by a few volts).

[0076] Fig. l is a circuit diagram of a synchronous converter with a comparator according to an aspect of the invention.

[0077] Specifically, there is provided a power train in the form of a synchronous buck converter. The buck converter comprises a high side switch 110, with corresponding high side gate drive 112, and a low side switch 120, with corresponding low side gate drive 122. The high side switch 110 is connected between a bus node (B) having a voltage (HVin) and a switch node (X). The low side switch 120 is connected between the switch node and ground.

[0078] Both the bus input and the output node (O) may be connected to filter capacitors. The switch node (X) is connected to the output node (which may, in turn, be connected to a load) via an output inductor 140. The output node is connected to ground via an output capacitor 150.

[0079] The high side gate drive 112 and the low side gate drive 122 are controlled by a controller 300, which determines the switching frequency and duty cycle at which the gate drives drive the switches. The high side gate drive 112 and the low side gate drive 122 are connected to a low voltage power supply 130 for driving the respective switches.

[0080] In some embodiments, and as depicted in Fig. 1, the high side gate drive 112 is connected to the low voltage power supply 130 via a bootstrap circuit 400. Specifically, the high side gate drive 112 is connected to the low voltage power supply 130 via a bootstrap diode 410. Furthermore, a bootstrap capacitor 420 is provided which connects the switch node to a bootstrap node.

[0081] In essence, the above-described components may be considered a synchronous converter. In an example, during operation of the synchronous converter, the bus voltage (HVin) may be around 400V-500V, and the buck output voltage (Vout) may be around 100V-350V. It is worth noting that the synchronous buck converter may be a synchronous boost converter with only minor modifications, fully within the understanding of the skilled person.

[0082] According to the disclosed invention, there is also provided a comparator 200 for sensing a difference between the voltage on the bus node (HVin), and a peak of the voltage on the switch node (VX, peak).

[0083] The comparator 200 is connected to the bootstrap node (connected to the switch node via bootstrap capacitor 420), and the bus node. Specifically, a base of the PNP transistor 210 is connected to the bus node, and an emitter of the PNP transistor 210 is connected to the bus node via a high voltage, low capacitance diode 220, a several kQ resistor 230 and bootstrap capacitor 420. Furthermore, a small capacitor 240 may be provided across the base emitter.

[0084] Furthermore, a collector of the PNP transistor 210 may be connected to a level shifter 250 for outputting a voltage indicative of the difference at a level that may be processed by typical control circuitry. Specifically, there is provided a high side resistor 252 connected between the output node (Oc) of the comparator 200 and a voltage sensing output node (Osens). There is a low side resistor 254 connected between the voltage sensing output node and ground. The low side resistor may also limit the average losses (e.g. to a few milliwatts). Further filtering or clamping to safe voltage levels may be applied to the output sensing node (Osens).

[0085] The voltage on the output sensing node (referred to as Vsens) will indicate the difference between the peak voltage at the switch node and the voltage on the bus node. In essence, the higher Vsens indicates a peak of the switch node approaching the voltage on the bus node.

[0086] The controller may operate in a first operation mode for charging of the output capacitor, and a second operation mode for sensing of the switch node resonant frequency.

[0087] When the controller 300 operates in a first operation mode, the switching frequency and / or the duty cycle of the high side switch 110 and the low side switch 120 is controlled such that a voltage on the output node is increased to a target voltage. Accordingly, the output capacitor 150 is charged, such that a voltage across the output capacitor 150 reaches a target value. The voltage on the output node will be such that no current flows into the load (i.e., the voltage is below the minimum load voltage, above which current would flow into the load), thereby charging the output capacitor 150.

[0088] When the controller 300 operates in the second control mode, the high side switch 110 is kept in an off state. The low side switch 120 in the second operation mode remains switching. In other words, when the output capacitor 150 is charged to a target voltage, the controller 300 may operate in the second control mode in which the high side switch 110 is kept in an off state, and the low side switch 120 alternates between an on-state and an off-state at a switching frequency. When the low side switch 120 is in an on-state, the output inductor 140 is charged by a current flowing through the charged output capacitor 150, output inductor 140, and low side switch 120, and so stores energy.

[0089] Operation when the low side switch is in an off-state is depicted in Fig. 2. By way of explanation, Fig. 2 presents the voltage on the switch node versus the (scaled) inductor current over time when the controller 300 is operating in the second control mode, and both the high side switch 110 and the low side switch 120 are closed. In this case, all voltage-current trajectories 1-3 are centered on the peak voltage (vxpeak) being equal to the voltage on the output node, and the output inductor 140 current being zero. Note that, if either the high side switch 110 or the low side switch 120 were turned on, the peak voltage would be clamped to ground or the voltage on the bus node.

[0090] Trace 1 depicts the case when the switch node peak voltage is below the bus voltage. At t=toff, the voltage begins to rise and reaches a maximum at zero inductor current, before reducing to slightly below zero where it is clamped by the low side switch 120 (diode conduction). At t=ton, the low side switch is turned on. Here, the peak voltage is too low because the switching frequency of the low side switch 120 is too high.

[0091] Trace 2 depicts the case where the switching frequency is too low. In this case, diode mode conduction of the high side switch 110 occurs. This means that energy is transferred from the output capacitor 150 to a capacitor provided across the bus node, otherwise known as boost operation. As, during the second control mode of the controller 300, the high side switch 110 is kept off, positive currents cannot be conducted by the high side switch 110.

[0092] Trace 3 depicts when the operation of the control is settled at a point at which the peak voltage has approached the voltage on the bus node, indicating that the switching frequency is well adjusted.

[0093] Accordingly, as seen in Fig. 2, the peak voltage on the switch node in the second operation mode will depend upon the switching frequency of the low side switch 120.

[0094] Fig. 3 is a simplified block diagram of a control loop for a switching frequency of the high side switch and the low side switch when the controller is operating in the second control mode. In other words, Fig. 3 represents a control loop of the circuit of Fig. 1 when the controller 300 is operation in the second control mode. In essence, the peak switch node voltage (Vx peak) is controlled to be equal to the bus voltage (HVin) using the switching frequency of the low side switch as the manipulating value.

[0095] More specifically, the comparator and level shifter receive the measured peak voltage on the switch node and the voltage on the bus node. A difference is taken between the two voltages, and an amplitude of the voltage difference is level shifted to provide a voltage output (Vsens) indicative of the difference, and that can be processed by control circuitry.

[0096] The switching frequency control and modulator (which may be implemented in controller 300), receives Vsens and determines a switching frequency based on (at least) the received voltage indicative of the difference. The switching frequency may be further based on the values of the voltage on the bus node and / or the output node. A duty cycle may further be determined. The determined switching frequency and the duty cycle may be provided to a pulse width modulator to produce control signals (GDL and GDH) for controlling the high side gate drive and the low side gate drive.

[0097] The control signals are then used to control the high side gate drive and low side gate drive to drive the high side switch and low side switch, respectively. As a result, there may be a change in Vx peak, which may be fed back to the comparator and subsequent switching frequency control and modulator. Overall, a feedback loop is proposed in which the switching frequency implemented by the gate drives is changed responsive to a difference between the peak switch node voltage and the bus voltage. Eventually, a switching frequency will be found at which the peak voltage just reaches (i.e., is substantially equal to, but the peak is only instantaneous) the bus voltage.

[0098] In some embodiments, this switching frequency can be used to derive the switch node resonant frequency according to the following:

[0099] / / d \ 2 . - \ 12] co = fs ■ I n + 2 ■ asin I - - 71 + - Vl — 2d I

[0100] \ \1 - d / d / where co is the switch node resonant frequency, fs is the determined switching frequency, and d = Vout / HVin. Note that equation [2] assumes that Vout < HVin / 2.

[0101] Fig. 4 is a simplified block diagram of the operation of a switching frequency control and pulse width modulation element of the control loop depicted in Fig. 3. In particular, an error signal is created by subtracting a constant (shown as Ref) and controlled to zero e.g., by an integrator or any standard PID controller, resulting in the switching frequency and using a pre-calculated initial value. As shown, fsO refers to the initial switching frequency, which is calculated based on rated component values, the bus voltage, and the voltage on the output node. Toff refers to the on-time of the lower switch, which is calculated also based on the voltage on the bus node, and the voltage on the output node.

[0102] To reiterate, the high side gate driving signal (GDH) is kept low during operation of the controller in the second control mode. The sequence is completed once the control error has settled at zero, which may take less than 0.1ms but can be adjusted to take milliseconds to better cope with the filter time constants used for input and output voltage measurements, as the voltage on the output node may decline during operation by the controller in the second control mode. The resulting frequency may then be used to derive the switch node resonant frequency as described above.

[0103] Figs. 5-7 present graphs depicting waveforms of different aspects of the synchronous converter when the controller is in a second operation mode according to an aspect of the invention.

[0104] Fig. 5 presents waveforms when the switching frequency of the low side switch is too low. That is the peak switch node voltage reaches the bus voltage and would exceed the bus voltage if it were not clamped by the diode mode operation of the high side switch (i.e., the high side switches 3rdquadrant characteristic). The bottom set of graphs is the same as the top set of graphs but for a time frame of 0.25 ps rather than 2.5ps - focusing on when the low side switch is in the off state. As a result, the switching frequency of the low side switch would be adjusted by the controller so as to lower the switch node peak voltage.

[0105] Fig. 6 presents waveforms when the switching frequency of the low side switch is too high. In this case, the peak voltage on the switch node is far below the voltage on the bus. Therefore, the switching frequency of the low side switch would be adjusted by the controller so as to raise the switch node peak voltage.

[0106] Finally, Fig. 7 presents waveforms when the switching frequency of the low side switch is selected / adjusted so that the peak voltage on the switch node falls within a predetermined threshold of the voltage on the bus node, and the peak voltage on the peak node is equal to the bus node for less than a threshold amount of time. Similarly to Fig. 5, the bottom set of graphs is the same as the top set of graphs but for a time frame of 0.25 ps rather than 2.5ps - focusing on when the low side switch is in the off state.

[0107] The switch node voltage peaks at a value within a few volts of the bus voltage. There may be a small variation between the switch node voltage peak and the bus voltage depending on specific details of the synchronous converter and comparator (such as the number of diodes between the switch node and the comparator, or indeed within the comparator, and / or in the case of the circuit depicted in Fig. 1, the gate drive supply / bootstrap voltage).

[0108] Then, once a waveform like that shown in Fig. 7 is detected, the switching frequency of the low side switch may be used to derive the switch node resonant frequency.

[0109] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0110] Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. An arrangement for determining a switch node resonant frequency of a synchronous converter, the synchronous converter comprising a high side switch (110) connected between a bus node (B) and a switch node (X), a low side switch (120) connected between the switch node and ground, a low side gate drive (122) connected to a low voltage power supply (130) and adapted to drive a gate of the low side switch, a high side gate drive (124) connected to the low voltage power supply and adapted to drive a gate of the high side switch, an output inductor (140) connected between the switch node and an output node (O), and an output capacitor (150) connected between the output node and ground, the arrangement comprising: a comparator (200) configured to determine a difference between a peak voltage on the switch node and a voltage on the bus node; a controller (300) configured to adjust the peak voltage on the switch node to be equal to the voltage on the bus node based on the difference by controlling the low side gate drive and the high side gate drive, wherein the controller (300) is configured to operate in a control mode in which the controller (300) is configured to: control the high side gate drive (112) to cause the high side switch (110) to remain in an off-state; and control the low side gate drive (122) to adjust a switching frequency of the low side switch (120) based on the difference, wherein the switch node resonant frequency is determined based on the switching frequency of the low side switch when the magnitude of the peak voltage on the switch node just reaches the bus voltage during one switching cycle.

2. The arrangement of claim 1, wherein an initial switching frequency of the low side gate drive (122) is based on a rated resonant frequency value of the synchronous converter.

3. The arrangement of claim 1 or 2, wherein the controller (300) is further configured, responsive to the difference during at least one cycle of the low side switch (120) falling below a predetermined threshold amount and the difference during the at least onecycle being zero for a predetermined maximum amount of time, to output the switching frequency of the low side switch.

4. The arrangement of claim 3, further comprising a processor configured to determine the switch node resonant frequency based, at least in part, on the output switching frequency.

5. The arrangement of claim 4, wherein the processor is configured to determine the switch node resonant frequency further based on a voltage on the output node (O) and the voltage on the bus node (B).

6. The arrangement of any of claims 1-4, wherein the controller (300) is configured to operate in the second control mode responsive to a voltage across the output capacitor (150) satisfying a predetermined condition.

7. The arrangement of claim 6, wherein the predetermined condition is satisfied when the voltage across the output capacitor (150) reaches 10-20% of the voltage on the bus node (B).

8. The arrangement of any of claims 1-7, wherein the controller (300) is configured to operate in a first control mode in which the controller is configured to: control a load connected to the output so that no current flows into the load; and control the high side gate drive (112) and the low side gate drive (114) to increase a voltage on the output node (O) to a target voltage.

9. The arrangement of any of claims 1-8, wherein the comparator (200) comprises: a PNP transistor (210) having a base connected to the bus node (B); a diode (220) and a resistor (230) connected in series between the switch node (X) and an emitter of the PNP transistor; and an output node (Oc) connected to a collector of the PNP transistor.

10. The arrangement of claim 9, wherein the comparator (200) further comprises a capacitor (240) connected between the base of the PNP transistor (210) and the emitter of the PNP transistor.

11. The arrangement of claim 9 or 10, wherein the comparator (200) further comprises a level shifter (250) configured to attenuate a voltage on the output node (Oc) of the comparator.

12. The arrangement of claim 11, wherein the level shifter (250) comprises: a high side resistor (252) connected between the output node (Oc) of the comparator (200) and a voltage sensing output node (Osens); and a low side resistor (254) connected between the voltage sensing output node and ground.

13. The arrangement of any of claims 1-12, wherein the high side gate drive (112) is connected to the low voltage power supply (130) via a bootstrap circuit (400), and wherein the comparator (200) is connected to the switch node (X) via the bootstrap circuit.

14. The arrangement of claim 13, wherein the bootstrap circuit (400) comprises: a diode (410) connecting the low voltage power supply (130) to a bootstrap node, the high side gate drive (112) connected to the bootstrap node, and a bootstrap capacitor (420) connecting the bootstrap node to the switch node (X), and wherein the comparator (200) is connected to the switch node via the bootstrap node.

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