Semiconductor device

Abstract

The present invention provides a semiconductor device that exhibits a high field effect mobility. The semiconductor device has an oxide semiconductor, a first through fourth insulators, and a first through third conductors, wherein: the second insulator is disposed on the first insulator; the oxide semiconductor is disposed on the first insulator and covers the second insulator; the first conductor and the second conductor are disposed on the oxide semiconductor; the third insulator is disposed on the first conductor and the second conductor and has an opening that overlaps with a region between the first conductor and the second conductor; the fourth insulator overlays the oxide semiconductor and is disposed in the opening; the third conductor is disposed on the fourth insulator in the opening; in a cross-sectional view in the channel width direction, the height of the second insulator is greater than the width of the second insulator; the oxide semiconductor has, in a region overlaying the third conductor, a first layer, a second layer on the first layer, and a third layer on the second layer; the first layer has gallium; the second layer has indium oxide; the third layer has indium, gallium, and oxygen; and the indium content in the second layer is higher than the indium content in the third layer.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an aggregate of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high field-effect mobility. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention includes an oxide semiconductor, first to fourth insulators, and first to third conductors. The second insulator is disposed over the first insulator. The oxide semiconductor is disposed over the first insulator and covers the second insulator. The first and second conductors are disposed over the oxide semiconductor. The third insulator is disposed over the first and second conductors and has a first opening overlapping with a region between the first conductor and the second conductor. The fourth insulator overlaps the oxide semiconductor and is disposed in the first opening. The third conductor is disposed in the first opening and on the fourth insulator. A side surface of the first insulator has a thickness of about 100 nm. a side surface of the first conductor, a side surface of the first conductor, and a side surface of the second conductor; a thickness of the first insulator is thicker than a thickness of the fourth insulator; a height of the second insulator is greater than a width of the second insulator in a cross-sectional view in the channel width direction; and the oxide semiconductor has, in a region overlapping with the third conductor, a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer containing gallium and oxygen, the second layer containing indium oxide, and the third layer containing indium, gallium, and oxygen, and the indium content in the second layer is higher than the indium content in the third layer.

[0013] In the above, it is preferable that the conduction band minimum of the first layer is located closer to the vacuum level than the conduction band minimum of the second layer, and the conduction band minimum of the third layer is located closer to the vacuum level than the conduction band minimum of the second layer.

[0014] In the above, it is preferable that the first layer contains indium, and that the indium content in the first layer is lower than the gallium content.

[0015] In the above, it is preferable that a side surface of a portion of the third insulator coincides or substantially coincides with a side surface of the first conductor and a side surface of the second conductor in a plan view.

[0016] In the above, the bottom surface of the third conductor preferably has a portion located lower than the bottom surface of the oxide semiconductor.

[0017] In the above, it is preferable that the fifth insulator is provided, and the first conductor and the second conductor each have a first conductive layer and a second conductive layer on the first conductive layer, the fifth insulator is disposed within the first opening and contacts the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor, the fifth insulator has a second opening overlapping with the region between the first conductive layer of the first conductor and the first conductive layer of the second conductor, and the shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is shorter than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor.

[0018] In the above, it is preferable that a portion of the side surface of the third insulator coincides or substantially coincides with a side surface of the second conductive layer of the first conductor and a side surface of the second conductive layer of the second conductor in a planar view.

[0019] In the above, the fifth insulator preferably includes silicon nitride.

[0020] In the above, the first conductive layer of the first conductor and the first conductive layer of the second conductor preferably contain tantalum nitride.

[0021] According to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0022] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B to 1D are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIGS. 3A and 3B are cross-sectional views showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIG. 5 is a cross-sectional view showing an example of a semiconductor device. FIGS. 6A to 6C are cross-sectional views showing an example of a semiconductor device. FIGS. 7A to 7C are cross-sectional views showing an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIG. 10A is a plan view showing an example of a semiconductor device. FIGS. 10B to 10D are cross-sectional views showing an example of a semiconductor device. FIG. 11A is a plan view showing an example of a semiconductor device. FIGS. 11B to 11D are cross-sectional views showing an example of a semiconductor device. FIG. 12A is a plan view showing an example of a semiconductor device. FIGS. 12B to 12D are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a plan view showing an example of a semiconductor device. FIGS. 13B to 13D are cross-sectional views showing an example of a semiconductor device. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A to 15C are cross-sectional views showing an example of a semiconductor device. FIGS. 16A and 16B are cross-sectional views showing an example of a semiconductor device. FIG. 17A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 17B to 17D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 18A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 18B to 18D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 19B to 19D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 20B to 20D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 21A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 21B to 21D are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 22A is a plan view showing an example of a manufacturing method of a semiconductor device. 22B to 22D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.FIG. 23A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 23B to 23D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 24A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 24B to 24D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 25B to 25D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 26A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 26B to 26D are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 27 is a band diagram of an oxide semiconductor. FIG. 28 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 29A to 29H are diagrams illustrating an example of a circuit structure of a memory cell. FIGS. 30A and 30B are perspective views illustrating a structural example of a semiconductor device. FIG. 31 is a block diagram illustrating a CPU. FIG. 32 is a block diagram illustrating a CPU. FIGS. 33A and 33B are perspective views of a semiconductor device.

[0073] Figures 34A and 34B are perspective views of a semiconductor device. Figures 35A and 35B are diagrams illustrating the hierarchy of a memory device in a semiconductor device. Figures 36A and 36B are diagrams illustrating an example of electronic equipment, and Figures 36C to 36E are diagrams illustrating an example of a mainframe computer. Figure 37 is a diagram illustrating an example of space equipment. Figure 38 is a diagram illustrating an example of a storage system applicable to a data center. Figures 39A and 39B are diagrams illustrating an example of the configuration of a display device. Figure 40 is a diagram illustrating an example of the configuration of a display device. Figure 41 is a diagram illustrating an example of the configuration of a display device. Figure 42 is a diagram illustrating an example of the configuration of a display device. Figures 43A to 43D are diagrams illustrating an example of the configuration of a display device. Figures 44A and 44B are diagrams illustrating an example of the configuration of a display device. Figures 45A and 45B are diagrams illustrating an example of the configuration of a display device. Figures 46A to 46D are diagrams illustrating an example of the configuration of a display device. Figures 47A to 47D are diagrams illustrating an example of the configuration of a display device. Figure 48 is a diagram illustrating an example of the configuration of a display device. Figures 49A to 49F are configuration examples of electronic devices, Figures 50A to 50F are configuration examples of electronic devices, and Figures 51A to 51G are configuration examples of electronic devices.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In order to make the invention easier to understand, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0029] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0030] The terms "film" and "layer" may be interchangeable depending on the circumstances. For example, the term "conductive layer" may be interchangeable with the term "conductive film." Or, for example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0031] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0032] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0033] Furthermore, in the drawings used in this specification and the like, the sidewall of the insulator at the opening portion of the insulator is shown as being perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed, but it may be tapered.

[0034] In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, but may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0035] In this specification, the term "having the same or substantially the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process for a memory device, a planarization process (typically a process using chemical mechanical polishing (CMP)) may expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process are configured to have the same height from the reference surface. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or substantially the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference surface, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or substantially the same height."

[0036] In this specification, "side edges that coincide or approximately coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or approximately coincide" is also used.

[0037] In this specification, the phrase "the planar shapes are identical or approximately identical" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be disposed inside the lower layer, or the upper layer may be disposed outside the lower layer. In these cases, the phrase "the planar shapes are identical or approximately identical" may also be used. Furthermore, when the planar shapes are identical or approximately identical, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned.

[0038] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0039] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 26D.

[0040] 1A to 1D are plan views and cross-sectional views of a semiconductor device having a transistor 200 over a substrate (not shown).

[0041] FIG. 1A is a plan view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1C is a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by the dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. The dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 1A, some elements are omitted and shown transparently for clarity. 2A shows an enlarged view of the vicinity of the conductor 260 in FIG. 1D. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1B. 8A shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1C. Note that in this specification and the like, a cross section in the channel width direction does not necessarily include the channel formation region of a transistor. The cross section in the channel width direction may also include a cross section parallel to the cross section in the channel width direction including the channel formation region.

[0042] The semiconductor device of this embodiment has an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an insulator 225 on the insulator 224, an oxide semiconductor 230 on the insulators 224 and 225, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide semiconductor 230, an insulator 250 on the oxide semiconductor 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. Furthermore, an insulator 255 is provided between the insulator 222, the conductor 242a1, the conductor 242b1, the conductor 242a2, the conductor 242b2, the insulator 275, and the insulator 280 and the insulator 250. Note that hereinafter, the conductors 242a and 242b may be collectively referred to as the conductors 242.

[0043] An insulator 275 is provided over the conductor 242 and the insulator 222, and an insulator 280 is provided over the insulator 275. An opening 201 is provided in the insulator 280 and the insulator 275. The side surfaces of the insulator 280 and the insulator 275 function as sidewalls of the opening 201. The side surfaces of the conductor 242a1, the conductor 242a2, the conductor 242b1, and the conductor 242b2 can also be considered as sidewalls of the opening 201. The insulators 250, 255, and 260 are disposed inside the opening 201. The insulators 224, 225, and part of the oxide semiconductor 230 are also disposed inside the opening 201. The opening 201 reaches the oxide semiconductor 230 and the insulator 222, and the insulator 250 is in contact with the oxide semiconductor 230 and the insulator 222 within the opening 201.

[0044] Here, an opening is formed in the bottom surface of the insulator 255, and the opening overlaps with a region between the conductor 242a1 and the conductor 242b1. In a cross-sectional view in the channel width direction (see FIG. 1B ), the insulator 224, the insulator 225, and the oxide semiconductor 230 are arranged in the opening of the insulator 255. The insulator 255 is provided along the sidewall and the bottom surface of the opening 201; therefore, the insulator 255 can also be considered as part of the sidewall and the bottom surface of the opening 201.

[0045] An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided under the insulator 216.

[0046] An insulator 241a is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is in contact with the upper surface of the conductor 242a. An insulator 241b is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is in contact with the upper surface of the conductor 242b. Note that hereinafter, the conductors 240a and 240b may be collectively referred to as the conductor 240. The insulators 241a and 241b may be collectively referred to as the insulator 241.

[0047] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200.

[0048] The conductor 242a has a region that functions as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a functions as a plug connected to the conductor 242a. The conductor 242b has a region that functions as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b functions as a plug connected to the conductor 242b.

[0049] The conductor 242a has a stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide semiconductor 230 are preferably conductors that are resistant to oxidation, such as metal nitrides. This can prevent the conductors 242a and 242b from being excessively oxidized by oxygen contained in the oxide semiconductor 230. Furthermore, the conductors 242a2 and 242b2 are preferably conductors such as metal layers that have higher conductivity than the conductors 242a1 and 242b1. This allows the conductors 242a and 242b to function as wirings or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 242a and 242b functioning as wirings or electrodes are provided in contact with the top surface of the oxide semiconductor 230 functioning as an active layer.

[0050] As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance D1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance D2 between the conductor 242a2 and the conductor 242b2. Here, the distance D2 refers to the shortest distance between the opposing side surfaces of the conductor 242a2 and the conductor 242b2. Furthermore, the distance D1 refers to the shortest distance between the opposing side surfaces of the conductor 242a1 and the conductor 242b1. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, shortening the channel length of the semiconductor device allows for the provision of a semiconductor device with high operating speed.

[0051] The opening 201 overlaps with a region between the conductor 242a2 and the conductor 242b2. Parts of the conductors 242a1 and 242b1 can also be considered to be formed so as to protrude into the opening 201. Therefore, the insulator 255 is in contact with the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the opening 201. The insulator 250 is in contact with the top surface of the insulator 222 and the top surface of the oxide semiconductor 230 in the region between the conductor 242a1 and the conductor 242b1.

[0052] The insulator 255 is preferably an insulator that is resistant to oxidation, such as a nitride. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and has the function of protecting the conductors 242a2 and 242b2. As will be described in detail later, after separating the conductors 242a1 and 242b1, it is preferable to perform heat treatment in an oxygen-containing atmosphere before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented.

[0053] The oxide semiconductor 230 is formed to cover the insulator 225. As shown in FIGS. 2B and 8A , the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. Therefore, the insulator 225 can also be said to have a fin-like shape. Here, the aspect ratio of the insulator 225 in a cross-sectional view in the channel width direction refers to the ratio of the length L of the insulator 225 in the A1-A2 direction (which can also be referred to as the width L of the insulator 225) to the length H of the insulator 225 in a direction perpendicular to the surface on which the insulator 225 is formed (for example, the insulator 224) (which can also be referred to as the height H of the insulator 225). The aspect ratio of the insulator 225 is preferably as large as possible without causing the insulator 225 to collapse during the manufacturing process of the transistor 200. The height H of the insulator 225 is preferably larger than the width L of the insulator 225.

[0054] The oxide semiconductor 230 and the conductor 242 are provided to cover the insulator 225 having a high aspect ratio. In the vicinity of the channel formation region of the transistor 200, the oxide semiconductor 230 is provided so as to be folded in half with the insulator 225 sandwiched therebetween, as shown in FIG. 2B . As a result, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided facing each other with the insulator 250 sandwiched between them at the upper part of the insulator 225, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224. That is, the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224 each function as a channel formation region. Therefore, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 compared to when the insulator 225 is not provided.

[0055] The increased channel width as described above can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. In addition, in the above structure, the oxide semiconductor 230 is provided to cover the insulator 225, thereby increasing the channel width without excessively increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, the above structure increases the area where the side surfaces of the conductor 260 and the oxide semiconductor 230 face each other, so that the transistor 200 can be normally off by controlling the threshold voltage.

[0056] Furthermore, as shown in FIG. 2B , it is preferable that the thickness t1 of the insulator 224 in the opening 201 is thicker than the thickness t2 of the insulator 250. With this configuration, the lower surface (which can also be referred to as the lower end or bottom edge) of the conductor 260 located in a region of the opening 201 that does not overlap with the oxide semiconductor 230 is located lower than the lower surface (which can also be referred to as the lower end or bottom edge) of the oxide semiconductor 230. Therefore, a sufficient electric field can be applied from the conductor 260 to the region from the upper end to the bottom end of the oxide semiconductor 230. This can reduce leakage current between the source electrode and the drain electrode via the bottom edge of the oxide semiconductor 230. Furthermore, poor characteristics of the transistor, such as normally-on state, due to the leakage current can be suppressed. That is, the electrical characteristics of the transistor 200 can be improved.

[0057] The oxide semiconductor 230 has a channel formation region. The oxide semiconductor 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor 230 may have a single-layer structure or a stacked structure of two or more layers.

[0058] The crystallinity of a semiconductor material used for the oxide semiconductor 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0059] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0060] For an oxide semiconductor that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0061] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0062] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0063] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0064] Here, the oxide semiconductor 230 used in the semiconductor device preferably contains indium oxide. For example, the oxide semiconductor 230 can be made of indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, or the like. The oxide semiconductor 230 can have a stacked structure. For example, the oxide semiconductor 230 can have a stacked structure of indium oxide and indium gallium zinc oxide on the indium oxide. As shown in FIG. 2B , the oxide semiconductor 230 can have a structure including an oxide semiconductor 230a on the insulator 224, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b. For example, the oxide semiconductor 230b can be made of indium oxide, and the oxide semiconductors 230a and 230c can be made of indium gallium zinc oxide. As described above, when the oxide semiconductor 230 contains indium oxide, a semiconductor device with high field-effect mobility can be provided. Furthermore, a semiconductor device having favorable electrical characteristics, frequency characteristics, and reliability can be provided. For a detailed structure of the oxide semiconductor 230, the description in Embodiment 2 can be referred to.

[0065] A channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200 are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0066] The channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0067] The source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. That is, the source and drain regions are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0068] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0069] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide). Note that an oxide semiconductor (or metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or metal oxide).

[0070] To stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0071] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than varying stepwise from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0072] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. Ｏ H may be formed, generating electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V Ｏ It is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0073] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V ＯH can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0074] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce V Ｏ It is preferable to prevent the amount of H from being reduced excessively. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0075] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress reduction in the hydrogen concentration in the source and drain regions.

[0076] The insulator 250 in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0077] 2A , the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0078] Examples of insulators that have the function of capturing or fixing hydrogen include metal oxides with an amorphous structure. For the insulators 250a and 250c, it is preferable to use, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides with an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0079] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulators 250a and 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulators 250a and 250c makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0080] For the insulators 250a and 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0081] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0082] In this embodiment, hafnium oxide is used as the insulator 250c. By providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0083] Next, it is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride for the insulator 250b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0084] The silicon oxide film used as the insulator 250b is preferably formed using a PEALD (Plasma Enhanced ALD) method.

[0085] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0086] In this specification and the like, a barrier insulator refers to an insulator with barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. Furthermore, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0087] Examples of the oxygen barrier insulator include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, and 275 each preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen barrier insulators.

[0088] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a has a barrier property against oxygen, which can prevent the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0089] The insulator 250a is provided in contact with the top surface and side surface of the oxide semiconductor 230 and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can prevent oxygen from being released from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0090] Furthermore, the insulator 250a prevents excessive oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and enables an appropriate amount of oxygen to be supplied to the oxide semiconductor 230. Therefore, excessive oxidation of the source and drain regions can be suppressed, which can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0091] An oxide containing one or both of aluminum and hafnium has barrier properties against oxygen and can therefore be suitably used as the insulator 250a.

[0092] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0093] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0094] The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with the side surface of the conductor 242, the side surface of the oxide semiconductor 230, and the top surface of the insulator 222. This structure can prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, an increase in resistivity due to oxidation of the conductor 242 caused by the oxygen contained in the insulator 280 can be prevented. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0095] A barrier insulator against hydrogen is preferably provided near each of the source and drain regions in order to suppress a decrease in the hydrogen concentrations in the source and drain regions of the oxide semiconductor 230. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0096] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a stacked structure of the above-mentioned barrier insulator against hydrogen.

[0097] Furthermore, because the side surfaces of the insulator 275 are sidewalls of the opening 201, regions of the source and drain regions of the oxide semiconductor 230 that overlap with the opening 201 (which can also be referred to as regions of the source and drain regions of the oxide semiconductor 230 that overlap with the conductors 242a1 and 242b1 but do not overlap with the conductors 242a2 and 242b2) are exposed from the insulator 275. In contrast, the insulator 255 that covers these regions of the oxide semiconductor 230 is preferably made of a barrier insulator against hydrogen (for example, silicon nitride). In this way, regions of the source and drain regions of the oxide semiconductor 230 that are not covered with the insulator 275 can also be covered with the insulator 255 that functions as a barrier insulator against hydrogen.

[0098] By providing the insulators 275 and 255 as described above, it is possible to suppress the diffusion of hydrogen in the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentrations in the source and drain regions, thereby making the source and drain regions n-type.

[0099] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, with the above structure, the semiconductor device can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve frequency characteristics. Specifically, the cutoff frequency can be improved.

[0100] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d, together with the conductor 260, are provided in the opening formed in the insulator 280. To miniaturize the transistor 200, the thicknesses of the insulators 250a to 250d are preferably small. The thicknesses of the insulators 250a to 250d are preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. Note that each of the insulators 250a to 250d may have a region with the above thickness at least in part.

[0101] Furthermore, the thickness of the silicon oxide film used as the insulator 250b is preferably 0.7 nm or more and 3 nm or less.

[0102] In order to thin the film thicknesses of the insulators 250a to 250d as described above, it is preferable to deposit the insulators 250a to 250d by using an atomic layer deposition (ALD) method. Furthermore, to provide the insulators 250a to 250d in openings such as the insulator 280, it is preferable to deposit the insulators by using an ALD method. Examples of ALD methods include thermal ALD, which uses only thermal energy to cause a reaction between a precursor and a reactant, and PEALD, which uses a plasma-excited reactant. The PEALD method may be preferable because it uses plasma, which enables film deposition at a lower temperature.

[0103] The ALD method can deposit atoms layer by layer, and therefore has the advantages of enabling the formation of extremely thin films, the formation of films on structures with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, the formation of films at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280 and the side ends of the conductors 242a and 242b, etc., with a thin film thickness as described above.

[0104] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0105] Although the above description has been given of a structure in which the insulator 250 has a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have a structure including at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0106] For example, as shown in Fig. 6A, the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is a structure in which the insulator 250d is removed from the structure shown in Fig. 2A.

[0107] It is preferable to use the ALD process two or more times in forming the insulator 250. For example, the insulator 250 preferably has a stacked structure of multiple insulating films, and two or more of the multiple insulating films are preferably formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulator 250. Furthermore, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0108] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 or the like. For example, it is preferable to provide an insulator that has a function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor 200 or the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, or the insulator 221. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0109] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as barrier insulators that suppress diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, one or more of the insulators 283, 282, 222, and 221 suppress diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., copper atoms ...

[0110] The insulators 283, 282, 222, and 221 each preferably have an insulator that functions to suppress the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide can be used. For example, the insulators 283 and 221 are preferably made of silicon nitride, which has a high hydrogen barrier property. Furthermore, for example, the insulator 282 is preferably made of aluminum oxide, which has a high ability to capture or fix hydrogen. Furthermore, for example, the insulator 222 is preferably made of hafnium oxide, which is a high-dielectric-constant (high-k) material and has a high ability to capture or fix hydrogen.

[0111] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-described materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0112] With this structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, the provision of the insulators 282 and 283 can prevent oxygen contained in the insulator 280 and the like from diffusing upward from the transistor 200 and the like. Furthermore, the provision of the insulators 222 and 221 can prevent oxygen contained in the oxide semiconductor 230 and the like from diffusing downward from the transistor 200 and the like. Thus, by surrounding the transistor 200 from above and below with insulators that have a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen into the oxide semiconductor can be prevented. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0113] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a high ability to capture or fix hydrogen, for the insulator 250c.

[0114] The insulator 225 is formed in contact with the upper surface of the insulator 224. As shown in FIGS. 2B and 8A , the insulator 225 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction. The height H of the insulator 225 is preferably greater than the width L of the insulator 225. The height H of the insulator 225 may be 1 to 20 times, preferably 1.3 to 15 times, and more preferably 1.5 to 10 times the width L of the insulator 225. For example, the width L may be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 8 nm to 30 nm. For example, the height H may be 30 nm to 300 nm, preferably 50 nm to 150 nm.

[0115] 2B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the insulator 225 and the top surface of the insulator 224 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0116] The upper portion of the insulator 225 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the oxide semiconductor 230 and the conductor 242 near the upper portion of the insulator 225.

[0117] The oxide semiconductor 230 and the conductor 242 are provided to cover the insulator 225 having such a high aspect ratio. In the vicinity of the channel formation region of the transistor 200, the oxide semiconductor 230 is provided so as to be folded in half with the insulator 225 sandwiched therebetween, as shown in FIG. 2B , and the insulator 250 and the conductor 260 are further provided to cover the oxide semiconductor 230. As a result, the channel width of the transistor 200 is increased by the side surface on the A1 side and the side surface on the A2 side of the insulator 225.

[0118] By increasing the channel width as described above, the on-state current, field-effect mobility, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, in the above structure, by providing the insulator 225, the channel width can be increased without increasing the area occupied by the transistor 200. This enables miniaturization or high integration of the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0119] The bottom surface of the insulator 224 is in contact with the insulator 222, and the top surface is in contact with the insulator 225 and the oxide semiconductor 230. The planar shape of the insulator 224 is similar to that of the oxide semiconductor 230, and the insulator 224 overlaps with the oxide semiconductor 230 in a planar view. That is, the side surface of the insulator 224 coincides with or substantially coincides with the side surface of the oxide semiconductor 230 in a planar view. Furthermore, at least part of the insulator 224 overlaps with the conductor 242a (the conductor 242a1 and the conductor 242a2) and the conductor 242b (the conductor 242b1 and the conductor 242b2) in a planar view. In other words, at least a portion of the side surface of the insulator 224 coincides or substantially coincides with the side surfaces of the conductor 242a (conductor 242a1 and conductor 242a2) and the conductor 242b (conductor 242b1 and conductor 242b2) in a plan view.

[0120] 2B , it is preferable that the thickness t1 of the insulator 224 in the opening 201 is thicker than the thickness t2 of the insulator 250. With this configuration, the bottom surface of the conductor 260 (conductor 260 a) located in the opening 201 can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference (t1 − t2) between the thickness t1 and the thickness t2.

[0121] By disposing the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the top end to the bottom end of the oxide semiconductor 230. In other words, the entire oxide semiconductor 230 is electrically surrounded by the electric field of the conductor 260 in the opening of the insulator 280 or the like, and can function as a channel formation region. This configuration prevents the bottom end of the oxide semiconductor 230 from functioning as a parasitic channel, thereby reducing leakage current between the source electrode and the drain electrode. Furthermore, it is possible to suppress characteristic defects, such as normally-on transistor behavior, that are caused by the parasitic channel. In other words, the electrical characteristics of the transistor 200 can be improved.

[0122] Furthermore, as described above, the oxide semiconductor 230 functions as a channel formation region from the top end to the bottom end, whereby the channel width can be increased, which can improve the on-state current, transconductance, frequency characteristics, and the like of the transistor 200.

[0123] In this specification and the like, a transistor structure in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is arranged so as to surround at least two sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to provide a transistor in which the short channel effect is less likely to occur.

[0124] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. By forming the transistor 200 in the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, which is expected to improve the on-state current or the field-effect mobility of the transistor.

[0125] The insulators 225 and 224 may be formed using an insulating material that can be used for the insulator 222, the insulator 275, the insulator 280, the insulator 250, and the like. Because the insulators 225 and 224 are in contact with the oxide semiconductor 230, as described above, an insulating material that releases little hydrogen is preferably used. Examples of insulating materials that release little hydrogen include silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). This can prevent hydrogen from entering the oxide semiconductor 230. In particular, using silicon nitride for at least one of the insulators 225 and 224 can improve the reliability of the transistor. The insulators 225 and 224 preferably function as barrier insulators against hydrogen and preferably have the property of preventing hydrogen from diffusing into the insulators or the function of capturing or fixing hydrogen inside the insulators. Therefore, the insulators 225 and 224 can also be made of the insulating material that functions as a barrier insulator against hydrogen as described above.

[0126] For example, silicon nitride can be used for the insulators 225 and 224. In this case, the region of the insulator 224 that does not overlap with the insulator 225 may be thinner than the region of the insulator 224 that overlaps with the insulator 225. Alternatively, hafnium silicate can be used for the insulator 225, and silicon nitride can be provided for the insulator 224. With such a configuration, the insulator 224 can suppress the diffusion of hydrogen from below, and the insulator 225 can capture or fix hydrogen in the region surrounded by the insulators 224 and 250. This allows the hydrogen concentration in the region surrounded by the insulators 224 and 250 to be reduced.

[0127] Here, the insulator 225 does not necessarily have to be insulating in the strict sense, and a semiconductor with a wide band gap and high insulating properties may be used as the insulator 225. For example, a metal oxide material having lower conductivity than the oxide semiconductor 230b or a wider band gap than the oxide semiconductor 230b can be used as the insulator 225. Such a metal oxide material is preferably a metal oxide containing a large amount of gallium. The proportion of gallium in the insulator 225 is preferably higher than the proportion of gallium in the oxide semiconductor 230b. Here, the proportions of gallium and indium are compared in atomic percentage. For example, gallium oxide may be used for the insulator 225. Alternatively, a metal oxide containing indium, gallium, and zinc may be used as such a metal oxide material. In this case, the proportion of gallium in the insulator 225 is preferably higher than the proportion of indium. For example, a metal oxide having a composition of In:Ga:Zn=1:3:2 (atomic ratio) or a composition close to that ratio can be used as the insulator 225.

[0128] The insulator 225 preferably contains a Group 13 element (also referred to as a Group III element), such as gallium or indium, in common with the oxide semiconductor 230b. By having a high insulating property and containing a metal element common to the metal element contained in the oxide semiconductor 230, trap levels at the interface with the oxide semiconductor 230 and in the vicinity thereof can be reduced. For example, compared to when a silicon-based insulating material is used for the insulator 225, when the above-mentioned metal oxide material is used for the insulator 225, trap levels at the interface between the insulator 225 and the oxide semiconductor 230 and in the vicinity thereof can be reduced. This can reduce leakage current at the interface between the oxide semiconductor 230b and the insulator 225. Furthermore, the influence of interface states that may be formed on the back channel side of the oxide semiconductor 230 is reduced, which can suppress photodegradation (e.g., negative bias light photodegradation) of the transistor and improve the reliability of the transistor.

[0129] 2B shows an example in which the oxide semiconductor 230 has a three-layer structure, but the present invention is not limited thereto. The oxide semiconductor 230 may have a two-layer structure or a four-layer or more layer structure. For example, when the oxide semiconductor 230 has a two-layer structure, the oxide semiconductor 230 may have a two-layer structure of an oxide semiconductor 230b and an oxide semiconductor 230c on the oxide semiconductor 230b, as shown in FIG. 3A. By forming the oxide semiconductor 230 into a two-layer structure and reducing its thickness, the amounts of impurities such as hydrogen and excess oxygen contained in the oxide semiconductor 230 can be reduced, thereby improving the reliability of the transistor 200.

[0130] Furthermore, even if the thickness of the oxide semiconductor 230 is thin as described above, by using a structure in which the oxide semiconductor 230 is provided so as to cover the insulator 225 having a high aspect ratio, the oxide semiconductor 230 can be supported by the insulator 225. This allows the oxide semiconductor 230 to be formed so as to extend upward relative to the substrate without being tilted. Therefore, the channel width can be increased without increasing the occupation area.

[0131] In particular, by using a metal oxide with high insulating properties for the insulator 225 as described above, trap states at and in the vicinity of the interface between the oxide semiconductor 230b and the insulator 225 can be reduced without providing the oxide semiconductor 230a. This can reduce leakage current at the interface between the oxide semiconductor 230b and the insulator 225. Furthermore, the influence of interface states that may be formed on the back channel side of the oxide semiconductor 230b can be reduced, thereby improving the reliability of the transistor 200.

[0132] Although the above example shows the case where the insulator 224 is provided under the insulator 225, the present invention is not limited to this. As shown in FIG. 3B , a configuration without the insulator 224 is also possible. In this case, the insulator 225 and the oxide semiconductor 230 are formed in contact with the top surface of the insulator 222. When the oxide semiconductor 230 is processed into an island shape or when the opening 201 is formed, part of the top surface of the insulator 222 may be removed. As a result, as shown in FIG. 3B , the top surface of the insulator 222 in a region overlapping with the oxide semiconductor 230 may be higher than the top surface of the insulator 222 in a region not overlapping with the oxide semiconductor 230.

[0133] In addition, although the above describes an example in which the side surface of the insulator 225 is located more inward than the side surface of the insulator 224, the present invention is not limited to this. As shown in Fig. 4A, the side surfaces of the insulator 225 and the insulator 224 can also be formed to be flush with each other. Here, a configuration can be adopted in which the lower end of the side surface of the insulator 225 and the upper end of the side surface of the insulator 224 coincide or approximately coincide with each other.

[0134] Although the above example shows the oxide semiconductor 230 covering the insulator 225, the present invention is not limited thereto. As shown in FIG. 4B , the oxide semiconductor 230 may be provided in a sidewall shape in contact with the side surface of the insulator 225. For example, when the conductor 242a1 and the conductor 242b1 are separated, the oxide semiconductor 230 may be removed from a portion in contact with the top surface of the insulator 225 and a portion in contact with the top surface of the insulator 222, and the oxide semiconductor 230 may remain in a portion in contact with the side surface of the insulator 225. Even when the oxide semiconductor 230 has the above structure, the channel width of the transistor 200 can be made sufficiently large by increasing the height H of the insulator 225.

[0135] 5, the insulator 224 can have a structure including an insulator 224a and an insulator 224b on the insulator 224a, and the insulator 225 can have a structure including an insulator 225a and an insulator 225b on the insulator 225a. Here, the insulators 224a and 225a can be made of the above-mentioned insulating material that releases little hydrogen, such as silicon nitride.

[0136] The insulator 225b may be made of an insulating material that functions as a hard mask during etching of the insulator 225a. For example, when silicon nitride is used for the insulator 225a, aluminum oxide may be used for the insulator 225b. In this case, the thickness of the insulator 225b may be thinner than that of the insulator 225a.

[0137] The insulator 224b may be made of an insulating material that functions as an etching stopper when the insulator 225a is etched. For example, if silicon nitride is used for the insulator 225a, aluminum oxide may be used for the insulator 224b. In this case, the thickness of the insulator 224b may be thinner than that of the insulator 224a.

[0138] Alternatively, the insulator 224b may be made of silicon nitride, which has a high hydrogen barrier property. If the insulator 224b can sufficiently suppress the diffusion of impurity components such as hydrogen contained in the insulator 224a, the insulator 224a may be made of an insulating material, such as silicon oxide, that is relatively permeable to hydrogen.

[0139] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductors 242a, 242b, and 260. When a conductive material containing metal and nitrogen is used as the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 are conductors that contain at least metal and nitrogen.

[0140] The conductor 242a and the conductor 242b are spaced apart from each other through the opening 201 and are in contact with the oxide semiconductor 230. As shown in FIG. 8A and other drawings, the conductor 242 is provided to cover the insulator 225 having a high aspect ratio.

[0141] 8A , the oxide semiconductor 230 and the conductor 242a are provided near the source or drain of the transistor 200 so as to be folded in half with the insulator 225 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top of the insulator 225, the side surface on the A3 side, the side surface on the A4 side, and near the insulator 224. Therefore, compared to when the insulator 225 is not provided, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the side surface on the A3 side and the side surface on the A4 side of the insulator 225. Note that while FIGS. 8A and 1C show the vicinity of the conductor 242a, the same applies to the conductor 242b. That is, the contact area between the conductor 242b and the oxide semiconductor 230 is increased, similar to the contact area between the conductor 242a and the oxide semiconductor 230 described above.

[0142] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the contact resistance between the conductor 242 and the oxide semiconductor 230 can be reduced without significantly increasing the area occupied by the transistor 200. Therefore, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also enables miniaturization or high integration of the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0143] As shown in FIGS. 1D and 2A , the conductor 242a and the conductor 242b preferably have a two-layer structure. The conductor 242a is a stacked film of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b is a stacked film of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the layer in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1). This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. Furthermore, it can suppress the extraction of oxygen from the oxide semiconductor 230, which can result in the formation of an excessive amount of oxygen vacancies. Furthermore, it is preferable to use a material that easily absorbs (extracts) hydrogen for the layers in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1) because the hydrogen concentration in the oxide semiconductor 230 can be reduced.

[0144] For the conductor 242a1 and the conductor 242b1, it is preferable to use a metal nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0145] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, when a nitride containing tantalum is used for the conductor 242a1 and the conductor 242b1, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0146] Furthermore, the conductors 242a2 and 242b2 preferably have higher conductivity than the conductors 242a1 and 242b1. For example, the film thickness of the conductors 242a2 and 242b2 is preferably greater than the film thickness of the conductors 242a1 and 242b1. Conductive materials containing, for example, tungsten, copper, or aluminum as a main component can be used for the conductors 242a2 and 242b2. The above structure can reduce the resistance of the conductors 242a2 and 242b2. This can increase the on-current of the transistor 200 and improve the operating speed of the semiconductor device according to this embodiment.

[0147] For example, tantalum nitride or titanium nitride can be used as the conductors 242a1 and 242b1, and tungsten can be used as the conductors 242a2 and 242b2.

[0148] With the above structure, the top surface of the oxide semiconductor 230 is exposed in the region between the conductor 242a1 and the conductor 242b1, and the insulator 250 is in contact with this region. Here, as shown in FIG. 6B , the top surface of the oxide semiconductor 230 in this region may be lower than the other regions. That is, in the oxide semiconductor 230, the top surface of the region between the conductor 242a1 and the conductor 242b1 may be lower than the top surface of the region overlapping with the conductor 242a1 or the conductor 242b1. In this case, the film thickness of the oxide semiconductor 230 in contact with the top surface of the insulator 225 may be thinner than the film thickness of the oxide semiconductor 230 in contact with the side surface of the insulator 225. Furthermore, the portion of the oxide semiconductor 230 in contact with the top surface of the insulator 225, or a portion thereof, may be removed, and a portion of the insulator 225 may be in contact with the insulator 250.

[0149] In order to prevent a decrease in the conductivity of the conductor 242a and the conductor 242b, it is preferable to use a crystalline oxide as the oxide semiconductor 230. It is also preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of a crystalline oxide can prevent the conductor 242a or the conductor 242b from extracting oxygen from the oxide semiconductor 230. It can also prevent a decrease in the conductivity of the conductor 242a and the conductor 242b.

[0150] 1B and 1D , the insulator 255 is disposed in an opening 201 formed in the insulator 280 or the like, and is in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top and side surface of the conductor 242a1, the top and side surface of the conductor 242b1, and the top surface of the insulator 222. In other words, the openings can be said to be formed in the insulator 255 so as to expose the island-shaped oxide semiconductor 230 in the openings 201. Furthermore, in the region where the openings are formed in the insulator 255, the insulator 250 is in contact with the oxide semiconductor 230, the insulator 224, and the insulator 222. Note that in FIG. 1B , the insulator 255 has openings only near the oxide semiconductor 230, but the present invention is not limited to this. The insulator 255 only needs to have an opening in at least a region sandwiched between the conductor 242a1 and the conductor 242b1 of the oxide semiconductor 230. Therefore, for example, the insulator 255 may have almost no region in contact with the insulator 222 and may be formed in a sidewall shape in the opening formed in the insulator 280.

[0151] The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. Because the insulator 255 is exposed to an oxidizing atmosphere, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation. Furthermore, because the insulator 255 is in contact with the conductor 242a2 and the conductor 242b2, it is preferable that the insulator 255 be an inorganic insulator that is resistant to oxidation of the conductor 242a2 and the conductor 242b2. Therefore, it is preferable that the insulator 255 be made of an insulating material that can be used for the insulator 250d, which has oxygen barrier properties. For example, silicon nitride can be used as the insulator 255.

[0152] By using such an insulator 255, the conductors 242a2 and 242b2 are not excessively oxidized even if heat treatment is performed in an oxygen-containing atmosphere after dividing the conductors 242a1 and 242b1 and before forming the insulator 250. For example, the thickness of the oxide film on the side surfaces of the conductors 242a2 and 242b2 near the conductor 260 can be set to 0.5 nm or more and 5 nm or less, preferably 0.5 nm or more and 3 nm or less, and more preferably 0.5 nm or more and 2 nm or less.

[0153] The insulator 255 is preferably thicker than any one of the insulators 250a to 250d. The thickness of the insulator 255 is preferably 1 nm to 20 nm, more preferably 1 nm to 15 nm, and even more preferably 3 nm to 10 nm; for example, the thickness can be approximately 5 nm. By setting the insulator 255 to the above thickness, the distance between the conductor 260 and the conductor 242a or 242b can be increased, and parasitic capacitance can be reduced. Note that the insulator 255 only needs to have a region with the above thickness in at least a portion. Furthermore, since the insulator 255 is provided in the opening formed in the insulator 280, it is preferable to form the insulator 255 by an ALD method or the like, which has good coverage.

[0154] Furthermore, the insulator 255 may have a stacked structure of two or more layers using the inorganic insulator that is resistant to oxidation. When the insulator 255 has a stacked structure of two or more layers, at least one layer must be made of the inorganic insulator that is resistant to oxidation. For example, the insulator 255 may have a two-layer structure of a silicon nitride film and a silicon oxide film on the silicon nitride film.

[0155] Furthermore, the insulator 255 functions as part of a mask when dividing the transistor 200 into the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 2A , in a cross-sectional view of the transistor 200, the side edges of the insulator 255 preferably coincide or substantially coincide with the side edges of the conductor 242a1 and the conductor 242b1.

[0156] Here, the portion of the conductor 242a1 on whose upper surface the insulator 255 is formed (hereinafter, may be referred to as the protrusion of the conductor 242a1) is formed to protrude further toward the conductor 260 than the conductor 242a2. Similarly, the portion of the conductor 242b1 on whose upper surface the insulator 255 is formed (hereinafter, may be referred to as the protrusion of the conductor 242b1) is formed to protrude further toward the conductor 260 than the conductor 242b2. As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the distance D1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance D2 between the conductor 242a2 and the conductor 242b2.

[0157] The distance D1 between the conductor 242a1 and the conductor 242b1 is preferably very small because it affects the channel length of the transistor 200. For example, the distance D1 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and is preferably 1 nm or more, or 5 nm or more. For example, the distance D1 is more preferably approximately 2 nm or more and 20 nm or less. This configuration makes it possible to further shorten the distance between the source and drain, thereby shortening the channel length accordingly. This improves the frequency characteristics of the transistor 200. In this way, by shortening the channel length of the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0158] 2A , the opposing side surfaces of the conductor 242a1 and the conductor 242b1 are substantially perpendicular to the top surface of the oxide semiconductor 230, but the present invention is not limited to this. For example, as shown in FIG. 7A , the opposing side surfaces of the conductor 242a1 and the conductor 242b1 may have a tapered shape. With such a shape, the distance between the conductor 260 and the oxide semiconductor 230 is reduced near the side ends of the conductor 242a1 and the conductor 242b1, and therefore a gate electric field can be effectively applied to the oxide semiconductor 230.

[0159] 7B, the opposing side surfaces of the conductors 242a1 and 242b1 may be tapered, and the opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered. Also, as shown in FIG. 7C, the taper angles of the conductors 242a1 and 242b1 may be more acute than the taper angles of the conductors 242a2 and 242b2.

[0160] Although the above example shows a two-layer stacked structure of the conductors 242a and 242b, the present invention is not limited to this. The conductors 242a and 242b can also be a single-layer structure or a stacked structure of three or more layers. For example, as shown in FIG. 6C , the conductors 242a and 242b can be a single-layer structure. In this case, the conductors 242a and 242b can be made of a conductive material that can be used for the conductors 242a1 and 242b1. In this case, as shown in FIG. 6C , the insulator 255 can be omitted, and the insulators 280 and 275 can be in contact with the insulator 250.

[0161] 1B and 1D , the conductor 260 is disposed in the opening 201 formed in the insulator 280 and the insulator 275. The conductor 260 is disposed in the opening 201 so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 with the insulator 250 interposed therebetween. Furthermore, as shown in FIG. 2A , part of the conductor 260 overlaps with part of the conductor 242a1 and part of the conductor 242b1 with the insulator 255 interposed therebetween. Furthermore, the top surface of the conductor 260 is disposed so as to be flush or substantially flush with the top of the insulator 255, the top of the insulator 250, and the top surface of the insulator 280.

[0162] In the opening 201 in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening 201 may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may have a tapered shape. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0163] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction, as shown in Figures 1A and 1B. With this configuration, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0164] Part of the conductor 260 is folded in half with the insulator 225 sandwiched therebetween. As a result, as shown in FIG. 2B , in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are arranged to face each other with the insulator 250 sandwiched therebetween at the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224. That is, the upper part of the oxide semiconductor 230, the side surface on the A1 side, the side surface on the A2 side, and the vicinity of the insulator 224 each function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the insulator 225 is not provided.

[0165] In Figure 1D and other figures, the conductor 260 is shown as having a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the conductor 260a.

[0166] The conductor 260a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0167] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 280, etc. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0168] The conductor 260b is preferably made of a highly conductive material. For example, the conductor 260b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0169] In the transistor 200, the conductor 260 is formed in a self-aligned manner to fill the opening 201 formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the opening 201 coincides with or substantially coincides with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Therefore, the conductor 260 can be arranged to overlap the region between the conductor 242a2 and the conductor 242b2 without alignment.

[0170] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance between wirings can be reduced.

[0171] For example, it is preferable that the insulators 216 and 280 each have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0172] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0173] Furthermore, the top surfaces of the insulators 216 and 280 may each be flattened.

[0174] It is preferable that the concentration of impurities such as water and hydrogen be reduced in the insulator 280. For example, it is preferable that the insulator 280 have an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0175] Conductor 240a and conductor 240b are formed in openings of insulators 275, 280, 282, and 283, respectively. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0176] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may also have a layered structure in which a first conductor is provided in contact with the side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 shown in FIG. 8A, and the second conductor corresponds to the conductor 240a2 shown in FIG. 8A.

[0177] Furthermore, when the conductor 240 has a layered structure, the first conductor disposed near the insulators 283, 282, 280, and 275 is preferably made of a conductive material that has a function of suppressing permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. Furthermore, the conductive material that has a function of suppressing permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. With such a structure, impurities such as water and hydrogen contained in layers above the insulator 283 can be prevented from entering the oxide semiconductor 230 through the conductors 240a and 240b.

[0178] The insulators 241a and 241b are formed in contact with the inner walls of the openings of the insulators 275, 280, 282, and 283, respectively. The inner side surface of the insulator 241a contacts the conductor 240a, and the inner side surface of the insulator 241b contacts the conductor 240b.

[0179] The insulator 241 may be a barrier insulating film that can be used for the insulator 275, etc. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide semiconductor 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0180] When the insulator 241 has a layered structure, it is preferable that the first insulator in contact with the inner wall of the opening, such as the insulator 280, and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0181] For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and further reduce hydrogen contamination of the conductor 240.

[0182] Although the above describes a configuration in which the insulator 241 has a two-layer stacked structure, the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, although the above describes a configuration in which the conductor 240 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers.

[0183] 8A and other figures show a configuration in which the conductor 240a is mainly in contact with the upper surface of the conductor 242a2, but the present invention is not limited to this. The conductor 240a may also cover the side surfaces of the conductor 242a2, the conductor 242a1, the oxide semiconductor 230, and the insulator 224. This configuration can increase the contact area between the conductor 240a and the conductor 242a. While the above description is directed to the conductor 240a, the same applies to the conductor 240b.

[0184] As described above, by increasing the contact area between the conductor 240 and the conductor 242, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This allows the on-state current, frequency characteristics, and the like of the transistor 200 to be improved without significantly increasing the area occupied by the transistor 200. This makes it possible to provide a semiconductor device with high operating speed. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. Furthermore, the storage capacity of a memory device using the semiconductor device can be increased.

[0185] Note that, as shown in FIG. 1A , the shape of the opening through which the conductor 240 and the insulator 241 are provided is rectangular in plan view, but is not limited thereto. For example, the opening may be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners in plan view. As shown in FIG. 1C , the opening is formed to overlap the oxide semiconductor 230 and the insulator 225. However, this is not limiting and the opening may be formed to overlap at least the conductor 242 a or the conductor 242 b. For example, as shown in FIG. 8B , a part of the opening (which can also be referred to as a part of the conductor 240) can overlap the insulator 225, and another part of the opening (which can also be referred to as the other part of the conductor 240) can be configured not to overlap the insulator 225. By configuring the conductor 240 so that a part of the conductor 240 overlaps the insulator 225, the margin for arranging the conductor 240 can be increased. Also, for example, as shown in FIG. 8C, the opening and the conductor 240 can be provided in an area that does not overlap with the insulator 225.

[0186] 1D , 8B , and 8C , the conductor 240a and the conductor 240b are arranged symmetrically with respect to the conductor 260, but the present invention is not limited to this. For example, as shown in FIG. 9A , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that part of the conductor 240a overlaps with the insulator 225 and the conductor 240b does not overlap with the oxide semiconductor 230. Further, as shown in FIG. 9B , in a cross-sectional view in the channel length direction, the conductor 240a may be arranged so that the entire or almost the entire conductor 240a overlaps with the insulator 225 and the conductor 240b does not overlap with the oxide semiconductor 230.

[0187] 10A to 10D , the semiconductor device of this embodiment may have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulators 222, 221, 224, and 225 each have a region that functions as a second gate insulator of the transistor 200. Here, FIGS. 10A to 10D correspond to FIGS. 1A to 1D , and therefore the above description can be referred to for detailed configurations.

[0188] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening formed in the insulator 216. Furthermore, the conductor 205 is preferably provided to extend in the channel width direction as shown in FIGS. 10A and 10B . With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0189] 10B and 10D, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides with or approximately coincides with the height of the upper surface of the insulator 216.

[0190] Here, the conductor 205a is composed of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0191] By using a conductive material that can reduce hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 via the insulator 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 205a, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductor 205a preferably contains titanium nitride.

[0192] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0193] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. Furthermore, when the transistor 200 is an n-channel transistor, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.

[0194] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore, diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0195] Although the above describes a layered structure of conductor 205a and conductor 205b, the present invention is not limited to this, and conductor 205 may have a single-layer structure or a layered structure of three or more layers. For example, when conductor 205 has a three-layer layered structure, the layered structure of conductor 205a and conductor 205b may further include a conductor made of the same material as conductor 205a provided on conductor 205b. In this case, the conductor may be formed so that the top surface of conductor 205b is lower than the top of conductor 205a, and the conductor fills the recess formed by conductor 205a and conductor 205b.

[0196] 1A to 1D , the insulator 224 is provided only in a region overlapping with the oxide semiconductor 230, but the present invention is not limited to this. For example, as shown in FIGS. 11A to 11D , the insulator 224 may be provided not only in a region overlapping with the oxide semiconductor 230 but also outside the opening 201. Here, FIGS. 11A to 11D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0197] In the semiconductor device of one embodiment of the present invention, the shape of the insulator 224 in a plan view may be made to match or substantially match the shape of the oxide semiconductor 230 in a plan view at least in the opening 201. In other words, the opening 201 preferably reaches the oxide semiconductor 230 and the insulator 222 in the vicinity of the oxide semiconductor 230. In this case, the insulator 224 is provided between the insulator 222 and the insulator 275, as shown in FIGS.

[0198] 1A to 1D , the transistor 200 includes one insulator 225, but the present invention is not limited thereto and may include a plurality of insulators 225. For example, as shown in FIGS. 12A to 12D , the insulators 225_1 and 225_2 may be arranged in the A1-A2 direction, and the oxide semiconductor 230 may be provided to cover the insulators 225_1 and 225_2. Here, FIGS. 12A to 12D correspond to FIGS. 1A to 1D , respectively, and therefore the above description can be referred to for detailed configurations.

[0199] 12B , by providing the insulator 225_1 and the insulator 225_2, the area where the oxide semiconductor 230 and the conductor 260 face each other across the insulator 250 can be increased compared to when only one insulator 225 is provided. This can increase the channel width per unit area. Furthermore, by providing the insulator 225_1 and the insulator 225_2 as shown in FIG. 12C , the contact area between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2) can be increased compared to when only one insulator 225 is provided. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 242a2 (conductor 242b2).

[0200] In the above description, the insulators 225 (insulators 225_1 and 225_2) have a rectangular shape extending in the A5-A6 direction, but the present invention is not limited to this. For example, the planar shape of the insulator 225 may be a circumferential shape (which may also be called a frame shape, annular shape, doughnut shape, or closed curve shape) in which both ends coincide or approximately coincide. For example, the insulators 225_1 and 225_2 shown in FIG. 12A may have a shape in which both ends are connected.

[0201] 1A to 1D, respectively. The semiconductor device shown in Figures 13A to 13D differs from the semiconductor device shown in Figures 1A to 1D in that insulators 271a and 271b are provided, insulator 255 is provided in a sidewall shape on the side wall of opening 201, and insulator 224 is not provided. Note that in Figure 13C, to make the structure of insulator 271a easier to see, dashed dotted line A3-A4 is drawn at a position that does not overlap with conductor 240a, unlike in Figure 1C.

[0202] The insulator 271a is provided in contact with the upper surface of the conductor 242a2 and coincides or substantially coincides with the conductor 242a2 in a planar view. Similarly, the insulator 271b is provided in contact with the upper surface of the conductor 242b2 and coincides or substantially coincides with the conductor 242b2 in a planar view. The upper surfaces of the insulators 271a and 271b contact the insulator 275. An opening is also formed in the insulator 271a, and the side surface of the insulator 271a contacts the insulator 241a through the opening. Similarly, an opening is also formed in the insulator 271b, and the side surface of the insulator 271b contacts the insulator 241b through the opening. Furthermore, in a planar view, the side end of the insulator 271a on the opening 201 side and the side end of the insulator 271b on the opening 201 side contact the insulator 255.

[0203] 13A to 13D , the insulators 271a and 271b can be made of an insulating material that can be used for the insulators 275 and 250, and it is preferable to use an insulating material that can be used for the insulator 275. For example, silicon nitride can be used for the insulators 271a and 271b. Note that in the example shown in FIGS. 13A to 13D , the insulators 271a and 271b may have a stacked structure of two or more layers. For example, when the insulators 271a and 271b have a two-layer stacked structure, silicon nitride can be used for the lower layer and silicon oxide can be used for the upper layer.

[0204] 13A to 13D, it is preferable to deposit insulating films to be the insulators 271a and 271b successively after depositing conductive films to be the conductors 242a2 and 242b2. With this structure, the conductors 242a2 and 242b2 can be protected by the insulators 271a and 271b during the manufacturing process of the semiconductor device. Therefore, the yield of the semiconductor device can be improved.

[0205] 13A to 13D, the insulator 255 is formed in a sidewall shape in contact with the side wall of the opening 201. Therefore, as shown in FIGS. 13B and 13C, the side surface of the insulator 255 contacts the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. Furthermore, the lower surface of the insulator 255 contacts the upper surface of the insulator 222, the upper surface of the conductor 242a1, and the upper surface of the conductor 242b1. With this configuration, the film thickness of the insulator 255 is equal to or approximately equal to the length of the protruding portion of the conductor 242a1 and the length of the protruding portion of the conductor 242b1.

[0206] The insulator 255 having the above-described configuration can be formed in a self-aligned manner by forming an insulating film that will become the insulator 255 after the opening 201 is formed and then anisotropically etching the insulating film. This allows the insulator 255 to be formed inside the opening 201 without forming a separate mask, thereby improving the productivity of the semiconductor device.

[0207] 13A to 13D , the insulator 224 is not provided, and therefore the insulator 225 and the oxide semiconductor 230 are in contact with the top surface of the insulator 222. However, this is not limiting, and the insulator 224 can also be provided between the insulator 225 and the oxide semiconductor 230 and the insulator 222.

[0208] 14A, the transistor 200, the capacitor 460, and the transistor 310 formed on a silicon substrate can function as a 2T (transistor) 1C (capacitor) memory cell. As shown in FIG. 14A, a layer including the transistor 200 and the capacitor 460 can be provided over a layer including the transistor 310. FIG. 15A shows a cross-sectional view of the transistor 200 in the channel width direction, FIG. 15B shows a cross-sectional view of the capacitor 460 in the channel width direction, and FIG. 15C shows a cross-sectional view of the transistor 310 in the channel width direction.

[0209] The transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes part of the substrate 311, and low-resistance regions 314a and 314b that function as source and drain regions. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 can be, for example, a single-crystal silicon substrate.

[0210] As shown in FIG. 15C , the transistor 310 has a semiconductor region 313 (a part of the substrate 311) where a channel is formed, which has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it utilizes the convex portion of the semiconductor substrate. An insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI (silicon-on-insulator) substrate.

[0211] Note that the transistor 310 illustrated in FIG. 14A is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0212] A wiring layer including an interlayer film, wiring, plugs, etc. may be provided between each structure. A plurality of wiring layers may be provided depending on the design. In this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as the wiring, and a part of the conductor may function as the plug.

[0213] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulators 320 and 322. A conductor 330 or the like is embedded in the insulators 324 and 326. The conductors 328 and 330 function as contact plugs or wirings.

[0214] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0215] The transistor 200 and the capacitor 460 are provided over the insulator 326. Here, the transistor 200 shown in FIG. 1D is used as the transistor 200. The structures of the transistor 200 and the layer in which the transistor 200 is formed are the same as those described above and are indicated by the same hatching patterns and symbols. For detailed structures, refer to the above description. Note that an insulator 285 is formed over the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed over the insulator 285. The insulator 285 can be formed using an insulating material that can be used for the insulator 216. The conductor 413 can be formed using a conductive material that can be used for the conductor 242.

[0216] The capacitor 460 includes an insulator 425 over the insulator 224, an oxide semiconductor 230 covering the insulator 425, a conductor 242b1 over the oxide semiconductor 230, an insulator 455 over the conductor 242b1, an insulator 454 over the insulator 455, and a conductor 456 over the insulator 454. The insulators 455, 454, and 456 are provided in openings 202 formed in the insulators 280, 275, and the like. As shown in FIGS. 14A , 15A , and 15B , the oxide semiconductor 230 and the conductor 242b1 are also used in the transistor 200. The opening 202 can be formed in the same process as the opening 201. The insulator 425 has a similar structure to the insulator 225 and can be formed in the same process. The insulator 455 has a similar structure to the insulator 255 and can be formed in the same process. The insulator 454 has a structure similar to that of the insulator 250 and can be formed in the same process. The conductor 456 has a structure similar to that of the conductor 260 and can be formed in the same process. Note that the conductor 260 can be provided in an extended state as described above and can function as a wiring. The conductor 456 can also be provided in an extended state and can function as a wiring.

[0217] Here, the capacitor 460 includes a conductor 242b1 functioning as a first electrode, a conductor 456 functioning as a second electrode, and an insulator 455 and an insulator 454 functioning as dielectrics. That is, the capacitor 460 includes a metal-insulator-metal (MIM) capacitor.

[0218] The capacitor 460 has a structure similar to that of the transistor 200 and can be formed in the same layer as the transistor 200 in parallel. However, the capacitor 460 differs from the transistor 200 in that the conductor 242b1 and the insulator 455 overlap with the conductor 456 and the insulator 454. For example, as shown in FIG. 15A , an opening is formed in part of the insulator 255 in the opening 201, and the opening overlaps with part of the oxide semiconductor 230. In addition, in a region where the opening in the insulator 255 overlaps with the oxide semiconductor 230, the conductor 242b1 is not formed on the oxide semiconductor 230. In contrast, as shown in FIG. 15B , no opening is formed in the insulator 455 in the opening 202, and the oxide semiconductor 230 is covered with the insulator 455. In addition, in the opening 202, the conductor 242b1 is in contact with the top surface of the oxide semiconductor 230, and the insulator 455 is in contact with the top surface of the conductor 242b1.

[0219] 15B , the insulator 425 of the capacitor 460 has a structure with a high aspect ratio, similar to the insulator 225. Therefore, the area where the conductor 242b1, the insulator 455, the insulator 454, and the conductor 456, which are provided along the top surface and side surface of the insulator 425, face each other can be increased. This allows the capacitance to be increased without significantly increasing the area occupied by the capacitor 460.

[0220] The conductor 458 is preferably provided in openings formed in the insulators 215, 216, 221, 222, and 224. The conductor 458 can have a structure similar to that of the conductor 240, for example. The top surface of the conductor 458 is in contact with the bottom surface of the oxide semiconductor 230 and can be electrically connected to the conductor 330. Note that although only one conductor 458 is shown in FIG. 14A , this is not a limitation, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. Furthermore, a structure in which the conductor 242b1 and part of the oxide semiconductor 230 are embedded in the openings formed in the insulators 215, 216, 221, 222, and 224 may be used. The top surface of the conductor 458 does not necessarily have to be in contact with the bottom surface of the oxide semiconductor 230. For example, the upper surface of the conductor 458 can be exposed from the upper surface of the insulator 285, and a conductor similar to the conductor 240 can be provided in contact with the upper surface of the conductor 242b2, and the conductor and the conductor 458 can be electrically connected via wiring.

[0221] With the above structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310 are electrically connected to form a 2T1C memory cell. Note that a 1T1C memory cell can also be formed by using a structure without the transistor 310. Furthermore, a 2T0C memory cell can also be formed by using a structure without the capacitor 460.

[0222] Here, the transistor 310 is preferably provided so as to overlap with at least one of the transistor 200 and the capacitor 460. For example, the transistor 310 may overlap with the transistor 200. With such a structure, the area occupied by the memory cell can be reduced.

[0223] 14A illustrates a structure in which the transistor 200 includes the insulator 225 and the capacitor 460 includes the insulator 425, but the present invention is not limited to this. For example, as illustrated in FIG. 14B , a structure in which the insulator 250, the conductor 260, the insulator 455, the insulator 454, and the conductor 456 are formed over the insulator 225 and the oxide semiconductor 230 without providing the insulator 425 may be used. That is, the transistor 200 and the capacitor 460 may share the insulator 225. This eliminates the need to separate the insulator 225 between the transistor 200 and the capacitor 460, thereby reducing the area occupied by the transistor 200 and the capacitor 460.

[0224] Although the structure shown in FIG. 14A illustrates a configuration in which the transistor 310 is formed on a silicon substrate, the present invention is not limited to this. For example, as shown in FIG. 16A , two transistors (hereinafter referred to as transistors 200a and 200b) having the same structure as the transistor 200 may be provided. Here, the transistors 200a and 200b are formed in the same layer and are arranged so that their channel length directions intersect with each other. Note that the transistors 200a and 200b have the same structure as the transistor 200, and therefore the components are indicated by the same hatched patterns and symbols. For detailed structure, please refer to the above description.

[0225] 16A , the capacitor 400 is provided over the insulator 285. The capacitor 400 includes a conductor 410 over the insulator 285, an insulator 430 over the conductor 410, and a conductor 420 over the insulator 430. The conductor 240b, the insulator 241b, the conductor 240c, and the insulator 241c are provided in contact with the bottom surface of the conductor 410. The conductor 240c and the insulator 241c are formed so as to be embedded in the openings of the insulators 282, 283, and 285, and have the same structure as the conductor 240b and the insulator 241c. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. With this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b are electrically connected to each other.

[0226] The capacitor 400 includes a conductor 410 functioning as a first electrode, a conductor 420 functioning as a second electrode, and an insulator 430 functioning as a dielectric. That is, the capacitor 400 forms an MIM capacitor.

[0227] The conductor 410 and the conductor 420 may be made of a conductive material that can be used for the conductor 260. For example, tungsten can be used for the conductor 410 and the conductor 420. Here, by using a structure in which the conductor 420 covers the conductor 410, the side surface of the conductor 410 can function as the capacitor 400. This allows the capacitance of the capacitor 400 to be increased. The conductor 413 can be formed simultaneously with the conductor 410.

[0228] Although the conductors 410, 413, and 420 each have a single-layer structure, they are not limited to this structure and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor with high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0229] The insulator 430 of the capacitor 400 is preferably made of a high-dielectric-constant (high-k) material. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials makes it possible to thicken the insulator 430 to suppress leakage current and ensure sufficient capacitance of the capacitor 400. Furthermore, since the insulator 430 is formed to cover the conductor 410, it is preferable to form the insulator 430 using a film formation method with good coverage, such as an ALD method or a CVD method.

[0230] The insulator 430 may also have a layered structure. It is preferable to use a layered structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-dielectric-constant (high-k) material. Materials with a high dielectric strength (materials with a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, and silicon oxide with carbon and nitrogen added. The insulator 430 may have a layered structure of aluminum oxide, a high-dielectric-constant (high-k) material, and silicon oxide with a high dielectric strength on the aluminum oxide.

[0231] For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, and zirconium oxide. For example, the insulator 430 can be an insulator stacked in this order: zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide. For example, the insulator 430 can be an insulator stacked in this order: hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide. By stacking insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor 400 can be suppressed.

[0232] Furthermore, a material that can have ferroelectricity may be used as the insulator 430. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0). Ferroelectric materials include hafnium oxide to which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. The ratio of the number of hafnium atoms to the number of element J1 can be set as appropriate; for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close to 1:1. Ferroelectric materials include zirconium oxide to which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added. Ferroelectric materials include hafnium ... (here, element J2 can be set as appropriate; for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close to 1:1. Furthermore, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0233] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0234] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0235] Although the above description has been given with reference to metal oxides and metal nitrides, the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides, or metal oxynitrides in which oxygen is added to the above metal nitrides, may also be used.

[0236] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulator 430 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0237] 16A, the shape of the capacitor 400 is a planar type, but the shape of the capacitor 400 in the memory device described in this embodiment is not limited to this. For example, the shape of the capacitor 400 may be a cylinder or a pillar.

[0238] An insulator 487 is provided to cover the capacitor 400, and an insulator 488 is provided to cover the insulator 487. The insulator 487 is preferably an insulator that has a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulator 487. The insulator 488 is preferably an insulator that has a function of suppressing diffusion of hydrogen. For example, silicon nitride, which has a higher hydrogen barrier property, may be used for the insulator 488.

[0239] 16A shows a structure in which the transistors 200a and 200b are provided in the same layer, but the present invention is not limited to this. For example, as shown in FIG. 16B, a structure in which a layer 401a including the transistor 200a is stacked on a layer 401b including the transistor 200b may be used. Note that the layers 401a and 401b have the same structure as the layers from the insulator 215 to the insulator 285 shown in FIG.

[0240] 16B, the conductor 240c and the insulator 241c may be formed in openings provided in the insulators 282 to 285 of the layer 401b and the insulators 215 to 285 of the layer 401a. With such a structure, the conductor 410 of the capacitor 400 and the conductor 260 of the transistor 200b can be electrically connected. Note that the conductor 410 and the conductor 260 of the transistor 200b do not need to be connected only by the conductor 240c. Two or more conductors may be used to electrically connect the conductor 410 and the conductor 260 of the transistor 200b.

[0241] Here, the transistor 200b is preferably provided so as to overlap with at least one of the transistor 200a and the capacitor 400. For example, the oxide semiconductor 230 of the transistor 200b is preferably provided so as to overlap with at least one of the oxide semiconductor 230 of the transistor 200a and the conductor 410 of the capacitor 400. With such a structure, the area occupied by the memory cell can be reduced.

[0242] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0243] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0244] <<Insulators>> Examples of insulators that can be used for at least one of the insulators 215, 216, 221, 222, 224, 225, 241, 250, 255, 271a, 271b, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, 425, 430, 454, 455, 487, and 488 include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0245] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select a material depending on the function of the insulator.

[0246] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0247] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0248] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulators containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0249] The insulator functioning as the gate insulator preferably has a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0250] <<Conductor>> As a conductor that can be used for at least one of the conductors 205, 240, 242, 260, conductor 316, conductor 328, conductor 330, conductor 410, conductor 413, conductor 420, conductor 456, and conductor 458, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. Examples of the conductor include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0251] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0252] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0253] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive materials containing the metal element and nitrogen described above may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0254] 1A to 1D , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

[0255] (A) in each figure is a plan view. Also, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Also, (D) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in (A) of each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. Note that some elements are omitted from the plan view (A) of each figure for clarity.

[0256] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0257] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0258] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. They can also be further classified into metal CVD (MCVD) and MOCVD, depending on the source gas used.

[0259] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0260] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0261] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0262] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0263] Furthermore, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0264] First, a substrate (not shown) is prepared, and an insulator 215 is formed on the substrate (see FIGS. 17A to 17D ). As described above, the insulator 215 can be formed using an insulator similar to one or more stacked films of the insulators 282 and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0265] Next, the insulator 216 is deposited over the insulator 215. The insulator 216 is preferably deposited by a sputtering method. The hydrogen concentration in the insulator 216 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. However, the deposition of the insulator 216 is not limited to a sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0266] The insulators 215 and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen content and reduces the amount of hydrogen mixed into the films between film formation steps.

[0267] 10A to 10D can be formed by forming an opening in the insulator 216 that reaches the insulator 215 and forming the conductor 205 in the opening. The conductor 205 can be formed by depositing a conductive film that can be used for the conductor 205 so as to fill the opening and removing part of the conductive film by CMP treatment.

[0268] Next, an insulator 221 is formed on the insulator 216 (see FIGS. 17A to 17D).

[0269] The insulator 221 may be any of the above insulators that have barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0270] Next, an insulator 222 is formed on the insulator 221 (see FIGS. 17A to 17D).

[0271] The insulator 222 is preferably an insulator containing one or both of an oxide of aluminum and hafnium. As the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. When the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in structures provided around the transistor are prevented from diffusing into the transistor through the insulator 222, and thus oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0272] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, hafnium oxide is formed as the insulator 222 by a thermal ALD method.

[0273] In this embodiment, silicon nitride is deposited as the insulator 221 by a PEALD method, and hafnium oxide is deposited as the insulator 222 by a thermal ALD method. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 221 in this manner, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide, which has a function of capturing or fixing hydrogen, for the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0274] Next, an insulating film 224f is formed on the insulator 222 (see FIGS. 17A to 17D). The insulating film 224f is an insulating film that will become the insulator 224 in a later process. Therefore, any of the insulating materials that can be used for the insulator 224 described above may be used. The insulating film 224f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0275] In this embodiment, the insulating film 224f is a stacked film of a silicon oxide film and an aluminum oxide film on the silicon oxide film. For example, the silicon oxide film can be formed by sputtering, and the aluminum oxide film can be formed by thermal ALD. With this configuration, the insulator 224 can have a stacked structure of an insulator 224a containing silicon oxide and an insulator 224b containing aluminum oxide, as shown in FIG.

[0276] Next, an insulating film is formed over the insulating film 224f and etched to form the insulator 225 (see FIGS. 17A to 17D ). The insulator 225 may be formed using any of the insulating materials that emit little hydrogen and can be used for the insulator 225. The insulating film that becomes the insulator 225 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0277] In this embodiment, the insulating film is a stacked film of a silicon nitride film and an aluminum oxide film on the silicon nitride film. For example, the silicon nitride film can be formed by sputtering, and the aluminum oxide film can be formed by thermal ALD. With this structure, the insulator 225 can have a stacked structure of an insulator 225a containing silicon nitride and an insulator 225b containing aluminum oxide, as shown in FIG. 5 . This stacked structure allows the aluminum oxide layer to function as a hard mask in the etching process of the silicon nitride layer of the insulator 225. This allows the side surface of the insulator 225 to be perpendicular or approximately perpendicular to the top surface of the insulating film 224f. With this structure, a smaller area and higher density can be achieved when providing multiple transistors.

[0278] Furthermore, without being limited to the above, a highly insulating metal oxide material may be used as the insulating film that becomes the insulator 225. For example, gallium oxide can be deposited as the insulating film by sputtering or ALD. Furthermore, for example, In—Ga—Zn oxide, in which the proportion of gallium is higher than the proportion of indium, can be deposited as the insulating film by sputtering or ALD. For example, In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2 can be deposited as the insulating film.

[0279] When forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not necessarily match.

[0280] The insulator 225 may be processed into an island shape by lithography. This processing can be performed by dry etching or wet etching. Dry etching is suitable for fine processing.

[0281] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left behind using a developer to form a resist mask. Next, etching is performed through the resist mask to process a conductor, semiconductor, insulator, or the like into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a photomask may not be used.

[0282] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0283] Furthermore, a hard mask made of an insulator or conductor may be used under the resist mask. For example, in the above example, an aluminum oxide film on the silicon nitride film functions as the hard mask. When using a hard mask, an insulating or conductive film serving as the hard mask material is formed, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of the desired shape. The silicon nitride film may be etched after removing the resist mask, or may be etched while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the silicon nitride film. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0284] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as masks can improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0285] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0286] A capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. A capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. The DF-CCP etching apparatus may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0287] Furthermore, by using a material that is difficult to etch, such as aluminum oxide, for the upper layer of the insulating film 224f, the insulating film 224f can function as an etching stopper when the insulator 225 is etched.

[0288] Note that although the above description shows a structure in which one insulator 225 is provided in the transistor 200, the present invention is not limited to this. A structure in which two or more insulators 225 are provided separately can also be used. For example, by using a structure in which the insulator 225_1 and the insulator 225_2 are provided, the transistor 200 having the structure shown in FIGS. 12A to 12D can be formed.

[0289] Next, an oxide semiconductor film 230f that will become the oxide semiconductor 230 is formed to cover the insulator 225 (see FIGS. 18A to 18D ). The oxide semiconductor film 230f is a metal oxide film that will become the oxide semiconductor 230 in a later step, and any of the above-described metal oxide films can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0290] Since the oxide semiconductor film 230f is formed along the insulator 225, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method or the like, which has good coverage. Furthermore, since it is preferable that the oxide semiconductor 230 has a high aspect ratio, it is preferable that the oxide semiconductor film 230f have a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f be formed by an ALD method, which allows for adjustment of the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the top surface and side surface of the insulator 225.

[0291] Here, the oxide semiconductor film 230f may be formed by the same method as that of the oxide semiconductor described in Embodiment 2. It is preferable to use indium oxide (for example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide) for the oxide semiconductor film 230f. When the oxide semiconductor film 230f contains indium oxide, a semiconductor device with high field-effect mobility can be provided. Furthermore, a semiconductor device with favorable electrical characteristics, frequency characteristics, and reliability can be provided.

[0292] For example, when the oxide semiconductor 230 has a three-layer structure including oxide semiconductors 230a to 230c as shown in FIG. 2B , films to be the oxide semiconductors 230a to 230b can be deposited by ALD, and a film to be the oxide semiconductor 230c can be deposited by sputtering. Specifically, the film to be the oxide semiconductor 230a can be deposited to have a composition of In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout. Alternatively, gallium oxide may be used for the film to be the oxide semiconductor 230a. Furthermore, indium oxide can be used for the film to be the oxide semiconductor 230b. Furthermore, the film to be the oxide semiconductor 230c can be deposited using an oxide target having a composition of In:Ga:Zn=1:1:1.2 (atomic ratio) or a composition thereabout.

[0293] The three-layer structure of the oxide semiconductors 230a to 230c is not limited to the above structure. For example, the oxide semiconductors 230a to 230c may be formed by an ALD method. In this structure, the oxide semiconductors 230a to 230c can be successively formed using a single manufacturing apparatus without using a sputtering method, thereby reducing manufacturing costs. After the oxide semiconductors 230a, 230b, and 230c are formed, microwave treatment may be performed on each of them. The microwave treatment can reduce impurities such as hydrogen contained in the oxide semiconductor 230 and improve the crystallinity of the oxide semiconductor 230.

[0294] Although the oxide semiconductor film 230f has a three-layer structure in the above description, the present invention is not limited thereto and may have a single-layer, two-layer, or four or more-layer structure. For example, the oxide semiconductor film 230f may have a two-layer structure including a film that becomes the oxide semiconductor 230b and a film that becomes the oxide semiconductor 230c. In this case, the insulator 225 preferably uses the metal oxide having high insulating properties. This structure can reduce trap levels at and near the interface between the insulator 225 and the oxide semiconductor 230b. This structure can improve the reliability of the transistor 200.

[0295] Next, heat treatment is preferably performed. The heat treatment of the oxide semiconductor film 230f may be performed by the same method as the heat treatment described in Embodiment 2.

[0296] For example, the heat treatment can be carried out at a flow rate ratio of nitrogen gas to oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0297] The heat treatment can improve the crystallinity of the oxide semiconductor 230. As a result, the on-state current, the subthreshold swing value (S value), the field-effect mobility, the frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0298] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0299] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f and the like as much as possible. Note that highly purified gas can also be used in the heat treatment before and after this step.

[0300] Furthermore, the heat treatment using oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This increases the crystalline regions in the oxide semiconductor film 230f, reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0301] Furthermore, by performing heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, and oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0302] Furthermore, by performing heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentration in the oxide semiconductor film 230f decreases. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0303] In particular, the oxide semiconductor film 230f (later the oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced is preferable because it has good reliability.

[0304] Note that it is preferable to perform a treatment for increasing the crystallinity of the oxide semiconductor film 230f during or after the formation of the oxide semiconductor film 230f. Examples of the treatment for increasing the crystallinity of the oxide semiconductor film 230f include heat treatment, plasma treatment, microwave (typically, 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. Note that a plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0305] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the oxide semiconductor film 230f multiple times during the formation of the oxide semiconductor film 230f. For example, when the oxide semiconductor film 230f is formed by an ALD method, it is preferable to perform a microwave plasma treatment after each atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity after each oxide semiconductor film 230f having a thickness within a predetermined range, which can improve productivity. Specifically, it is preferable to form a first oxide semiconductor film having a thickness of 1 nm to 10 nm as the oxide semiconductor film 230f, perform the first microwave plasma treatment, and then form a second oxide semiconductor film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment. Note that the methods for forming the first oxide semiconductor film and the second oxide semiconductor film are not particularly limited, and ALD or sputtering may be used, respectively. In particular, forming the first oxide semiconductor film by an ALD method is preferable because it can prevent elements of the layers constituting the formation surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film. This is particularly suitable when the elements contained in the layers constituting the formation surface inhibit crystallization of the oxide semiconductor (for example, when silicon, carbon, or the like is contained). The first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Although a stacked structure of the first oxide semiconductor film and the second oxide semiconductor film is illustrated here, the present invention is not limited to this. The oxide semiconductor film 230f can be formed as a single layer or a stacked structure of three or more layers.

[0306] Furthermore, treatment for increasing the crystallinity of the oxide semiconductor film 230f may be performed after the oxide semiconductor film 230f is formed. Specifically, this treatment may be performed directly on the formed oxide semiconductor film 230f, or may be performed via another film, such as an insulating film, formed on the oxide semiconductor film 230f. For example, microwave plasma treatment may be performed after the oxide semiconductor film 230f is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, or the like) may be formed after the oxide semiconductor film 230f is formed, and then heat treatment or microwave plasma treatment may be performed on the oxide semiconductor film 230f via the insulating film.

[0307] Note that the above-described treatment for increasing the crystallinity of the oxide semiconductor film 230f can also serve as treatment for removing impurities contained in the oxide semiconductor film 230f. For example, carbon, hydrogen, nitrogen, and the like contained in the oxide semiconductor film 230f can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of the oxide semiconductor film 230f in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor film 230f can be reduced.

[0308] When performing the treatment to increase the crystallinity of the oxide semiconductor film 230f, the temperature of the heat treatment (or the temperature of the substrate) is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher and 700° C. or lower, 100° C. or higher and 600° C. or lower, or 300° C. or higher and 450° C. or lower.

[0309] By increasing the crystallinity of the oxide semiconductor film 230f, a highly reliable transistor can be realized.

[0310] Next, a conductive film 242_1f is formed over the oxide semiconductor film 230f, and a conductive film 242_2f is formed over the conductive film 242_1f (see FIGS. 18A to 18D ). The conductive film 242_1f is a conductive film that becomes the conductor 242a1 and the conductor 242b1, and the conductive film 242_2f is a conductive film that becomes the conductor 242a2 and the conductor 242b2. A conductive material that can be used for the conductor 242a1 and the conductor 242b1 may be used for the conductive film 242_1f, and a conductive material that can be used for the conductor 242a2 and the conductor 242b2 may be used for the conductive film 242_2f. Hereinafter, the conductive films 242_1f and 242_2f may be collectively referred to as conductive films 242f.

[0311] The conductive films 242_1f and 242_2f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, tantalum nitride may be formed as the conductive film 242_1f by a sputtering method. Furthermore, tungsten may be formed as the conductive film 242_2f by a sputtering method. By forming the conductive film 242f to cover the oxide semiconductor film 230f, the contact area between the oxide semiconductor film 230f and the conductors 242a and 242b can be increased without increasing the area occupied by the oxide semiconductor film 230f. This can improve the on-state current and frequency characteristics of the transistor 200.

[0312] Note that an insulating film to be the insulators 271a and 271b may be further formed over the conductive film 242_2f. For example, as the insulating film, a silicon nitride film may be formed by a sputtering method, and a silicon oxide film may be further formed thereover by a sputtering method. By providing such an insulating film, the transistor 200 shown in FIGS. 13A to 13D can be formed.

[0313] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f are processed into island shapes by lithography to form the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 (see FIGS. 19A to 19D ). At this time, the insulator 222 is exposed in a region that does not overlap with the conductor 242_1 and the conductor 242_2.

[0314] For the above processing, a dry etching method or a wet etching method can be used. Processing by dry etching is suitable for fine processing. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. The insulating film 224f, the oxide semiconductor film 230f, the conductive film 242_1f, and the conductive film 242_2f may be processed under different conditions. When the above processing is performed, a hard mask may be provided over the conductive film 242_2f.

[0315] Here, the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 are preferably processed collectively into an island shape. In this case, the side edges of the conductor 242_1 and the conductor 242_2 preferably coincide with or substantially coincide with the side edges of the oxide semiconductor 230. Furthermore, the side edges of the insulator 224 preferably coincide with or substantially coincide with the side edges of the oxide semiconductor 230. Such a structure can reduce the number of steps required to manufacture a semiconductor device according to one embodiment of the present invention. Therefore, a highly productive method for manufacturing a semiconductor device can be provided.

[0316] By processing the insulator 224 into an island shape as described above, the bottom surface of the conductor 260 can be located below the bottom surface of the oxide semiconductor 230 in the transistor 200. This allows a sufficient electric field to be applied from the conductor 260 to the entire oxide semiconductor 230. Therefore, the electrical characteristics of the transistor 200 can be improved.

[0317] The side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a structure, a reduction in area and high density can be achieved when a plurality of transistors are provided.

[0318] However, the present invention is not limited to the above, and the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 may be, for example, greater than or equal to 60° and less than 90°. Tapering the side surfaces in this manner improves coverage with the insulator 275 and the like in subsequent steps, and reduces defects such as voids.

[0319] 3B , a structure without the insulator 224 is also possible. In this case, when the oxide semiconductor 230 is processed into an island shape, part of the top surface of the insulator 222 may be removed. As a result, as shown in FIG. 3B , the top surface of the region of the insulator 222 that overlaps with the oxide semiconductor 230 may become higher than the top surface of the region of the insulator 222 that does not overlap with the oxide semiconductor 230.

[0320] Next, an insulator 275 is formed to cover the insulator 224, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2, and then an insulator 280 is formed over the insulator 275 (see FIGS. 20A to 20D). The insulators described above may be used for the insulators 275 and 280.

[0321] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0322] As the insulator 280, it is preferable to form an insulator with a flat upper surface by forming an insulating film to be the insulator 280 and performing CMP treatment on the insulating film. Note that it is also possible to form a silicon nitride film on the insulator 280 by, for example, a sputtering method and perform CMP treatment on the silicon nitride until it reaches the insulator 280.

[0323] The insulators 275 and 280 can each be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0324] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film by a PEALD method as the insulator 275. Alternatively, it is preferable to form an aluminum oxide film by a sputtering method and then form a silicon nitride film thereon by a PEALD method as the insulator 275. By using the above structure for the insulator 275, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0325] In this manner, the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 can be covered with the insulator 275 having a function of suppressing oxygen diffusion. This can suppress direct diffusion of oxygen from the insulator 280 or the like to the oxide semiconductor 230, the conductor 242_1, and the conductor 242_2 in a later step.

[0326] The insulator 280 is preferably formed using silicon oxide by a sputtering method. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. The hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. Heat treatment may be performed before the deposition of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be deposited successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment can be performed under the above-described heat treatment conditions.

[0327] Next, the conductor 242_2, the insulator 275, and the insulator 280 are processed by lithography to form an opening 201 that reaches the conductor 242_1 and the insulator 222 (see FIGS. 21A to 21D ). Here, the conductor 242_2 is divided to form the conductor 242a2 and the conductor 242b2. The opening 201 is formed so that at least a portion of the opening 201 overlaps with the oxide semiconductor 230. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening 201 is D2, which corresponds to the distance D2 between the conductor 242a2 and the conductor 242b2. That is, the width D2 of the opening 201 is greater than the distance D1 between the conductor 242a1 and the conductor 242b1.

[0328] The lithography method can be any of the above-mentioned methods, as appropriate. In order to finely process the openings in the insulator 280, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0329] The above processing is preferably performed using a dry etching method. Dry etching is capable of anisotropic etching and is therefore suitable for forming openings 201 with a high aspect ratio. Note that the above description can be referred to for the conditions for the dry etching method and the dry etching apparatus.

[0330] 19A to 19D show the steps of forming the insulator 224. However, the insulating film 224f can also be processed to form the insulator 224 in the steps of FIGS. 21A to 21D . In this case, the insulating film 224f is further etched after the insulator 275 is etched. As a result, a region of the insulator 224 that does not overlap with the oxide semiconductor 230 in the opening 201 is removed, and an opening reaching the insulator 222 is formed. With this structure, the transistor 200 having the structure shown in FIGS. 11A to 11D can be formed.

[0331] Next, an insulating film 255A is formed to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIGS. 22A to 22D ). The insulating film 255A is an insulating film that will become the insulator 255 in a later process, and any of the above-described insulators can be used. The insulating film 255A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0332] Since the insulating film 255A is formed along the opening 201, it is preferable that the insulating film 255A has good coverage. Therefore, it is preferable that the insulating film 255A be formed using an ALD method or the like that has good coverage. For example, it is preferable that the insulating film 255A be formed of silicon nitride using the PEALD method.

[0333] Next, the conductor 242_1 and the insulating film 255A are processed by lithography in the opening 201 to form an opening that reaches the oxide semiconductor 230 (see FIGS. 23A to 23D ). Here, an insulator 255 having an opening is formed from the insulating film 255A, and the conductor 242_1 is divided to form the conductor 242a1 and the conductor 242b1. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is D1, which corresponds to the distance D1 between the conductor 242a1 and the conductor 242b1. Because the opening is formed inside the opening formed in the insulator 280, the distance D1 between the conductor 242a1 and the conductor 242b1 is shorter than the distance D2 between the conductor 242a2 and the conductor 242b2.

[0334] The lithography method can be any of the above-described methods, as appropriate. In order to finely process the openings in the insulator 255, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0335] 23A and 23D , the insulator 255 has an opening formed therein so as to expose the island-shaped oxide semiconductor 230; however, the present invention is not limited to this. In this step, it is sufficient that the conductor 242a1 and the conductor 242b1 are separated from each other by a distance D1. Therefore, for example, an opening substantially similar to the opening 201 may be formed in the insulator 255, except for the portions that contact the top surfaces of the conductors 242a1 and 242b1. However, in this case, the insulator 255 may be formed in a sidewall shape in contact with the sidewall of the opening 201.

[0336] The above processing is preferably performed using a dry etching method. Dry etching is capable of anisotropic etching and is therefore suitable for performing fine processing such as opening the insulator 255 in the opening 201. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus.

[0337] Although the above describes an example in which lithography is used to process the insulator 255, the present invention is not limited to this. For example, the insulator 255 may be anisotropically etched without using a mask. This allows the insulator 255 to be formed in a sidewall shape in contact with the sidewall of the opening 201, as shown in FIGS. 13A to 13D .

[0338] 4B , a portion of the oxide semiconductor 230 in contact with the upper portion of the insulator 225 is removed, and a portion of the oxide semiconductor 230 in contact with the side surface of the insulator 225 remains, forming a sidewall-shaped oxide semiconductor 230.

[0339] In this manner, the conductors 242a2 and 242b2, which are spaced apart by a distance D2, and the conductors 242a1 and 242b1, which are spaced apart by a distance D1, can be formed. With this configuration, the distance between the source and drain of the transistor 200 can be shortened, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0340] 14A and 14B can be manufactured in parallel. In this case, when the conductor 242a1 and the conductor 242b1 of the transistor 200 are formed, the capacitor 460 does not need to be subjected to the etching treatment, and the oxide semiconductor 230 may be covered with the conductor 242b1 in the region where the capacitor 460 is to be formed. In this way, the capacitor 460 including the conductor 242b1, the insulator 454, and the conductor 456 can be manufactured in parallel with the transistor 200.

[0341] Note that ashing treatment using oxygen plasma may be performed after processing the conductor 242_1 and after processing the conductor 242_2. By performing such oxygen plasma treatment, impurities generated during the etching treatment and diffused into the oxide semiconductor 230 and the like can be removed. Examples of the impurities include those originating from components contained in a workpiece of the etching treatment and components contained in a gas used in the etching treatment. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. When chlorine gas is used in the etching treatment, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove chlorine attached to the oxide semiconductor 230. Removing the impurities attached to the oxide semiconductor 230 in this manner can improve the electrical characteristics and reliability of the transistor.

[0342] Furthermore, a cleaning treatment may be performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 during the etching process. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves in some cases.

[0343] Wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. Wet cleaning may also be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. Wet cleaning may also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0344] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0345] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or higher, more preferably 900 kHz or higher, because damage to the oxide semiconductor 230 and the like can be reduced by using such a frequency.

[0346] The cleaning process may be repeated multiple times, and different cleaning solutions may be used for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0347] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused into the oxide semiconductor 230 can be removed. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved.

[0348] It is preferable to perform heat treatment after the etching or cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and still more preferably 350° C. to 400° C. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, the heat treatment is preferably performed at 350° C. for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the oxide semiconductor 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230, converting the hydrogen into H ２ As a result, hydrogen remaining in the oxide semiconductor 230 is recombined with the oxygen vacancies to form V Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and reliability can be improved. Furthermore, variation in the electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an oxygen atmosphere and then successively in a nitrogen atmosphere without exposure to the air. Furthermore, the heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0349] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Therefore, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0350] 2B and other figures, even when the oxide semiconductor 230 has a stacked structure and a metal oxide with relatively low conductivity or a metal oxide with a wide band gap is used for the oxide semiconductor 230c, the resistance of the region overlapping with the conductor 242a and the region overlapping with the conductor 242b in the oxide semiconductor 230 can be reduced as described above. This allows source and drain regions to be formed in the oxide semiconductor 230c.

[0351] As described above, the insulator 255, which has an inorganic insulator that is resistant to oxidation, is provided in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. This prevents the conductors 242a2 and 242b2 from being excessively oxidized by the heat treatment, even if the conductors 242a2 and 242b2 are made of a tungsten film that is relatively easily oxidized.

[0352] Note that part of the top surface of the oxide semiconductor 230 in a region between the conductor 242a1 and the conductor 242b1 might be removed by the processing of the conductor 242_1 or a subsequent cleaning treatment, etc. As a result, in the oxide semiconductor 230, the top surface of the region between the conductor 242a1 and the conductor 242b1 might be lower than the top surface of a region overlapping with the conductor 242a1 or the conductor 242b1, as shown in FIG.

[0353] Next, an insulating film 250A to be the insulator 250 is formed along the side surface and bottom surface of the opening 201 formed in the insulator 280 or the like (see FIGS. 24A to 24D ). Here, the insulating film 250A is in contact with the insulator 255, the conductor 242a, the conductor 242b, the insulator 222, and the oxide semiconductor 230.

[0354] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250A is preferably formed using an ALD method. Like the insulator 250 described above, the insulating film 250A is preferably formed to a thin film thickness, and it is necessary to minimize film thickness variation. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizer) are alternately introduced. The film thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. Furthermore, the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, atomic layers can be deposited one by one on the bottom and side surfaces of the opening, allowing the insulating film 250A to be formed with good coverage on the opening.

[0355] When the insulating film 250A is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, HCl, or the like as an oxidizing agent, hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0356] The insulator 250 can have a layered structure as shown in FIG. 2 and the like. For example, as shown in FIG. 2A, the insulator 250 can have a layered structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited as the insulator 250a by a thermal ALD method, silicon oxide can be deposited as the insulator 250b by a PEALD method, hafnium oxide can be deposited as the insulator 250c by a thermal ALD method, and silicon nitride can be deposited as the insulator 250d by a PEALD method.

[0357] Furthermore, after the insulating film 250A or any of the insulators constituting the insulating film 250A is formed, it is preferable to perform microwave plasma treatment in an atmosphere containing oxygen. Here, the microwave plasma treatment may refer to treatment using, for example, an apparatus having a power source that generates high-density plasma using microwaves. In this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0358] In the microwave plasma treatment, it is preferable to use a microwave plasma treatment apparatus having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave plasma treatment apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, 2.45 GHz. The use of high-density plasma allows high-density oxygen radicals to be generated. Furthermore, the power of the power supply that applies microwaves to the microwave plasma treatment apparatus is preferably 1000 W to 10,000 W, more preferably 2000 W to 5,000 W. The microwave plasma treatment apparatus may also have a power supply that applies RF to the substrate side. Furthermore, applying RF to the substrate side allows oxygen ions generated by the high-density plasma to be efficiently introduced into the oxide semiconductor 230.

[0359] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa or higher and 1000 Pa or lower, and more preferably being 300 Pa or higher and 700 Pa or lower. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, about 250°C. After the oxygen plasma treatment, a heat treatment may be carried out without exposure to the outside air. The heat treatment temperature is, for example, preferably 100°C or higher and 750°C or lower, and more preferably 300°C or higher and 500°C or lower.

[0360] Furthermore, for example, the microwave plasma treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２The oxygen flow rate ratio (O + Ar) is greater than 0% and less than or equal to 100%. ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ The oxygen flow rate ratio (O ２ / (O ２ +Ar)) is set to 10% or more and 30% or less. By performing microwave plasma treatment in an atmosphere containing oxygen in this manner, the carrier concentration in the oxide semiconductor 230 can be reduced. Furthermore, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave plasma treatment, an excessive reduction in the carrier concentration in the oxide semiconductor 230 can be prevented.

[0361] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to a region between the conductor 242 a and the conductor 242 b of the oxide semiconductor 230. The action of the plasma, microwaves, or the like can reduce the V in the region. Ｏ The H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. Here, when using the structure shown in FIG. 2A or the like, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With such a structure, hydrogen generated by microwave plasma treatment can be captured or fixed in the insulating film 250A. In this way, V included in the channel formation region can be removed. Ｏ As a result, oxygen vacancies in the channel formation region and V Ｏ By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0362] The oxygen implanted into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions with an unpaired electron, also called O radicals). The oxygen implanted into the channel formation region may take one or more of the above forms, and oxygen radicals are particularly preferred. Furthermore, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0363] Furthermore, the microwave plasma treatment can also remove impurities such as carbon in the oxide semiconductor 230. Removal of carbon, which is an impurity in the oxide semiconductor 230, can improve the crystallinity of the oxide semiconductor 230. In particular, when the oxide semiconductor 230 is formed by an ALD method, carbon contained in a precursor may be taken into the oxide semiconductor 230, so it is preferable to remove carbon by microwave plasma treatment.

[0364] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. The region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when microwave plasma treatment is performed in an oxygen-containing atmosphere. Therefore, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz to 300 GHz, for example, 2.4 GHz to 2.5 GHz.

[0365] The conductors 242a and 242b shield the oxide semiconductor 230 from microwaves, high-frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not reach a region of the oxide semiconductor 230 that overlaps with either the conductor 242a or the conductor 242b. As a result, the microwave plasma treatment can reduce V Ｏ Since the amount of H is reduced and an excessive amount of oxygen is not supplied, a decrease in the carrier concentration can be prevented.

[0366] Here, an insulator 255 having a barrier property against oxygen is provided in contact with the side surfaces of the conductor 242a2 and the conductor 242b2, thereby making it possible to prevent an oxide film from being formed on the side surfaces of the conductor 242a2 and the conductor 242b2 by microwave plasma processing.

[0367] In this manner, oxygen vacancies and V Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions that function as source or drain regions can be suppressed, and the conductivity (low-resistance region state) before the microwave plasma treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0368] Furthermore, by performing microwave plasma treatment to modify the film quality of the insulator 250, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, in a post-process such as deposition of a conductive film to be the conductor 260 or post-treatment such as heat treatment, diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230 and the like can be suppressed. In this way, improving the film quality of the insulator 250 can improve the reliability of the transistor.

[0369] When the insulator 250 has a stacked structure of insulators 250a to 250d, microwave plasma treatment is preferably performed after the formation of the insulator 250b. Furthermore, microwave plasma treatment may be performed again after the formation of the insulator 250c. In this manner, microwave plasma treatment in an oxygen-containing atmosphere may be performed multiple times (at least twice or more). The microwave plasma treatment may also serve as the heat treatment of the oxide semiconductor film 230f. Therefore, the microwave plasma treatment may cause the growth of a crystalline region in the oxide semiconductor 230.

[0370] After the microwave plasma treatment, heat treatment may be performed while the reduced pressure state is maintained. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment while the reduced pressure state is maintained after the microwave plasma treatment may be repeated multiple times. By repeatedly performing the heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. Furthermore, the heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the heat treatment may cause growth of a crystalline region in the oxide semiconductor 230.

[0371] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially deposited (see FIGS. 25A to 25D ). The conductive films 260A and 260B are deposited so as to fill the openings 201 formed in the insulator 280 or the like. The conductive films 260A and 260B can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, titanium nitride is deposited as the conductive film 260A by a CVD method, and tungsten is deposited as the conductive film 260B by a CVD method. Note that the deposition of the conductive films 260A and 260B may be performed while heating the substrate. Heating the substrate can also serve as the heat treatment for the oxide semiconductor film 230f described above. Therefore, the heating of the substrate may cause the growth of a crystalline region of the oxide semiconductor 230 .

[0372] Next, the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portions of the insulator 255, the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the opening 201 are removed. As a result, the insulator 255, the insulator 250, and the conductor 260 (the conductor 260a and the conductor 260b) are formed in the opening 201 (see FIGS. 26A to 26D).

[0373] As a result, the insulator 255 is provided in contact with the insulator 280, the insulator 275, and the insulator 222 in the opening 201. The insulator 250 is provided in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the oxide semiconductor 230, the insulator 224, and the insulator 222 in the opening 201. The conductor 260 is provided to fill the opening 201 with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0374] Next, the insulator 282 is formed over the insulator 255, the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 1A to 1D ). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. Alternatively, the insulator 282 may be formed by forming a first layer by an ALD method and then forming a second layer thereon by a sputtering method.

[0375] Furthermore, by depositing the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. At this time, the insulator 282 is preferably deposited while heating the substrate. Depositing the insulator 282 in this manner allows a suitable amount of oxygen to be supplied from the insulator 280 to the oxide semiconductor 230 through the insulator 250. Furthermore, providing the insulator 250a in the insulator 250 can prevent excessive oxygen from being supplied into the insulator 250 and causing excessive oxidation of the conductors 242a and 242b near the insulator 250.

[0376] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen implanted into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less oxygen is implanted into the insulator 280, and the more likely the oxygen amount is to saturate even if the insulator 282 is thin. Furthermore, the greater the bias power, the more oxygen is implanted into the insulator 280. By reducing the RF power, the amount of oxygen implanted into the insulator 280 can be suppressed. Note that when applying a substrate bias using an RF power supply, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0377] Furthermore, by forming a second layer by sputtering on top of the first layer formed by ALD, the upper end of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collisions caused by sputtering film formation.

[0378] Alternatively, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0379] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 1A to 1D). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulator 283 can be reduced by using a sputtering method, which does not require the use of molecules containing hydrogen in the deposition gas. In this embodiment, silicon nitride is formed as the insulator 283 by a sputtering method.

[0380] Here, it is preferable to successively deposit the insulators 282 and 283 without exposing them to the air environment. Depositing the insulators 282 and 283 without exposing them to the air environment can prevent impurities or moisture from the air environment from adhering to the insulators 282 and 283, and can keep the interface or the vicinity of the interface between the insulators 282 and 283 clean.

[0381] In this embodiment, a silicon nitride film is formed as the insulator 283, and an aluminum oxide film is formed as the insulator 282. By using silicon nitride, which has a function of suppressing hydrogen diffusion, for the insulator 283, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide, which has a function of capturing or fixing hydrogen, for the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0382] Next, openings reaching the conductor 242a and the conductor 242b are formed in the insulators 275, 280, 282, and 283 (see FIGS. 1A to 1D ). The openings may be formed by lithography. The openings are preferably formed by processing the workpiece using dry etching. Dry etching is suitable for forming openings with a high aspect ratio because it allows anisotropic etching. When performing anisotropic etching, reactive ion etching, for example, is preferably performed. The conditions for the dry etching method and the dry etching apparatus can be described above. While the shape of the openings in FIG. 1A is rectangular in plan view, the shape is not limited thereto. For example, the openings may be circular, approximately circular such as elliptical, polygonal such as rectangular, or polygonal such as rectangular with rounded corners in plan view.

[0383] Next, after the openings are formed, heat treatment may be performed. The temperature for the heat treatment may be 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, the heat treatment is preferably performed in an atmosphere containing neither an oxidizing gas nor oxygen gas because the conductors 242a and 242b are exposed. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. This can reduce oxygen vacancies in the channel formation region of the oxide semiconductor 230. The heat treatment can also serve as the heat treatment for the oxide semiconductor film 230f. Therefore, the heat treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0384] Here, because the side surface of the insulator 280 is exposed through the opening, the heat treatment can outwardly diffuse oxygen contained in the insulator 280, thereby controlling the amount of oxygen contained in the insulator 280. Meanwhile, because the insulators 282 and 283, which have a barrier property against oxygen, are provided on the insulator 280, oxygen does not outwardly diffuse from the upper surface of the insulator 280. This can prevent excessive outward diffusion of oxygen from the insulator 280 and the formation of oxygen vacancies in the insulator 280. Furthermore, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. This can prevent excessive oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the heat treatment.

[0385] In this manner, the amount of oxygen in the insulator 280 can be more suitably adjusted, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. This reduces oxygen vacancies in the oxide semiconductor 230 and prevents excessive oxygen from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the step of exposing the side surfaces of the insulator 280 can also serve as the step of forming openings into which the conductors 240a and 240b are to be embedded, which simplifies the manufacturing process of the semiconductor device.

[0386] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a, and the insulator 241b in the opening that reaches the conductor 242b (see FIGS. 1A to 1D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film using a PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0387] Furthermore, dry etching, for example, may be used to anisotropically etch the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductors 240a and 240b. Note that this anisotropic etching may form recesses in parts of the upper surfaces of the conductors 242a and 242b.

[0388] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b is preferably a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240a and the conductor 240b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0389] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the upper surface of the insulator 283. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 1A to 1D). Note that the CMP processing may remove portions of the upper surface of the insulator 283.

[0390] As described above, by providing the conductor 240a in contact with the conductor 242a, the conductor 240a functioning as one of the source and drain of the transistor 200 can be electrically connected to a wiring. Furthermore, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b functioning as the other of the source and drain of the transistor 200 can be electrically connected to a wiring.

[0391] Note that a conductive film functioning as a wiring or a conductive film functioning as a plug can be formed over the conductor 240a and the conductor 240b.

[0392] In this manner, the semiconductor device shown in FIG. 1 can be manufactured.

[0393] The semiconductor device according to this embodiment includes an OS transistor. In this embodiment, by using indium oxide (e.g., indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide) for the oxide semiconductor layer of the OS transistor, a semiconductor device with high field-effect mobility can be provided. For example, the electrical characteristics, on-state current, S value, frequency characteristics, and the like of the transistor can be improved. Furthermore, a highly reliable semiconductor device can be provided.

[0394] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0395] Embodiment 2 In this embodiment, an oxide semiconductor that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor with a stacked structure, it may be difficult to form a boundary between stacked films, as described later.

[0396] [Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0397] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, IAZO). Examples of usable metal oxides include indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide) can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0398] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0399] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0400] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0401] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0402] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0403] A structural example of an oxide semiconductor that can increase the field-effect mobility of a transistor will be described. For example, it is preferable to use a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the oxide semiconductor has indium oxide and IGZO on the indium oxide. In addition, it is preferable to use IGZO containing nitrogen as the oxide semiconductor. For example, it is preferable to use IGZO containing nitrogen during or after film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. As the oxide semiconductor, at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO is preferably used.

[0404] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0405] The oxide semiconductor of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for an oxide semiconductor, the density of defect states in the oxide semiconductor can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0406] Note that the crystallinity of the metal oxide contained in the oxide semiconductor is not particularly limited. For example, the oxide semiconductor may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor has crystallinity, deterioration of transistor characteristics may be suppressed.

[0407] The crystallinity of an oxide semiconductor can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these techniques may be used for analysis.

[0408] The oxide semiconductor of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor having a CAAC structure can also be said to have a structure having layered crystal parts.

[0409] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor on which the oxide semiconductor is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor is to be formed.

[0410] When an oxide semiconductor has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor is formed.

[0411] When electron diffraction is performed on an oxide semiconductor having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0412] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0413] A cross-sectional TEM image of an oxide semiconductor having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region in the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots that are high in brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0414] When an oxide semiconductor having a CAAC structure is viewed from a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor has crystallinity.

[0415] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content as an oxide semiconductor, the on-state current of a transistor can be increased and the frequency characteristics can be improved. For example, indium oxide is preferably used as the oxide semiconductor.

[0416] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, it becomes a metal oxide with high crystallinity, for example, a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used as the oxide semiconductor. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn = 2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn = 4:1 [atomic ratio] or a composition close thereto can be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0417] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Thus, the reliability of a transistor including an oxide semiconductor can be improved.

[0418] For example, the oxide semiconductor may be an In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof may be used. Alternatively, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof may be used.

[0419] The oxide semiconductor can be an In—Zn oxide containing an element M. Specifically, metal oxides having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn=1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn=1:1:0.5 (atomic ratio) or a composition thereabout, In:M:Zn=1:1:2 (atomic ratio) or a composition thereabout, In:M:Zn=4:2:3 (atomic ratio) or a composition thereabout, In:M:Zn=1:3:2 (atomic ratio) or a composition thereabout, or In:M:Zn=1:3:4 (atomic ratio) or a composition thereabout can be used.

[0420] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0421] Furthermore, when forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not match.

[0422] The composition of a metal oxide used in an oxide semiconductor can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0423] The oxide semiconductor of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor has a two-layer structure including a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor has a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0424] The first to third layers may each be made of the metal oxides described above.

[0425] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Increasing the In content in the second layer can increase the on-state current and improve the frequency characteristics.

[0426] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0427] By sandwiching the second layer between the first layer and the third layer, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0428] For example, a band diagram of the oxide semiconductor 230 including the oxide semiconductors 230a to 230c shown in FIG. 2B and its vicinity is shown in FIG. 27. In FIG. 27, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 27 also shows the valence band maximum (VBM) and the conduction band minimum (CBM) of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250 when no voltage is applied between the gate and the source. The vacuum level Vac is indicated by a dashed line in FIG. 27.

[0429] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250. Therefore, the relationship in level between the upper ends of the valence bands and the relationship in level between the lower ends of the conduction bands will be mainly described with reference to the band diagram in FIG. 27 .

[0430] Depending on the constituent elements and compositions of the oxide semiconductors 230a, 230b, and 230c, the oxide semiconductor 230b may be sandwiched between the oxide semiconductors 230a and 230c, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor 230b, as shown in FIG. 27 . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 27 ) flows in the oxide semiconductor 230b. This can increase the on-state current, improve reliability, and the like.

[0431] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0432] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen can be prevented from diffusing from below the first layer or from above the third layer to the second layer. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen and water contained in the oxide semiconductor due to heat or the like applied after the formation of the oxide semiconductor.

[0433] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0434] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0435] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0436] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0437] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described compositions stacked together. For example, the first layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0438] [Method for Manufacturing Oxide Semiconductor] The oxide semiconductor of one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0439] The oxide semiconductor of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0440] The oxide semiconductor of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor has a two-layer structure, the oxide semiconductor can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0441] The first film formation method is preferably a film formation method that causes less damage to the surface on which the oxide semiconductor is formed than the second film formation method. This can prevent the formation of a mixed layer at the interface between the oxide semiconductor and the layer on which the oxide semiconductor is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which may lead to higher crystallinity of the oxide semiconductor.

[0442] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0443] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0444] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0445] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed using the second film formation method on a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when a heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0446] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor. Furthermore, it is possible to prevent alloying with the layer on which the metal oxide is to be formed. Therefore, it is possible to improve the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the oxide semiconductor.

[0447] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0448] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with superior coverage compared to the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the oxide semiconductor can be improved. Therefore, the oxide semiconductor can be well coated on steps, openings, etc. with a high aspect ratio.

[0449] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer having high crystallinity on the first layer having low crystallinity, or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor, including the vicinity of the interface with the surface on which the oxide semiconductor is formed.

[0450] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to be crystalline. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor.

[0451] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0452] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0453] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0454] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0455] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor on a layer that is a surface to be formed by an ALD method.

[0456] When an oxide semiconductor is formed using the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using HCl, etc. as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor can be reduced.

[0457] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0458] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0459] The second layer is preferably formed by sputtering.

[0460] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0461] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0462] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0463] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0464] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer to be formed and the metal oxide can be reduced to an extent that it cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0465] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0466] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0467] In the oxide semiconductor of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0468] For example, when SIMS analysis is performed on an oxide semiconductor formed on a silicon oxide film, which is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0469] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0470] By reducing the thickness of the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor.

[0471] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0472] The oxide semiconductor of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0473] When the oxide semiconductor has a three-layer structure, the oxide semiconductor can be manufactured by forming a first layer on a surface to be formed by a first film formation method, then forming a second layer by a second film formation method, and finally forming a third layer by the first film formation method.

[0474] Even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, the oxide semiconductor can have a structure in which the entire oxide semiconductor including the first layer and the third layer has the CAAC structure by crystal growth using the second layer as a nucleus. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0475] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0476] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0477] Because the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor can have both high crystallinity and high coverage throughout the entire layer.

[0478] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0479] When an oxide semiconductor is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0480] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0481] As described above, in the method for forming an oxide semiconductor according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers in this case) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown in a solid phase using the second layer as a nucleus or seed to form an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a deposition method, i.e., a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0482] In an oxide semiconductor, a region having a CAAC structure is preferably present widely throughout the entire layer. A region having a CAAC structure in a first layer is crystallinely connected to a region having a CAAC structure in a second layer. A region having a CAAC structure in a third layer is crystallinely connected to a region having a CAAC structure in a second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. An oxide semiconductor may be expressed as a single layer with no clearly observable interface. An oxide semiconductor may be expressed as a single layer.

[0483] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or approximately parallel to the surface on which the oxide semiconductor is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or approximately parallel to the normal direction of the surface on which the oxide semiconductor is formed.

[0484] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0485] When the oxide semiconductor has a three-layer structure, the oxide semiconductor can also be manufactured by forming a first layer on a surface to be formed by a first film formation method, then forming a second layer by the first film formation method, and then forming a third layer by the second film formation method.

[0486] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content in the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0487] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, in cross-sectional observation of the oxide semiconductor using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the second layer.

[0488] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0489] In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0490] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) that are introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0491] One or more of the first to third layers may have a stack of layers with different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide with a high Ga content by the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer by the first film formation method.

[0492] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0493] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0494] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor.

[0495] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0496] When performing microwave plasma treatment, the substrate may be heated to a temperature of at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and preferably at most 500°C or at most 450°C.

[0497] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0498] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the impurity hydrogen can be removed from the oxide semiconductor. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor, the oxygen vacancies in the oxide semiconductor can be further reduced.

[0499] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0500] On the other hand, a reaction occurs between part of the oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor, in other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0501] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0502] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0503] The crystallinity of the layer formed by the first film formation method can be increased, which can further increase the crystallinity of a layer formed thereover, thereby increasing the crystallinity of the entire oxide semiconductor.

[0504] Oxygen supplied to an oxide semiconductor can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into an oxide semiconductor is preferably in one or more of the above forms, and is particularly preferably in the form of an oxygen radical.

[0505] After the oxide semiconductor is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0506] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer (in other words, the crystalline molecules formed using the ALD method) formed using the first film formation method.

[0507] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0508] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after the ALD film formation, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0509] Furthermore, it is preferable that at least a portion of the first layer or the second layer formed using the first film formation method is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method serves as a nucleus or seed. It is preferable that the region in the first layer or the second layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0510] Furthermore, because the CAAC is formed from the top to the bottom of the first or second layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be increased. Therefore, the method for manufacturing an oxide semiconductor according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0511] As described above, by performing microwave plasma treatment and / or heat treatment, the crystallinity of the entire oxide semiconductor can be increased. Furthermore, impurities in the oxide semiconductor can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor is reduced, the crystallinity can be further improved.

[0512] By increasing the crystallinity of an oxide semiconductor, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor using the oxide semiconductor can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0513] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor, or may be performed after an insulating film or the like is formed over the oxide semiconductor.

[0514] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, a treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the oxide semiconductor by heat or the like applied after the treatment.

[0515] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, and the like. Alternatively, oxygen may be supplied to the first layer or the second layer formed by the first film formation method by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition, or may be left as it is. When the deposited oxide film is left as it is, the oxide film can be used as a layer (second layer or third layer) provided on the first layer or second layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0516] The oxide semiconductor of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0517] Furthermore, an oxide semiconductor having a CAAC structure formed using the above-described two types of film formation methods may have higher film relative permittivity, film density, and film hardness, as compared with an oxide semiconductor having a CAAC structure formed using one type of film formation method.

[0518] By using an oxide semiconductor having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0519] The oxide semiconductor of one embodiment of the present invention can be manufactured by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor of one embodiment of the present invention can be manufactured without using the second film formation method. For example, after forming a first layer by the first film formation method, one or both of microwave plasma treatment and heat treatment can be performed to increase the crystallinity of the first layer. Therefore, the crystallinity of a second layer formed on the first layer by the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, the crystallinity of the oxide semiconductor can be increased by performing one or both of microwave plasma treatment and heat treatment after forming the second layer. Therefore, a CAAC structure can be formed in the oxide semiconductor.

[0520] As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed by the first film formation method can be used as a nucleus or seed to cause solid-phase growth of the oxide semiconductor thereover, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can also be referred to as an AG CAAC.

[0521] When the oxide semiconductor has a stacked structure of two or more layers, it can also be manufactured by forming a metal oxide using one type of film formation method. When the oxide semiconductor has a two-layer structure of a first layer and a second layer on the first layer, the oxide semiconductor can be manufactured by, for example, forming the first layer and the second layer in this order by a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. Furthermore, when the oxide semiconductor has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can also be formed by a sputtering method. Furthermore, part of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer may be formed by ALD.

[0522] [Oxide Semiconductor of Transistor] The oxide semiconductor of this embodiment can be used as a semiconductor layer of a transistor.

[0523] The oxide semiconductor of this embodiment can be used for the oxide semiconductor 230 included in each transistor described in Embodiment 1. For example, the first layer can be used for the oxide semiconductor 230a, the second layer can be used for the oxide semiconductor 230b, and the third layer can be used for the oxide semiconductor 230c. The layer that is a surface to be formed corresponds to the insulator 224 described in Embodiment 1.

[0524] The oxide semiconductor of this embodiment preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or substantially parallel to a surface on which the metal atoms are formed in a crystal portion.

[0525] It is estimated that an oxide semiconductor having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0526] In the semiconductor device described in the above embodiment, metal atoms are arranged in a layered manner in the oxide semiconductor 230 in a direction parallel or substantially parallel to the surface on which the oxide semiconductor 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or substantially parallel to the surface on which the oxide semiconductor 230 is formed. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0527] When the oxide semiconductor of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferabl...

Claims

It has an oxide semiconductor, first to fourth insulators, and first to third conductors. The second insulator is disposed on the first insulator. The oxide semiconductor is disposed on the first insulator and covers the second insulator. The first conductor and the second conductor are disposed on the oxide semiconductor. The third insulator is disposed on the first conductor and the second conductor and has a first opening that overlaps with the region between the first conductor and the second conductor. The fourth insulator overlaps with the oxide semiconductor and is disposed within the first opening. The third conductor is disposed on the fourth insulator within the first opening. The side surface of the first insulator coincides with or substantially coincides with the side surfaces of the oxide semiconductor, the first conductor, and the second conductor in plan view. The film thickness of the first insulator is thicker than the film thickness of the fourth insulator. In a cross-sectional view in the channel width direction, the height of the second insulator is greater than the width of the second insulator. The oxide semiconductor has a first layer, a second layer on the first layer, and a third layer on the second layer in a region overlapping with the third conductor. The first layer has gallium and oxygen. The second layer has indium oxide. The third layer has indium, gallium, and oxygen. The indium content in the second layer is higher than the indium content in the third layer. Semiconductor device. 　 In claim 1, The lower end of the conduction band of the first layer is located on the vacuum level side relative to the lower end of the conduction band of the second layer. A semiconductor device in which the lower end of the conduction band of the third layer is located on the vacuum level side relative to the lower end of the conduction band of the second layer. 　 In claim 1, The first layer has indium. A semiconductor device in which the indium content in the first layer is lower than the gallium content. 　 In claim 1, Some side surfaces of the third insulator coincide with or substantially coincide with the side surfaces of the first conductor and the second conductor in plan view. Semiconductor device. 　 In claim 1, The lower surface of the third conductor has a portion located below the lower surface of the oxide semiconductor. Semiconductor device. 　 In claim 1, It has a fifth insulator. The first conductor and the second conductor each have a first conductive layer and a second conductive layer on the first conductive layer. The fifth insulator is disposed within the first opening and is in contact with the upper surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the upper surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. The fifth insulator has a second opening that overlaps with a region between the first conductive layer of the first conductor and the first conductive layer of the second conductor. The shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor. Semiconductor device. 　 In claim 6, A side surface of a part of the third insulator coincides with or substantially coincides with the side surfaces of the second conductive layer of the first conductor and the second conductive layer of the second conductor in a plan view. Semiconductor device. In claim 6, The fifth insulator contains silicon nitride. Semiconductor device. 　 In claim 6, The first conductive layer of the first conductor and the first conductive layer of the second conductor contain tantalum nitride. Semiconductor device.

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