Light detection device and electronic apparatus

Abstract

The present disclosure relates to a light detection device and an electronic apparatus with which it is possible to miniaturize pixels. This light detection device comprises a vertical transistor which includes: a gate electrode having a trench electrode formed by boring a semiconductor substrate to at least a section thereof in the depth direction; and a first source / drain region and a second source / drain region, one of which is a source and the other of which is a drain. The first source / drain region is formed in the vicinity of an interface of a first surface of the semiconductor substrate, and the second source / drain region is formed in the vicinity of a second surface of the semiconductor substrate, opposite to the first surface, below the gate electrode. The technology of the present disclosure can be applied, for example, to a light detection device that generates and outputs an imaging signal corresponding to the amount of incident light.

Description

Photodetector and electronic equipment

[0001] The present disclosure relates to a photodetector and an electronic device, and more particularly to a photodetector and an electronic device that enable miniaturization of pixels.

[0002] Regarding transistors provided in pixel circuits of solid-state imaging devices, for example, Patent Document 1 proposes a transistor in which two high-concentration n-type regions connected to a source electrode or a drain electrode are stacked vertically, sandwiching a low-concentration n-type region in which a channel is formed.

[0003] International Publication No. 2020 / 075583

[0004] In photodetection devices such as CMOS image sensors, there is a demand for further miniaturization of pixel size.

[0005] The present disclosure has been made in view of such circumstances, and makes it possible to miniaturize pixels.

[0006] A photodetector according to a first aspect of the present disclosure comprises a vertical transistor having a gate electrode having a trench electrode portion dug into at least a portion of a semiconductor substrate in a depth direction, and a first source-drain region and a second source-drain region, one of which serves as a source and the other as a drain, wherein the first source-drain region is formed near the interface of a first surface of the semiconductor substrate, and the second source-drain region is formed below the gate electrode and near the interface of a second surface of the semiconductor substrate opposite the first surface.

[0007] An electronic device according to a second aspect of the present disclosure includes a vertical transistor having a gate electrode having a trench electrode portion dug into at least a portion of a semiconductor substrate in a depth direction, and a first source / drain region and a second source / drain region, one of which serves as a source and the other as a drain, wherein the first source / drain region is formed near the interface of a first surface of the semiconductor substrate, and the second source / drain region is formed below the gate electrode and near the interface of a second surface of the semiconductor substrate opposite the first surface.

[0008] In the first and second aspects of the present disclosure, a vertical transistor is provided having a gate electrode having a trench electrode portion dug into at least a portion of the depth direction of a semiconductor substrate, and a first source / drain region and a second source / drain region, one of which serves as a source and the other as a drain, wherein the first source / drain region is formed near the interface of a first surface of the semiconductor substrate, and the second source / drain region is formed below the gate electrode and near the interface of a second surface of the semiconductor substrate opposite the first surface.

[0009] The photodetector and electronics may be stand-alone devices or may be modules that are incorporated into other devices.

[0010] 1 is a diagram showing a schematic configuration of a photodetection device to which the technology of the present disclosure is applied; FIG. 2 is a diagram showing an example of the circuit configuration of a sensor pixel and a readout circuit; FIG. 3 is a diagram showing an example in which a readout circuit is shared; FIG. 4 is a diagram showing an example of the configuration of a pixel transistor; FIG. 5 is a diagram showing a first modified example of a pixel transistor; FIG. 6 is a diagram showing a second modified example of a pixel transistor; FIG. 7 is a diagram showing a third modified example of a pixel transistor; FIG. 8 is a diagram showing a fourth modified example of a pixel transistor; FIG. 9 is a cross-sectional view showing a first configuration example of a readout circuit; FIG. 10 is a plan view showing a second configuration example of a readout circuit; FIG. 11 is a cross-sectional view showing a second configuration example of a readout circuit; FIG. 12 is a cross-sectional view showing a third configuration example of a readout circuit; FIG. 13 is a plan view showing a third configuration example of a readout circuit; FIG. 14 is a diagram showing a circuit configuration example of the third configuration example of a readout circuit; FIG. 15 is a cross-sectional view showing a fourth configuration example of a readout circuit; FIG. 16 is a plan view showing a fifth configuration example of a readout circuit; FIG. 17 is a cross-sectional view showing a sixth configuration example of a readout circuit; FIG. 18 is a plan view showing a sixth configuration example of a readout circuit; FIG. 19 is a diagram explaining a first method of manufacturing a pixel transistor; FIG. 19 is a diagram explaining a first method of manufacturing a pixel transistor; FIG. 19 is a diagram explaining a first method of manufacturing a pixel transistor. FIG. 1 is a diagram illustrating a second manufacturing method of a pixel transistor. FIG. 2 is a diagram illustrating a second manufacturing method of a pixel transistor. FIG. 3 is a block diagram illustrating an example configuration of an electronic device to which the technology of the present disclosure is applied. FIG. 4 is a diagram illustrating an example use of an image sensor. FIG. 5 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. FIG. 6 is a block diagram illustrating an example of the functional configuration of a camera head and a CCU. FIG. 7 is a block diagram illustrating an example of a schematic configuration of a vehicle control system. FIG. 8 is an explanatory diagram illustrating an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0011] Modes for carrying out the technology of the present disclosure (hereinafter referred to as embodiments) will be described below with reference to the accompanying drawings. The description will be given in the following order: 1. Schematic configuration example of a photodetector 2. Example pixel circuit 3. Configuration example of a pixel transistor 4. First modified pixel transistor 5. Second modified pixel transistor 6. Third modified pixel transistor 7. Fourth modified pixel transistor 8. First configuration example of a readout circuit 9. Second configuration example of a readout circuit 10. Third configuration example of a readout circuit 11. Fourth configuration example of a readout circuit 12. Fifth configuration example of a readout circuit 13. Sixth configuration example of a readout circuit 14. Method for manufacturing a pixel transistor 15. Configuration example of an electronic device 16. Example of use of an image sensor 17. Example of application to an endoscopic surgery system 18. Example of application to a moving body

[0012] In this specification and drawings, identical or similar parts are denoted by identical or similar reference numerals, and redundant explanations are omitted as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, there may be parts in which the dimensional relationships and ratios differ between the drawings.

[0013] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read, and if it is rotated 180 degrees and observed, up and down are read inverted.

[0014] In the drawings described below, regarding the p-type impurity concentration, "p+" indicates a higher impurity concentration than "p", and regarding the n-type impurity concentration, "n-" indicates a lower impurity concentration than "n".

[0015] The technology disclosed herein can be applied to photodetection devices in general that have a pixel array in which pixels are arranged two-dimensionally in a matrix, and that photoelectrically convert incident light to output a pixel signal corresponding to the amount of light. The light to be detected may be light in the visible light range including wavelengths such as R (Red), G (Green), and B (Blue), or light in the non-visible light range such as infrared light. Alternatively, light in both the visible and non-visible light ranges may be used. The photodetection device can be used as a solid-state imaging device that generates and outputs an image signal corresponding to the amount of incident visible light, or as a light receiving device (ranging sensor) in a ranging system that receives infrared light irradiated as active light and measures the distance to a subject using a direct ToF or indirect ToF method.

[0016] 1. Schematic Configuration Example of Photodetector FIG. 1 is a diagram showing a schematic configuration of a photodetector to which the technology of the present disclosure is applied.

[0017] 1 has a three-layer laminated structure in which three substrates, a first substrate 11, a second substrate 12, and a third substrate 13, are bonded together. The first substrate 11, the second substrate 12, and the third substrate 13 are laminated in this order.

[0018] The first substrate 11 has a semiconductor substrate 41 made of, for example, silicon (Si), and a pixel region 52 in which a plurality of sensor pixels 51 are two-dimensionally arranged in a matrix is ​​formed on the semiconductor substrate 41. The sensor pixel 51 includes, for example, a photodiode PD and a transfer transistor TG.

[0019] The second substrate 12 has a semiconductor substrate 42 made of, for example, silicon (Si), and a readout circuit 61 is formed on the semiconductor substrate 42, which outputs pixel signals based on charges generated in the sensor pixels 51. The readout circuit 61 may be provided corresponding to one sensor pixel 51 formed on the first substrate 11, or may be provided corresponding to multiple sensor pixels 51. The second substrate 12 also has multiple pixel drive wirings 62 extending in the row direction and multiple vertical signal lines 63 extending in the column direction formed thereon.

[0020] The third substrate 13 has a semiconductor substrate 43 made of, for example, silicon (Si), and a logic circuit 71 that processes pixel signals is formed on the semiconductor substrate 43. The logic circuit 71 includes, for example, a vertical drive circuit 81, a column processing circuit 82, a horizontal drive circuit 83, a system control circuit 84, and the like.

[0021] The vertical drive circuit 81 is configured by, for example, a shift register, selects a predetermined pixel drive wiring 62, supplies a pulse for driving the readout circuit 61 to the selected pixel drive wiring 62, and drives the readout circuit 61 row by row. That is, the vertical drive circuit 81 selects and scans signals based on signal charges generated in accordance with the amount of light received by the sensor pixels 51 in the pixel region 52 in the vertical direction row by row, and supplies the signals to the column processing circuit 82 through the vertical signal line 63.

[0022] The column processing circuit 82 has a column signal processing circuit for each vertical signal line 63, and performs predetermined signal processing on signals output from the readout circuit 61 on a row-by-row basis via the vertical signal line 63. For example, the column processing circuit 82 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion for removing fixed pattern noise specific to pixels.

[0023] The horizontal drive circuit 83 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, selects each of the column signal processing circuits in the column processing circuit 82 in turn, and causes each of the column signal processing circuits to output a pixel signal from an output terminal 85.

[0024] The system control circuit 84 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the system control circuit 84 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 81, column processing circuit 82, horizontal drive circuit 83, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The system control circuit 84 then outputs the generated clock signals and control signals to the vertical drive circuit 81, column processing circuit 82, horizontal drive circuit 83, etc.

[0025] The photodetector 1 configured as described above has a structure known as a column AD system, in which column signal processing circuits that perform CDS processing and AD conversion processing are arranged in each column. The photodetector 1 outputs to the outside a signal generated in the sensor pixels 51 of the pixel region 52 according to the amount of received light. The photodetector 1 can be used, for example, as a solid-state imaging device that detects the distribution of incident light intensity of infrared light or visible light and captures an image, or as a light receiving device in a distance measurement system that receives light (reflected light) that is irradiated as active light from an object and reflects it, using a direct ToF system or an indirect ToF system to measure the distance to the object.

[0026] 2. Example of Pixel Circuit FIG. 2 shows an example of the circuit configuration of the sensor pixel 51 and the readout circuit 61. As shown in FIG.

[0027] The sensor pixel 51 includes, for example, at least a photodiode PD serving as a photoelectric conversion unit and a transfer transistor TG electrically connected to the photodiode PD. The readout circuit 61 includes a floating diffusion FD, a reset transistor RST, a switching transistor FDG, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL are each configured, for example, by an n-type MOS transistor (MOS FET). The sensor pixel 51 is formed on the first substrate 11, and the readout circuit 61 is formed on the second substrate 12.

[0028] The photodiode PD photoelectrically converts incident light and generates an electric charge (signal charge) according to the amount of incident light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TG, and the anode is electrically connected to a reference potential line (e.g., ground).

[0029] The transfer transistor TG controls the transfer of charges generated in the photodiode PD. When the transfer transistor TG is turned on, it transfers the charges generated in the photodiode PD to the floating diffusion FD. The drain of the transfer transistor TG is electrically connected to the floating diffusion FD, and the gate is electrically connected to a pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 62 described in FIG. 1.

[0030] The floating diffusion FD is a charge storage unit that temporarily stores the charge transferred from the photodiode PD, and a charge-voltage converter that generates a voltage according to the amount of charge. The floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the reset transistor RST.

[0031] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to its gate, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. This pixel drive wiring is part of the pixel drive wiring 62 described in FIG. 1. When the potential of the floating diffusion FD is reset, the switching transistor FDG is also controlled to the on state at the same time.

[0032] The switching transistor FDG is used to change the gain of the charge-to-voltage conversion in the floating diffusion FD. The drain of the switching transistor FDG is connected to the source of the reset transistor RST and the floating diffusion FD, and the source of the switching transistor FDG is connected to the additional capacitance SubFD. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, if the capacitance of the floating diffusion FD (FD capacitance C) is large during charge-to-voltage conversion, the V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, the pixel signal is large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, to prevent V from becoming too large (in other words, to reduce it) when converted to voltage by the amplifier transistor AMP, the FD capacitance C must be large. Based on these factors, when the switching transistor FDG is turned on, the additional capacitance SubFD corresponding to the switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the switching transistor FDG on and off, the FD capacitance C can be made variable, and the conversion efficiency can be switched. The pixel drive wiring supplied to the gate of the switching transistor FDG is part of the pixel drive wiring 62 described in FIG.

[0033] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of charge accumulated in the floating diffusion FD. The amplification transistor AMP is connected in series with the selection transistor SEL and connected to a vertical signal line 63 via the selection transistor SEL. The amplification transistor AMP forms a source follower together with a load circuit section in a column signal processing circuit connected to the vertical signal line 63. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit via the vertical signal line 63. The drain of the amplification transistor AMP is connected to a power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0034] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to a vertical signal line 63, and the gate of the selection transistor SEL is connected to a pixel drive line. When the selection transistor SEL is turned on by the pixel drive line supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 63. This pixel drive line is part of the pixel drive line 62 described in FIG. 1.

[0035] 2, the sensor pixels 51 and the readout circuits 61 are provided in a one-to-one correspondence, but the readout circuits 61 may be provided for a plurality of sensor pixels 51. An example in which the readout circuits 61 are provided for a plurality of sensor pixels 51 will be described with reference to FIG.

[0036] 3 shows an example in which four sensor pixels 51 share one readout circuit 61. Here, "shared" means that the outputs of the four sensor pixels 51 are input to a common readout circuit 61. When distinguishing between the four sensor pixels 51 that share one readout circuit 61, they are referred to as sensor pixels 51A, 51B, 51C, and 51D, as shown in FIG. 3. The sensor pixels 51A, 51B, 51C, and 51D are formed on, for example, the first substrate 11, and the readout circuit 61 is formed on, for example, the second substrate 12.

[0037] The sensor pixels 51A, 51B, 51C, and 51D have common components. The reference numerals of the components of the sensor pixel 51A are suffixed with "a," the reference numerals of the components of the sensor pixel 51B are suffixed with "b," the reference numerals of the components of the sensor pixel 51C are suffixed with "c," and the reference numerals of the components of the sensor pixel 51D are suffixed with "d."

[0038] In this way, one readout circuit 61 may be provided for a plurality of sensor pixels 51. Although not shown in the drawings, the number of sensor pixels 51 that share one readout circuit 61 may be other than four. For example, two or eight sensor pixels 51 may share one readout circuit 61.

[0039] The following describes a transistor structure that can be employed for any of the reset transistor RST, switching transistor FDG, amplification transistor AMP, and selection transistor SEL that make up the readout circuit 61. In the following description, when there is no need to particularly distinguish between the reset transistor RST, switching transistor FDG, amplification transistor AMP, and selection transistor SEL that make up the readout circuit 61, they will be referred to as pixel transistors Tr.

[0040] 3. Configuration Example of Pixel Transistor> FIG. 4 is a diagram showing a configuration example of a pixel transistor Tr.

[0041] Fig. 4A shows a plan view of pixel transistors Tr1 and Tr2, which are two pixel transistors Tr with the same configuration. Fig. 4B shows a cross-sectional view of the pixel transistor Tr1 portion of the plan view of Fig. 4A taken along line XX', and Fig. 4C shows a plan view of Fig. 4B taken along line YY'. While Fig. 4 describes pixel transistor Tr1, the same applies to pixel transistor Tr2.

[0042] As shown in A of Fig. 4, the pixel transistors Tr1 and Tr2 are arranged side by side in the substrate region of the semiconductor substrate 42. As shown in A and B of Fig. 4, the substrate region of the semiconductor substrate 42 is formed of a p-type semiconductor region 112, which is a semiconductor region of a first conductivity type (p-type). Shallow trench isolation (STI) 111 made of an insulating film such as an SiO2 film is formed around the pixel transistors Tr1 and Tr2, and the pixel transistors Tr1 and Tr2 are electrically isolated from each other by the STI 111.

[0043] 4B, the pixel transistor Tr1 has a gate electrode Tr1-G (Tr1-PG, Tr1-VG), a first source-drain region T1r-SD1, and a second source-drain region T1r-SD2. One of the first source-drain region T1r-SD1 and the second source-drain region T1r-SD2 serves as the source of the pixel transistor Tr1, and the other serves as the drain of the pixel transistor Tr1.

[0044] The first source / drain region T1r-SD1 and the second source / drain region T1r-SD2 are formed of n-type semiconductor regions, which are semiconductor regions of the second conductivity type (n-type). The first source / drain region T1r-SD1, which is one of the first source / drain region T1r-SD1 and the second source / drain region T1r-SD2, is formed near the interface with the first surface 42A of the semiconductor substrate 42, and the other, the second source / drain region T1r-SD2, is formed near the interface with the second surface 42B opposite the first surface 42A of the semiconductor substrate 42. The first surface 42A of the semiconductor substrate 42 is the front surface of the semiconductor substrate 42, and the second surface 42B is the back surface. The first source / drain region T1r-SD1 is connected to a contact wiring 121, and the second source / drain region T1r-SD2 is connected to a junction electrode 132 via a contact wiring 131. The bonding electrode 132 is an electrode that is electrically connected by metal bonding such as Cu-Cu bonding to a bonding electrode of the wiring layer of the third substrate 13 that is attached to the lower side in B of Fig. 4. On the second surface 42B side of the semiconductor substrate 42, the area other than the contact wiring 131 and the bonding electrode 132 is covered with an insulating film 141.

[0045] The gate electrode Tr1-G has a planar electrode portion Tr1-PG formed above the first surface 42A of the semiconductor substrate 42 and a trench electrode portion Tr1-VG buried within the semiconductor substrate 42. A contact wiring 122 is connected to the planar electrode portion Tr1-PG of the gate electrode Tr1-G, and a predetermined gate voltage is supplied to the gate electrode Tr1-G via the contact wiring 122. A gate insulating film 113 is formed between the gate electrode Tr1-G and the semiconductor substrate 42, and a low-concentration n-type semiconductor region 114, in which a channel is formed, is formed around the trench electrode portion Tr1-VG below the planar electrode portion Tr1-PG. The low-concentration n-type semiconductor region 114 is a semiconductor region with a lower impurity concentration than the n-type semiconductor regions forming the first source / drain region T1r-SD1 and the second source / drain region T1r-SD2. The gate electrode Tr1-G is formed, for example, of polysilicon or a metal material such as titanium (Ti) or tungsten (W). The gate insulating film 113 is formed, for example, of a SiO2 film or the like.

[0046] The planar shape of the trench electrode portion Tr1-VG is formed in a rectangular shape, for example, as shown in FIG. 4C, and a low-concentration n-type semiconductor region 114 is formed around the rectangular gate electrode Tr1-G via a gate insulating film 113.

[0047] 4B, the trench electrode portion Tr1-VG is formed from the first surface 42A of the semiconductor substrate 42 to a depth position near the second surface 42B of the semiconductor substrate 42 in the substrate depth direction, and is connected to a second source / drain region T1r-SD2 formed on the second surface 42B side of the semiconductor substrate 42 via a gate insulating film 113. The second source / drain region T1r-SD2 is formed on the second surface 42B side of the semiconductor substrate 42 directly below (below) the gate electrode Tr1-G.

[0048] As described above, the pixel transistor Tr is a vertical transistor having a gate electrode Tr1-G including a trench electrode portion Tr1-VG formed from the first surface 42A of the semiconductor substrate 42 to a depth position near the second surface 42B. The pixel transistor Tr has a first source / drain region T1r-SD1 and a second source / drain region T1r-SD2 that serve as a source and a drain, with the first source / drain region T1r-SD1 being formed near the interface with the first surface 42A of the semiconductor substrate 42, and the other, the second source / drain region T1r-SD2, being formed below the gate electrode Tr1-G and near the interface with the second surface 42B of the semiconductor substrate 42. In the example of FIG. 4 , the second source / drain region T1r-SD2 is formed directly below the gate electrode Tr1-G (the trench electrode portion Tr1-VG) on the second surface 42B side of the semiconductor substrate 42. In this pixel transistor Tr, the channel length L corresponds to the length of the trench electrode portion Tr1-VG in the substrate depth direction, and the channel width W is the outer periphery diameter (the sum of the four sides) of the rectangular trench electrode portion Tr1-VG. By arranging the first source / drain region T1r-SD1 and the second source / drain region T1r-SD2 at a distance in the substrate depth direction on the first surface 42A side and the second surface 42B side of the semiconductor substrate 42, respectively, and setting the substrate depth direction to the channel length L, the planar area of ​​the pixel transistor Tr can be reduced. This enables pixel miniaturization and makes it easy to maintain pixel transistor characteristics even when further miniaturization is performed. The channel length L can be adjusted by adjusting the length of the trench electrode portion Tr1-VG in the substrate depth direction, and the channel width W can be adjusted by adjusting the outer periphery diameter of the trench electrode portion Tr1-VG, thereby adjusting the characteristics of the pixel transistor Tr.

[0049] The first source / drain region T1r-SD1 formed on the first surface 42A of the semiconductor substrate 42 is connected to the contact wiring 121 on the first surface 42A side, and the second source / drain region T1r-SD2 formed on the second surface 42B side of the semiconductor substrate 42 is connected to the contact wiring 131 on the second surface 42B side. By arranging one of the source and drain wirings of the pixel transistor Tr on the second surface 42B side of the semiconductor substrate 42, it is possible to reduce the wiring on the first surface 42A side of the semiconductor substrate 42.

[0050] 4. First Modification of Pixel Transistor FIG. 5 shows a first modification of the pixel transistor Tr.

[0051] The cross-sectional views shown in A and B of Fig. 5 correspond to the cross-sectional view shown in B of Fig. 4. In Fig. 5 and subsequent figures, parts corresponding to those in the configuration example shown in Fig. 4 are given the same reference numerals, and explanations of those parts will be omitted as appropriate, with the explanation focusing on parts that differ from Fig. 4. In the following explanation, the configuration example shown in Fig. 4 will be referred to as a basic configuration example.

[0052] In the first modified example, the position of the second source / drain region T1r-SD2 formed on the second surface 42B side of the semiconductor substrate 42 differs from that of the basic configuration example shown in FIG. 4. In the basic configuration example shown in FIG. 4, the second source / drain region T1r-SD2 was formed directly below the gate electrode Tr1-G (the trench electrode portion Tr1-VG). In contrast, in the pixel transistor Tr1 of FIG. 5A, the second source / drain region T1r-SD2 is located to the right of the center of the trench electrode portion Tr1-VG, and is located in a region that partially overlaps with the trench electrode portion Tr1-VG and the p-type semiconductor region 112 in plan view. In the pixel transistor Tr1 of FIG. 5B, the amount of movement of the second source / drain region T1r-SD2 from the center of the trench electrode portion Tr1-VG to the right in the figure is even greater, and the second source / drain region T1r-SD2 is completely separated from the trench electrode portion Tr1-VG in plan view. 5A and 5B, the second source / drain region T1r-SD2 is in contact with the low-concentration n-type semiconductor region 114, which is the region modulated by the gate electrode Tr1-G. As described above, the second source / drain region T1r-SD2 does not necessarily need to be located directly below the gate electrode Tr1-G (its trench electrode portion Tr1-VG), as long as at least a portion of it is located in the region modulated by the gate electrode Tr1-G.

[0053] 5. Second Modification of Pixel Transistor FIG. 6 shows a second modification of the pixel transistor Tr.

[0054] The cross-sectional view shown in FIG. 6 corresponds to the cross-sectional view shown by B in FIG.

[0055] In the second modified example shown in FIG. 6 , the second source / drain region T1r-SD2 is disposed to the right of the center of the trench electrode portion Tr1-VG, as in the first modified example. The second source / drain region T1r-SD2 is disposed away from the trench electrode portion Tr1-VG and in a position partially in contact with the p-type semiconductor region 112. In the basic configuration example, the trench electrode portion Tr1-VG was formed to a depth that did not reach the second surface 42B of the semiconductor substrate 42. In contrast, in the second modified example, the trench electrode portion Tr1-VG reaches the second surface 42B of the semiconductor substrate 42 and penetrates the semiconductor substrate 42. In this way, the trench electrode portion Tr1-VG of the gate electrode Tr1-G having a vertical gate electrode structure may have a depth that is a portion of the substrate thickness and does not penetrate the semiconductor substrate 42, as in the basic configuration example, or may be formed to penetrate the semiconductor substrate 42, as in the second modified example. In this case, the channel length L is the thickness of the semiconductor substrate 42, which makes it possible to suppress process variations during trench formation. The channel length L can be adjusted by the thickness of the semiconductor substrate 42 .

[0056] 6. Third Modification of Pixel Transistor FIG. 7 shows a third modification of the pixel transistor Tr.

[0057] The cross-sectional views shown in A and B of FIG. 7 correspond to the cross-sectional view shown in B of FIG.

[0058] 7A, the STI 111 in the basic configuration example shown in FIG. 4 is changed to a full trench isolation (FTI) 161 that penetrates the semiconductor substrate 42. Instead of the FTI 161, for example, a deep trench isolation (DTI) that is dug deeper into the semiconductor substrate 42 than the STI 111 may be used. The FTI 161 is formed of an insulating film such as SiO2.

[0059] 7B, the STI 111 in the basic configuration example is changed to a p-type semiconductor region 162 that penetrates the semiconductor substrate 42. The impurity concentration of the p-type semiconductor region 162 is higher than that of the p-type semiconductor region 112, which is the substrate region. The p-type semiconductor region 162 may be grounded.

[0060] In this way, the element isolation portion that isolates the pixel transistor Tr may be the STI 111, or may be configured with the FTI 161, the p-type semiconductor region 162, or the like.

[0061] 7. Fourth Modification of Pixel Transistor FIG. 8 shows a fourth modification of the pixel transistor Tr.

[0062] Fig. 8A is a plan view of a pixel transistor Tr according to a fourth modification. Fig. 8B shows a cross-sectional view of the pixel transistor Tr1 portion of the plan view of Fig. 8A taken along line XX', and Fig. 8C shows a plan view of Fig. 8B taken along line YY'.

[0063] In the fourth modification, the gate electrode Tr1-G has a planar electrode portion Tr1-PG and two trench electrode portions Tr1-VG, which differs from the basic configuration example of FIG. 4 in that there is only one trench electrode portion Tr1-VG. In this way, the pixel transistor Tr1 may have a configuration including multiple trench electrode portions Tr1-VG. While the example of FIG. 8 shows two trench electrode portions Tr1-VG, there may be three or more trench electrode portions Tr1-VG. By providing multiple trench electrode portions Tr1-VG, the effective channel width can be increased, thereby improving the transistor characteristics.

[0064] The number of trench electrode portions Tr1-VG may be one, and may be formed in a U-shape in plan view to have a fin shape that surrounds the low-concentration n-type semiconductor region 114 where the channel is formed on three sides (three surfaces). Alternatively, a plurality of fin-shaped trench electrode portions Tr1-VG may be provided.

[0065] 8. First Configuration Example of Readout Circuit Next, a configuration in which the above-described pixel transistor Tr is applied to all pixel transistors of the readout circuit 61 will be described.

[0066] FIG. 9 is a cross-sectional view showing a first configuration example of the readout circuit 61, and FIG. 10 is a plan view showing the first configuration example of the readout circuit 61. As shown in FIG.

[0067] 9 and 10 show the arrangement of the four pixel transistors that make up the readout circuit 61, namely, the reset transistor RST, the switching transistor FDG, the amplification transistor AMP, and the selection transistor SEL. Fig. 10A is a plan view of the four pixel transistors as seen from the first surface 42A side of the semiconductor substrate 42, and Fig. 10B is a plan view of the four pixel transistors as seen from the second surface 42B side of the semiconductor substrate 42. For convenience, the cross-sectional view of Fig. 9 shows the four pixel transistors lined up.

[0068] The switching transistor FDG, reset transistor RST, amplifier transistor AMP, and select transistor SEL in Figures 9 and 10 each employ the configuration of the pixel transistor Tr described in Figure 4. In Figures 9 and 10, the symbol "Tr1" for the pixel transistor Tr1 shown in Figure 4 is replaced with the symbols "FDG," "RST," "AMP," and "SEL" corresponding to the switching transistor FDG, reset transistor RST, amplifier transistor AMP, and select transistor SEL, respectively, and the contact wirings 121, 122, and 131 are indicated with the symbols "FDG," "RST," "AMP," and "SEL" added. For example, looking at the switching transistor FDG on the far left in Figure 9, the gate electrode FDG-G corresponds to the gate electrode Tr1-G in Figure 4, the first source / drain region FDG-SD1 corresponds to the first source / drain region T1r-SD1 in Figure 4, and the second source / drain region FDG-SD2 corresponds to the second source / drain region T1r-SD2 in Figure 4. 4, and the contact wiring 122-FDG connected to the gate electrode FDG-G corresponds to the contact wiring 122 in Fig. 4. The contact wiring 131-FDG connected to the second source-drain region FDG-SD2 corresponds to the contact wiring 131 in Fig. 4. The same applies to the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL.

[0069] The contact wiring 121-FDG connected to the first source-drain region FDG-SD1, which serves as the drain of the switching transistor FDG, is connected to the floating diffusion FD, and the contact wiring 131-FDG connected to the second source-drain region FDG-SD2, which serves as the source, is connected to an additional capacitance SubFD. The contact wiring 122-FDG connected to the gate electrode FDG-G of the switching transistor FDG is connected to a part of the pixel drive wiring 62 (FIG. 1).

[0070] The contact wiring 121-RST connected to the first source-drain region RST-SD1 which serves as the source of the reset transistor RST is connected to the floating diffusion FD, and the contact wiring 131-RST connected to the second source-drain region RST-SD2 which serves as the drain is connected to the power supply line VDD. The contact wiring 122-RST connected to the gate electrode RST-G of the reset transistor RST is connected to a part of the pixel drive wiring 62 (FIG. 1).

[0071] The contact wiring 121-AMP connected to the first source-drain region AMP-SD1 serving as the source of the amplifier transistor AMP is connected to the contact wiring 121-SEL connected to the first source-drain region SEL-SD1 of the select transistor SEL, and the contact wiring 131-AMP connected to the second source-drain region AMP-SD2 serving as the drain is connected to the power supply line VDD. The contact wiring 122-AMP connected to the gate electrode AMP-G of the amplifier transistor AMP is connected to the floating diffusion FD.

[0072] The contact wiring 121-SEL connected to the first source-drain region SEL-SD1 that serves as the drain of the select transistor SEL is connected to the contact wiring 121-AMP that is connected to the first source-drain region AMP-SD1 of the amplifying transistor AMP, and the contact wiring 131-SEL connected to the second source-drain region SEL-SD2 that serves as the source is connected to the vertical signal line 63. The contact wiring 122-SEL connected to the gate electrode SEL-G of the select transistor SEL is connected to a part of the pixel drive wiring 62 (FIG. 1).

[0073] Although not shown in Figure 9 due to space constraints, as shown in A of Figure 10, on the first surface 42A side of the semiconductor substrate 42, a contact wiring 181 is arranged that connects to the p-type semiconductor region 112, which is the substrate region of the semiconductor substrate 42, and supplies a predetermined voltage (including ground).

[0074] 4 for each of the four pixel transistors constituting the readout circuit 61, it is possible to reduce the plane area while maintaining the pixel transistor characteristics, thereby enabling pixel miniaturization. Furthermore, by adjusting the length of the trench electrode portion Tr1-VG in the substrate depth direction or adjusting the outer diameter, it is possible to adjust the channel length L and channel width W, and therefore the characteristics of the pixel transistor Tr can also be adjusted.

[0075] Arranged on the second surface 42B side of the semiconductor substrate 42 are contact wiring 131-FDG connected to the additional capacitance SubFD, contact wiring 131-RST and contact wiring 131-AMP connected to the power supply line VDD, and contact wiring 131-SEL connected to the vertical signal line 63. By moving some of the wiring of the readout circuit 61 to the second surface 42B side of the semiconductor substrate 42, it is possible to suppress the congestion of wiring around the floating diffusion FD, reduce coupling, and improve conversion efficiency. In addition, by moving the wiring connected to the power supply line VDD (contact wiring 131-RST, 131-AMP) to the second surface 42B side of the semiconductor substrate 42, it is possible to reduce power supply noise.

[0076] 11 is a cross-sectional view showing a second configuration example of the readout circuit 61, and Fig. 12 is a plan view showing the second configuration example of the readout circuit 61. In Fig. 11 and Fig. 12, parts corresponding to those in the first configuration example of the readout circuit 61 shown in Fig. 9 and Fig. 10 are denoted by the same reference numerals.

[0077] When the second configuration example shown in FIGS. 11 and 12 is compared with the first configuration example shown in FIGS. 9 and 10, the following points are different.

[0078] In the first configuration example, on the first surface 42A side of the semiconductor substrate 42, the first source-drain region AMP-SD1 serving as the source of the amplifier transistor AMP and the first source-drain region SEL-SD1 of the select transistor SEL are connected via contact wirings 121-AMP, 121-SEL, etc. In the second configuration example, these are omitted, and the region near the first surface 42A between the gate electrode AMP-G of the amplifier transistor AMP and the gate electrode SEL-G of the select transistor SEL is connected by the low-concentration n-type semiconductor region 114.

[0079] In the first configuration example, the first source-drain region FDG-SD1 of the switching transistor FDG, which is arranged on the first surface 42A side of the semiconductor substrate 42, and the first source-drain region RST-SD1 of the reset transistor RST are provided separately and connected to the floating diffusion FD. In contrast, in the second configuration example, the first source-drain region FDG-SD1' of the switching transistor FDG and the contact wiring 121-FDG' are shared, and the first source-drain region RST-SD1 of the reset transistor RST and the contact wiring 121-RST are omitted. As is clear from comparing FIG. 12A with FIG. 10B, the number of contact wirings 121 on the first surface 42A side of the semiconductor substrate 42 is reduced from four to one.

[0080] In addition, instead of sharing the first source-drain region FDG-SD1' of the switching transistor FDG with the contact wiring 121-FDG', the first source-drain region RST-SD1' of the reset transistor RST may be shared with the contact wiring 121-RST', and the first source-drain region FDG-SD1 of the switching transistor FDG and the contact wiring 121-FDG may be omitted.

[0081] The second configuration example of the readout circuit 61 configured as described above has the same effects as the first configuration example described above. In addition, since the wiring on the first surface 42A side of the semiconductor substrate 42 can be reduced even more than in the first configuration example, it is possible to further improve the conversion efficiency compared to the first configuration example.

[0082] 10. Third Configuration Example of Readout Circuit FIG. 13 is a cross-sectional view showing a third configuration example of the readout circuit 61, and FIG. 14 is a plan view showing the third configuration example of the readout circuit 61. As shown in FIG.

[0083] When the third configuration example shown in FIGS. 13 and 14 is compared with the second configuration example shown in FIGS. 11 and 12, the following points are different.

[0084] In the second configuration example, on the second surface 42B side of the semiconductor substrate 42, the second source-drain region RST-SD2 of the reset transistor RST is connected to the power supply line VDD via the contact wiring 131-RST, and the second source-drain region AMP-SD2 of the amplifier transistor AMP is also connected to the power supply line VDD via the contact wiring 131-AMP. In the third configuration example, the second source-drain region RST-SD2 of the reset transistor RST and the second source-drain region AMP-SD2 of the amplifier transistor AMP are integrated into the second source-drain region AMP / RST-SD2 and connected to a single contact wiring 131-AMP / RST. The contact wiring 131-AMP / RST is connected to the power supply line VDD. In this case, the pixel circuit corresponds to a configuration in which the drain of the reset transistor RST and the drain of the amplifier transistor AMP are combined into a single line and connected to the power supply line VDD, as shown in FIG. 15. As is clear from comparing the plan views of FIG. 14B and FIG. 12B, the number of lines on the second surface 42B side of the semiconductor substrate 42 can be reduced by one. The configuration of the first surface 42A side of the semiconductor substrate 42 is the same as that of the second configuration example.

[0085] The third configuration example of the readout circuit 61 configured as described above has the same effects as the second configuration example described above. Furthermore, since the number of wirings connected to the power supply line VDD on the second surface 42B side of the semiconductor substrate 42 can be further reduced than in the second configuration example, the reduction in wiring capacitance, in other words, the reduction in IR-Drop, can be reduced. The second surface 42B side of the semiconductor substrate 42 includes contact wiring 131-SEL, which is connected to the vertical signal line 63 and outputs pixel signals. The reduction in the number of wirings other than the contact wiring 131-SEL, which is the signal output wiring, allows the signal output wiring and other wirings (for example, the contact wiring 131-AMP / RST connected to the power supply line VDD) to be spaced apart, thereby reducing noise in the pixel signals.

[0086] In the second configuration example, the first source / drain region FDG-SD1' on the first surface 42A side of the semiconductor substrate 42 is shared, but the second surface 42B side of the semiconductor substrate 42 is not shared. In the third configuration example, the first source / drain region FDG-SD1' on the first surface 42A side of the semiconductor substrate 42 and the second source / drain region AMP / RST-SD2 on the second surface 42B side of the semiconductor substrate 42 are shared. Although not shown, a configuration may be adopted in which the first surface 42A side of the semiconductor substrate 42 is not shared, but the second source / drain region AMP / RST-SD2 on the second surface 42B side of the semiconductor substrate 42 is shared. In other words, a configuration may be adopted in which at least one of the source / drain regions on the first surface 42A side and the second surface 42B side of the semiconductor substrate 42 is shared.

[0087] 11. Fourth Configuration Example of Readout Circuit FIG. 16 is a cross-sectional view showing a fourth configuration example of the readout circuit 61, and FIG. 17 is a plan view showing the fourth configuration example of the readout circuit 61. As shown in FIG.

[0088] The fourth configuration example in Figures 16 and 17 illustrates an example in which the second modified example of the pixel transistor Tr described with reference to Figure 6, i.e., a pixel transistor Tr1 having trench electrode portions Tr1-VG penetrating the semiconductor substrate 42, is applied to four pixel transistors constituting the readout circuit 61. Comparing the fourth configuration example with the first configuration example of the readout circuit 61 shown in Figure 9, the second source / drain regions FDG-SD2, RST-SD2, AMP-SD2, and SEL-SD2 of each of the four pixel transistors have moved from directly below the trench electrode portions FDG-VG, RST-VG, AMP-VG, and SEL-VG, and the trench electrode portions FDG-VG, RST-VG, AMP-VG, and SEL-VG penetrate the semiconductor substrate 42. As is clear from comparing the plan view of the second surface 42B side of the semiconductor substrate 42 shown in Figure 17B with Figure 10B, in the fourth configuration example, the trench electrode portions FDG-VG, RST-VG, AMP-VG, and SEL-VG reach the second surface 42B of the semiconductor substrate 42. The configuration of the first surface 42A side of the semiconductor substrate 42 is the same as the first configuration example of the readout circuit 61 shown in FIG.

[0089] As described above, by adopting the configuration of the pixel transistor Tr according to the second modification example described in FIG. 6 for each of the four pixel transistors constituting the readout circuit 61, it is possible to reduce the plane area while maintaining the pixel transistor characteristics, thereby enabling pixel miniaturization. Furthermore, since the channel length L and channel width W can be adjusted, the characteristics of the pixel transistor Tr can also be adjusted. The channel length L is adjusted by the thickness of the semiconductor substrate 42.

[0090] Arranged on the second surface 42B side of the semiconductor substrate 42 are contact wiring 131-FDG connected to the additional capacitance SubFD, contact wiring 131-RST and contact wiring 131-AMP connected to the power supply line VDD, and contact wiring 131-SEL connected to the vertical signal line 63. Furthermore, by moving some of the wiring of the readout circuit 61 to the second surface 42B side of the semiconductor substrate 42, it is possible to suppress the density of wiring around the floating diffusion FD, reduce coupling, and improve conversion efficiency. Furthermore, by moving the wiring connected to the power supply line VDD (contact wiring 131-RST, 131-AMP) to the second surface 42B side of the semiconductor substrate 42, it is possible to reduce power supply noise.

[0091] 12. Fifth Configuration Example of Readout Circuit FIG. 18 is a cross-sectional view showing a fifth configuration example of the readout circuit 61, and FIG. 19 is a plan view showing the fifth configuration example of the readout circuit 61. As shown in FIG.

[0092] The fifth configuration example shown in Figures 18 and 19 is a configuration in which the pixel transistor of the second configuration example of the readout circuit 61 shown in Figure 11 is changed to the pixel transistor Tr1 of Figure 6 having a trench electrode portion Tr1-VG that penetrates the semiconductor substrate 42. In the fifth configuration example, the first source-drain region AMP-SD1 that serves as the source of the amplifier transistor AMP and the first source-drain region SEL-SD1 of the select transistor SEL are omitted from the configuration of the readout circuit 61 of the fourth configuration example shown in Figures 16 and 17, and a low-concentration n-type semiconductor region 114 is formed in a region near the first surface 42A between the gate electrode AMP-G of the amplifier transistor AMP and the gate electrode SEL-G of the select transistor SEL. In addition, the first source-drain region FDG-SD1 of the switching transistor FDG and the first source-drain region RST-SD1 of the reset transistor RST, which are arranged on the first surface 42A side of the semiconductor substrate 42, are shared by the first source-drain region FDG-SD1' of the switching transistor FDG. The contact wirings 121-FDG and 121-RST are shared by the contact wiring 121-FDG'. As is clear from a comparison of the plan views of FIG. 19A and FIG. 17A, the number of contact wirings 121 on the first surface 42A side of the semiconductor substrate 42 has been reduced from four to one.

[0093] The fifth configuration example of the readout circuit 61 configured as described above has the same effects as the fourth configuration example described above. In addition, since the wiring on the first surface 42A side of the semiconductor substrate 42 can be reduced even more than in the fourth configuration example, it is possible to further improve the conversion efficiency compared to the fourth configuration example.

[0094] 13. Sixth Configuration Example of Readout Circuit FIG. 20 is a cross-sectional view showing a sixth configuration example of the readout circuit 61, and FIG. 21 is a plan view showing the sixth configuration example of the readout circuit 61. As shown in FIG.

[0095] The sixth configuration example shown in FIGS. 20 and 21 is a configuration in which the pixel transistor of the third configuration example of the readout circuit 61 shown in FIG. 13 is replaced with the pixel transistor Tr1 of FIG. 6, which has a trench electrode portion Tr1-VG penetrating the semiconductor substrate 42. The sixth configuration example is a configuration in which the second source-drain region RST-SD2 of the reset transistor RST and the second source-drain region AMP-SD2 of the amplifier transistor AMP on the second surface 42B side of the semiconductor substrate 42 of the readout circuit 61 of the fifth configuration example shown in FIGS. 18 and 19 are replaced with a single second source-drain region AMP / RST-SD2. The second source-drain region AMP / RST-SD2 is connected to a single contact wiring 131-AMP / RST and connected to the power supply line VDD via the contact wiring 131-AMP / RST. As is clear from comparing the plan views of FIGS. 21B and 19B, the number of contact wirings 131 on the second surface 42B side of the semiconductor substrate 42 has been reduced from four to three. The configuration of the first surface 42A side of the semiconductor substrate 42 is the same as that of the fifth configuration example.

[0096] The sixth configuration example of the readout circuit 61 configured as described above has the same effects as the fifth configuration example described above. Furthermore, since the number of wirings connected to the power supply line VDD on the second surface 42B side of the semiconductor substrate 42 can be further reduced than in the fifth configuration example, the reduction in wiring capacitance, in other words, the reduction in IR-Drop, can be reduced. The second surface 42B side of the semiconductor substrate 42 includes contact wiring 131-SEL, which is connected to the vertical signal line 63 and outputs pixel signals. The reduction in the number of wirings other than the contact wiring 131-SEL, which is the signal output wiring, allows the signal output wiring and other wirings (for example, the contact wiring 131-AMP / RST connected to the power supply line VDD) to be spaced apart, thereby reducing noise in the pixel signals.

[0097] In the fifth configuration example, the first source / drain region FDG-SD1' on the first surface 42A side of the semiconductor substrate 42 is shared, but the second surface 42B side of the semiconductor substrate 42 is not shared. In the sixth configuration example, the first source / drain region FDG-SD1' on the first surface 42A side of the semiconductor substrate 42 and the second source / drain region AMP / RST-SD2 on the second surface 42B side of the semiconductor substrate 42 are shared. Although not shown, a configuration may be adopted in which the first surface 42A side of the semiconductor substrate 42 is not shared, but the second source / drain region AMP / RST-SD2 on the second surface 42B side of the semiconductor substrate 42 is shared. In other words, a configuration in which at least one of the source / drain regions on the first surface 42A side and the second surface 42B side of the semiconductor substrate 42 is shared may be adopted.

[0098] 22 to 26, a method for manufacturing the pixel transistor Tr1 shown in Fig. 4 will be described. <First Method for Manufacturing Pixel Transistor> First, a first method for manufacturing the pixel transistor Tr1 will be described with reference to Figs. 22 to 24.

[0099] First, as shown in FIG. 22A, an STI 111 is formed on the first surface 42A side of the semiconductor substrate 42. Specifically, a trench is formed by digging to a predetermined depth into the p-type semiconductor region 112 in the region where the STI 111 is to be formed on the first surface 42A side of the semiconductor substrate 42, and an insulating film such as an SiO film is embedded in the formed trench, thereby forming the STI 111. When forming an FTI 161 as in the third modification shown in FIG. 7, a trench penetrating the semiconductor substrate 42 is formed and embedded with an insulating film. When isolation is performed by the p-type semiconductor region 162, p-type impurities such as boron (B) and gallium (Ga) are ion-implanted into the semiconductor substrate 42.

[0100] Next, as shown in FIG. 22B, the semiconductor substrate 42 in the region where the trench electrode portion Tr1-VG of the gate electrode Tr1-G is to be formed is removed using, for example, dry etching, to form a trench 211 dug to a predetermined depth.

[0101] 22C, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the side and bottom vicinity of the trench 211 to form a low-concentration n-type semiconductor region 114. Furthermore, n-type impurities are ion-implanted into the bottom side of the trench 211, which is in the vicinity of the second surface 42B of the semiconductor substrate 42, to form a second source / drain region T1r-SD2 having an impurity concentration higher than that of the low-concentration n-type semiconductor region 114. Furthermore, an oxidation process is performed on the side and bottom of the trench 211 using, for example, the ISSG method, to form an oxide film, thereby forming a gate insulating film 113.

[0102] 23A, a gate electrode material is buried inside the trench 211 and also formed to a predetermined thickness on the upper surface of the semiconductor substrate 42 to form a gate electrode Tr1-G consisting of a planar electrode portion Tr1-PG and a trench electrode portion Tr1-VG. The gate electrode material may be, for example, polysilicon or a metal material such as titanium (Ti) or tungsten (W).

[0103] 23B, a first source / drain region T1r-SD1 is formed by ion-implanting n-type impurities such as phosphorus (P) or arsenic (As) near the gate electrode Tr1-G on the first surface 42A side of the semiconductor substrate 42. Thereafter, a contact wiring 121 connected to the first source / drain region T1r-SD1, a contact wiring 122 connected to the gate electrode Tr1-G, etc. are formed.

[0104] Next, as shown in Fig. 23C, the semiconductor substrate 42 is turned upside down so that the second surface 42B faces up, and an insulating film 141 is formed to a predetermined thickness using a CVD (Chemical Vapor Deposition) method or the like. Note that Fig. 23C and Fig. 24 show a state in which the semiconductor substrate 42 is not turned upside down. The insulating film 141 can be formed of, for example, SiO2, SiN, SiON, or the like.

[0105] Next, as shown in FIG. 24A, of the insulating film 141 formed on the second surface 42B side of the semiconductor substrate 42, a region 221 connected to the second source / drain region T1r-SD2 is removed by etching or the like.

[0106] Next, as shown in Fig. 24B, a metal material such as copper (Cu), aluminum (Al), or tungsten (W) is filled into the opened region 221 to form the contact wiring 131. Furthermore, as shown in Fig. 24C, a wide opening is made above the contact wiring 131 and a metal material is filled in to form the bonding electrode 132. The bonding electrode 132 is made of a metal material such as copper (Cu), aluminum (Al), or tungsten (W), and may be made of a different material from or the same as the contact wiring 131.

[0107] According to the first manufacturing method, the pixel transistor Tr1 shown in FIG. 4 can be manufactured by the above steps.

[0108] <Second Method for Manufacturing Pixel Transistor> Next, a second method for manufacturing the pixel transistor Tr1 will be described with reference to FIGS.

[0109] 25A, an STI 111 is formed on the first surface 42A side of a semiconductor substrate 42. This process is the same as that in the first manufacturing method, but differs from that in the first manufacturing method in the thickness of the semiconductor substrate 42. The second manufacturing method uses a semiconductor substrate 42 that is thicker than that used in the first manufacturing method.

[0110] Next, as shown in B of FIG. 25, the semiconductor substrate 42 in the region where the trench electrode portion Tr1-VG of the gate electrode Tr1-G is to be formed is removed using, for example, dry etching, to form a trench 211 dug to a predetermined depth.

[0111] 25C, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the side and bottom vicinity of the trench 211 to form a low-concentration n-type semiconductor region 114. Furthermore, n-type impurities are ion-implanted into the bottom side of the trench 211 to form a second source / drain region T1r-SD2. Furthermore, a gate insulating film 113 is formed on the side and bottom surfaces of the trench 211. Unlike the first manufacturing method, the semiconductor substrate 42 is thick, and therefore the region where the second source / drain region T1r-SD2 is formed is near the bottom surface of the trench 211 but is slightly separated from the second surface 42B of the semiconductor substrate 42.

[0112] 26A, a gate electrode Tr1-G consisting of a planar electrode portion Tr1-PG and a trench electrode portion Tr1-VG is formed, and a first source / drain region T1r-SD1, contact wirings 121, 122, etc. are also formed. This process is similar to the processes in FIG. 23A and B of the first manufacturing method.

[0113] Next, as shown in Fig. 26B, a predetermined thickness is removed from the second surface 42B side of the semiconductor substrate 42 using CMP (Chemical Mechanical Polishing) or the like, thereby thinning the semiconductor substrate 42. The thinned semiconductor substrate 42 has the same thickness as the semiconductor substrate 42 in the first manufacturing method, and the state in Fig. 26B is the same as the state in Fig. 23B in the first manufacturing method.

[0114] 26C, an insulating film 141 is formed by a CVD method or the like on the second surface 42B side of the thinned semiconductor substrate 42. The subsequent steps of forming the contact wiring 131 and the bonding electrode 132 are the same as those in the first manufacturing method, and therefore a description thereof will be omitted.

[0115] According to the second manufacturing method, the pixel transistor Tr1 shown in FIG. 4 can be manufactured by the above steps.

[0116] 15. Configuration Examples of Electronic Devices The above-described photodetector 1 can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0117] FIG. 27 is a block diagram showing an example of the configuration of an electronic device.

[0118] 27 , electronic device 301 includes an optical system 302, a photodetector 303, a DSP (Digital Signal Processor) 304, a display device 305, an operation system 306, a memory 307, a recording device 308, and a power supply system 309. DSP 304, display device 305, operation system 306, memory 307, recording device 308, and power supply system 309 are interconnected via a bus 310. Electronic device 301 is, for example, an imaging device capable of capturing still images and moving images.

[0119] The optical system 302 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 303 , forming an image on the light-receiving surface (sensor portion) of the photodetector 303 .

[0120] The photodetector 303 has the same configuration as the photodetector 1 described above. Electrons are accumulated as signal charges in the photodetector 303 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 302. A signal corresponding to the electrons accumulated in the photodetector 303 is then supplied to the DSP 304.

[0121] The DSP 304 performs various signal processing on the signal from the photodetector 303 to generate an image, and temporarily stores the image data in a memory 307. The image data stored in the memory 307 is recorded in a recording device 308 or supplied to a display device 305 to display the image. In addition, an operation system 306 accepts various operations by a user and supplies operation signals to each block of the electronic device 301, and a power supply system 309 supplies the power necessary to drive each block of the electronic device 301.

[0122] In the electronic device 301 configured as described above, by applying the above-described photodetector 1 as the photodetector 303, it becomes possible to miniaturize pixels, and even when miniaturization is performed, it becomes easy to maintain the pixel transistor characteristics, thereby making it possible to generate high-quality captured images.

[0123] 16. Example of Use of Image Sensor FIG. 28 is a diagram showing an example of use of the above-described photodetector 1 as an image sensor.

[0124] When the above-described photodetector 1 is an image sensor, it can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0125] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0126] 17. Application Example to Endoscopic Surgery System The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0127] FIG. 29 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0128] 29 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0129] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0130] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0131] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0132] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0133] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0134] The light source device 11203 is composed of a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0135] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0136] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0137] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0138] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0139] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissue and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0140] FIG. 30 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0141] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0142] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0143] The imaging unit 11402 is composed of an imaging element. The imaging element constituting the imaging unit 11402 may be a single (single-chip type) or multiple (multi-chip type). When the imaging unit 11402 is composed of a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is composed of a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0144] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0145] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0146] The communication unit 11404 is configured by a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0147] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0148] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0149] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404.

[0150] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0151] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0152] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0153] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0154] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0155] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0156] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0157] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 11402 of the camera head 11102 in the above-described configuration. Specifically, the above-described light detection device 1 can be used as the imaging unit 11402. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to obtain clearer images of the surgical site while miniaturizing the camera head 11102.

[0158] Although an endoscopic surgery system has been described as an example here, the technology disclosed herein may also be applied to other systems, such as a microsurgery system.

[0159] 18. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0160] FIG. 31 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0161] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 31 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0162] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0163] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0164] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0165] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0166] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0167] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0168] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0169] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0170] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 31, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0171] FIG. 32 is a diagram showing an example of the installation position of the imaging unit 12031.

[0172] In FIG. 32, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0173] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0174] 32 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0175] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for detecting a phase difference.

[0176] For example, based on distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the closest three-dimensional object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which travels autonomously without relying on driver operation.

[0177] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into categories such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0178] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching processing on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0179] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the image capture unit 12031 of the above-described configuration. Specifically, the above-described light detection device 1 can be applied as the image capture unit 12031. By applying the technology according to the present disclosure to the image capture unit 12031, it is possible to obtain a more easily visible captured image and acquire distance information while still reducing the size of the image capture unit 12031. Furthermore, using the obtained captured image and distance information, it is possible to reduce driver fatigue and increase the safety of the driver and the vehicle.

[0180] In the above example, a photodetector in which the first conductivity type is p-type and the second conductivity type is n-type and electrons are used as signal charges has been described, but the present disclosure can also be applied to a photodetector in which holes are used as signal charges. That is, the first conductivity type can be n-type and the second conductivity type can be p-type, and the aforementioned semiconductor regions can be configured with semiconductor regions of opposite conductivity types.

[0181] Furthermore, the present disclosure is not limited to application to photodetection devices that detect the distribution of incident light amount of visible light and capture it as an image, but is also applicable to photodetection devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc. as an image, and in a broad sense, to photodetection devices in general (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure or capacitance and capture it as an image.

[0182] The embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the technology of the present disclosure.

[0183] The effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0184] The technology disclosed herein may employ the following configurations. (1) A photodetector including a vertical transistor having a gate electrode having a trench electrode portion dug into at least a portion of a semiconductor substrate in a depth direction, and a first source / drain region and a second source / drain region, one of which serves as a source and the other as a drain, wherein the first source / drain region is formed near an interface with a first surface of the semiconductor substrate, and the second source / drain region is formed below the gate electrode and near an interface with a second surface of the semiconductor substrate opposite the first surface. (2) The photodetector described in (1), wherein at least a portion of the second source / drain region is disposed in a region modulated by the gate electrode. (3) The photodetector described in (1) or (2), wherein the gate electrode includes a plurality of the trench electrode portions. (4) The photodetector described in any of (1) to (3), wherein the gate electrode includes the trench electrode portion having a fin shape. (5) The photodetector described in any of (1) to (4), wherein the gate electrode includes the trench electrode portion penetrating the semiconductor substrate. (6) The photodetector according to any one of (1) to (5), including a plurality of transistors as a readout circuit that reads out charges generated in a photoelectric conversion unit in accordance with the amount of incident light received, and at least one of the transistors in the readout circuit is the vertical transistor. (7) The photodetector according to (6), wherein the plurality of transistors in the readout circuit are the vertical transistors, and at least one of the first source / drain region formed on the first surface of the semiconductor substrate and the second source / drain region formed on the second surface is shared by a plurality of transistors. (8) The photodetector according to any one of (1) to (7), wherein the vertical transistors are separated by an element isolation portion, and the element isolation portion is formed by filling a trench of a predetermined depth with an insulating film, or is formed by an insulating film or a high-concentration semiconductor region that penetrates the semiconductor substrate.(9) An electronic device comprising: a vertical transistor having a gate electrode having a trench electrode portion dug into at least a portion of a semiconductor substrate in a depth direction; and a first source / drain region and a second source / drain region, one of which serves as a source and the other as a drain, wherein the first source / drain region is formed near the interface with a first surface of the semiconductor substrate; and the second source / drain region is formed below the gate electrode and near the interface with a second surface of the semiconductor substrate opposite the first surface.

[0185] 1 Photodetector device, 11 First substrate, 12 Second substrate, 13 Third substrate, 41 Semiconductor substrate, 42 Semiconductor substrate, 42A First surface, 42B Second surface, 43 Semiconductor substrate, 51, 51A, 51B, 51C, 51D Sensor pixel, 52 Pixel area, 61 Readout circuit, 62 Pixel drive wiring, 63 Vertical signal line, PD Photodiode, TG Transfer transistor, AMP Amplifying transistor, FD Floating diffusion, FDG Switching transistor, RST Reset transistor, SEL Select transistor, SubFD Additional capacitance, VDD Power supply line, Tr, Tr1, Tr2 Pixel transistor, Tr1-G Gate electrode, Tr1-PG Planar electrode portion, Tr1-VG Trench electrode portion, T1r-SD1 First source / drain region, T1r-SD2 Second source / drain region, 111 STI, 112 p-type semiconductor region, 113 gate insulating film, 114 low-concentration n-type semiconductor region, 121 contact wiring, 122 contact wiring, 131 contact wiring, 132 junction electrode, 141 insulating film, 301 electronic device, 303 photodetector

Claims

1. A photodetector comprising: a gate electrode having a trench electrode portion dug at least partially in the depth direction of a semiconductor substrate; and a vertical transistor having a first source-drain region where one is a source and the other is a drain and a second source-drain region. The first source-drain region is formed near the interface of the first surface of the semiconductor substrate, and the second source-drain region is formed below the gate electrode and near the interface of the second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate.

2. The photodetector according to claim 1, wherein at least a part of the second source-drain region is arranged in a region modulated by the gate electrode.

3. The photodetector according to claim 1, wherein the gate electrode has a plurality of the trench electrode portions.

4. The photodetector according to claim 1, wherein the gate electrode has a fin-shaped trench electrode portion.

5. The photodetector according to claim 1, wherein the gate electrode has a trench electrode portion penetrating the semiconductor substrate.

6. Having a plurality of transistors as a readout circuit for reading out charges generated in a photoelectric conversion portion according to the amount of incident light received, and at least one of the transistors in the readout circuit is the vertical transistor. The photodetector according to claim 1.

7. The plurality of transistors in the readout circuit are the vertical transistors, and at least one of the first source-drain region formed on the first surface of the semiconductor substrate and the second source-drain region formed on the second surface of the semiconductor substrate is shared by a plurality of transistors. The photodetector according to claim 6.

8. The vertical transistor is separated by an element isolation portion, and the element isolation portion is formed by embedding an insulating film in a trench having a predetermined depth, or is formed by an insulating film or a high-concentration semiconductor region penetrating the semiconductor substrate. The photodetector according to claim 1.

9. An electronic device including an optical detection device, the optical detection device comprising: a gate electrode having a trench electrode portion dug into at least a part of the depth direction of a semiconductor substrate; a vertical transistor having a first source-drain region where one is a source and the other is a drain, and a second source-drain region; the first source-drain region being formed near the interface of the first surface of the semiconductor substrate; and the second source-drain region being formed near the interface of the second surface on the side opposite to the first surface of the semiconductor substrate and below the gate electrode.

Images