Integrated current resistor sensing for multi-level converter

Abstract

Circuits and methods are provided that more effectively and efficiently implement multi-level converter circuits. A switched mode power supply is configured to be coupled between a reference potential and a voltage input source Vin, and includes a terminal configured to source an output voltage Vout and an output current Iout to a load. A current-sensitive element coupled between voltage input source Vin and the switched mode power supply conducts an input current Iin to the switched mode power supply and provides a sensing voltage related to input current Iin. An analog to digital converter provides digital representations of analog voltages presented thereto. A controller receives digital representations from the analog to digital converter and estimates output current Iout based upon the digital representations and an efficiency factor Eff.

Description

INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTERGregory Szczeszynski, Antony RoutledgeCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims the benefit of and priority to in their entirety the following United States Provisional Patent Applications filed herewith on January 12, 2024, which are all incorporated by reference in their entirety:

[0002] Application No. 63 / 620,507 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0003] Application No. 63 / 620,623 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0004] Application No. 63 / 620,613 entitled “INTEGRATED CURRENT RESISTOR SENSING FOR MULTI-LEVEL CONVERTER;”

[0005] Application No. 63 / 620,465 entitled “STARTUP INTERLOCK FOR POWER CONVERTER CIRCUITS;”

[0006] Application No. 63 / 620,331 entitled “FULLY DIFFERENTIAL LEVEL SHIFT IN A NOISY ENVIRONMENT;”

[0007] Application No. 63 / 620,450 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0008] Application No. 63 / 620,469 entitled “CAPACITOR SENSING AND CAPACITOR BALANCING SYSTEMS AND METHODS;”

[0009] Application No. 63 / 620,678 entitled “RECONFIGURABLE MULTI-LEVEL POWER CONVERTER TO CHARGE PUMP MODE AND FRACTIONAL CHARGE PUMP MODE;”

[0010] Application No. 63 / 620,417 entitled “INPUT CURRENT SLEW FOR A MULTI¬LEVEL CONVERTER;”

[0011] Application No. 63 / 620,726 entitled “ADJUSTING OVERVOLTAGE PROTECTION BASED ON MODE OF OPERATION SYSTEMS AND METHODS;’’

[0012] Application No. 63 / 620,737 entitled “HYBRID PEAK AVERAGE CURRENT MODE CONTROL;”

[0013] Application No. 63 / 620,741 entitled “CURRENT LIMITED VOLTAGE MODE CONTROL OF MULTIPLE INPUTS;”

[0014] Application No. 63 / 620,527 entitled “MULTI-FUNCTION COMP PIN SYSTEMS AND METHODS;”

[0015] Application No. 63 / 620,488 entitled “LEVEL SHIFTER AND BOOT CAPACITOR CIRCUITS, SYSTEMS, AND METHODS;”

[0016] Application No. 63 / 620,553 entitled “MULTI-LEVEL REVERSE CURRENT BLOCKING SYSTEMS AND METHODS;”

[0017] Application No. 63 / 620,638 entitled “GENERAL STARTUP FOR MULTILEVEL POWER CONVERTER CIRCUITS;”

[0018] Application No. 63 / 620,733 entitled “PRECISION ANALOG TO DIGITAL CIRCUIT TUNED VOLTAGE AND CURRENT MODE DC-DC CONVERTER;”

[0019] Application No. 63 / 620,738 entitled “PREDICTIVE CONTROL LOOP PRECHARGING DURING A MULTI-LEVEL ZONE CHANGE;”

[0020] Application No. 63 / 620,764 entitled “DETECTOR CIRCUIT FOR DETECTINGONE OF MULTI-INPUT CONTROLLING SIGNALS THAT CONTROLS A CONTROL LOOP CIRCUIT;”

[0021] Application No. 63 / 620,607 entitled “STARTUP VOLTAGE SELECTION FOR MULTI-LEVEL POWER CONVERTER CIRCUITS;”

[0022] Application No. 63 / 620,575 entitled “MULTI-LEVEL CAPACITOR FAULT DETECTION SYSTEMS AND METHODS;”

[0023] Application No. 63 / 620,582 entitled “PARELLEL OPERATION OF MULTI¬LEVEL POWER CONVERTERS;” and

[0024] Application No. 63 / 620,763 entitled “AVERAGE AND PEAK CURRENTSENSE SYSTEMS AND METHODS.”BACKGROUND

[0025] This disclosure relates to electronic circuits, and more particularly for example to multi-level power converters.

[0026] Many electronic products, including mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD, LED displays, and the like) use multiple voltage levels for operation. For example, radio frequency (RF) transmitter power amplifiers may operate at relatively high voltages (e.g., 12V or more), whereas logic circuitry may operate at a relatively low voltage level (e.g., 1-3V) and other circuitry may operate at an intermediate voltage level (e.g., 5-10V).

[0027] Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output.

[0028] One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled switches to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. When a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it.

[0029] There is a continued need for improved circuits and methods for more effectively and efficiently operating and implementing various type of electrical circuits and devices, including for example multi-level converter circuits.SUMMARY

[0030] Embodiments of the present disclosure include systems, circuits, and methods for operating and implementing various electronics circuits, including multi-level converter circuits.

[0031] One embodiment of the present disclosure encompasses a circuit including a switched mode power supply having a first terminal configured to be coupled to a reference potential, a second terminal configured to receive input current lin from a voltage input source Vin, and a third terminal configured to source an output voltage Vout and an output current lout to a load. A current-sensitive element is configured to be coupled between the voltage input source Vin and the second terminal of the switched mode power supply; the current-sensitive element is configured to conduct input current lin to the switched mode power supply and to provide a sensing voltage related to the magnitude of input current lin. An analog to digital converter includes at least one analog terminal and a plurality of digital terminals, and is configured to provide digital representations at the plurality of digital terminals corresponding to voltages applied to the at least one analog terminal. A controller is coupled to the analog to digital converter and is configured to receive the digital representations. The controller is configured to compute an estimate of the output current lout based upon the digital representations and an efficiency factor Eff which represents an efficiency of power conversion by the switched mode power supply. In at least some of such embodiments, selection circuitry is included and configured to selectively apply to the at least one analog input terminal: (i) the sensing voltage; (ii) the voltage of the voltage input source Vin; and (iii) the output voltage Vout. In at least some of such embodiments, the controller is configured to compute the estimate of the output current lout according to the formula lout = [(Vin x Iin) / Vout] x Eff.

[0032] Another embodiment of the present disclosure encompasses a method which includes providing a switched mode power supply having a first terminal for coupling to a reference potential, a second terminal for receiving input current lin from a voltage input source Vin, and a third terminal for sourcing an output voltage Vout and an output current lout to a load. The method includes coupling a current-sensitive element between the voltage input source Vin and the second terminal of the switched mode power supply for conducting input current lin thereto. The current-sensitive element provides a sensing voltage thereacross related to the magnitude of the input current lin. The method includes converting the sensingvoltage to a digital representation of the input current lin. The digital representation of the input current lin and an efficiency factor Eff, are provided to a digital controller; efficiency factor Eff represents the efficiency of power conversion by the switched mode power supply. The method includes using the digital controller to compute an estimate of the output current lout. In at least some of such embodiments, the method includes: a) converting the voltage of the voltage input source Vin to a digital representation thereof; b) converting the output voltage Vout to a digital representation thereof; and c) providing the digital representations of the voltage of the voltage input source Vin and the output voltage Vout to the digital controller for computing the estimate of the output current lout. In at least some of such embodiments, the estimate of the output current lout is computed according to the formula lout = [(Vin x Iin) / Vout] x Eff.

[0033] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of embodiments of the present disclosure will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the appended sheets of drawings that will first be described briefly.DESCRIPTION OF THE DRAWINGS

[0034] FIG. 1A is an example power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0035] FIG. IB is an example power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0036] FIG. 2A is an example dual integrated circuit (IC) power converter circuit with internal input current sense, in accordance with one or more embodiments of the present disclosure.

[0037] FIG. 2B is an example dual IC power converter circuit with external input current sense, in accordance with one or more embodiments of the present disclosure.

[0038] FIG. 3A is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0039] FIG. 3B is an example functional block diagram of a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0040] FIG. 4 is a diagram illustrating an example charging function in step down regulation mode of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0041] FIG. 5 is a diagram illustrating an example charging function in step down divide by 3 charge pump mode, in accordance with one or more embodiments of the present disclosure.

[0042] FIG. 6 is a functional block diagram illustrating aspects of an example power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0043] FIG. 7 is a block diagram illustrating an example system implementing a power converter circuit, in accordance with one or more embodiments of the present disclosure.

[0044] FIG. 8A is a circuit diagram illustrating an example 3-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0045] FIG. 8B is a circuit diagram illustrating an example 4-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0046] FIG. 8C is a circuit diagram illustrating an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0047] FIG. 9 is an example M-level converter circuit, in accordance with one or more embodiments of the present disclosure.

[0048] FIG. 10 is a block diagram of an example embodiment of control circuitry for an M-level converter cell, in accordance with one or more embodiments of the present disclosure.

[0049] FIG. 11 is a block diagram of a circuit including components used in estimating the output current lout supplied to a load by a switched mode power supply based upon the input current lin drawn into the switched mode power supply from an input voltage source Vin, in accordance with one or more embodiments of the present disclosure.

[0050] FIG. 12 is a flowchart illustrating a method of calculating the estimate for output current lout, in accordance with one or more embodiments of the present disclosure.

[0051] FIG. 13 is a simplified block diagram showing a Hall effect sensor used to provide a voltage representing the input current lin drawn into the switched mode power supply from input voltage source Vin, in accordance with one or more embodiments of the present disclosure.

[0052] FIG. 14 is a simplified block diagram showing the use of a switching MOSFET device in the upper level of a multi-level power converter circuit to provide a voltage representing the input current lin drawn into the multi-level power converter circuit from input voltage source Vin, in accordance with one or more embodiments of the present disclosure.

[0053] FIG. 15 is a block diagram similar to FIG. 11 but showing the switched mode power supply operated in Boost mode, in accordance with one or more embodiments of the present disclosure.

[0054] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It is noted that sizes of various components and distances between these components are not drawn to scale in the figures. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.DETAILED DESCRIPTION

[0055] The present disclosure encompasses novel circuits, architectures, systems, and methods that more effectively and efficiently address the configuration and operation of multilevel converter circuits. It will be appreciated that various improvements disclosed herein encompass innovative circuits, hardware components, architectures, and related logic that are applicable to applications beyond multi-level converter circuits.

[0056] FIGs. 1 -6 illustrate various embodiments of a high efficiency 4-level step-down and step-up power converter for battery charging applications, such as single cell Li-ion and Li- polymer battery applications. In the illustrated embodiments, the power converter is configured to deliver up to 5 amperes (A) of charging current in regulation mode and in a divide-by-3 charge pump mode, though other configurations are within the scope of the present disclosure.The power converter can be configured, for example, into dual ICs operation for 9A charging current in regulation mode and in divide-by-3 charge pump mode. Although a 4-level power converter is illustrated, it will be appreciated that the embodiments described herein may be applicable to various M-level implementations, where M >= 3.

[0057] In some implementations, for example, the power converter may supply an input range of approximately 4.5 V to 18 V input to support both universal serial bus (USB) and wireless inputs, and in a reverse step-up mode, the output may be programmable from 4.8 V to 16 V in 100 mV step with a programmable output current limit up to 1.7 A. This input voltage range may be used, for example, to support fast charging of single Li-Ion cells from USB and wireless input. It will be appreciated that other voltage and current ranges and limits may be implemented depending on the application. It will also be appreciated that while compatibility with USB is described herein, other wired interfaces and protocols may be implemented with the power converter of the present disclosure.

[0058] In various embodiments, the power converter may be implemented as a single integrated circuit (IC) (see, e.g., Figs. 1A-B), dual-integrated circuits (see, e.g., Figs. 2A-B), or in other configurations depending on the implementation. In various embodiments, the power converter may operate as a parallel charger along with a main charger, as shown in Fig. 3B, to provide the desired functionality noted herein and, for example, as illustrated in Figs. 4 and 5 for the desired charging functionality for various applications, as would be understood by one skilled in the art. Fig. 3B may represent a system level point of view of a mobile architecture having a parallel charger and a main charger that accepts power from a wired port (e.g., a wired USB) or from a wireless interface. The parallel charger for one or more embodiments may represent an IC as illustrated in Figs. 1-3 A, for example, and may function to charge a battery for some portion of the charging profile (e.g., as shown in Figs. 4 and 5), while the main charger charges the battery for other portions of the charging profile. In various embodiments, the parallel charger may also be configured to function as the main charger as well, depending upon the desired application. The novel architecture disclosed herein may be implemented to enable (i) improved efficiency (e.g., at 9 A charging current) in a low -profile solution; (ii) low electromagnetic interference (EMI) fixed-frequency operation under heavy load conditions; (iii) input and output current and voltage, IC temperature monitoring and telemetry via interintegrated circuit (EC) technology; and / or (iv) full protection including input and output under voltage lockout (UVLO), input and output over voltage protection (OVP), input and outputover current protection (OCP), and IC over- temperature with fault and warning status. In some implementations, the power converter supports divide-by-3, step-down and step-up regulating modes, dual external disconnect switch control, and / or paralleled operation.

[0059] In the illustrated embodiments, the power converter is implemented as a multi-level charge pump incorporating power switches and control circuitry. The power converter’s internal bias may be provided by the system battery through a VOUT connection (e.g., pin). The charging input can be USB (or other wired input) or wireless input by an external FET register control. In some implementations, the power converter may be programmed to different operating modes, which may include a step-down regulation mode, a step-down divide-by-3 charge pump mode, and a reverse step-up mode.

[0060] In a step-down regulation mode, the power converter operates as a multi-level stepdown regulator to support USB power delivery (USB-PD) (or other wired protocol) or fixed input charging. During a constant-current (CC) phase, the maximum charging current may be limited for example, by configuring registers. When the input current does not reach a predetermined maximum input setting, the charge current is set to a predetermined maximum output setting. If the input current reaches the input maximum setting, then the charge current throttles and maintains input current at the input maximum setting. This allows maximum charging current while ensuring that the charge current does not go above a battery maximum current rating and the input current does not trip adapter over-current protection.

[0061] During a constant- voltage (CV) phase, the CV regulation may be limited, for example, by configuring registers. In operation, a single-wire sense pin or other sensor is configured to sense the output voltage VOUT, which is compared to a predetermined value stored in a register, VOUT_REG. The voltage differential between the battery’s positive terminal and negative terminal is sensed and compared to a predetermined value stored in a register, VBATT_REG. In some implementations, a single-wire sense pin or other sensor senses VBATTP (battery voltage at positive terminal) and a single-wire sense pin or other sensor senses VBATTN (battery volage at negative terminal). The CV regulates to the lower of the two settings. If the VOUT sensed voltage reaches VOUT_REG first, then CV is regulated to VOUT_REG. If the VBATTP sensed voltage reaches VBATT_REG first, then CV is regulated to VB ATT_REG. This provides a fast battery top off while preventing voltage above safety limit.

[0062] In a step-down divide-by-3 charge pump mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a divide- by-3 step-down charge divider to support USB-Programmable Power Supply (USB-PPS) or other charging protocol or programmable input charging. In some embodiments, the power converter allows the USB-PPS adapter to control voltage and current and ignores conflicting settings (e.g., settings stored in registers for IOUT_MAX, VOUT_REG and VBATT_REG). In this mode, the power converter monitors an IIN_MAX setting, shuts down the power train (which includes switches to configure, enable and disable various modes of operation) and disconnects external FET when IIN current exceeds IIN_MAX setting. In the illustrated embodiment, the output current is up to 10A in dual IC operation and 5 A in single IC operation.

[0063] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register) the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired protocol or standard) or wireless input. The power converter draws power from the system battery and regulates VIN to the VOUT_REG programmable setting of 4.8V to 16V. The VIN output current limit may be set, for example, by an IIN_MAX register.

[0064] In some embodiments, to enable the IC, both an EN pin and an IC_EN bit are set to logic high (1). When either the EN pin or IC_EN bit is set to logic low (0), the IC is disabled. After the IC is enabled, the FOR status bit sets to 1 to indicate the IC has a fresh power up.

[0065] In some embodiments, the power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs may be controlled by registers (e.g., 1-bit registers V_EXTG, EXTG_EN and EXTGX). The V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V, in the illustrated embodiment. The EXTGX bits select which FET(s) to turn on. The EXTG_EN bit enables the gate driver to turn on the selected FET(s). In various embodiments, the external FET can be turned on or off independently from other IC operations except when the IC is disabled. The EXT_EN_IND status bit set to 1 when external FET is enabled. When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT! or EXT2 detects an OVP, then the respected FET would not turn on from the off mode.

[0066] In various embodiments, the power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path may be configured between the external FET on time and the power train on time to minimize in-rush current. Next, both PT_EN pin and PT_EN bit are set to logic high (1) to turn on the power train. When either PT_EN pin or PT_EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train may be configured to turn on first before the master IC. The COMP, SYNC and SYNCH pins from two ICs gate the power train and synchronize the operation. The SYNC_SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down the power train operation when fault is detected.

[0067] In a reverse step-up mode (which may be selected, for example, by setting a corresponding register), the power converter is configured as a multi-level step-up regulator to power peripheral device(s) connected to USB (or other wired port) or wireless input. The power converter draws power from the system battery and regulates VIN pin to a VOUT_REG programmable setting of 4.8V to 16V. The VIN output current limit is set by IIN_MAX register.

[0068] To enable the IC, both the EN pin and IC_EN bit are set to logic high (1). When either EN pin or IC_EN bit is set to logic low (0), the IC is disabled. After the IC enables, the POR status bit sets to 1 to indicate the IC has a fresh power up. The power converter provides a gate driver to control two external N-channel MOSFETs and sense inputs to monitor source input voltage at each FET. The external FETs are controlled by register bits, such as V_EXTG, EXTG_EN and EXTGX. The V_EXTG bit sets the gate drive voltage and can be set to 9V or 5V, for example. The EXTGX bits select which FET(s) to turn on. The EXTG_EN bit enables the gate driver to turn on the selected FET(s). The external FET can be turned on or off independently from other IC operation except when the IC is disabled. The EXT_EN_IND status bit set to 1 when external FET is enabled.

[0069] When a fault is detected and triggers a shutdown, the external FET may be turned off automatically. If EXT1 or EXT2 detects an OVP, then the respective FET would not turn on from off mode. The power train is enabled after all the registers have been initialized and the target input external FET is turned on. Sufficient time based on capacitance on the power path should be given between external FET on time to power train on time to minimize in-rush current. Next, both PT_EN pin and PT_EN bit are set to logic high (1) to turn on the powertrain. When either PT_EN pin or PT_EN pin is logic low, the power train is off. In dual IC operation, the slave IC power train is turned on before the master IC. The COMP, SYNC and SYNCH pins from the two ICs gate the power train and synchronize the operation. S YNC_SEL pin sets the IC to master mode or slave mode. IC internal fault and programmable fault detection shuts down power train operation when a fault is detected.

[0070] In accordance with various embodiments, an example power converter initialization, an example power up sequence, and an example fault handling will now be described for the three different operating modes. In an example step-down regulation mode, the initialization and power up sequence uses EXT1 as an example. The same sequence may apply to EXT2 with the only change in EXTGX bit and related EXT2 register settings. First, pull EN to logic high and then set IC_EN bit=l at lOOus(TBD) after EN is logic high to enable IC. IC startup from POR stage, POR bit reports 1 indicating fresh IC startup. Next, the POR bit is read to confirm the IC is enabled. The FREQUENCY register is then set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT_REG register is set to the target regulation voltage on the VOUT sense pin in CV operation. The VBATT_REG register is set to the target regulation voltage on the VBATTP sense pin in CV operation. The IOUT_MAX register is set to the target maximum charger current in CC operation, and the IIN_MAX register is set to a value below the adapter current limit. Next, the FAULT and WARNING registers was set to a desired setting. Each Fault and Warning enables at a different time based on IC status and operating mode. The WATCHDOG register is then set to a desired setting.

[0071] The MODE register and other related registers are set for step-down regulation mode, including power train setup and enablement of an external FET, while checking for faults. In a dual IC operation, the external FETs are controlled by the master IC. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the external FET after the shutdown fault is initiated. Next, the power train is enabled. In a dual IC operation, the slave IC power train is turned on before the master IC. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation.

[0072] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), an externalFET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0073] An example step-down divide-by-3 power converter mode initialization and power up sequence will now be described. The initialization and power up sequence uses EXT1 as an example, but it will be appreciated that the same sequence applies to EXT2 with a change in EXTGX bit and related EXT2 register settings. The EN is pulled to logic high and then IC_EN bit=l at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from POR stage, POR bit reports 1 indicating fresh IC startup. The POR bit is read to confirm the IC is enabled. The FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The IIN_MAX register is set to a value below the adapter current limit. VOUT_REG, VBATT_REG and I0UT_MAX registers are not used in step-down divide-by-3 charge pump mode. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. The FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at different time based on IC status and operating mode.

[0074] The MODE register and other registers are set for step-down divide-by-three mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter.

[0075] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault.

[0076] An example reverse step-up mode initialization and power up sequence will now be described. This initialization and power up sequence uses EXT2 as an example, but the same sequence applies to EXT1 with the change in EXTGX bit and related EXT1 register setting. The value EN is pulled to logic high and then IC_EN bit is set to 1 at lOOus(TBD) after EN is logic high to enable IC. The IC starts up from the POR stage, and the POR bit reports 1 indicating a fresh IC startup. The POR bit is read to confirm the IC is enabled. Next, the FREQUENCY register is set to a desired setting. In dual IC operation, both ICs are set to the same frequency setting. The VOUT_REG register is set to the target regulation voltage at VIN. Next, the IIN_MAX register is set to the target current limit. VBATT_REG and I0UT_MAX registers are not used in reverse step-up mode. FAULT, WARNING, and WATCHDOG registers are set to desired settings. Each Fault and Warning enables at a different time based on IC status and operating mode.

[0077] The MODE register and other registers are set for reverse step-up mode, including power train setup and external FET setup, while checking for faults. If a fault (e.g., OVP event) is detected, then a shutdown register may be set to “1” to indicate a fault shutdown event and a sequence to enable the power train or external FET, as appropriate, after the shutdown fault is initiated. Next, the power train is enabled. After the power train is enabled, a bit may be set to indicate that the power train is ready and charging the battery. In some embodiments, a watchdog timer may be set to periodically check the IC status during charging operation. Voltage and current regulation in step-down divide-by-3 charge pump mode may be controlled by the PPS adapter. In dual IC operation, the slave IC power train is turned on before the master IC and is controlled by the master IC.

[0078] If a fault event is detected, then the IC determines which faults events were triggered, such as the power train may be set to enable but it is off due to fault(s), or an external FET is set to enable but the FET is off due to fault(s). The shutdown procedure may include resetting register values and repeating setup steps of enabling the power train, external FET, or other component that is disabled due to a fault. The EXT2 or VIN pins are not configured to detect OVP as it is set as the output in reverse step-up mode. But if EXT2 or VIN pin detects an OVP event, then IC_STATUS1 and IC_STATUS2 would report the fault event.

[0079] In an example system 700 illustrated in FIG. 7, a power converter 720 is implemented in a host 710 (e.g., a device or system) that includes a battery 730 and various system components 740. The host 710 may be any system or device that implements a powerconverter as described herein, including but not limited to a smart phone, tablet, portable electronics, a mobile device, low power electronics, and other electronic systems. The battery 730 may include one or more batteries that store electricity for use by the host 710, such as single cell Li-ion and Li-polymer batteries.

[0080] The power converter 720 may be configured to convert electricity stored in the battery 730 to a desired system voltage, VSYS, for powering various system components 740, which may include one or more logic devices 742, memories 744, communications components 746, input / output (I / O) components 748, circuitry 750, and other components 752. The power converter 720 may also supply power to one or more external devices 760, such as a component connected to the host 710 through a wired or wireless connection, such as a USB compatible device. The power converter 720 may also be configured to receive power from an external power source 712 and convert the received power to the battery 730 for storage, or to the system components 740 and / or external device 760, as applicable.

[0081] In various embodiments, the one or more logic devices 742 and memories 744 may be configured to perform operations of the host 710. A logic device 742 may be implemented as a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), or other programmable logic device(s). The logic device 742 and other components may be configured through hardwiring, software execution, or a combination of both. In various embodiments, the host 710 includes one or more memory devices designed to retain data, such as software instructions for execution by the logic device. The memory may include volatile and non-volatile memories, such as randomaccess memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), non-volatile randomaccess memory (NVRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically-erasable programmable read-only memory (EEPROM), flash memory, hard disk drives, or other memory types. The logic device may be configured to execute software instructions residing in the memory, thereby accomplishing method steps and operations.

[0082] Referring to FIGs. 8A-8C, the converter circuit may be configured to switch between two or more switch states. One or more PWM duty cycle controllers may be provided to set the time in each switch state based on the voltage at VOUT. For example, FIG. 8 A is a schematic diagram of a 3 -level DC-to-DC buck converter circuit 800 that may be used as theconverter circuit 920 of FIG. 9. A set of four switches, S1-S4, is series-coupled between VIN and circuit ground. A fly capacitor Cl is coupled in series with switches S3 and S4, and in parallel with switches SI and S2. An inductor LI is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and the voltage across the output capacitor COUT is VOUT.

[0083] In the illustrated example, the presence of the single fly capacitor Cl in the converter circuit 800 enables four switch states that each generate one of three voltage levels at node Lx. In a first switch state, S2 and S4 are closed and SI and S3 are open, effectively bypassing Cl and connecting Lx to circuit ground (voltage level at Lx = GND). In a second switch state, S2 and S4 are open and SI and S3 are closed, effectively bypassing Cl and connecting Lx to VIN (voltage level at Lx = VIN). In a third switch state SI and S4 are open and S2 and S3 are closed, connecting Cl from VIN to LX, and thus charging Cl with inductor LI current flowing into a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2. In a fourth switch state, SI and S4 are closed and S2 and S3 are open, connecting Cl from Lx to GND and thus discharging Cl with inductor LI current flowing to a load. The voltage across Cl will be about VIN / 2 and the voltage level at Lx will also equal about VIN / 2 (e.g., this may assume that Cl was previously charged in state three). Accordingly, the illustrated converter circuit 800 has two switch states that generate a voltage level of VIN / 2 at the Lx node.

[0084] If the converter circuit 800 is toggled between switch states three and four (avoiding switch state two that bypasses the fly capacitor Cl), the inductor LI sees small jumps in the voltage level at Lx, going from GND to only VIN / 2 and back to GND, which results in reduced voltage ripple across the inductor LI and less filtering to smooth VOUT than a converter circuit with only SI and S2 switches.

[0085] Adding additional series switches Sx and fly capacitors Cx to the 2-level converter circuit 800 increases the number of switch states and resulting voltage levels between VIN and circuit ground that can be applied to the Lx node, thus generating an even smaller voltage ripple across the inductor L. This reduces the filtering requirements to get a smooth output voltage. For example, a 4-level DC-to-DC buck converter circuit (see, e.g., FIG. 8B) includes 6 series- coupled switches SLS6 and two fly capacitors Cx (X = 2). Consequently, a 4-level converter circuit can define 4 voltage levels (VIN, GND, 'AVIN, and AVIN) at node LX from 8 switch states (3 switch states result in the AVIN level at Lx, and 3 other switch states result in the%VIN level at Lx). For some applications, VOUT is set low enough that the voltage level at node Lx alternates between GND and the next higher voltage level available. For higher output voltages, the switching pattern may never use GND. For example, in a 4-level converter circuit, an output VOUT set to 0.5*VIN can be achieved by alternating the Lx node between % VIN and ' V.

[0086] A different interpretation of a multi-level converter circuit is that the fly capacitors Cx create a charge-pump for the buck converter circuit. Unlike a standard charge-pump where the output is restricted to one output, a multi-level converter circuit allows the fly capacitors Cx to be coupled to create multiple intermediate voltages. For the 4-level example, the two fly capacitors each act as a ! charge-pump with the additional benefit that any input voltage that is a sum of !4 ratios can be created, including VIN and GND.

[0087] A multi-level converter circuit couples the fly capacitors Cx in different combinations in order to bring the voltage level at the Lx node down or up. As noted above, when a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it, which creates a control problem in maintaining an average voltage.

[0088] Resolving the charge-balance problem so as to maintain an average voltage across the single capacitor in a 3 -level converter circuit will now be described. For example, in a 3- level converter circuit, one way to generate the Level- 1 (GND) and Level-3 (VIN) voltage levels at the Lx node is to not use the fly capacitors Cl for these Lx voltage levels. However, for the Level 2 (VIN / 2) voltage level at Lx, two separate switch states can be used: one switch state charges the capacitor (S3 and S2 closed, SI and S4 open) and the other switch state discharges the capacitor (S3 and S2 open, SI and S4 closed). The control of a 3-level converter circuit may operate such that each time the converter circuit switches states to Level-2, a controller can alternate between charging and discharging the single capacitor to maintain its voltage. A voltage comparator can be used to monitor the capacitor to help decide on a charging state or a discharging state. For instance, if the capacitor voltage is below VIN / 2, then a controller would select charge (the third switch state), and if the capacitor voltage is above VIN / 2, then the controller would select discharge (the fourth switch state).

[0089] Referring to FIGs. 8B, a 4-level converter circuit 830 (X = 2) illustrates the chargebalance difficulty when more capacitors are present. A Level- 1 voltage level (GND) and aLevel-4 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level ( / a VIN) and Level-3 voltage level (% VIN) at Lx each can be achieved by any of three different switch states. At higher orders of a multi-level converter circuit (X > 2), more switch states are possible for generating the intermediate levels between VIN and GND. The problem gets more complicated with a 5 -level converter circuit (X= 3). A Level- 1 voltage level (GND) and a Level-5 voltage level (VIN) at the Lx node are each determined by a single switch state. However, the Level-2 voltage level CAVIN) and Level-4 voltage level (3A VIN) at Lx each can be achieved by any of four different switch states, the Level-3 voltage level (2 / 4 VIN) at Lx can be achieved by any of six different switch states.

[0090] As should be clear from these examples, determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. As previously noted, most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of switch states generally assume that all system variables - such as input voltage and output current - are constant during the sequence. This is unrealistic for a real- world environment, where all system variables tend to be dynamic.

[0091] In a 2- Level example, the converter circuit switches between two switch states: SI closed and S2 open (voltage level at Lx = VIN), or SI open and S2 closed (voltage level at Lx = GND). A PWM duty cycle controller sets the time in each switch state based on the voltage at VOUT, which determines the amplitude of the average voltage at Lx (noting that, the average Lx voltage in theory is equal to the VOUT average voltage, but that, due to parasitics, the Lx average voltage is higher and / or lower (for negative currents) than the VOUT average). As can be appreciated, the inductor L sees large jumps in the voltage level at Lx, from GND to VIN and back to GND. The resulting voltage ripple across the inductor L necessitates a significant amount of filtering to smooth VOUT.

[0092] An alternative way of reducing the voltage ripple across the inductor L is to add more series switches as well as charge transfer capacitors as energy storage elements to transfer charge from VIN to VOUT. As noted above, such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors” and may be external components coupled to an integrated circuit embodiment of a converter circuit. The presence of X fly capacitors Cx defines a multi-level capacitive converter circuit capable of generating M - X + 2 voltage levels at node Lx from 2(X+i}switch states.

[0093] FIG. 8C is schematic diagram of a generalized Af-level multi-level converter cell 870 that may be used as the converter circuit 920 of FIG. 9. A set of switches, S 1 -S[ 2*(M - 1)], is series-coupled between VIN and circuit ground. The set of switches are organized in switch pairs: SI & S2, S3 & S4, ... S[2*(M - 2)+l] & S[2*(M- 1)]. A set of M - 2 fly capacitor Cx is coupled in series with certain respective switches, and in parallel with switches in between those switches. In terms of switch pairs, there are M - 1 pairs of switches, or one more than the number of fly capacitors. An optional inductor L is coupled to an output capacitor COUT and to a node Lx between switches SI and S2, and again the voltage across the output capacitor COUT is VOUT- The inductor L doubles as a virtual current source that facilitates movement of charge between the fly capacitors Cx. This creates a very efficient form of charge transfer, but introduces the problem of charge-balancing the fly capacitors Cx.

[0094] In various embodiments, each fly capacitor Cx has a first terminal coupled between an outer high-side switch S[2*x + 1] and an inner high-side switch S[2*x-1], where “high- side” refers to the VIN side of the converter circuit. Each fly capacitor Cx has a second terminal coupled between an outer low-side switch S[2*x + 2] and an inner low-side switch S[2*x], where “low-side” refers to the circuit ground (GND) side of the converter circuit. Thus, for an M - 3 multi-level converter cell, a first terminal of the single (X - 1) fly capacitor Cl would be coupled between outer high-side switch S3 and inner high-side switch SI, and a second terminal of the capacitor Cl would be coupled between inner low-side switch S2 and outer low-side switch S4. Accordingly, each fly capacitor Cx within the multi-level converter cell 870 has four switches that can affect current flow through that fly capacitor Cx.

[0095] In some embodiments, a voltage detector, which may be a simple comparator-type circuit, is provided to sense the voltage across a corresponding fly capacitor Cx with respect to a reference voltage, VREF, which represents a desired target voltage for the fly capacitor Cx. Every fly capacitor Cx may have a target average voltage in order to maintain proper output level. For an M-level converter and capacitor Cx, where x = 1, 2, ... [M - 2], its target voltage is:Vtarget

[0096] The voltage detector may be configured to output a HIGH / LOW status signal, CFX_H / L, indicating with the voltage across the corresponding fly capacitor Cx is greater thanVREF or less than VREF. The CF _H / L status signal is coupled to control circuitry for the switches associated with the fly capacitor Cv.

[0097] The control circuitry for the four switches that can affect current flow through a fly capacitor Cx set states for those switches in part as a function of the voltage across the fly capacitor Cx as measured by the associated voltage detector and conveyed by the CFV_H / L status signal. Accordingly, for ease of understanding, it can be said that each fly capacitor Cx “controls” its own pairs of high-side and low-side switches. If it is assumed that current flow in the inductor is charging the output VOUT, there are four possible states that can be defined for the pairs of high-side and low-side switches for each fly capacitor Cx.

[0098] In a switch state in which the outer high- side and inner low- side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a charging configuration (whether or not charging actually occurs may depend on the switch states for other fly capacitors Cx). In a switch state in which the inner high-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be in a discharging configuration (whether or not discharging actually occurs may depend on the switch states for other fly capacitors Cx). In a switching state in which the inner low-side and outer low-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would be bypassed. In a switching state in which the outer high-side and inner high-side switches associated with fly capacitor Cx are closed and all other associated switches are open, fly capacitor Cx would again be bypassed.

[0099] While each fly capacitor Cx can control both of its own pairs of high-side and low- side switches, in general, methods of control disclosed herein may utilize either the outer switches or the inner switches controllable by each corresponding capacitor. For example, referring to FIG. 8B, in “outer-switch” methods, fly capacitor Cl will control its outer switches S3 and S4, fly capacitor C2 will control its outer switches S5 and S6, etc. Conversely, for example, in “inner-switch” methods, fly capacitor Cl will control its inner switches SI and S2, fly capacitor C2 will control its inner switches S3 and S4, etc. The switch states of either pair (inner or outer) of switches controlled by a fly capacitor Cx may be complementary - that is, no fly capacitor Cx closes or opens both of its high-side and low-side controlled switches at the same time. If each fly capacitor Cx controls its outer-switches, then no fly capacitor controls the left-over innermost switches SI and S2. If instead each fly capacitor Cx controls its inner-switches, then no fly capacitor controls the left-over outermost switches S [ 2*(M- 1) ] and S[2*(M-2)+l]. Switch states for the left-over switches are also complementary.

[0100] FIG. 9 is a high-level block diagram of an example circuit that includes a power converter 900, in accordance with one or more embodiments of the present disclosure. In the illustrated example, the power converter 900 includes a converter circuit 920 and a controller 910. The converter circuit 920 and controller 910 may be configured to implement, for example, any of the multi-level power converter circuits as previously described with reference to FIGs. 1A-8C, and as described further herein. In the illustrated embodiment, the converter circuit 920 is configured to receive an input voltage VIN from a voltage source and transform the input voltage VIN into an output voltage VOUT. In some embodiments of the power converter 900, auxiliary circuitry (not shown), such as a bias voltage generator(s), a clock generator, a voltage control circuit, etc., may also be present and coupled to the converter circuit 920 and the controller 910.

[0101] The controller 910 receives a set of input signals and produces a set of output signals. Some of these input signals arrive along a signal path connected to the converter circuit 920. These input signals carry information that is indicative of the operational state of the converter circuit 920. The controller 910 may also receive a clock signal CLK (for synchronous converter circuits 920) and one or more external input / output signals TO that may be analog, digital (encoded or direct signal lines), or a combination of both. Based upon the received input signals, the controller 910 produces a set of control signals back to the converter circuit 920 that control the internal components of the converter circuit 920 (e.g., internal switches, such as low voltage FETs / MOSFETs) to cause the converter circuit 920 to boost or buck VIN to VOUT. In some embodiments, an auxiliary circuit (not shown) may provide various signals to the controller 910 (and optionally directly to the converter circuit 920), such as the clock signal CLK, the input / output signals I / O, as well as various voltages, such as a general supply voltage VDD and a transistor bias voltage VBIAS.

[0102] FIG. 10 is a block diagram of one embodiment of advanced control circuitry 1000 for an M-level converter cell 1000 such as the generalized version depicted in FIG. 8B. The M- level converter cell 1020 is shown coupled to an output block 1001 comprising an inductor L and an output capacitor COUT (conceptually, the inductor L also may be considered as being included within the A -level converter cell 1020). The advanced control circuitry 1000 functions as a control loop coupled to the output of the M-level converter cell 1020 and toswitch control inputs of the A -level converter cell 1020. In general, the advanced control circuitry 1000 is configured to monitor the output (e.g., voltage and / or current) of the M-level converter cell 1020 and dynamically generate a set of switch control inputs to the M- level converter cell 1020 that attempt to stabilize the output voltage and / or current at specified values, taking into account variations of VIN and output load. In alternative embodiments, the advanced control circuitry 1000 may be configured to monitor the input of the M-level converter cell 1020 (e. ., voltage and / or current) and / or an internal node of the M- level converter cell 1020 (e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the advanced control circuitry 1000 may be configured to monitor the voltage and / or current of a node (e.g. , input terminal, internal node, or output terminal) of the M-level converter cell 1020. The advanced control circuitry 1000 may be incorporated into, or separate from, the overall controller for a power converter 100 embodying the M-level converter cell 1020.

[0103] A first block comprises a feedback controller 1002, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-ON- time controller, a hysteretic controller, or any other variant. The feedback controller 1002 is shown as being coupled to VOUT from the Af-level converter cell 1020. In alternative embodiments, the feedback controller 1002 may be configured to monitor the input of the M- level converter cell 1020 and / or an internal node of the A -level converter cell 1020. The feedback controller 1002 produces a signal directly or indirectly indicative of the voltage at VOUT that determines in general terms what needs to be done in the multi-level converter cell 1020 to maintain desired values for VOUT: charge, discharge, or tri-state (i.e. , open, with no current flow).

[0104] In the illustrated example, the feedback controller 1002 includes a feedback circuit 1004, a compensation circuit 1006, and a PWM generator 1008. The feedback circuit 1004 may include, for example, a feedback-loop voltage detector which compares VOUT (or an attenuated version of VOUT) to a reference voltage which represents a desired VOUT target voltage (which may be dynamic) and outputs a control signal to indicate whether VOUT is above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

[0105] The compensation circuit 1006 is configured to stabilize the closed-loop response of the feedback controller 1002 by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller 1002. The compensation circuit 1006 may be implemented in known manner, and may include LC and / or RC circuits.

[0106] The PWM generator 1008 generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the multi-level converter cell 1020. In addition, in some embodiments, the PWM generator 1008 may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOLT and the reference voltage (thus indicating that some levels of the M-level converter cell 1020 should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., whether VOUT is greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit 1006, or from the output of the feedback circuit 1004, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUT is from a target output voltage, thus allowing faster charging of the inductor L if the VOUT is severely under regulated.

[0107] A second block comprises a multi-level controller 1010, the primary function of which is to select the switch states that generate a desired VOUT while maintaining a chargebalance state on the fly capacitors within the M-level converter cell 1020 every time an output voltage level is selected, regardless of what switch state or states were used in the past.

[0108] The multi-level controller 1010 includes a Voltage Level Selector 1012 which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector 1012 may be coupled to VOUT and / or VJN, and, in some embodiments, to the HIGH / LOW status signals, CF H / L, from the voltage detectors coupled to corresponding fly capacitors Cx within the M- level converter cell 1020. A function of the Voltage Level Selector 1012 is to translate the received signals to an output voltage Target Level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector 1012 typically will consider at least VOUT and VJN to determine which Target Level should charge or discharge the output of the M- level converter cell 1020 with a desired rate. For example, in a 6-level converter circuit, the available Target Levels are Level-1 (GND), Level-2 (1 / 5VIN), Level-3 (2 / 5VIN),Level-4 (3 / 5VIN), Level-5 (4 / 5VIN), and Level-6 (VIN), which may be represented as a count value from 1-6 (or 0-5).

[0109] As an example, in a 4-Level converter circuit, if VIN = 12V and VOUT nominally should be 3V, then the Voltage Level Selector 1012 may indicate that a Target Level of “2” can be selected, which results in a 1 / 3VIN voltage level at Lx i.e. , 4V). The PWM control signal sets a duty cycle between that Target Level and another Target Level (e.g., GND) so that the average voltage level at Lx will be about 3 V

[0110] In general, for steady-state operations, the Target Level voltage closest to VOUT that either charges or discharges the inductor L may be selected for simplicity of the selection algorithm. In general, for transient response, a Target Level that is higher (for charging) or lower (for discharging) than the closest Target Level may be selected to quickly charge or discharge the inductor L. The Voltage Level Selector 1012 may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. In some embodiments, the Voltage Level Selector 1012 can implement advanced methods (described below) that try to speed up charging or discharging based on additional factors, such as inductor voltage drop, load transients, the magnitude of output deviations, and / or external input signals from external sources. The output of the Voltage Level Selector 1012 may include duty cycle information (e.g., derived from the input PWM control signal) as well as switch state.

[0111] The output of the Voltage Level Selector 1012 is coupled to a Multi-Level Switch State Selector 1014, which generally would be coupled to the status signals, CFT_H / L, from the voltage detectors for the fly capacitors Cx. Taking into account the Target Level generated by the Voltage Level Selector 1012, the Multi-Level Switch State Selector 1014 determines a pattern of switch states for the desired output level that generally achieves charge-balancing the fly capacitors Cx. The Multi-Level Switch State Selector 1014 may be implemented, for example, as comparison circuitry and combinatorial logic, as a look-up table (LUT), or as more generalized processor circuitry. The output of the Multi-Level Switch State Selector 1014 is coupled to the switches of the multi-level converter cell 1020 (through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes a pattern of switch state settings determined by the Multi-Level Switch State Selector 1014. The pattern of switch state settings selects the configuration of the switches within the multi-level converter cell 1020.

[0112] In general (but not always), for PWM-based control systems, the Voltage Level Selector 1012 and the M-level Switch State Selector 1014 only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector 1012 selects which level results in charging of the inductor L and the M-level Switch State Selector 1014 sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector 1012 selects which level can discharge the inductor L and the AMevel Switch State Selector 1014 sets which version of that level to use. Thus, the Voltage Level Selector 1012 and the Af-level Switch State Selector 1014 generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signal to change the state of the Voltage Level Selector 1012. Further, there may be situations or events where it is desirable for the CF _H / L status signal(s) to cause the Af-level Switch State Selector 1014 to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the M- level Switch State Selector 1014 to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

[0113] One notable benefit of the control circuitry shown in FIG. 10 is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

[0114] In alternative unregulated charge-pumps embodiments, the feedback controller 1002 and the Voltage Level Selector 1012 may be omitted, and instead a clock signal CLK may be applied to the M- level Switch State Selector 1014. The M-level Switch State Selector 1014 would generate a pattern of switch state settings that periodically charge balances the fly capacitors Cx regardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VIN changes or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors Cx.

[0115] In some embodiments, the M-level Switch State Selector 1014 may take into account the current II flowing through the inductor L by way of an optional currentmeasurement input 1016, which may be implemented in conventional fashion.

[0116] In an M-level multi-level converter circuit, the configuration of switches that achieves Level- 1 (e.g., GND) or Level-Af (e.g., VIN) effectively bypasses the fly capacitors Cx. Conversely, for all intermediate voltage levels, at least one fly capacitor Cx is coupled to VOUT and there are always at least two configurations of switches that can achieve any intermediate voltage level. For any particular intermediate voltage level, at least one configuration of switches results in charging the associated fly capacitor and at least one other configuration of switches results in discharging the associated fly capacitor. One aspect of the present disclosure is the realization that any achievable output voltage VOUT requiring intermediate voltage levels can be attained by dynamically selecting patterns of switch configurations - that is, by selecting switch configurations without regard to or memory of the switch configurations of any previous switching cycle - to select appropriate Levels, and doing so in a way that purposefully selects either charging or discharging switch configurations that also balance charge across the fly capacitors Cx.

[0117] Embodiments of the disclosure use the following approach for positive inductor L current (charging VOUT):(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer high-side switch in outer-switch control methods, or the inner low-side switch for inner-switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer low-side switch for outer-switch control methods, or the inner high-side switch for inner-switch control methods).

[0118] For negative inductor L current (discharging VOUT), the selection of switches inverts. Accordingly:(1) a fly capacitor Cx that needs charging will be set to close its charging switch (the outer low-side switch in outer-switch control methods, or the inner high-side switch for inner- switch control methods); and(2) a fly capacitor Cx that needs discharging will be set to close its discharging switch (the outer high-side switch for outer-switch control methods, or the inner low-side switch for inner-switch control methods).

[0119] Note again that whether or not charging actually occurs for a particular fly capacitor Cx generally depends on the switch states for all other fly capacitors. For a fly capacitor C(x) to actually charge or discharge, the next inward (if one exists) fly capacitor C(x-1 ) (for outer-switch control methods) or the previous outward (if one exists) fly capacitor C(x+7) (for inner- switch control methods) must be set to the opposite state (i.e., discharge or charge) so that a bypass situation does not occur.

[0120] For any multi-level converter circuit of order M that can create M voltage levels - i.e., Level- 1 (e.g., GND) through Level -A (e.g., VIN) - then the following switch count rules apply for any Level-m:(1) M - m low-side switches must be set to be closed (ON);(2) m - 1 high-side switches must be set to be closed (ON); and(3) switches that are not required to be ON must be set to be OFF (open).

[0121] With these switch count rules in mind, the following generalized capacitor control method applies for each state change of the Multi-Level Switch State Selector 1014:Step 1) Select a fly capacitor that has not previously been selected;Step 2) If the voltage of the selected fly capacitor is above its Vtarget and there are remaining (i.e., not been set by this method in this cycle) low-side or high-side switches that can be set to be closed to enable a discharge path for the selected fly capacitor, then set those switches that enable a discharge path for the selected fly capacitor to be closed, decrement one or more appropriate counters (e.g. , for the number of low-side switches set to be closed and the number of high-side switches set to be closed), and flag the current fly capacitor as “done” (i.e. , as having been selected); otherwise (since the voltage of the selected fly capacitor is below its Vtarget) set the switches that enable a charging path for the selected fly capacitor to be closed and flag the current fly capacitor as “done”;Step 3) Loop to Step 1 until all fly capacitors have been selected;Step 4) For the remaining pair of left-over switches, set the high-side switch or the low-side switch to be closed based on the switch count rules and the counter values.

[0122] With the above generalized capacitor control method, more specific multi-level charge-balancing control methods can be created. Examples can be found, for example, in U.S. Patent Publication No. 20230148059, which is incorporated by reference herein in its entirety.

[0123] Fig. 11 shows a switched mode power supply 1108. Switched mode power supply 1108 may be, for example, a buck converter or a multi-level power converter of the type described above in Fig. 8A through Fig.10. As will be explained below, switched mode power converter 1108 may also be operated as a boost converter with minor modifications. Switchedmode power supply 1108 has a first terminal coupled to a reference potential, e.g. ground potential. It also includes a second terminal for receiving input current lin from a voltage input source Vin 1100. It further includes a third terminal configured to source an output voltage Vout and an output current lout to a load 1124 on node 1122. As shown in Fig. 11, the third terminal of switched mode power supply 1108 is coupled to output node 1122 by inductor 1110, and a capacitor 1120 extends from node 1122 to ground.

[0124] In instances wherein load 1124 is a re-chargeable battery, and switched mode power supply 1108 is being used to charge the battery, it is highly desired that the output current lout be monitored to protect the battery. For example, to properly protect the battery, the output current lout should not be allowed to exceed a maximum threshold value. The most direct approach to monitoring output current lout is to directly measure the output current lout. However, previous efforts to provide accurate output current lout sensing have introduced problems such as decreased power converter performance, and increased bill of materials.

[0125] In the present invention, the output current lout for a multi-level converter or other switched mode power supply is approximated in a manner that does not materially affect the power converter performance, and does not increase the bill of materials.

[0126] The average output current lout is approximated from the input voltage Vin, the output voltage Vout, and by measuring an average input current lin, multiplied by an efficiency factor Eff of the system. The mathematical formula used to approximate output current lout is lout — [(Vi„ X Iin) / Vout] X Eff wherein Vin is the voltage of the voltage input source 1100; lin is the input current sourced to switched mode power supply 1 108;Vout is the output voltage sourced by the third terminal of switched mode power supply 1108 to the load; andEff represents the efficiency (expressed as a percentage) of power conversion by switched mode power supply 1108.

[0127] In one example, the multi-level power converter, or other switched mode power supply, has an efficiency Eff of 95% with a percentage error of between 1 to 2 %. It should benoted that the efficiency factor Eff could be affected by correction factors which may increase or decrease the efficiency percentage, such as inductor loss, switching frequency, and the temperature of the integrated circuit. Approximation of output current lout is sufficient if the error is within an acceptable tolerance. In one example, if the output current lout accuracy required is 5%, and the accuracy of the measured input current lin is within 2%, then as long as the error in approximating output current lout is less than 3%, the approximation of output current lout will still be within the 5% accuracy requirement.

[0128] Still referring to Fig. 11, the input current lin sourced by voltage input source Vin 1100 is passed through a current- sensitive element 1104, shown in Fig. 11 as being a resistor. However, as will be explained below, current sensitive element 1104 could also be a Hall effect device or a MOSFET device. The purpose of resistor 1104 is to provide a sensing voltage that is dropped across the opposing ends of resistor 1104. This sensing voltage may then be used to generate a digital representation of input current lin. Resistor 1104 may either be fabricated on the same integrated circuit as has been described above, or resistor 1104 may be an external resistor coupled to designated pins of the integrated circuit.

[0129] Sensing resistor 1104 is coupled between nodes 1102 and 1104, i.e., between voltage input source Vin 1100 and the second terminal of switched mode power supply 1108. Current sensing resistor is configured to conduct input current Im to switched mode power supplyl l08 and to provide a sensing voltage across nodes 1102 and 1106 that is related to the magnitude of the input current Im.

[0130] Shown in Fig. 11 is a multiplexer 1125 which can select one of several voltage sources for communication to an analog to digital converter 1126. Fig. 11 conceptually shows that one of the voltage sources that can be selected by multiplexer 1125 is the differential sensing voltage provided across sensing resistor 1104 by nodes 1102 and 1106. However, sensing resistor 1104 is typically selected to be a very low ohmic resistor to avoid significant power losses across such resistor. Since resistor 1104 has a low ohmic value, the sensing voltage dropped across resistor 1104 is also relatively small; therefore, the sensing voltage dropped across resistor 1104 requires amplification before being selected by multiplexer 1125 for presentation to analog to digital converter 1126. Such amplification may be provided, for example, by a differential amplifier which receives the sensing voltage developed across resistor 1104, and which provides an amplified differential output voltage based upon such sensing voltage. In addition, the voltage at node 1102 is the voltage input source Vin, whilethe voltage node 1106 is just slightly below the voltage input source Vin. The voltage input source Vin may vary widely, and may range, for example, between approximately 4.5 V up to 18 V. Thus, the voltages at nodes 1102 and 1106 can potentially be at or near 18 V, i.e., in an upper voltage domain. In contrast, the components used to form multiplexer 1125 and analog to digital converter 1125 may be relatively low voltage, small geometry devices intended to operate in a lower voltage domain. Accordingly, the signals provided by the differential amplifier may require level shifting from the higher voltage domain to the lower voltage domain before being selected by multiplexer 1125 to analog to digital converter 1126. Suitable differential amplifier and voltage level shifting circuitry for amplifying, level shifting, and buffering the sensing voltage are described in related patent application No. [Attorney Docket #: 61658.32PV01] being filed concurrently herewith and entitled “Fully Differential Level Shift In A Noisy Environment”, the contents of which are hereby incorporated by reference.

[0131] Still referring to Fig. 11, voltage input source Vin is shown as an input to the Vin Sensor block 1130 which senses the voltage of voltage input source Vin. The output of Vin Sensor Block 1130 is provided as an input to multiplexer 1125. Once again, the voltage of voltage input source Vin may range up to 18 V. For the same reasons explained above regarding the sensing voltage developed across resistor 1104, it may be desired to level shift and buffer the voltage received by Vin Sensor Block 1130 before providing to multiplexer 1125 a voltage in the lower voltage domain representative of the actual Vin voltage in the upper voltage domain. This voltage level shifting / buffering function may be performed by Vin Sensor Block 1130, and a suitable voltage level shifting / buffering circuit is provided in the aforementioned patent application No. [Attorney Docket #: 61658.32PV01] being filed concurrently herewith and entitled “Fully Differential Level Shift In A Noisy Environment”.

[0132] Also shown in Fig. 11 is Vout Sensor block 1132 which receives the Vout voltage provided on node 1122. Vout Sensor block 1132 provides a representation of the Vout voltage to another input of multiplexer 1125. The Vout voltage is typically lower than that of Vin, and in a battery charging application, Vout will typically be similar to the voltage of the battery being charged. Thus, while level shifting of the Vout voltage into a lower voltage domain may not be required, Vout Sensor block 1132 may include circuitry for buffering or conditioning the Vout voltage before presenting a representation of the Vout voltage to multiplexer 1125.

[0133] Temperature Sensor block 1134 is also shown in Fig. 11. Temperature Sensor block contains circuitry for providing a voltage representative of the operating temperature of theintegrated circuit. As shown in Fig. 11, the voltage output by Temperature Sensor Block 1134 is presented to a further input of multiplexer 1125.

[0134] Multiplexer 1125 can be controlled to selectively apply one of its above-described input signals for transmission to analog to digital converter 1126. Analog to digital converter 1126 includes at least one analog terminal coupled to multiplexer 1125 for receiving an analog input voltage, and a series of digital output terminals. In some cases, analog to digital converter 1126 may include a pair of differential analog input terminals for receiving an incoming differential analog voltage. Analog to digital converter 1126 provides digital representations at its series of digital output terminals corresponding to analog voltages applied to its analog terminal(s). In turn, the digital representations provided by the digital output terminals of analog to digital converter 1126 are presented to corresponding digital input terminals of controller 1128. The analog input signals that can be selected by multiplexer for presentation to analog to digital converter 1126 include, without limitation: (1) a representation of the sensing voltage developed across resistor 1104; (2) a representation of the voltage input source Vin provided by Vin Sensor block 1130; (3) a representation of the output voltage Vout provided by Vout Sensor block 1132; and (4) a representation of the operating temperature provided by Temperature Sensor block 1134. Multiplexer 1125 can also be seen in the functional block diagram of Fig. 3 wherein one of several input sources (including VinRes, Vin, Vout, and Temp Sense) may be selectively coupled to the block labeled “ADC”.

[0135] Control of multiplexer 1125, and the determination of which of the various input signals is to be selected by multiplexer 1125 at any given time for presentation to analog to digital converter 1126, is managed by controller 1128. Controller 1128 is programmed to, among other things, compute an estimate of the output current lout based upon the digital representations received from analog to digital converter 1126 and an efficiency factor Eff representing an efficiency of power conversion by switched mode power supply 1108. In this regard, controller 1128 is programmed to compute the estimate of the output current lout sourced by the third terminal (or output terminal) of switched mode power supply 1 108 according to the formula: lout = [(Vin x Iin) / Vout] x Eff wherein Vin is the voltage of the voltage input source 1100; lin is the input current to switched mode power supply 1108; Vout is the output voltage sourced by the third terminal(or output terminal) of switched mode power supply 1108; and Eff represents the efficiency of power conversion by switched mode power supply 1108.

[0136] As described above, switched mode power supply 1108 may be a multi-level converter circuit of the type described above in Fig. 8 A through Fig.10. The efficiency of power conversion Eff for a multi-level power converter circuit is typically dependent, at least in part, upon the operating temperature of the circuit. Referring again to Fig. 11 , controller 1128 is able to receive an indication of the temperature of the integrated circuit via Temp Sensor block 1134, multiplexer 1125, and analog to digital converter 1126. In this case, multiplexer 1125 selectively applies a voltage related to the operating temperature of the integrated circuit to an analog terminal of the analog to digital converter, and the analog to digital converter provides a digital signal on its series of digital terminals corresponding to the operating temperature of the circuit. After receiving the digital signal corresponding to the operating temperature of the circuit, controller 1128 can select a value for the efficiency of power conversion Eff in accordance with the operating temperature of the circuit. Selection of the efficiency factor Eff may be performed by controller 1128 by, for example, using the current temperature reading to select a corresponding entry in a lookup table in which values for the efficiency of power conversion Eff are stored in relation to the operating temperature of the circuit. Alternatively, controller 1128 may adjust a nominal value for Eff using a linear approximation or other mathematical equations based upon the difference between a nominal operating temperature and the current operating temperature.

[0137] In the case that switched mode power supply 1108 is a multi-level power converter, it has already been noted above in reference to Figs. 8 A, 8B and 8C that such multilevel power converters include switching elements that are configured to be selectively turned on and off by pulse width modulated control signals that are switched at a specified frequency. The efficiency of power conversion Eff for a multi-level power converter may be dependent in part on the switching frequency and / or the pulse width of such pulse width modulated control signals. Accordingly, controller 1128 may be configured to select a value for the efficiency of power conversion Eff in accordance with at least one of: a) the switching frequency; and / or b) pulse width of the pulse width modulated control signals.

[0138] Fig. 12 illustrates a method for calculating an estimate of output current lout being supplied by a switched mode power supply. In practicing such method, switched mode power supply 1108 is provided. As described with reference to Fig. 11 , switched mode power supply1108 has a first terminal for coupling to a reference potential (e.g., ground), a second terminal for receiving current from a voltage input source Vin, and a third terminal for sourcing an output voltage Vout and an output current lout to load 1124. The method includes coupling a current-sensitive element, e.g., a sense resistor 1104 between the voltage input source Vin and the second terminal of switched mode power supply 1108 for conducting an input current lin thereto; as already described, a sensing voltage is developed across the current-sensitive element related to the magnitude of the input current lin. In Fig. 12, step 1200 includes sensing the voltage developed across the current- sensitive element (sense resistor 1104).

[0139] After sensing the sensing voltage in step 1200, step 1202 converts the sensing voltage to a digital representation of the input current lin. This digital representation of the input current lin is provided to controller 1128, along with an efficiency factor Eff, wherein Eff represents the efficiency of power conversion by the switched mode power supply. The method includes the step of using controller 1128 to compute an estimate of the output current lout, as represented by step 1220 in Fig. 12.

[0140] Still referring to Fig. 12, step 1204 includes sensing the voltage of the voltage input source Vin. Step 1206 includes converting the Vin voltage to a digital representation thereof. Similarly, step 1208 includes sensing the Vout voltage, and step 1210 includes converting the Vout voltage to a digital representation thereof. As indicated by the arrows leading from steps 1206 and 1210 to step 1220, the digital representations of the voltage of the voltage input source Vin and the output voltage Vout are provided to controller 1128 for computing the estimate of the output current lout. As indicated in step 1220, the estimate of lout is calculated from the digital representations of Vin, Vout, lin, and efficiency factor Eff, as by using the formula lout=[(Vin X Iin) / Vout] X Eff.

[0141] Step 1212 includes the sensing of the current operating temperature of the integrated circuit. Step 1214 includes converting an analog voltage representative of the sensed temperature to a digital representation thereof. The method may include selecting a value of the efficiency of power conversion Eff based upon the sensed operating temperature. The digital representation of the sensed temperature may either be used to obtain a corresponding value for Eff, for example from a lookup table, as shown in step 1216, or may be used directly to compute Eff using a linear approximation or other mathematical equations, as indicated by line 1218 in Fig. 12. It may be noted that sense resistor 1104 in Fig. 11 may experience changesin its resistance value based on operating temperature. Assuming that sense resistor 1104 is internal (i.e., it is fabricated on the same integrated circuit as switched mode power supply 1108 along with the components that sense the voltage across resistor 1104), then such changes in resistance value are readily corrected by controller 1128, either in the process of selecting the efficiency factor Eff as a function of operating temperature or by other digital processing accounting for operating temperature.

[0142] The above-described method may, if desired, include the step of selecting a value for the efficiency of power conversion Eff in accordance with at least one of the switching frequency and pulse width of pulse width modulated control signals used to control the operation of a multi-level power converter.

[0143] The computed estimate of output current lout may be used for several different purposes, as indicated in step 1222. For example, estimate of output current lout may be used to help regulate the operation of switched mode power supply 1108. The estimate of output current lout may also be communicated to a protection circuit configured to prevent the output current lout sourced to a battery or other load from exceeding a predetermined maximum value. In other instances, the estimated output current lout may be communicated by a telemetry network to monitor the charging of a battery or other load.

[0144] Fig. 13 illustrates another embodiment wherein the current-sensitive element used to generate a sensing voltage indicative of input current lin drawn by switched mode power supply 1108 is a Hall-effect sensor 1304 rather than a conventional sense resistor. A Halleffect sensor typically provides first and second terminals for conducting a current, as well as third and fourth terminals for providing a voltage representative of the magnitude of current flowing through the first and second terminals. As shown in Fig. 13, the first and second terminals of Hall-effect sensor 1304 are placed in series between voltage input source 1100 and switched mode power supply 1108. The third and fourth terminals of Hall-effect sensor 1304 are shown providing signals 1102 and 1106 which collectively provide a differential sensing voltage indicative of input current lin. This differential sensing voltage is shown being directed into analog to digital converter 1126 for simplicity, though an amplifier would typically be used to amplify such differential sensing voltage, and multiplexer 1125 (see Fig. 11) would typically be used to selectively couple the amplified differential voltage to analog to digital converter 1126.

[0145] Fig. 14 illustrates another embodiment wherein the current-sensitive element used to generate a sensing voltage indicative of input current lin drawn by switched mode power supply 1108 is a MOSFET device. In Fig. 14, the upper three switching MOSFET devices 1400, 1402 and 1404 are shown within a multi-level power converter 1408. Input current lin being drawn from voltage input source Vin enters multi-level power converter 1408 through the drain terminal of uppermost MOSFET device 1400 (assuming that MOSFET device 1400 is conducting), and a voltage drop is created across the drain and gate terminals of MOSFET device 1400 related to the amount of current lin being conducted thereby. The voltage drop across the drain and gate terminals of MOSFET device 1400 can be provided, via node 1102 and line 1406, as a differential sensing voltage to analog to digital converter 1126 for conversion to a digital representation of input current lin. This differential sensing voltage is shown in Fig. 14 as being directly applied to analog to digital converter 1126 for simplicity, though an amplifier would typically be used to amplify such differential sensing voltage, and multiplexer 1125 (see Fig. 11) would typically be used to selectively couple the amplified differential sensing voltage to analog to digital converter 1126.

[0146] As described above, selection of the efficiency factor Eff may depend upon, for example, operating temperature, switching frequency and / or duty cycle of PWM control signals used to control switched mode power supply 1108. Another factor which may influence the power conversion efficiency Eff of switched mode power supply 1108 are variations introduced by wafer fabrication of the integrated circuits incorporating switched mode power supply 1108 and its supporting circuitry. When integrated circuits are tested at Final Test (at the wafer level or individual die level), a measurement of the ON resistance of the switching FETS is produced. As the “silicon comer” varies (from weak to strong devices), the efficiency of the switching FET devices may change. Accordingly, it may be desired to adjust, or tweak, the selection of the Efficiency factor Eff to account for variations in silicon efficiency over the “silicon comer”, e.g., by modifying the values saved in the Efficiency factor lookup table based upon Final Test measurements, or by storing a scaling factor in controller 1128 based upon Final Test measurements.

[0147] It may be noted that while, in the present description of Figs. 11-14, it is assumed that the switched mode power converter is acting to convert a higher voltage VIN to a lower voltage VOUT, the switched mode power converter could also be operated in a Boost mode without major modification. Fig. 15 is a modified version of Fig. 11 to illustrate operation inBoost mode, and components corresponding to those described in Fig. 11 are identified by like reference numerals. In Fig. 15, switched mode power converter 1108 is used to boost input voltage Vin_boost to output voltage Vout_boost, and to supply output current Iout_boost. This means that current in resistor 1104 flows in the opposite direction (from switched mode power converter 1108 toward node 1102), and that node 1106 is at a higher voltage than node 1102. Nonetheless, the same current sensing circuit may be used. The polarity of the differential voltage created across resistor 1104 is reversed, but this is easily compensated for by swapping nodes 1102 and 1106 going into analog-to-digital converter 1126. When switched mode power supply 1108 is operated in Boost mode, sense resistor 1104 would be used to generate a sensing voltage indicative of the current Iout_boost flowing out of switched mode power supply 1108 toward node 1102, and this sensing voltage could then be used to estimate the input current Iin_boost flowing into switched mode power supply 1108 from Vin_boost. The equation for computing the estimate of Iin_boost would take the following form: lin boost — I Voul boost lout boost] / [Vin boost X Effboost], wherein Vin boost is the input voltage applied to switched mode power supply 1108;Ln boost is the current being sourced to switched mode power supply 1108 by Vinboost;Vout boost is the output voltage provided by switched mode power supply 1108 to node 1102; lout boost is the output current supplied by switched mode power supply 1108 to node 1102; andEffboost represents the efficiency (expressed as a percentage) of power conversion in Boost mode by switched mode power supply 1108.In this case, a separate lookup table could be provided for selecting the Eff_boost efficiency factor when operated in Boost mode, as signaled by a reversal in the polarity of the sensing voltage developed across sensing resistor 1104.

[0148] It is also possible, if desired, to use analog-to-digital converter 1126 in a fully differential mode whereby, when the voltages on nodes 1102 and 1106 are the same (i.e., no current flowing through resistor 1104), then ADC 1126 outputs a midpoint digital code corresponding to null, or zero. Then, when current does begin to flow through resistor 1104 in onedirection or the other, ADC 1126 outputs a digital code that is either greater than the midpoint digital code corresponding to a positive current in buck mode operation, or less than the midpoint digital code corresponding to a negative current in boost mode operation.

[0149] Further aspects of the present disclosure include the following:

[0150] Aspect 1 includes a circuit comprising: a switched mode power supply having a first terminal configured to be coupled to a reference potential, a second terminal configured to receive current from a voltage input source (Vin), and a third terminal configured to source an output voltage (Vout) and an output current (lout) to a load; a current-sensitive element being configured to be coupled between the voltage input source (Vin) and the second terminal of the switched mode power supply, the current-sensitive element being configured to conduct an input current (lin) to the switched mode power supply and to provide a sensing voltage related to a magnitude of the input current (lin); an analog to digital converter comprising at least one analog terminal and a plurality of digital terminals, the analog to digital converter being configured to provide digital representations at the plurality of digital terminals corresponding to voltages applied to the at least one analog terminal; and a controller coupled to the analog to digital converter and configured to receive the digital representations, the controller configured to compute an estimate of the output current (lout) based upon the digital representations and an efficiency factor Eff representing an efficiency of power conversion by the switched mode power supply.

[0151] Aspect 2 includes the circuit of aspect 1, further comprising selection circuitry configured to selectively apply to the at least one analog input terminal: (i) the sensing voltage; (ii) voltage of the voltage input source (Vin); and (iii) the output voltage (Vout).

[0152] Aspect 3 includes the circuit of any of aspects 1-2 wherein the controller is configured to compute the estimate of the output current (lout) sourced by the third terminal of the switched mode power supply according to the formula lout = [(Vin x Iin) / Vout] x Eff, wherein: Vin is the voltage of the voltage input source; lin is the input current to the switched mode power supply; Vout is the output voltage sourced by the third terminal of the switched mode power supply; and Eff represents the efficiency of power conversion by the switched mode power supply.

[0153] Aspect 4 includes the circuit of any of aspects 1-3, wherein the current-sensitive element is a resistor.

[0154] Aspect 5 includes the circuit of any of aspects 1-4, wherein the current- sensitive element is a Hall effect current sensor.

[0155] Aspect 6 includes the circuit of any of aspects 1-5, wherein the current- sensitive element is a MOSFET device.

[0156] Aspect 7 includes the circuit of any of aspects 1-6, wherein the switched mode power supply is a multi-level power converter.

[0157] Aspect 8 includes the circuit of any of aspects 1-7, wherein the current- sensitive element is a MOSFET device, and wherein the MOSFET device is a switching device in the multi-level power converter.

[0158] Aspect 9 includes the circuit of any of aspects 1-8, wherein: the switched mode power supply is a multi-level power converter; and the efficiency of power conversion (Eff) by the multi-level power converter is dependent in part on an operating temperature of the circuit.

[0159] Aspect 10 includes the circuit of any of aspects 1-9, further including a temperature sensor configured to provide a voltage related to the operating temperature of the circuit; wherein the selection circuitry selectively applies voltage related to the operating temperature of the circuit to the at least one analog terminal of the analog to digital converter, the analog to digital converter being configured to provide a digital signal on the plurality of digital terminals corresponding to the operating temperature of the circuit; and the controller selects a value for the efficiency of power conversion (Eff) in accordance with the operating temperature of the circuit.

[0160] Aspect 11 includes the circuit of any of aspects 1-10, wherein the controller includes a lookup table storing values for the efficiency of power conversion Eff in relation to the operating temperature of the circuit.

[0161] Aspect 12 includes the circuit of any of aspects 1-1 1 , wherein: the switched mode power supply is a multi-level power converter including switching elements configured to selectively be turned on by pulse width modulated control signals; the efficiency of power conversion (Eff) by the multi-level power converter is dependent in part on at least one of switching frequency and pulse width of the pulse width modulated control signals; and thecontroller is configured to select a value for the efficiency of power conversion (Eff) in accordance with at least one of switching frequency and pulse width of the pulse width modulated control signals.

[0162] Aspect 13 includes a method comprising: providing a switched mode power supply having a first terminal for coupling to a reference potential, a second terminal for receiving current from a voltage input source (Vin), and a third terminal for sourcing an output voltage (Vout) and an output current (lout) to a load; coupling a current-sensitive element between the voltage input source (Vin) and the second terminal of the switched mode power supply for conducting an input current (lin) thereto, the current-sensitive element providing a sensing voltage thereacross related to the magnitude of the input current (lin); converting the sensing voltage to a digital representation of the input current (lin); providing the digital representation of the input current (lin) and an efficiency factor Eff, to a digital controller, wherein Eff represents the efficiency of power conversion by the switched mode power supply; and using the digital controller to compute an estimate of the output current (lout).

[0163] Aspect 14 includes the method of aspect 13, further comprising: converting the voltage of the voltage input source (Vin) to a digital representation thereof; converting the output voltage (Vout) to a digital representation thereof; and providing the digital representations of the voltage of the voltage input source (Vin) and the output voltage (Vout) to the digital controller for computing the estimate of the output current (lout).

[0164] Aspect 15 includes the method of any of aspects 13-14 wherein the estimate of the output current (lout) is computed according to the formula lout = [(Vin x Iin) / Vout] x Eff.

[0165] Aspect 16 includes the method of any of aspects 13-15, including using the computed estimate of the output current (lout) to regulate operation of the switched mode power supply.

[0166] Aspect 17 includes the method of any of aspects 13-16, including communicating the computed estimated of output current (lout) to a protection circuit configured to prevent the output current (lout) sourced to the load by the switched mode power supply from exceeding a predetermined maximum value.

[0167] Aspect 18 includes the method of any of aspects 13-17, wherein the current-sensitive element is a resistor.

[0168] Aspect 19 includes the method of any of aspects 13-18, wherein the current-sensitive element is a Hall effect current sensor.

[0169] Aspect 20 includes the method of any of aspects 13-19, wherein the current-sensitive element is a MOSFET device.

[0170] Aspect 21 includes the method of any of aspects 13-20, wherein the switched mode power supply is a multi-level power converter, and wherein the MOSFET device is a switching device in the multi-level power converter.

[0171] Aspect 22 includes the method of any of aspects 13-21, wherein the efficiency of power conversion Eff by the switched mode power supply is dependent in part on operating temperature, the method further including: sensing an operating temperature; and selecting a value of the efficiency of power conversion Eff based upon the sensed operating temperature.

[0172] Aspect 23 includes the method of any of aspects 13-22, wherein selecting the value of the efficiency of power conversion Eff includes obtaining the value of the efficiency of power conversion Eff from a lookup table based upon the sensed operating temperature.

[0173] Aspect 24 includes the method of any of aspects 13-23, wherein the switched mode power supply is a multi-level power converter having switching elements that are selectively turned on by pulse width modulated control signals, and wherein the efficiency of power conversion Eff by the multi-level power converter is dependent in part on at least one of the frequency and pulse width of the pulse width modulated control signals, the method further including the step of selecting a value for the efficiency of power conversion (Eff) in accordance with at least one of the frequency and pulse width of the pulse width modulated control signals.

[0174] General Benefits and Advantages of Multi-Level Power Converters

[0175] Embodiments of the current invention improve the power density and / or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and / or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

[0176] More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:

[0177] - adaptability to applications in which input and / or output voltages may have a wide dynamic -range (e.g., varying battery input voltage levels, varying output voltages);

[0178] - efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.)',

[0179] - efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;

[0180] - enabling design optimizations for power efficiency, power density, and formfactor of the power converter - for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and / or to lower an overall bill of materials;

[0181] - the ability to take advantage of the performance of smaller, low voltage transistors;

[0182] - adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power-over Ethernet, etc.)

[0183] - adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g., LCDs and LEDs of all types);

[0184] - the ability to be implemented in a number of IC technologies (e.g., MOSFETs,GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

[0185] The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters includeportable and mobile computing and / or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z- Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery-backup systems and / or power conversion for processing systems and / or electronic / op- tical networking systems), internet-of-things (IOT) devices (e.g. , smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC / DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and / or infotainment systems), and other devices and systems that utilize portable electricity generating sources and / or require power conversion.

[0186] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.11a, b, g, ac, ax), as well as other radio communication standards and protocols.

[0187] Programmable Embodiments

[0188] Some or all aspects of the invention, particularly the Multi-Level Switch State Selector 1014 of FIG. 10, may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the algorithms included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (i.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client / server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and / or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code maybe applied to input data to perform the functions described in this disclosure and generate output information. The output information may be applied to one or more output devices in known fashion.

[0189] Each such computer program may be implemented in any desired computer language (including machine, assembly, or high-level procedural, logical, or object-oriented programming languages) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different computers or processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.

[0190] Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non- transitory storage media or device (e.g. , solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently or permanently), the storage media or device being readable by a general or special purpose programmable computer or processor for configuring and operating the computer or processor when the storage media or device is read by the computer or processor to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer or processor to operate in a specific or predefined manner to perform the functions described in this disclosure.

[0191] Fabrication Technologies & Options

[0192] In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multi-levelpower converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC-based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiC ), hafnium dioxide (HFO2), or aluminum oxide AI2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and / or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

[0193] Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

[0194] The controller(s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and / or combinatorial logic.

[0195] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0196] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

[0197] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0198] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high- resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (z.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0199] Voltage levels may be adjusted, and / or voltage and / or logic signal polarities reversed, depending on a particular specification and / or implementing technology (e.g. , NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greatercurrents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

[0200] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0201] A number of embodiments of the disclosure have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.

[0202] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the disclosure, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the disclosure includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

CLAIMSWHAT IS CLAIMED IS:

1. A circuit comprising: a) a switched mode power supply having a first terminal configured to be coupled to a reference potential, a second terminal configured to receive current from a voltage input source (Vin), and a third terminal configured to source an output voltage (Vout) and an output current (lout) to a load; b) a current-sensitive element being configured to be coupled between the voltage input source (Vin) and the second terminal of the switched mode power supply, the current-sensitive element being configured to conduct an input current (lin) to the switched mode power supply and to provide a sensing voltage related to a magnitude of the input current (lin); c) an analog to digital converter comprising at least one analog terminal and a plurality of digital terminals, the analog to digital converter being configured to provide digital representations at the plurality of digital terminals corresponding to voltages applied to the at least one analog terminal; and d) a controller coupled to the analog to digital converter and configured to receive the digital representations, the controller configured to compute an estimate of the output current (Tout) based upon the digital representations and an efficiency factor Eff representing an efficiency of power conversion by the switched mode power supply.

2. The circuit recited by claim 1 further comprising selection circuitry configured to selectively apply to the at least one analog input terminal:(i) the sensing voltage;(ii) voltage of the voltage input source (Vin); and(iii) the output voltage (Vout).

3. The circuit recited by claim 2 wherein the controller is configured to compute the estimate of the output current (lout) sourced by the third terminal of the switched mode power supply according to the formula lout = [(Vin x Iin) / Vout] x Eff wherein:Vin is the voltage of the voltage input source; tin is the input current to the switched mode power supply;Vout is the output voltage sourced by the third terminal of the switched mode power supply; andEff represents the efficiency of power conversion by the switched mode power supply.

4. The circuit recited by claim 1 wherein the current-sensitive element is a resistor.

5. The circuit recited by claim 1 wherein the current-sensitive element is a Hall effect current sensor.

6. The circuit recited by claim 1 wherein the current-sensitive element is a MOSFET device.

7. The circuit recited by claim 1 wherein the switched mode power supply is a multi-level power converter.

8. The circuit recited by claim 7 wherein the current-sensitive element is a MOSFET device, and wherein the MOSFET device is a switching device in the multi-level power converter.

9. The circuit recited by claim 2 wherein: a) the switched mode power supply is a multi-level power converter; and b) the efficiency of power conversion (Eff) by the multi-level power converter is dependent in part on an operating temperature of the circuit.

10. The circuit recited by claim 9 further including a temperature sensor configured to provide a voltage related to the operating temperature of the circuit, and wherein:a) the selection circuitry selectively applies voltage related to the operating temperature of the circuit to the at least one analog terminal of the analog to digital converter, the analog to digital converter being configured to provide a digital signal on the plurality of digital terminals corresponding to the operating temperature of the circuit; and b) the controller selects a value for the efficiency of power conversion (Eff) in accordance with the operating temperature of the circuit.

11. The circuit recited by claim 10 wherein the controller includes a lookup table storing values for the efficiency of power conversion Eff in relation to the operating temperature of the circuit.

12. The circuit recited by claim 1 wherein: a) the switched mode power supply is a multi-level power converter including switching elements configured to selectively be turned on by pulse width modulated control signals; b) the efficiency of power conversion (Eff) by the multi-level power converter is dependent in part on at least one of switching frequency and pulse width of the pulse width modulated control signals; and c) the controller is configured to select a value for the efficiency of power conversion (Eff) in accordance with at least one of switching frequency and pulse width of the pulse width modulated control signals.

13. A method comprising: a) providing a switched mode power supply having a first terminal for coupling to a reference potential, a second terminal for receiving current from a voltage input source (Vin), and a third terminal for sourcing an output voltage (Vout) and an output current (lout) to a load; b) coupling a current-sensitive element between the voltage input source (Vin) and the second terminal of the switched mode power supply for conducting an input current (lin) thereto, the current-sensitive element providing a sensing voltage thereacross related to the magnitude of the input current (lin); c) converting the sensing voltage to a digital representation of the input current (lin);d) providing the digital representation of the input current (lin) and an efficiency factor Eff, to a digital controller, wherein Eff represents the efficiency of power conversion by the switched mode power supply; and e) using the digital controller to compute an estimate of the output current (lout).

14. The method recited by claim 13 further comprising: a) converting the voltage of the voltage input source (Vin) to a digital representation thereof; b) converting the output voltage (Vout) to a digital representation thereof; and c) providing the digital representations of the voltage of the voltage input source (Vin) and the output voltage (Vout) to the digital controller for computing the estimate of the output current (lout).

15. The method recited by claim 14 wherein the estimate of the output current (lout) is computed according to the formula lout = [(Vin x Iin) / Vout] x Eff.

16. The method recited by claim 13 including using the computed estimate of the output current (lout) to regulate operation of the switched mode power supply.

17. The method recited by claim 13 including communicating the computed estimated of output current (lout) to a protection circuit configured to prevent the output current (lout) sourced to the load by the switched mode power supply from exceeding a predetermined maximum value.

18. The method recited by claim 13 wherein the current- sensitive element is a resistor.

19. The method recited by claim 13 wherein the current-sensitive element is a Hall effect current sensor.

20. The method recited by claim 13 wherein the current-sensitive element is a MOSFET device.

21. The method recited by claim 20 wherein the switched mode power supply is a multi-level power converter, and wherein the MOSFET device is a switching device in the multi-level power converter.

22. The method recited by claim 13 wherein the efficiency of power conversion Eff by the switched mode power supply is dependent in part on operating temperature, the method further including: a) sensing an operating temperature; and b) selecting a value of the efficiency of power conversion Eff based upon the sensed operating temperature.

23. The method recited by claim 22 wherein selecting the value of the efficiency of power conversion Eff includes obtaining the value of the efficiency of power conversion Eff from a lookup table based upon the sensed operating temperature.

24. The method recited by claim 13 wherein the switched mode power supply is a multi-level power converter having switching elements that are selectively turned on by pulse width modulated control signals, and wherein the efficiency of power conversion Eff by the multilevel power converter is dependent in part on at least one of the frequency and pulse width of the pulse width modulated control signals, the method further including the step of selecting a value for the efficiency of power conversion (Eff) in accordance with at least one of the frequency and pulse width of the pulse width modulated control signals.

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