Back-contact cell and manufacturing method therefor, and battery assembly

Abstract

The present invention relates to the technical field of back-contact cells, and in particular to a back-contact cell and a manufacturing method therefor, and a battery assembly. The back-contact cell comprises a silicon wafer having a front surface and a back surface, and first semiconductor layers and second semiconductor layers which are disposed on the back surface and are alternately arranged in a Y-axis direction of the silicon wafer; and the ends of each second semiconductor layer extend to the outer surfaces of the ends of first semiconductor layers adjacent to the second semiconductor layer to form transition regions. The back-contact cell further comprises a silicon alloy layer disposed outward in a Z-axis direction and containing metal silicide; the silicon alloy layer is disposed on the outer surfaces of the second semiconductor layers and extends to the outer surfaces of first doped silicon crystal layers adjacent to the second semiconductor layers; and insulating grooves are formed in the portions of the silicon alloy layer corresponding to the transition regions. The manufacturing process is simpler, and expensive low-temperature silver paste and transparent conductive film layers do not need to be used, thereby greatly reducing the production costs of a battery, and ensuring excellent battery conversion efficiency.

Description

Back contact battery, preparation method thereof, and battery assembly

[0001] Cross-references to related publications

[0002] The present disclosure claims priority to Chinese patent application No. 2024100775032 filed with the Patent Office of China on January 19, 2024, entitled “A back-contact battery, a method for preparing the same, and a battery assembly”, and Chinese patent application No. 2024100775066 filed with the Patent Office of China on January 19, 2024, entitled “A back-contact battery, a method for preparing the same, and a battery assembly”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure belongs to the technical field of back-contact batteries, and particularly relates to a back-contact battery, a preparation method thereof, and a battery assembly. Background Art

[0004] At present, the back contact battery structure generally includes a silicon wafer, a first semiconductor layer and a second semiconductor layer arranged on the back of the silicon wafer; and a conductive film layer and a metal grid line respectively arranged on the outer surfaces of the first semiconductor layer and the second semiconductor layer; and a passivation layer and an optional anti-reflection layer sequentially arranged on the front of the silicon wafer. The process flow is generally as follows: S101, double-sided polishing of the silicon wafer; S102, coating the back of the silicon wafer with a first mask layer for protection; S103, texturing and cleaning the silicon wafer to form a velvet surface opposite to the first mask layer, and then removing the first mask layer to form a silicon wafer with a single-sided texturing and single-sided polishing structure; S104, coating the back of the silicon wafer with a first semiconductor layer and a second mask layer in sequence; S105, etching an opening on the back of the silicon wafer, removing the second mask layer and part of the first semiconductor layer to form a first opening area; S106, cleaning the silicon wafer to remove the first semiconductor layer in the first opening area; S1 07. An amorphous layer and an anti-reflection layer are formed in sequence on the front side of the silicon wafer, and a second semiconductor layer is formed on the back side; S108. Openings are etched on the back side of the silicon wafer to form second opening areas that are arranged alternately with the first opening areas; S109. The silicon wafer is cleaned to remove the second mask layer in the second opening areas; S110. A conductive film layer is deposited on the back side of the silicon wafer; S111. An insulating groove is formed between the first opening area and the second opening area by etching; S112. Metal electrodes (i.e., fine gates) are formed on the first opening area and the second opening area of ​​the silicon wafer, and then a main gate perpendicular to the metal electrodes is formed.

[0005] However, existing back-contact battery structures require depositing a conductive film layer on the back of a silicon wafer. Currently, the conductive film layer typically uses a transparent conductive film, ITO (indium tin oxide) or TCO (tantalum conductive oxide). Etching is then used to form an insulating trench between the first and second openings, and metal grid electrodes are formed on the first and second openings of the silicon wafer. The metal grid electrodes are typically formed using low-temperature silver paste. Consequently, the use of expensive transparent conductive film and low-temperature silver paste contributes to high battery costs.

[0006] In addition, existing back-contact cells also need to remove the conductive film layer between the first opening area and the second opening area to form an insulating groove; the third etching laser grooving on the back side is all selective grooving on the transparent conductive film layer or the transparent conductive film layer and the P-type (or transparent N-type) amorphous silicon passivation layer. Because the material is transparent, the laser cannot be resonantly absorbed, resulting in great difficulty in laser grooving; and the use of wet etching has a more complicated process and a greater impact on the battery cell, further increasing the difficulty of large-scale mass production of back-contact cells.

[0007] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0008] Summary of the Invention

[0009] The present invention aims to overcome the drawback of prior art back-contact cells, which require the use of expensive transparent conductive film and low-temperature silver paste while maintaining excellent cell conversion efficiency, resulting in high cell costs. The present invention provides a back-contact cell, a method for preparing the cell, and a cell assembly. The present invention simplifies the manufacturing process and eliminates the need for expensive low-temperature silver paste and transparent conductive film, significantly reducing cell production costs while maintaining excellent cell conversion efficiency.

[0010] In order to achieve the above-mentioned objectives, in a first aspect, the present disclosure provides a back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprising a first doped silicon crystal layer, the second semiconductor layer comprising a second doped silicon crystal layer, and an end portion of the second semiconductor layer extends to an outer surface of an adjacent end portion of the first semiconductor layer to form a transition region, the back-contact battery further comprising a silicon alloy layer containing metal silicide arranged outward along the Z-axis direction, the silicon alloy layer being arranged on an outer surface of the second semiconductor layer and extending to an outer surface of the adjacent first doped silicon crystal layer, and an insulating groove being provided on a portion of the silicon alloy layer corresponding to the transition region; wherein the square resistance of the silicon alloy layer is 5-70Ω / □.

[0011] In some optional embodiments of the present disclosure, the metal element contained in the metal silicide includes at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

[0012] In some optional embodiments of the present disclosure, the metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide.

[0013] In some optional embodiments of the present disclosure, the thickness of the silicon alloy layer is 2-30 nm.

[0014] In some optional embodiments of the present disclosure, the silicon alloy layer further contains a doping element, and the doping element includes boron or phosphorus.

[0015] In some more optional embodiments of the present disclosure, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1-250:3-800, optionally 1:1-250:3-500, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

[0016] In this disclosure, the unit of the surface doping index is cm<-3> / nm. That is, the effective doping concentration of the corresponding doped silicon crystal layer is measured in cm<-3> and the thickness is measured in nm.

[0017] In some optional embodiments of the present disclosure, the effective doping concentration of the silicon alloy layer is 1e17 cm-3-1e18 cm-3.

[0018] In some optional embodiments of the present disclosure, the thickness of the first doped silicon crystal layer is 50-300 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3.

[0019] In some optional embodiments of the present disclosure, the thickness of the second doped silicon crystal layer is 10-50 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3.

[0020] In some optional embodiments of the present disclosure, the first semiconductor layer further includes a first passivation layer disposed on the back side of the silicon wafer, and at least a portion of the first passivation layer is located between the back side of the silicon wafer and the first doped silicon crystal layer.

[0021] Optionally, the second semiconductor layer further includes a second passivation layer disposed on the back side of the silicon wafer, the second passivation layer being located between the back side of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes an intrinsic amorphous silicon layer or a second tunneling oxide layer.

[0022] Optionally, the intrinsic amorphous silicon layer has a thickness of 5-15 nm, and the second tunneling oxide layer has a thickness of 1.5-2.5 nm.

[0023] In some optional embodiments of the present disclosure, the first passivation layer is provided to fully cover the back side of the silicon wafer, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on the side of the first passivation layer away from the back side of the silicon wafer, the second doped silicon crystal layer and the part of the first passivation layer covered by it form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers.

[0024] In some optional embodiments of the present disclosure, the first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer.

[0025] Optionally, a thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:1:0.05-1.25.

[0026] Optionally, the thickness of the first tunnel oxide layer is 1.5-2.5 nm.

[0027] In some optional embodiments of the present disclosure, in the transition region, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided.

[0028] In some optional embodiments of the present disclosure, the width of the insulating groove is 0.03-0.15 mm.

[0029] In some optional embodiments of the present disclosure, the back contact cell is not provided with a main grid and a fine grid.

[0030] In some optional embodiments of the present disclosure, the back-contact cell further includes a front passivation layer disposed outwardly on the front side of the silicon wafer.

[0031] Optionally, the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous superimposed doped amorphous silicon, intrinsic amorphous superimposed doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide superimposed doped polycrystalline silicon.

[0032] In a second aspect, the present disclosure provides a method for preparing a back-contact battery, comprising the following steps:

[0033] S1. Forming a first semiconductor layer on the back side of a silicon wafer and defining first openings in the first semiconductor layer at intervals along the Y-axis of the silicon wafer; then forming a second semiconductor layer on the back side and defining second openings in a portion of the second semiconductor layer that covers an outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer, and the second semiconductor layer comprises a second doped silicon crystal layer;

[0034] S2, forming a metal thin film layer on the back surface obtained in S1;

[0035] S3. Then, heat treatment is performed in an oxygen-free environment to allow the metal in the metal film layer to react with the silicon in the corresponding doped silicon crystal layer in contact with it to form a silicon alloy layer, and the sheet resistance of the silicon alloy layer is controlled to be 5-70Ω / □;

[0036] S4. Perform a third etching on a portion of the silicon alloy layer located between the first opening region and the second opening region to form an insulating trench.

[0037] In some optional embodiments of the present disclosure, the metal thin film layer has a thickness of 5-20 nm.

[0038] In some optional embodiments of the present disclosure, the metal film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel-containing alloy metal film, an aluminum-containing alloy metal film, a platinum-containing alloy metal film, a cobalt-containing alloy metal film layer, a titanium-containing alloy metal film, and a tungsten-containing alloy metal film.

[0039] In some optional embodiments of the present disclosure, the metal film layer in S2 is obtained by magnetron sputtering or evaporation.

[0040] Optionally, the conditions of the magnetron sputtering include: vacuum degree of 5×10-3Pa-5×10-1Pa, sputtering power of 2-5kW, and sputtering time of 30-90s.

[0041] Optionally, the evaporation conditions include: vacuum degree of 5×10-3Pa-5×10-1Pa, evaporation heating power of 5-10kW, and evaporation time of 30-120s.

[0042] In some optional embodiments of the present disclosure, the process of heat treatment in an anaerobic environment described in S3 includes: in an anaerobic environment, using laser irradiation at 300-350°C for rapid photothermal treatment for 5-60s; or, in an anaerobic environment, annealing treatment at 100-220°C for 5-30min.

[0043] In some optional embodiments of the present disclosure, the third etching in S4 adopts laser technology, and the laser used is a laser with a pulse width of picoseconds.

[0044] In some optional implementations of the present disclosure, the process of S1 specifically includes:

[0045] S101, providing silicon wafers;

[0046] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0047] S103, performing a first etching on the first semiconductor layer and the mask layer in the preset area on the back side obtained in S102 to form first opening areas distributed at intervals;

[0048] S104, then removing all remaining mask layers;

[0049] S105, then forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer sequentially formed on the back surface;

[0050] S106 , performing a second etching on the area on the back side obtained in S105 where the first semiconductor layer remains, so as to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area.

[0051] In some other optional implementations of the present disclosure, the process of S1 specifically includes:

[0052] S11, provide silicon wafer;

[0053] S12, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0054] S13, performing a first etching on the first doped silicon crystal layer and the mask layer in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0055] S14, then removing all remaining mask layers;

[0056] S15, then forming a second doped silicon crystal layer on the back surface obtained in S14, the second doped silicon crystal layer and a portion of the first passivation layer covered by the second doped silicon crystal layer forming a second semiconductor layer;

[0057] S16, then performing a second etching on the area on the back side obtained in S15 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening area spaced apart from the first opening area.

[0058] In a third aspect, the present disclosure provides a back-contact battery, which is prepared by the preparation method of the back-contact battery described in the second aspect.

[0059] In a fourth aspect, the present disclosure provides a battery assembly comprising the back-contact battery described in the first aspect, or the back-contact battery described in the third aspect, and a welding strip directly provided on the surface of the silicon alloy layer corresponding to different conductive areas in the back-contact battery. Beneficial effects:

[0060] The present disclosure utilizes the above-mentioned technical solution, particularly the use of a silicon alloy layer containing metal silicide with a specific conductivity as an electrode lead-out method, replacing the conventional back-contact battery's transparent conductive film layer combined with silver metal fine grid lines. This simplifies the manufacturing process and eliminates the need for expensive low-temperature silver paste and transparent conductive film layers (such as ITO), significantly reducing battery production costs while ensuring excellent battery conversion efficiency. The silicon alloy layer not only achieves good ohmic contact between silicon and metal, but also has a suitably high conductivity (i.e., low sheet resistance), so it can directly replace the transparent conductive film, silver fine grid, and main grid in the back-contact battery of the prior art.

[0061] The silicon alloy layer disclosed in the present invention has high conductivity (i.e., low square resistance) and can be directly used as an electrode lead-out line without the need for additional fine grids and main grids. Instead, it can directly conduct current, with a short manufacturing process. At the same time, it does not require the use of expensive low-temperature silver paste and transparent conductive film layers, greatly reducing the production cost of the battery while ensuring excellent battery conversion efficiency.

[0062] In the disclosed preparation method, a metal film layer is deposited on the silicon surface of the first and second semiconductor layers. After heat treatment, the silicon and metal react to form a metal silicide, which can form a highly conductive silicon alloy layer. This can form a good current path, allowing electrons and holes inside the silicon wafer to escape to the battery surface and conduct to the external circuit. The reason why the two can form a silicon alloy layer with good ohmic contact is that, using nickel as an example, it is reflected in at least the following aspects:

[0063] 1. Compatibility: Silicon and nickel have similar lattice structures, with similar lattice parameters and crystal structures, which makes them highly compatible when forming the SiNi2 alloy phase. Compatibility means having a similar arrangement in the crystal structure, which facilitates interaction and diffusion between atoms.

[0064] 2. Chemical affinity: Silicon and nickel have a certain chemical affinity. When adsorbed on the silicon surface, nickel metal forms a strong chemical bond with silicon, forming a Si-Ni bond, which helps form a stable SiNi2 alloy phase. This chemical affinity helps increase the fluctuation boundary diffusion rate and promotes the interaction between silicon and nickel.

[0065] 3. Conductivity: The SiNi2 alloy phase has a high conductivity. Due to the high conductivity of the SiNi2 alloy phase, the current can be effectively conducted between the metal and the semiconductor, thereby forming a good ohmic contact.

[0066] Moreover, metal silicide can significantly reduce the direct contact resistance between silicon and metal (forming an excellent ohmic contact between silicon and metal), and the formation of metal silicide requires a certain temperature, such as WSix, TiSix, CoSix, PtSix, and NiSix, where x is a natural number that satisfies the valence balance. Their formation temperatures decrease in sequence, among which nickel silicide (NiSix) requires the lowest formation temperature, especially the lattice symmetry and crystal silicon constant of the single crystal NiSi2 phase are close to those of single crystal silicon. Therefore, the formation of the NiSi2 phase requires the least driving force, that is, the required temperature is the lowest, and it can even be formed when metal nickel is plated on the surface of single crystal silicon and heated to 150°C. In the preparation method disclosed herein, a suitable metal silicide silicon alloy layer can be selected based on the temperature characteristics of the passivation structure of each semiconductor layer. For example, nickel silicide, aluminum silicide, and platinum silicide have relatively low formation temperatures and are suitable for configuring heterojunction structures with intrinsic amorphous silicon passivation and low-temperature processes for combined passivation structures. The relatively high temperatures required for W, Ti, and Co to form silicon alloys with silicon make them suitable for configuring Topcon cell structures with tunneling oxide passivation. The present disclosure can be widely applied in the production of solar cells and semiconductor chips.

[0067] In the optional solution disclosed herein, especially for the combined passivated back contact cell, it is easier to use laser grooving for the third back etching, which further simplifies the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0069] FIG1 is a schematic structural diagram of a back-contact battery according to an embodiment of the present disclosure, wherein a first semiconductor layer and a front stack are formed;

[0070] FIG2 is a schematic structural diagram of a mask layer formed on FIG1 ;

[0071] FIG3 is a schematic structural diagram of a first opening area in FIG2 ;

[0072] FIG4 is a schematic diagram of the structure of FIG3 after removing the mask layer;

[0073] FIG5 is a schematic structural diagram of a second semiconductor layer formed on FIG4 ;

[0074] FIG6 is a schematic structural diagram of a second opening area in FIG5;

[0075] FIG7 is a schematic structural diagram of a metal thin film layer formed on FIG6 and subjected to oxygen-free annealing to form a silicon alloy layer;

[0076] FIG8 is a schematic structural diagram of an insulating groove provided on FIG7;

[0077] FIG9 is a schematic structural diagram of another embodiment of the back-contact battery disclosed herein.

[0078] FIG10 is a schematic diagram of the structure of the first main grid, the second main grid and the insulating layer in Comparative Example 1.

[0079] Description of Reference Numerals

[0080] 1. Silicon wafer, 2. First tunneling oxide layer, 3. Front stack, 4. First doped polycrystalline layer, 5. Intrinsic amorphous silicon layer, 6. Second doped silicon crystal layer, 7. Nickel-silicon alloy layer, 8. Metal film layer, 9. Insulation trench, 10. First main gate, 11. Second main gate, 12. Insulation layer, 13. First fine gate, 14. Second fine gate, a1. Mask layer. DETAILED DESCRIPTION

[0081] In the present disclosure, unless otherwise specified, directional words such as “upper, lower, left, right” are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0082] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0083] In the present disclosure, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0084] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0085] In this disclosure, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0086] In the present disclosure, the sheet resistance of the corresponding layer refers to the surface of the structure where the layer is located after the deposition of the layer, and the surface resistance of the structure is obtained by testing the surface of the structure where the layer is located using the four-point probe (4PP) method. For example, the sheet resistance of the silicon alloy layer is obtained by testing the surface after the silicon alloy layer is plated. The working principle of the four-point probe method is to contact the material with four equidistant and collinear probes for measurement. This method is called the four-point probe method. Direct current (DC) is driven between the two outer probes, and the voltage is measured between the two inner probes. When measuring on small samples or near the edge, a geometric correction factor is usually required because the current path is affected by the geometric structure of the sample. The most accurate value can be obtained in the center area of ​​the sample. In the present disclosure, the sheet resistance of the corresponding layer is obtained by performing the same test in the center area of ​​the sample to be measured.

[0087] In a first aspect, the present disclosure provides a back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer arranged on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprising a first doped silicon crystal layer, the second semiconductor layer comprising a second doped silicon crystal layer, and an end portion of the second semiconductor layer extending to the outer surface of an adjacent end portion of the first semiconductor layer to form a transition region, the back-contact battery further comprising a silicon alloy layer containing metal silicide arranged outward along the Z-axis direction, the silicon alloy layer being arranged on the outer surface of the second semiconductor layer and extending to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove being provided on a portion of the silicon alloy layer corresponding to the transition region; wherein the square resistance of the silicon alloy layer is 5-70Ω / □.

[0088] It should be noted that in the transition region, the first semiconductor layer and the second semiconductor layer are sequentially arranged from the inside to the outside in the Z-axis direction on the back of the silicon wafer. The first semiconductor layer and the second semiconductor layer extend along the X-axis direction of the silicon wafer respectively.

[0089] In the present disclosure, one of the first doped silicon crystal layer and the second doped silicon crystal layer is N-type and the other is P-type.

[0090] The silicon alloy layer has a low sheet resistance, indicating that the silicon alloy layer has a suitably high electrical conductivity. In the present disclosure, the metal element contained in the metal silicide can be selected based on the electrical conductivity of the silicon alloy layer. In some optional embodiments of the present disclosure, the metal element contained in the metal silicide includes at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

[0091] Optionally, the metal elements contained in the metal silicide include at least one of nickel, aluminum, and platinum, which is more suitable for being configured into a back contact battery structure of a heterojunction battery structure (i.e., the passivation layers of the two semiconductor layers are both intrinsic amorphous silicon) and a combined passivation structure (i.e., the first passivation layer and the second passivation layer are tunneling oxide layer and intrinsic amorphous silicon, respectively).

[0092] In some optional embodiments of the present disclosure, the metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide. In the present disclosure, there is no limitation on the specific form (or specific compound composition) of the various metal silicides; as long as they are products of reactions between raw material elements containing silicon and metal, the objectives and technical effects of the present disclosure can be achieved. For example, the nickel silicide can be in the form of NiSi2, NiSi, or Ni2Si.

[0093] In some optional embodiments of the present disclosure, the thickness of the silicon alloy layer is 2-30 nm, optionally 2-15 nm. This appropriately thick silicon alloy layer can form a good ohmic contact without adversely affecting the battery structure due to the potential excessive consumption of silicon in the first doped silicon crystal layer and the second doped silicon crystal layer. This helps form a good ohmic contact at the interface while minimizing damage to the corresponding doped silicon crystal layers and without destroying the battery structure, thereby effectively conducting current between the metal and semiconductor.

[0094] Optionally, the square resistance of the silicon alloy layer is 5-36Ω / □, and the thickness of the silicon alloy layer is 2-15nm, which is more conducive to improving the battery conversion efficiency.

[0095] In some optional embodiments of the present disclosure, the silicon alloy layer further contains a doping element, and the doping element includes boron or phosphorus.

[0096] In some more optional embodiments of the present disclosure, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1-250:3-800, optionally 1:1-250:3-500, wherein the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

[0097] Optionally, the ratio of the surface doping index of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1-100:10-200. Alternatively, the ratio may be 1:15-100:40-500. Alternatively, the ratio may be 1:15-100:40-200.

[0098] In the scheme of the ratio of the surface doping index of the above-mentioned optional silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer disclosed in the present invention, the thickness and doping concentration of each layer are matched, which can better control the concentration of carriers, improve electron mobility and reduce resistance, and is more conducive to improving the stability of the preparation process and the overall performance of the battery.

[0099] In some optional embodiments of the present disclosure, the effective doping concentration of the silicon alloy layer is 1e17 cm-3-1e18 cm-3.

[0100] In some optional embodiments of the present disclosure, the thickness of the first doped silicon crystal layer is 50-300 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3.

[0101] In some optional embodiments of the present disclosure, the thickness of the second doped silicon crystal layer is 10-50 nm, and the effective doping concentration is 1e19 cm-3-4e20 cm-3. The thickness of the second doped silicon crystal layer of the present disclosure is thicker than that of the prior art to provide an appropriate amount of silicon for the formation of the silicon alloy layer.

[0102] The second doped silicon crystal layer may be a doped amorphous layer or a doped microcrystalline layer.

[0103] In some specific optional embodiments, the back contact cell is a combined passivation structure, the thickness of the second doped silicon crystal layer is 10-40 nm, and / or the second doped silicon crystal layer is a doped amorphous layer, which is more conducive to improving the cell conversion efficiency.

[0104] In some optional embodiments of the present disclosure, the first semiconductor layer further includes a first passivation layer disposed on the back side of the silicon wafer, and at least a portion of the first passivation layer is located between the back side of the silicon wafer and the first doped silicon crystal layer.

[0105] In some optional embodiments of the present disclosure, the first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer.

[0106] Optionally, the thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:1:0.05-1.25. In this optional solution, the appropriate thickness ratio of the silicon alloy layer to the first tunneling oxide layer can balance electron mobility and tunneling effect to a certain extent, further improving the conductivity of the silicon alloy layer while maintaining battery stability.

[0107] Optionally, a thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:0.20-1.25.

[0108] Optionally, the thickness of the first tunnel oxide layer is 1.5-2.5 nm.

[0109] In some optional embodiments of the present disclosure, the second semiconductor layer further includes a second passivation layer disposed on the back side of the silicon wafer, and the second passivation layer is located between the back side of the silicon wafer and the second doped silicon crystal layer.

[0110] Optionally, the second passivation layer includes an intrinsic amorphous silicon layer or a second tunneling oxide layer.

[0111] Optionally, the intrinsic amorphous silicon layer has a thickness of 5-15 nm, and the second tunneling oxide layer has a thickness of 1.5-2.5 nm.

[0112] In some optional embodiments of the present disclosure, the first passivation layer is provided to fully cover the back side of the silicon wafer, the first doped silicon crystal layer and the second doped silicon crystal layer are both located on the side of the first passivation layer away from the back side of the silicon wafer, the second doped silicon crystal layer and the portion of the first passivation layer it covers form a second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. In this structure, the second doped silicon crystal layer shares a portion of the first passivation layer to form the second semiconductor layer, and the first doped silicon crystal layer and the second doped silicon crystal layer are both doped polycrystalline layers. Because polycrystalline silicon is composed of many grains with grain boundaries between them, this structure gives polycrystalline silicon a higher degree of crystallinity and grain boundary density than an amorphous layer, which is conducive to the formation of a silicon alloy layer. It enables the metal to form a better bond at the grain boundaries of the polycrystalline silicon, forming a stable silicon alloy layer, thereby more conducive to the formation of a high-quality silicon alloy layer, while also improving the consistency of the silicon alloy layer in the first doped silicon crystal layer region and the second doped silicon crystal layer region.

[0113] In some other optional embodiments of the present disclosure, the first passivation layer includes a first tunneling oxide layer, the first doped silicon crystal layer is a first doped polycrystalline layer, and the second passivation layer includes an intrinsic amorphous silicon layer. The second doped silicon crystal layer can be a doped amorphous layer or a doped microcrystalline layer. In this solution, the back-contact cell has a combined passivation structure, which has higher cell conversion efficiency than other passivation structures.

[0114] In some optional embodiments of the present disclosure, within the transition region, the extended end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction, or a mask layer is provided. Direct contact is optional, and compared to providing a mask layer between the first and second semiconductor layers, this is more conducive to reducing impurities or surface scattering introduced by the mask layer, thereby helping to improve carrier mobility in the device.

[0115] In some optional embodiments of the present disclosure, the width of the insulating groove is 0.03-0.15 mm, and optionally 0.03-0.1 mm. The present disclosure matches the insulating layer with an appropriate width to a specific silicon alloy layer, thereby preventing electron migration between the silicon alloy layers and avoiding unnecessary electron loss. This further facilitates isolation between the first semiconductor layer and the second semiconductor layer, and allows for better electrode extraction.

[0116] The silicon alloy layer disclosed in the present invention has high conductivity and forms excellent ohmic contact. It can be directly used as an electrode lead-out line without the need for additional fine grids and main grids. Instead, it can directly conduct current, with a short manufacturing process. At the same time, it does not require the use of expensive low-temperature silver paste and transparent conductive film layers, greatly reducing the production cost of the battery while ensuring excellent battery conversion efficiency.

[0117] In some optional embodiments of the present disclosure, the back-contact cell further includes a front passivation layer disposed outwardly on the front side of the silicon wafer.

[0118] In some embodiments of the present disclosure, the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous superimposed doped amorphous silicon, intrinsic amorphous superimposed doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide superimposed doped polycrystalline silicon.

[0119] In the present disclosure, an anti-reflection layer may or may not be provided on the outer surface of the front passivation layer as required. The thickness and material of the front passivation layer and the anti-reflection layer, as well as the doping concentration of doped amorphous silicon, doped microcrystalline silicon or doped polycrystalline silicon in the front passivation layer can all be carried out with reference to the prior art. For example, the thickness of the front passivation layer is 5-30nm, the effective doping concentration of doped amorphous silicon, doped microcrystalline silicon or doped polycrystalline silicon is 1e19cm-3-1e20cm-3, and the thickness of the anti-reflection layer is 50-150nm. For example, the type of the anti-reflection layer can be, for example, at least one of silicon nitride, silicon oxide, silicon oxynitride, etc.

[0120] In a second aspect, the present disclosure provides a method for preparing a back-contact battery, comprising the following steps:

[0121] S1. Forming a first semiconductor layer on the back side of a silicon wafer and defining first openings in the first semiconductor layer at intervals along the Y-axis of the silicon wafer; then forming a second semiconductor layer on the back side and defining second openings in a portion of the second semiconductor layer that covers an outer surface of the first semiconductor layer; wherein the first semiconductor layer comprises a first doped silicon crystal layer, and the second semiconductor layer comprises a second doped silicon crystal layer;

[0122] S2, forming a metal thin film layer on the back surface obtained in S1;

[0123] S3. Then, heat treatment is performed in an oxygen-free environment to allow the metal in the metal film layer to react with the silicon in the corresponding doped silicon crystal layer in contact with it to form a silicon alloy layer, and the sheet resistance of the silicon alloy layer is controlled to be 5-70Ω / □;

[0124] S4. Perform a third etching on a portion of the silicon alloy layer located between the first opening region and the second opening region to form an insulating groove.

[0125] In the preparation method disclosed herein, the metal in the metal film layer reacts with the silicon in the corresponding semiconductor layer in contact with it to form a metal silicide, and is inevitably doped with doping elements other than the silicon in the corresponding semiconductor layer. The doping concentration of the doping element can be adjusted by the conditions for forming the metal film layer, the conditions for heat treatment and the doping concentration of the corresponding semiconductor layer.

[0126] In some optional embodiments of the present disclosure, the metal film layer has a thickness of 5-20 nm. Optionally, after heat treatment of the metal film layer of suitable thickness, the obtained silicon alloy layer has a thickness of 2-20 nm.

[0127] The metal film layer may be a thin film layer of a single metal or a thin film layer in the form of an alloy. In some optional embodiments of the present disclosure, the metal film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel-containing alloy metal film, an aluminum-containing alloy metal film, a platinum-containing alloy metal film, a cobalt-containing alloy metal film, a titanium-containing alloy metal film, and a tungsten-containing alloy metal film.

[0128] In some optional embodiments of the present disclosure, the metal film layer in S2 is obtained by magnetron sputtering or evaporation.

[0129] Optionally, the magnetron sputtering conditions include: a vacuum level of 5×10-3 Pa to 5×10-1 Pa, a sputtering power of 2-5 kW, and a sputtering time of 30-90 seconds. Using this optional magnetron sputtering method can result in a metal film layer with lower defect density, better crystallinity, and uniformity, which is more conducive to achieving higher film quality and deposition rate.

[0130] Optionally, the evaporation conditions include: a vacuum degree of 5×10-3 Pa to 5×10-1 Pa, an evaporation heating power of 5-10 kW, and an evaporation time of 30-120 s. Using the evaporation option can reduce the presence of impurities and is more conducive to achieving higher film purity.

[0131] In some optional embodiments of the present disclosure, the process of heat treatment in an anaerobic environment described in S3 includes: in an anaerobic environment, using laser irradiation at 300-350°C for rapid photothermal treatment for 5-60s; or, in an anaerobic environment, annealing treatment at 100-220°C for 5-30min. The photothermal treatment refers to heat treatment under irradiation of a light source, that is, by locally focusing the laser energy on the surface or body of the material, so that the material absorbs light energy and converts it into heat energy, thereby causing a local temperature rise. It can be understood that a heating treatment at a certain temperature is also performed while the laser irradiation is being performed. The annealing treatment refers to heat treatment only without light source irradiation.

[0132] In the present disclosure, the third etching of S4 can etch only the silicon alloy layer in depth, or can etch through part of the second semiconductor layer (such as the second doped silicon crystal layer) or the entire layer (i.e., through the second passivation layer), forming insulating grooves of different depths or thicknesses.

[0133] In the present disclosure, the third etch described in S4 can be performed using conventional wet etching. However, further research by the present inventors has revealed that ohmic contact has already been formed between the silicon alloy layer and the corresponding doped silicon layer, making it difficult to create directional grooves using wet etching. Even if a groove is created using wet etching, it may still affect other structures. Therefore, in some alternative embodiments of the present disclosure, the third etch described in S4 utilizes laser technology.

[0134] Optionally, the laser used is a laser with a pulse width of picoseconds. Picosecond lasers, firstly, can achieve very fine processing due to the extremely short pulses produced by picosecond lasers. Secondly, due to the very short pulse duration of picosecond lasers, the heat-affected zone produced in the material is relatively small, which helps to avoid thermal damage caused during the processing. Thirdly, the pulse energy produced by picosecond lasers is relatively low, so the material is less thermally affected during the laser irradiation process. This is more conducive to reducing the thermal impact of the laser irradiation process, avoiding thermal damage that may be caused during the processing, and minimizing deformation, cracking or other thermal effects of the material.

[0135] In some optional implementations of the present disclosure, the process of S1 specifically includes:

[0136] S101, providing silicon wafers;

[0137] S102, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0138] S103, performing a first etching on the first semiconductor layer and the mask layer in the preset area on the back side obtained in S102 to form first opening areas distributed at intervals;

[0139] S104, then removing all remaining mask layers;

[0140] S105, then forming a second semiconductor layer on the back surface obtained in S104, wherein the second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer sequentially formed on the back surface;

[0141] S106 , performing a second etching on the area on the back side obtained in S105 where the first semiconductor layer remains, so as to expose the first semiconductor layer and form a second opening area spaced apart from the first opening area.

[0142] In some other optional implementations of the present disclosure, the process of S1 specifically includes:

[0143] S11, provide silicon wafer;

[0144] S12, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer in sequence formed on the back side;

[0145] S13, performing a first etching on the first doped silicon crystal layer and the mask layer in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0146] S14, then removing all remaining mask layers;

[0147] S15, then forming a second doped silicon crystal layer on the back surface obtained in S14, the second doped silicon crystal layer and a portion of the first passivation layer covered by the second doped silicon crystal layer forming a second semiconductor layer;

[0148] S16, then performing a second etching on the area on the back side obtained in S15 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening area spaced apart from the first opening area.

[0149] The back-contact cell disclosed herein may further include the steps of sequentially forming a front passivation layer and an optional anti-reflection layer on the front side of the silicon wafer. This step may be performed after forming the second semiconductor layer and then performing a second etching step, or may be performed before or after forming the first passivation layer. The compositions of the front passivation layer and anti-reflection layer are the same as those described in the first aspect above and are not further described here.

[0150] The back contact battery disclosed in the present invention does not have a main grid and a fine grid. When it is used for assembly, the electrode wires can be directly welded. Specifically, the electrode is referenced when the component is packaged, that is, the outer surfaces of the P-pole region formed in the area of ​​the first semiconductor opening area and the N-pole region formed in the area of ​​the second semiconductor opening area are respectively soldered with solder strips using tin paste. The solder strips are copper strips, aluminum strips, etc.

[0151] In a third aspect, the present disclosure provides a back-contact battery, which is prepared by the preparation method of the back-contact battery described in the second aspect, and the structure and composition of the back-contact battery are the same as those of the back-contact battery of the first aspect.

[0152] In a fourth aspect, the present disclosure provides a battery assembly comprising the back-contact battery described in the first aspect, or the back-contact battery described in the third aspect, and a welding strip directly provided on the surface of the silicon alloy layer corresponding to different conductive areas in the back-contact battery.

[0153] The embodiments of the present disclosure are described in detail below, which are exemplary and are only configured to explain the present disclosure but are not to be construed as limiting the present disclosure.

[0154] Example 1

[0155] A back contact cell as shown in FIG8 is prepared according to the following method:

[0156] S1 includes:

[0157] S101, providing a silicon wafer 1;

[0158] S102. First, a front passivation layer (specifically, a 6nm-thick intrinsic amorphous silicon layer, a 10nm-thick doped amorphous silicon layer with an effective doping concentration of 5e19cm-3) and a 100nm-thick anti-reflection layer (specifically, silicon nitride) are formed on the front surface to form a front stack 3. Then, a first semiconductor layer and a mask layer a1 are formed on the back surface of the silicon wafer 1. The first semiconductor layer includes a first tunneling oxide layer 2 and an N-type first doped polycrystalline layer 4, which are sequentially formed on the back surface, as shown in Figures 1 and 2. The first doped polycrystalline layer 4 has a thickness of 80nm and an effective doping concentration of 1e20cm-3; the first tunneling oxide layer 2 has a thickness of 2nm; and the mask layer a1 has a thickness of 50nm and is specifically made of silicon nitride.

[0159] S103, as shown in FIG3, performing a first etching on the back surface of the first semiconductor layer obtained in S102 to form first opening regions Wp with a width of 500 μm and distributed at intervals;

[0160] S104, then removing the mask layer a1, as shown in FIG4;

[0161] S105. Then, a second semiconductor layer is formed on the back surface obtained in S104. As shown in FIG5 , the second semiconductor layer includes an intrinsic amorphous silicon layer 5 and a P-type second doped silicon crystal layer 6 (specifically, a doped amorphous silicon layer) sequentially formed on the back surface. The second doped silicon crystal layer 6 has a thickness of 10 nm and an effective doping concentration of 1e20 cm-3. The thickness of the intrinsic amorphous silicon layer 5 is 10 nm.

[0162] S106 , performing a second etching on the area on the back side where the first semiconductor layer remains obtained in S105 , as shown in FIG6 , to expose the first semiconductor layer and form a second opening area Wn with a width of 150 μm spaced apart from the first opening area Wp.

[0163] S2. Forming a metal thin film layer 8 to fully cover the back surface obtained in S106. As shown in FIG7 , the thickness of the metal thin film layer 8 is 8 nm. The metal thin film layer 8 is a nickel metal film layer.

[0164] The metal film layer 8 is obtained by magnetron sputtering. The specific process is as follows: the battery cell obtained in S106 is placed in the magnetron sputtering equipment, and the vacuum is evacuated to a vacuum degree of 5×10-2Pa. The sputtering power of the nickel target is set to 2.4kW, and sputtering is performed for 34s to obtain a nickel metal film with a thickness of 8nm.

[0165] S3. The intermediate product obtained in S2 is subjected to heat treatment in an oxygen-free environment to allow the metal of the metal film layer 8 to react with the silicon in the contacting doped amorphous silicon layer or doped polycrystalline silicon layer to form a nickel-silicon alloy layer 7; as shown in FIG7 ; the nickel-silicon alloy layer 7 has a thickness of 8 nm and a sheet resistance of 35 Ω / □.

[0166] The nickel-silicon alloy layer 7 contains nickel silicide (NiSi2, NiSi) and doping element phosphorus with an effective doping concentration of 5e17 cm-3; the heat treatment method is: annealing at 150°C for 20 minutes in an oxygen-free environment.

[0167] S4. Then, a third etching is performed on the portion of the nickel-silicon alloy layer 7 between the second opening area and the first opening area on the back side obtained in S3, as shown in FIG8 , to form an insulating groove 9 with a width of 0.05 mm; the third etching adopts laser technology, and the laser pulse width is 10 picoseconds.

[0168] Example 2

[0169] The process was carried out in accordance with Example 1, differing only in the heat treatment process of S3, which was a rapid photothermal treatment performed at 300°C in an oxygen-free environment for 30 seconds using laser irradiation. In this example, the resulting nickel-silicon alloy layer had a thickness of 8 nm, a sheet resistance of 37 Ω / □, and an effective doping concentration of 1e17 cm⁻³.

[0170] Example 3

[0171] Refer to Example 1. The only difference from Example 1 is that the metal film layer in S2 is obtained by evaporation and has the same thickness as that in Example 1. The specific process is as follows: the evaporation vacuum degree is 5×10-2Pa, the evaporation heating power is 8kW, and the evaporation time is 60s.

[0172] Example 4

[0173] The process is carried out with reference to Example 1. The only difference from Example 1 is that the metal film layer in S2 is an aluminum metal film layer, and the preparation process of the aluminum metal film layer is as follows: the vacuum degree remains unchanged according to Example 1, and the sputtering power of the aluminum target is set to 2.4kW; sputtering is performed for 30s; and an aluminum metal film with a thickness of 8nm is obtained; an aluminum-silicon alloy layer is correspondingly obtained in S3, and the thickness of the aluminum-silicon alloy layer is 8nm, the square resistance is 42Ω / □, and the effective doping concentration is 5e17cm-3.

[0174] Example 5

[0175] The process was carried out with reference to Example 1. The only difference from Example 1 was that the metal film layer in S2 was a platinum metal film layer. The preparation process of the platinum metal film layer was as follows: the vacuum degree remained unchanged according to Example 1, the sputtering power of the platinum target was set to 2.5 kW; sputtering was performed for 30 seconds; a platinum metal film with a thickness of 8 nm was obtained; and a platinum-silicon alloy layer was correspondingly obtained in S3. The platinum-silicon alloy layer had a thickness of 8 nm, a sheet resistance of 40 Ω / □, and an effective doping concentration of 5e17 cm-3.

[0176] Example 6

[0177] The process is carried out with reference to Example 1. The only difference from Example 1 is that in S105 , the doped amorphous silicon layer in the second semiconductor layer is replaced by a doped microcrystalline silicon layer. The thickness of the doped microcrystalline silicon layer is 10 nm.

[0178] Example 7

[0179] The method is carried out with reference to Example 1. The only difference from Example 1 is that the structure of the second semiconductor layer in S1 is different. It is formed by the second doped silicon crystal layer 6 and the first tunneling oxide layer 2 in the corresponding region. As shown in FIG9 , S1 is specifically:

[0180] S11, providing a silicon wafer 1;

[0181] S12. First, a front passivation layer (which is the same as that in Example 1) and an anti-reflection layer (which is the same as that in Example 1) are sequentially formed on the front side of the silicon wafer 1 to form a front stack 3. Then, a first semiconductor layer and a mask layer are sequentially formed on the back side of the silicon wafer 1. The first semiconductor layer includes a first tunneling oxide layer 2 and a first doped polycrystalline layer 4 sequentially formed on the back side.

[0182] S13, performing a first etching on the first doped polycrystalline layer 4 and the mask layer in the preset area on the back side obtained in S12 to form first opening areas distributed at intervals;

[0183] S14, then removing all remaining mask layers;

[0184] S15, then forming a second doped silicon crystal layer 6 on the back surface obtained in S14, the second doped silicon crystal layer 6 and the portion of the first tunnel oxide layer 2 covered by the second doped silicon crystal layer 6 forming a second semiconductor layer;

[0185] S16. Then, a second etching is performed on the area of ​​the back surface obtained in S15 where the first semiconductor layer remains, to expose a portion of the first semiconductor layer, thereby forming a second opening region spaced apart from the first opening region. The thickness (or doping concentration) of each corresponding layer is the same as in Example 1, with only the structure being different.

[0186] Example 8

[0187] Refer to Example 1. The only difference from Example 1 is that the thickness of the silicon alloy layer is controlled to be 19 nm. To meet this thickness, the process conditions need to be adjusted: the sputtering power of the nickel target is set to 4 kW; sputtering is performed for 40 seconds; and a nickel metal film with a thickness of 20 nm is obtained.

[0188] Example 9

[0189] The process is carried out with reference to Example 1. The only difference from Example 1 is that the effective doping concentration of the first doped polycrystalline layer in S102 is adjusted to 5e19 cm-3, so that the ratio of the surface doping index of the silicon alloy layer to the first doped polycrystalline layer is 1:10.

[0190] Example 10

[0191] The process is carried out with reference to Example 1. The only difference from Example 1 is that the thickness of the first doped polycrystalline layer in S102 is adjusted to 300 nm, so that the ratio of the surface doping index of the silicon alloy layer to the first doped polycrystalline layer is 1:5.3.

[0192] Example 11

[0193] The process is carried out with reference to Example 1. The only difference from Example 1 is that the effective doping concentration of the second doped silicon crystal layer in S105 is adjusted to 1e19 cm-3, so that the ratio of the surface doping index of the silicon alloy layer to the second doped silicon crystal layer is 1:16.

[0194] Example 12

[0195] The process is carried out with reference to Example 1. The only difference from Example 1 is that the thickness of the second doped silicon crystal layer in S105 is adjusted to 50 nm, so that the ratio of the surface doping index of the silicon alloy layer to the second doped silicon crystal layer is 1:32.

[0196] Example 13

[0197] The process is carried out with reference to Example 1. The only difference from Example 1 is that the thickness of the first tunneling oxide layer in S102 is adjusted to 1 nm, so that the ratio of the thickness of the silicon alloy layer to the first tunneling oxide layer is 1:0.125.

[0198] Example 14

[0199] The process is carried out with reference to Example 1, with the only difference from Example 1 being that the width of the insulating groove in S4 is 0.15 mm.

[0200] Example 15

[0201] The process is carried out with reference to Example 1. The only difference from Example 1 is that the sputtering power in the magnetron sputtering of the metal film layer in S2 is 5 kW, and a nickel metal film with a thickness of 20 nm is obtained under this condition; the nickel-silicon alloy layer obtained after the heat treatment in S3 has a thickness of 20 nm, a sheet resistance of 30 Ω / □, and an effective doping concentration of 1e18 cm-3.

[0202] Example 16

[0203] The process was carried out with reference to Example 1. The only difference from Example 1 was that the annealing temperature in the heat treatment in S3 was 180°C, and the annealing time was the same as the heat treatment time in Example 1. Under these conditions, the nickel-silicon alloy layer obtained had a thickness of 8 nm, a sheet resistance of 40 Ω / □, and an effective doping concentration of 6e17 cm-3.

[0204] Example 17

[0205] Refer to Example 1, and the only difference from Example 1 is that the third etching described in S4 adopts wet etching. The specific process of wet etching is: using printed protective ink to form an insulating groove mask pattern on the back side to expose the area where the insulating groove is required to be formed, and then using a corrosive solution to corrode the exposed conductive film layer to form an insulating groove, and then using an alkaline solution (whose composition is specifically sodium hydroxide solution with a concentration of 2wt%) to remove the protective ink.

[0206] Example 18

[0207] The process is carried out with reference to Example 1. The only difference from Example 1 is that the first semiconductor layer in S102 is replaced by a first intrinsic amorphous silicon layer and an N-type first doped amorphous silicon layer formed in sequence on the back side; the thickness of the first intrinsic amorphous silicon layer and the N-type first doped amorphous silicon layer are both 10 nm, and the effective doping concentration of the first doped amorphous silicon layer is the same as the first doped polycrystalline layer in Example 1.

[0208] Example 19

[0209] The method of Example 1 is referred to, except that S104 is not performed, that is, part of the mask layer is retained.

[0210] Comparative Example 1

[0211] The process is carried out with reference to Example 1. The only difference from Example 1 is that S2-S3 are not performed, but a traditional conductive film layer and metal fine grid lines are used. Specifically, the following steps are performed:

[0212] S01. After S1, a transparent conductive film layer (ITO) is laid on the first semiconductor layer and the second semiconductor layer in sequence to fully cover the outside. The thickness of the transparent conductive film layer is 100 nm.

[0213] S02. Then, a third etching is performed on the transparent conductive film layer portion on the back side located in the transition area between the second opening area and the first opening area by wet etching to form an insulating groove 9 (the width is the same as that in Example 1), that is, wet grooving; the specific process of wet etching is: using printed protective ink to form an insulating groove mask pattern on the back side to expose the area where the insulating groove is required to be formed, and then using a corrosive solution to corrode the exposed conductive film layer to form an insulating groove 9, and then using an alkaline solution (whose composition is specifically sodium hydroxide solution with a concentration of 2wt%) to remove the protective ink.

[0214] S03, forming metal fine gate lines (i.e., first fine gate 13 and second fine gate 14) on the second opening region and the corresponding region of the first opening region, respectively. The metal fine gate lines are arranged parallel to the first semiconductor layer and the second semiconductor layer and parallel to the X-axis direction of the silicon wafer;

[0215] Then proceed to the following steps S5-S6:

[0216] S5. Alternately prepare an insulating layer 12 on the surface of the first opening area and the surface of the second opening area; the insulating layer 12 is prepared by printing insulating ink in a screen printing manner.

[0217] S6. Prepare the first busbar 10 and the second busbar 11 along the Y-axis direction in the lateral direction where the insulating layer 12 is provided, as shown in FIG10 . The preparation process is screen printing of silver busbars.

[0218] Comparative Example 2

[0219] The process is carried out with reference to Comparative Example 1. The only difference from Comparative Example 1 is that the insulating groove is etched using laser, specifically ultraviolet laser with a pulse width of 10 ns.

[0220] Comparative Example 3

[0221] The process is carried out with reference to Example 1. The only difference from Example 1 is that the heat treatment of S3 is not performed. In this solution, only a metal nickel film layer is plated without forming a metal silicide. The square resistance of the metal nickel film layer is 55Ω / □.

[0222] Test Case

[0223] The back-contact cells obtained in the above examples and comparative examples were subjected to battery performance testing after welding electrode wires. Specifically, solder paste was used to solder the outer surfaces of the P-pole region formed in the region of the first semiconductor opening and the N-pole region formed in the region of the second semiconductor opening, using the same method used for electrode assembly packaging. The soldering tapes were made of copper or aluminum (copper was used in this test example). The results of the performance tests are shown in Table 1.

[0224] Comparison of process flow (also called manufacturing process):

[0225] The process flow adopted in the embodiment (8 steps): texturing and cleaning to form a double-sided polished silicon wafer → first semiconductor layer deposition → first etching opening → second semiconductor layer deposition → second etching opening → deposition of metal film layer → heat treatment to form a silicon alloy layer → second etching to form an insulating groove.

[0226] Comparative Example 1 process flow (10 steps): texturing and cleaning to form a double-sided polished silicon wafer → deposition of the first semiconductor layer → first etching opening → deposition of the second semiconductor layer → second etching opening → deposition of the conductive film layer ITO → grooving of the insulating groove → screen printing of fine grid → brushing of insulating ink → screen printing of the main grid.

[0227] Non-silicon costs refer to the costs of cell production other than silicon wafers, specifically including silver paste, target materials, chemicals, gases, depreciation, and others. The calculation was based on a preliminary estimate of the non-silicon costs of conventional back-contact cell production in Comparative Example 1. In Comparative Example 1, silver paste accounted for 39% of the non-silicon costs, and target materials accounted for 7%. Because the present disclosure uses common metal targets, which are cheaper and require less than ITO targets, the target material costs in the present disclosure are calculated as 4% of the non-silicon costs.

[0228] Table 1

[0229] The above results show that compared to the comparative examples, the embodiments of the present disclosure achieve a simpler manufacturing process and eliminate the need for expensive low-temperature silver paste and transparent conductive film layers, significantly reducing battery production costs while maintaining excellent battery conversion efficiency. In contrast, the conventional structures of Comparative Examples 1-2 have long manufacturing processes and high production costs, and the battery conversion efficiency of Comparative Example 3 is significantly lower.

[0230] Optionally, according to Example 1 and Examples 2-19, it can be seen that the use of the optional structure or process solution disclosed in the present invention can further improve the battery conversion efficiency while ensuring a short process and low production cost.

[0231] The above describes in detail the optional embodiments of the present disclosure, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure can be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as the contents disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0232] The present disclosure adopts the above-mentioned technical solution, especially adopts a silicon alloy layer containing metal silicide with a specific conductivity as an electrode lead-out method, replacing the electrode lead-out method of the conventional back-contact battery which combines a transparent conductive film layer with silver metal fine grid lines. The process is simpler and there is no need to use expensive low-temperature silver paste and transparent conductive film layer (such as ITO), which greatly reduces the production cost of the battery while ensuring excellent battery conversion efficiency.

Claims

1. A back-contact battery, comprising a silicon wafer having a front side and a back side, a first semiconductor layer and a second semiconductor layer disposed on the back side and alternately arranged along the Y-axis direction of the silicon wafer, the first semiconductor layer comprising a first doped silicon crystal layer, the second semiconductor layer comprising a second doped silicon crystal layer, and an end portion of the second semiconductor layer extending to an outer surface of an end portion of an adjacent first semiconductor layer to form a transition region, characterized in that, The back contact battery further includes a silicon alloy layer containing metal silicide disposed outward along the Z-axis direction. The silicon alloy layer is disposed on the outer surface of the second semiconductor layer and extends to the outer surface of the adjacent first doped silicon crystal layer, and an insulating groove is formed in a part of the silicon alloy layer corresponding to the transition region; wherein, the sheet resistance of the silicon alloy layer is 2. The back contact battery according to claim 1, characterized in that, The metal elements contained in the metal silicide include at least one of nickel, aluminum, platinum, cobalt, titanium, and tungsten.

3. The back contact battery according to claim 2, characterized in that, The metal silicide includes at least one of nickel silicide, aluminum silicide, and platinum silicide.

4. The back-contact battery according to any one of claims 1 to 3, characterized in that, The thickness of the silicon alloy layer is 2 - 30 nm.

5. The back contact battery according to any one of claims 1 to 4, characterized in that, The silicon alloy layer further contains doping elements, and the doping elements include boron or phosphorus.

6. The back-contact battery according to claim 5, characterized in that, The surface doping index ratio of the silicon alloy layer to the first doped silicon crystal layer and the second doped silicon crystal layer is 1:1 - 250:3 - 800, where the surface doping index is the ratio of the effective doping concentration of the corresponding doped silicon layer to the thickness of the doped silicon layer.

7. The back-contact battery according to claim 6, characterized in that, The effective doping concentration of the silicon alloy layer is 1e17 cm-3 - 1e18 cm-3; and / or The thickness of the first doped silicon crystal layer is 50 - 300 nm, and the effective doping concentration is 1e19 cm-3 - 4e20 cm-3. The thickness of the second doped silicon crystal layer is 10 - 50 nm, and the effective doping concentration is 1e19 cm-3 - 4e20 cm-3.

8. The back-contact battery according to any one of claims 1 to 7, characterized in that, The first semiconductor layer further includes a first passivation layer provided on the back surface of the silicon wafer, and at least a part of the first passivation layer is located between the back surface of the silicon wafer and the first doped silicon crystal layer.

9. The back-contact battery according to claim 8, characterized in that, The second semiconductor layer further includes a second passivation layer provided on the back surface of the silicon wafer. The second passivation layer is located between the back surface of the silicon wafer and the second doped silicon crystal layer; the second passivation layer includes an intrinsic amorphous silicon layer or a second tunneling oxide layer. The thickness of the intrinsic amorphous silicon layer is 5 - 15 nm, and the thickness of the second tunneling oxide layer is 1.5 - 2.5 nm; Or The first passivation layer is provided to completely cover the back surface of the silicon wafer, and both the first doped silicon crystal layer and the second doped silicon crystal layer are located on the side of the first passivation layer away from the back surface of the silicon wafer. The second doped silicon crystal layer and the covered part of the first passivation layer form the second semiconductor layer, and both the first doped silicon crystal layer and the second doped silicon crystal layer are doped polycrystalline layers.

10. The back contact battery according to claim 8, wherein, The first passivation layer includes a first tunneling oxide layer, and the first doped silicon crystal layer is a first doped polycrystalline layer; where The thickness ratio of the silicon alloy layer to the first tunneling oxide layer is 1:0.05 - 1.25, and / or the thickness of the first tunneling oxide layer is 1.5 - 2.5 nm.

11. The back-contact battery according to any one of claims 1 to 10, characterized in that, In the transition region, the extension end of the second semiconductor layer is in direct contact with the first semiconductor layer in the thickness direction or a mask layer is provided. and / or The width of the insulating groove is 0.03 - 0.15 mm.

12. The back-contact battery according to any one of claims 1 to 11, characterized in that, The back contact battery does not have fine grids and main grids. and / or The back contact battery further includes a front passivation layer provided on the front surface of the silicon wafer, where the front passivation layer is any one of intrinsic amorphous silicon, intrinsic amorphous silicon superimposed with doped amorphous silicon, intrinsic amorphous silicon superimposed with doped microcrystalline silicon, tunneling silicon oxide, and tunneling silicon oxide superimposed with doped polycrystalline silicon.

13. A method for preparing a back-contact battery, characterized in that, Comprising the following steps: S1. Form a first semiconductor layer on the back surface of the silicon wafer, and spaced-apart first opening regions are formed along the Y-axis direction of the silicon wafer on the first semiconductor layer; then form a second semiconductor layer on the back surface, and a second opening region is formed on the portion of the second semiconductor covering the outer surface of the first semiconductor; wherein, the first semiconductor layer includes a first doped silicon crystal layer, and the second semiconductor layer includes a second doped silicon crystal layer; S2. Form a metal thin film layer on the back surface obtained in S1; S3. Then, perform heat treatment in an oxygen-free environment to cause the metal in the metal thin film layer to react with the silicon in the corresponding doped silicon crystal layer in contact therewith to form a silicon alloy layer, and control the sheet resistance of the silicon alloy layer to be S4. Perform a third etching on the portion of the silicon alloy layer located between the first opening region and the second opening region to form an insulating groove.

14. The preparation method of the back-contact battery according to claim 13, wherein, The thickness of the metal thin film layer is 5 - 20 nm; and / or The metal thin film layer is at least one of a nickel metal film layer, an aluminum metal film layer, a platinum metal film layer, a cobalt metal film layer, a titanium metal film layer, a tungsten metal film layer, a nickel-containing alloy metal film, an aluminum-containing alloy metal film, a platinum-containing alloy metal film, a cobalt-containing alloy metal film layer, a titanium-containing alloy metal film, and a tungsten-containing alloy metal film; and / or The metal thin film layer in S2 is obtained by magnetron sputtering or evaporation coating, and the conditions of the magnetron sputtering include : the vacuum degree is 5×10−3 Pa - 5×10−1 Pa, the sputtering power is 2 - 5 kW, and the sputtering time is 30 - 90 s; The conditions of the evaporation coating include: the vacuum degree is 5×10−3 Pa - 5×10−1 Pa, the evaporation heating power is 5 - 10 kW, and the evaporation time is 30 - 120 s.

15. The method for preparing a back-contact battery according to claim 13 or 14, characterized in that, The process of heat treatment in an oxygen-free environment in S3 includes: In an oxygen-free environment, laser irradiation is carried out at 300 - 350 °C for 5 - 60 s for rapid photo-thermal treatment; Or, in an oxygen-free environment, annealing treatment is carried out at 100 - 220 °C for 5 - 30 min.

16. The preparation method of the back-contact battery according to any one of claims 13 to 15, characterized in that, The third etching in S4 uses laser technology, and the laser used is a laser with a picosecond-level pulse width.

17. The method for preparing a back-contact battery according to any one of claims 13 to 16, characterized in that, The process of S1 specifically includes: S101. Provide a silicon wafer; S102. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer formed in sequence on the back surface; S103. Perform a first etching on the first semiconductor layer and the mask layer in a preset area on the back surface obtained in S102 to form spaced-apart first opening regions; S104. Then remove all the remaining mask layers; S105. Then form a second semiconductor layer on the back surface obtained in S104. The second semiconductor layer includes a second passivation layer and a second doped silicon crystal layer formed in sequence on the back surface; S106. Then perform a second etching on the area of the back surface obtained in S105 where the first semiconductor layer remains to expose the first semiconductor layer and form second opening regions arranged at intervals with the first opening regions.

18. The preparation method of the back-contact battery according to any one of claims 13 to 17, characterized in that, The process of S1 specifically includes: S11. Provide a silicon wafer; S12. Sequentially form a first semiconductor layer and a mask layer on the back surface of the silicon wafer. The first semiconductor layer includes a first passivation layer and a first doped silicon crystal layer formed in sequence on the back surface; S13. Perform a first etching on the first doped silicon crystal layer and the mask layer in a preset area on the back surface obtained in S12 to form spaced-apart first opening regions; S14. Then remove all the remaining mask layers; S15. Then, a second doped silicon crystal layer is formed on the back surface obtained in S14, and the second doped silicon crystal layer and a part of the first passivation layer covered thereby form a second semiconductor layer; S16. Then, a second etching is performed on the region of the back surface obtained in S15 where the first semiconductor layer remains, to expose a part of the first semiconductor layer, and a second opening region arranged at intervals with the first opening region is formed.

19. A back-contact battery, characterized in that, It is obtained by the method for manufacturing a back-contact battery according to any one of claims 13 to 18.

20. A battery assembly, characterized in that, It includes a back-contact battery according to any one of claims 1 to 12, or includes the back-contact battery according to claim 19, and a solder strip directly disposed on the surface of a silicon alloy layer corresponding to different conductive regions in the back-contact battery.

Images