Time synchronization method and apparatus for chip, and electronic device and storage medium

Abstract

Disclosed in the embodiments of the present disclosure are a time synchronization method and apparatus for a chip, and an electronic device and a storage medium. The method comprises: generating a pulse signal according to a preset cycle; in response to the pulse signal, capturing a time snapshot of at least one timer in at least one chip, wherein the time snapshot represents time information of the timer when a preset state of the pulse signal occurs; and on the basis of time snapshots of all the timers, performing time synchronization on the timers in the at least one chip. The embodiments of the present disclosure can realize, on the basis of unified time snapshots, time synchronization between a plurality of chips and between timers corresponding to a plurality of processor cores in a chip. Time snapshots can be completely captured by hardware without software involvement, so that the introduction of errors and delay can be effectively reduced, thereby improving the accuracy of time synchronization.

Description

Chip time synchronization method, device, electronic device and storage medium

[0001] This disclosure claims priority to Chinese patent application number CN202410083732.5 filed with the State Intellectual Property Office on January 19, 2024, entitled “Chip time synchronization method, device, electronic device and storage medium,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0002] The present disclosure relates to the field of computer-assisted driving technology, and in particular to a chip time synchronization method, device, electronic device, and storage medium. Background Art

[0003] Time synchronization is fundamental to sensor data fusion in scenarios like intelligent driving. Time synchronization typically involves two key steps: measuring time errors and adjusting time. Measuring time errors typically involves measuring the time difference between a slave clock and a master clock, while adjusting time typically involves compensating the slave clock's time based on the time difference to achieve synchronization between the slave and master clocks. System-on-chips (SoCs) typically include multiple hardware timers, such as real-time clocks (RTCs), hardware timers within Ethernet cards, and hardware timers in Peripheral Component Interconnect Express (PCIE) modules. These hardware timers maintain the time of their corresponding modules. Within a chip, these hardware timers are typically distributed across one or more core domains. Each core domain includes a processor core (referred to as a core) and at least one hardware timer corresponding to that core. Software on one processor core cannot access the hardware timer corresponding to another processor core. Using multi-level synchronization to synchronize the hardware timers corresponding to multiple processor cores within a single chip can easily introduce significant latency.

[0004] Summary of the Invention

[0005] The embodiments of the present disclosure provide a chip time synchronization method, device, electronic device, and storage medium, which can effectively avoid or reduce the introduction of delays and improve the accuracy of time synchronization.

[0006] One aspect of an embodiment of the present disclosure provides a chip time synchronization method, comprising: generating a pulse signal according to a preset period; capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal, the time snapshot representing time information of the timer in a preset state of the pulse signal; and performing time synchronization on each timer in the at least one chip based on the time snapshot of each timer.

[0007] Another aspect of an embodiment of the present disclosure provides a chip time synchronization device, including: a pulse signal generating module, for generating a pulse signal according to a preset period; a time snapshot capturing module, for capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal, wherein the time snapshot represents time information of the timer in a preset state of the pulse signal; and a time synchronization module, for performing time synchronization on each timer in the at least one chip based on the time snapshot of each timer.

[0008] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the chip time synchronization method described in any of the above embodiments of the present disclosure.

[0009] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a processor; a memory for storing instructions executable by the processor; the processor for reading the executable instructions from the memory and executing the instructions to implement the chip time synchronization method described in any of the above embodiments of the present disclosure; or, the electronic device comprises the chip time synchronization device provided in any of the above embodiments.

[0010] Another aspect of the embodiments of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the chip time synchronization method provided by any of the above embodiments of the present disclosure is executed.

[0011] Based on the methods, devices, electronic devices and storage media provided in the above embodiments of the present disclosure, a time snapshot of at least one hardware timer in at least one chip can be captured based on a periodic pulse signal trigger, and then time synchronization of each timer can be achieved based on the time snapshot, so that time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip can be achieved based on a unified time snapshot. Since the time snapshot can be completely captured by hardware without the need for software participation, the introduction of errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is an exemplary application scenario of the chip time synchronization method provided by the present disclosure;

[0013] FIG2 is a schematic flow chart of a chip time synchronization method provided by an exemplary embodiment of the present disclosure;

[0014] FIG3 is a schematic flow chart of a chip time synchronization method provided by another exemplary embodiment of the present disclosure;

[0015] FIG4 is a schematic diagram of time snapshots of different timers provided by an exemplary embodiment of the present disclosure;

[0016] FIG5 is a schematic flow chart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure;

[0017] FIG6 is a schematic flow chart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure;

[0018] FIG7 is a schematic flow chart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure;

[0019] FIG8 is a schematic diagram showing the principle of a chip time synchronization method provided by an exemplary embodiment of the present disclosure;

[0020] FIG9 is a schematic flow chart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure;

[0021] FIG10 is a schematic flow chart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure;

[0022] FIG11 is a schematic diagram showing the principle of a chip time synchronization method provided by another exemplary embodiment of the present disclosure;

[0023] FIG12 is a schematic structural diagram of a chip time synchronization device provided by an exemplary embodiment of the present disclosure;

[0024] FIG13 is a schematic structural diagram of a chip time synchronization device provided by another exemplary embodiment of the present disclosure;

[0025] FIG14 is a schematic structural diagram of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure;

[0026] FIG15 is a schematic structural diagram of a chip time synchronization device provided by another exemplary embodiment of the present disclosure;

[0027] FIG16 is a schematic structural diagram of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure;

[0028] FIG17 is a schematic structural diagram of a chip time synchronization device provided by another exemplary embodiment of the present disclosure;

[0029] FIG18 is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0031] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0032] Overview of the Disclosure

[0033] In the process of implementing the present disclosure, the inventors discovered that time synchronization is the basis for sensor data fusion in scenarios such as intelligent driving. Time synchronization generally includes two key steps: measuring time error and adjusting time. Among them, measuring time error generally involves measuring the time difference between the slave clock and the master clock, and adjusting time generally involves compensating the slave clock time based on the time difference to achieve time synchronization between the slave clock and the master clock. A system-on-chip (SoC) generally includes multiple hardware timers, such as a real-time clock (RTC), a hardware timer inside an Ethernet card (which can be referred to as a network card timer), a hardware timer of a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) module (which can be referred to as a PCIE timer), etc. These hardware timers maintain the time of the corresponding modules. For a chip, these hardware timers are generally distributed in one or more core domains (Core Domain) of the chip. Each core domain can include a processor core (processor core can be referred to as a core) and at least one hardware timer corresponding to the core. Software on one processor core cannot access the hardware timer corresponding to another processor core. If the hardware timers corresponding to multiple processor cores in a single chip are synchronized through multi-level synchronization, large delays are likely to be introduced.

[0034] Exemplary Overview

[0035] FIG1 is an exemplary application scenario of the chip time synchronization method provided by the present disclosure. As shown in FIG1 , in a scenario where time synchronization of at least one chip (SOC) is required, such as scenarios such as autonomous driving and assisted driving, FIG1 takes three chips (including SOC1, SOC2 and SOC3) as an example. Each chip may include one or more core domains, including CORE1 Domain, CORE2 Domain, ..., and each core domain may include a core and one or more timers corresponding to the core. For example, a core domain may include a core (such as CORE1 in the figure), a network card timer, a PCIE timer, etc. Using the chip time synchronization method disclosed in the present disclosure, a pulse signal can be generated by any chip in the at least one chip (such as SOC1) according to a preset period; in response to the pulse signal, a time snapshot of at least one timer in the at least one chip is captured, and the time snapshot represents the time information of the timer in the preset state of the pulse signal; based on the time snapshot of each timer, time synchronization is performed on each timer in the at least one chip. The present disclosure can achieve time synchronization between multiple chips and between timers corresponding to multiple processor cores within a chip based on a unified time snapshot. Since the time snapshot can be completely captured by hardware without the need for software participation, it can effectively reduce the introduction of errors and delays and improve the accuracy of time synchronization.

[0036] The chip time synchronization method disclosed in the present invention is not limited to application in intelligent driving scenarios, but can also be applied to any other scenarios requiring chip time synchronization, without limitation to the specific scenarios.

[0037] Exemplary Methods

[0038] FIG2 is a flow chart of a chip time synchronization method provided by an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, such as an in-vehicle computing platform. As shown in FIG2 , the method of the embodiment of the present disclosure may include the following steps:

[0039] Step 201: Generate a pulse signal according to a preset period.

[0040] Among them, the preset period can be any period, for example, the preset period can be 1 second, 2 seconds, 5 seconds, etc., or the preset period can be 1 millisecond, 2 milliseconds, 4 milliseconds, etc., or the preset period can be 1 microsecond, 2 microseconds, 4 microseconds, etc. The specific preset period and the time magnitude of the period can be set according to actual needs.

[0041] In some optional embodiments, the pulse signal may include a high level (or 1) signal and a low level (or 0) signal.

[0042] In some optional embodiments, the pulse signal can be generated by any applicable pulse signal generating circuit. For example, the pulse signal generating circuit can be provided in any timer circuit, and the pulse signal generating circuit triggers the generation of a pulse signal when the timer reaches a preset period, for example, converting a low-level signal into a high-level signal.

[0043] In some optional embodiments, a common timer may be provided in any chip to generate a pulse signal through the common timer.

[0044] In some optional examples, step 201 may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a hardware circuit of a pulse signal generating module.

[0045] Step 202 : In response to the pulse signal, capture a time snapshot of at least one timer in at least one chip, where the time snapshot represents time information of the timer in a preset state of the pulse signal.

[0046] At least one chip is to be time-synchronized. The number of chips can be set according to actual needs. Each chip can include at least one timer, such as the aforementioned real-time clock, network card timer, PCIE timer, etc.

[0047] In some optional embodiments, for any timer, the timer's hardware circuitry can capture a time snapshot of the timer in response to a pulse signal. For example, the timer's hardware circuitry can capture a time snapshot of the timer in response to a pulse signal in a preset state, and the time snapshot can be written to a register to facilitate subsequent time synchronization. The preset state can be the rising edge of the pulse signal, i.e., the state at which the pulse signal changes from a low level to a high level.

[0048] In some optional examples, step 202 may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a hardware circuit of a time snapshot capturing module.

[0049] Step 203: Time synchronization is performed on each timer in at least one chip based on the time snapshot of each timer.

[0050] After capturing a time snapshot for each timer, each timer to be synchronized can be synchronized based on the time synchronization requirements. For example, one timer, Timer A, can be used as the master clock (or master time), and the times of all other timers in each timer, except Timer A, can be synchronized with Timer A. Another example is to use multiple timers in each timer as master clocks, and synchronize the other timers with the corresponding master clocks to form multiple time domains. The specific time synchronization method can be set according to actual needs.

[0051] In some optional embodiments, for time synchronization of multiple timers within a chip, a preset timer within the chip can be used as a master clock, and other timers within the chip except the preset timer can be used as slave clocks (or slave times), and the times of other timers can be adjusted to synchronize the time of other timers with the preset timer.

[0052] In some optional embodiments, for time synchronization of multiple chips, each chip may include one or more timers. A preset chip among the multiple chips may be used as a master chip, the preset timer in the master chip may be used as a master clock, and other timers in the master chip other than the preset timer and timers in other chips among the multiple chips other than the preset chip may be used as slave clocks. The slave clocks may be adjusted based on the time difference between a time snapshot of the slave clock and a time snapshot of the master clock to achieve time synchronization between the slave clock and the master clock. Alternatively, multiple timers in the master chip may be used as master clocks, and other timers may be synchronized with the corresponding master clocks, forming multiple time domains. For example, the network card timer and PCIE timer corresponding to the preset core of the master chip may be used as master clocks, the network card timer corresponding to other cores in the master chip and the network card timer of other chips may be synchronized with the network card timer corresponding to the preset core of the master chip, and the PCIE timers corresponding to other cores in the master chip and the PCIE timers of other chips may be synchronized with the PCIE timer corresponding to the preset core of the master chip, thereby forming two time domains: the network card time domain and the PCIE time domain. The specific number of time domains can be set according to actual synchronization requirements.

[0053] In some optional embodiments of the present disclosure, for time synchronization of timers, a time snapshot of a timer serving as a master clock and a time snapshot of a timer serving as a slave clock may be obtained by the processor of the chip, and based on the time snapshot of the master clock and the time snapshot of the slave clock, the timer of the slave clock may be time-adjusted to achieve the purpose of time synchronization. In the case where the chip processor includes multiple cores, for the timer corresponding to each core, the core may obtain a time snapshot of the master clock and a time snapshot of the slave clock corresponding to the core, and then the timer of the slave clock may be time-adjusted based on the time snapshot of the master clock and the time snapshot of the slave clock to achieve the purpose of time synchronization. Optionally, the processor of the chip or each core in the processor may implement time adjustment of the timer of the slave clock based on the time snapshot of the master clock and the time snapshot of the slave clock by executing a time synchronization software program, so that the timer of the slave clock is synchronized with the timer of the corresponding master clock.

[0054] In some optional examples, step 203 may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a time synchronization module.

[0055] The chip time synchronization method provided in this embodiment can capture a time snapshot of at least one hardware timer in at least one chip based on a periodic pulse signal trigger, and then realize time synchronization of each timer based on the time snapshot, so that time synchronization between multiple chips and between timers corresponding to multiple processor cores in a chip can be realized based on a unified time snapshot. Since the time snapshot can be completely captured by hardware without the participation of software, the introduction of errors and delays can be effectively reduced, and the accuracy of time synchronization can be improved.

[0056] FIG3 is a schematic flow chart of a chip time synchronization method provided by another exemplary embodiment of the present disclosure.

[0057] In some optional embodiments, as shown in FIG3 , step 202 of capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal may include:

[0058] Step 2021: transmit the pulse signal to each timer in at least one chip, so that each timer responds to the pulse signal and writes the time snapshot corresponding to each timer into the corresponding register.

[0059] The generated pulse signal can be transmitted to each timer in each chip to trigger each timer to capture its own time snapshot and write the time snapshot into a corresponding register.

[0060] In some optional embodiments, the pulse signal can be transmitted to each timer in each chip using any feasible method. For example, the pulse signal output terminal of the timer that generates the pulse signal can be connected to the time snapshot capture circuit of each timer in each chip. The pulse signal output terminal can also be connected to the time snapshot capture circuit of the timer that generates the pulse signal. When the pulse signal enters a preset state, the time snapshot capture circuit of each timer is triggered to capture the time information of the timer in the preset state of the pulse signal as the time snapshot of the timer. A register for storing the time snapshot of the timer can be set for each timer, and the captured time snapshot can be written to the register for storage.

[0061] In some optional examples, step 2021 can be executed by the processor calling the corresponding instructions stored in the memory, or can be implemented by hardware circuits such as the pulse signal transmission unit, the capture unit, and the register.

[0062] Step 2022: Obtain a time snapshot of each timer from the register corresponding to each timer.

[0063] The processor of each chip (or each core in the processor) can obtain a time snapshot of the timer as the master time and a time snapshot of the timer in the processor as the slave time from the register corresponding to the timer.

[0064] In some optional embodiments, the register may be set inside or outside the timer, and the register may be connected to a time snapshot capture circuit of the timer to facilitate the time snapshot capture circuit to write the time snapshot into the register.

[0065] In some optional examples, step 2022 may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a snapshot acquisition unit executed by the processor.

[0066] This embodiment transmits a pulse signal to each timer, triggering each timer to capture a time snapshot at the same time, and can write the time snapshot into a register, thereby facilitating recording of the time information of each timer at the same moment, and facilitating accurate measurement of the time difference between the master timer and the slave timer, without the need to consider delay compensation, thereby helping to improve the accuracy of time synchronization.

[0067] In some optional embodiments, FIG4 is a schematic diagram of time snapshots of different timers provided by an exemplary embodiment of the present disclosure. As shown in FIG4 , timer A and timer B are two timers, T0 is a time snapshot captured by the hardware (capture circuit) of timer A, and T1 represents a time snapshot captured by the hardware of timer B. At the rising edge of the pulse signal (i.e., the preset state), the hardware of timer A and timer B simultaneously captures the time snapshot, and the obtained T0 and T1 represent the time information of timer A and timer B at the same moment (i.e., the rising edge of the pulse signal). The time difference can be calculated by subtracting T1 from T0, which can be used for time synchronization between timer B and timer A. Based on this, after obtaining the time snapshots of each timer, the time difference between the timer as the master time and the timer as the slave time can be calculated according to the actual synchronization requirements, so as to perform time compensation on the timer as the slave time and realize time synchronization between the slave time timer and the master time timer.

[0068] In some optional embodiments, obtaining a time snapshot of each timer from a register corresponding to each timer in step 2022 may include:

[0069] An interrupt request is detected, where the interrupt request is triggered based on a pulse signal or based on a register corresponding to each timer; in response to detecting the interrupt request, a time snapshot of each timer is obtained from the register corresponding to each timer.

[0070] In this case, the processor of each chip (or each core within the processor) can detect an interrupt request. The interrupt request can be triggered based on a pulse signal or based on the registers corresponding to each timer. For example, the pulse signal can be transmitted to a logic device that generates the interrupt signal. The logic device is connected to the processor (or core) and sends the interrupt signal to the processor (or core). The processor (or core) detects the interrupt signal and confirms that the interrupt request has been detected. For another example, an interrupt signal can be triggered when a new time snapshot is written to a register. The processor (or core) detects the interrupt signal and confirms that the interrupt request has been detected. After detecting the interrupt request, the processor can obtain a time snapshot of the master timer and a time snapshot of the slave timer within the processor, or each core can obtain a time snapshot of the master timer and a time snapshot of the slave timer corresponding to the core, to compensate the time of the slave timer within the processor, so that the slave timer is synchronized with the master timer. In other words, each processor is responsible for the time synchronization of its own slave timer with the master timer, or each core is responsible for the time synchronization of its own slave timer with the master timer.

[0071] In some optional embodiments, for the time synchronization of multiple chips, if the master time timer is in the preset chip, for the non-preset chip among the multiple chips, the non-preset chip can obtain a time snapshot of the master time timer from the preset chip through the communication interface between the non-preset chip and the preset chip.

[0072] This embodiment triggers an interrupt request through a pulse signal or a register corresponding to each timer. In response to detecting the interrupt request, a time snapshot of the timer is obtained from the register corresponding to the timer, thereby realizing real-time and effective triggering of time synchronization, ensuring that an accurate and effective time snapshot can be obtained, and avoiding the situation where an erroneous time snapshot is obtained due to the failure to capture a new time snapshot, thereby improving the reliability of time synchronization.

[0073] FIG5 is a flowchart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0074] In some optional embodiments, as shown in FIG5 , step 203 of synchronizing the time of each timer in at least one chip based on the time snapshot of each timer may include:

[0075] Step 2031 : Based on the time snapshot of the first preset timer among the timers and the time snapshots of the other timers except the first preset timer among the timers, determine a first time difference between the other timers and the first preset timer.

[0076] The first preset timer may be a pre-set timer serving as a master timer, and the other timers may be timers serving as slave timers. The number of the other timers may be one or more.

[0077] In some optional embodiments, for time synchronization of a chip, if the chip processor is a single-core processor, the chip processor obtains a time snapshot of a first preset timer and a time snapshot of other timers, and calculates the time difference between the time snapshot of the other timers and the time snapshot of the first preset timer as the first time difference between the other timers and the first preset timer. If the chip processor includes multiple cores, each core obtains a time snapshot of the first preset timer and a time snapshot of other timers corresponding to the core, and determines the first time difference between the other timers corresponding to the core and the first preset timer.

[0078] In some optional embodiments, for the case of time synchronization of multiple chips, each chip determines the first time difference between other timers in the chip and the first preset timer in the manner of the above embodiment (including both single-core and multi-core cases). It can be understood that for the preset chip where the first preset timer is located, the preset chip can directly obtain the time snapshot of the first preset timer. For a chip that does not include the first preset timer, the chip can obtain the time snapshot of the first preset timer from the preset chip through the communication interface between the chip and the preset chip that includes the first preset timer. For example, after capturing the time snapshot, the preset chip can send the time snapshot of the first preset timer to other chips through the communication interface.

[0079] In some optional examples, step 2031 may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by the time difference determination unit.

[0080] Step 2032: Based on the first time difference, time compensation is performed on other timers to synchronize the time of the other timers with the time of the first preset timer.

[0081] Each other timer may have a corresponding first time difference. For any other timer, time compensation may be performed on the other timer based on the first time difference corresponding to the other timer. The first time difference represents the time difference between the other timer and the first preset timer. Therefore, by performing time compensation on the other timer based on the first time difference, the difference between the other timer and the first preset timer can be eliminated or reduced, thereby achieving the purpose of time synchronization.

[0082] In some optional examples, step 2032 may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a time compensation unit.

[0083] This embodiment calculates the first time difference between the time snapshot of other timers and the time snapshot of the first preset timer, and can perform time compensation on other timers based on the first time difference, so that the time of other timers is synchronized with the time of the first preset timer. Since the first time difference is obtained by calculating the time snapshot of the two timers at the same time, the first time difference has a higher accuracy, thereby improving the accuracy of the time synchronization of other timers with the first preset timer.

[0084] In some optional embodiments, determining the first time difference between the other timers and the first preset timer based on the time snapshot of the first preset timer among the timers and the time snapshots of the other timers except the first preset timer among the timers in step 2031 may include:

[0085] Each chip in at least one chip is respectively used as a target chip, and in response to the target chip including a first preset timer, based on the time snapshots of other timers in the target chip except the first preset timer, a first time difference between the other timers and the first preset timer is determined; and the time snapshot of the first preset timer is transmitted to other chips in the at least one chip except the target chip; in response to the target chip not including the first preset timer, a time snapshot of the first preset timer is received from the chip including the first preset timer, and based on the time snapshot of the first preset timer and the time snapshots of each timer in the target chip, a first time difference between each timer and the first preset timer is determined.

[0086] For each chip in at least one chip, the chip is used as a target chip. If the target chip includes a first preset timer, the first time difference between the other timers and the first preset timer can be calculated based on the time snapshots of the other timers in the target chip except the first preset timer and the time snapshot of the first preset timer. Specifically, for any other timer, the difference between the time snapshot of the first preset timer and the time snapshot of the other timer can be used as the first time difference, or the difference between the time snapshot of the other timer and the time snapshot of the first preset timer can be used as the first time difference, and the specific details are not limited. Moreover, after capturing the time snapshot, the target chip can also transmit the time snapshot of the first preset timer to the other chips in at least one chip except the target chip, so that the other chips use the first preset timer as the main time timer to synchronize the timers in the other chips. Specifically, the target chip can transmit the time snapshot of the first preset timer to the other chips through the communication interface between the other chips. The communication interface can be any implementable interface, such as a synchronous serial bus interface (SPI), a bidirectional bus interface (I2C), a CAN interface, a universal asynchronous receiver-transmitter (UART), an Ethernet interface, and can be flexibly configured according to actual needs. If the target chip includes multiple cores, and the first preset timer is a timer corresponding to a preset core among the multiple cores, each core can be used as a target core. If the timers corresponding to the target core include the first preset timer, the first time difference between the other timers and the first preset timer can be determined based on the time snapshots of the other timers corresponding to the target core other than the first preset timer and the time snapshot of the first preset timer. If the timers corresponding to the target core do not include the first preset timer, a time snapshot of the first preset timer can be received from the preset core, and based on the time snapshots of the timers corresponding to the target core and the time snapshot of the first preset timer, the first time difference between each timer corresponding to the target core and the first preset timer can be calculated. The target core can obtain the first time difference of the first preset timer from the preset core through inter-core communication. If the first preset timer is a common timer outside the multiple cores in the target chip, each core in the target chip can access the common timer to obtain a time snapshot of the first preset timer. Each core can calculate the first time difference between each timer corresponding to the core and the first preset timer based on the time snapshot of each timer corresponding to the core and the time snapshot of the first preset timer.

[0087] If the target chip does not include the first preset timer, the target chip may receive a time snapshot of the first preset timer from a chip that includes the first preset timer. The target chip may determine a first time difference between each timer in the target chip and the first preset timer based on the time snapshot of the first preset timer and the time snapshots of each timer in the target chip. Similarly, if the target chip includes multiple cores, each core may determine a first time difference between each timer corresponding to the core and the first preset timer based on the time snapshot of the first preset timer and the time snapshots of each timer corresponding to the core.

[0088] This embodiment can realize time synchronization between multiple chips, and the time synchronization of each timer of multiple chips is realized based on the time snapshot of each timer at the same moment. The calculated first time difference has high accuracy, which helps to improve the accuracy of multi-chip time synchronization.

[0089] FIG6 is a flowchart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0090] In some optional embodiments, each chip in the at least one chip may include at least one processor core; and each processor core may correspond to at least one timer.

[0091] In some optional embodiments, as shown in FIG6 , generating a pulse signal according to a preset period in step 201 may include:

[0092] In step 2011 , a common timer in a preset chip in at least one chip generates a pulse signal according to a preset period.

[0093] The preset chip can be configured according to actual needs. A common timer can be set in the preset chip, and the common timer can include a pulse signal generating circuit, which is responsible for generating a pulse signal according to a preset period.

[0094] In some optional embodiments, the common timer can be connected to each timer in a preset chip and each timer in other chips to transmit a pulse signal to each timer, so as to trigger each timer to capture a time snapshot of the timer in the preset state of the pulse signal.

[0095] In some optional embodiments, the common timer can be connected to each timer via a transmission line. Specifically, the pulse signal output end of the common timer is connected to the time snapshot capture circuit of each timer to trigger the time snapshot capture circuit to capture the time snapshot of the timer. The common timer can also transmit the pulse signal to the time snapshot capture circuit of the common timer to trigger the common timer to capture the time snapshot of the common timer.

[0096] In some optional embodiments, the pulse signal of the common timer may also be transmitted to other chips through connections between the pins of the chip and the pins of other chips.

[0097] In some optional examples, step 2011 may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a common timer in a preset chip in at least one chip.

[0098] The step 202 of capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal may include:

[0099] In step 202a, each chip in at least one chip is used as a target chip. In response to the target chip being a preset chip, the target chip responds to a pulse signal, and a time snapshot of at least one timer corresponding to at least one processor core in the target chip and a time snapshot of a common timer are captured.

[0100] The preset chip is a chip that includes a common timer. If the target chip is the preset chip, the target chip can capture a time snapshot of each timer corresponding to each core in the target chip, as well as a time snapshot of the common timer, in response to the pulse signal. Specifically, a time snapshot capture circuit for each timer corresponding to each core in the target chip can capture a time snapshot of that timer in response to the pulse signal. A time snapshot capture circuit for the common timer can also capture a time snapshot of the common timer in response to the pulse signal.

[0101] In some optional embodiments, the common timer can be set outside the core of the preset chip or within the preset core (i.e., the preset processor core) of the preset chip. If the common timer is set outside the core, each core in the preset chip can access the common timer and obtain a time snapshot of the common timer. In this case, each core can set access rights to the common timer. For example, only the preset core is allowed to write and read the common timer, while other cores can only read the common timer. In other words, the preset core can both read the time snapshot of the common timer and perform time compensation on the common timer, thereby synchronizing the common timer with any timer corresponding to the preset core. By setting access rights for each core to the common timer, the time reliability of the common timer can be guaranteed, preventing different cores from accessing the common timer through write access, which may cause the common timer to become unstable. If the common timer is set within the preset core, the preset core can read and write the common timer, while other cores can only read the common timer, for example, by reading the time snapshot of the common timer through inter-core communication or by other means. Alternatively, the public timer can be set outside each core domain in the preset chip, such as outside each domain of SOC1 in Figure 1, and the access rights of each core of SOC1 to the public timer can be set. Alternatively, the public timer can also be set within the preset core domain of the preset chip, such as within the CORE1 Domain of SOC1 in Figure 1, so that the preset core within the preset core domain can read and write to the public timer, while other cores except the preset core can only read the public timer.

[0102] In some optional examples, step 202a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a first capture unit corresponding to each timer in a preset chip and a second capture unit corresponding to a common timer.

[0103] Step 203 of synchronizing the time of each timer in at least one chip based on the time snapshot of each timer may include the following steps:

[0104] Step 2031a: Determine a second time difference between the common timer and the second preset timer based on a time snapshot of a second preset timer corresponding to a preset processor core in the target chip and a time snapshot of the common timer.

[0105] The preset processor core and the second preset timer can be set to any timer corresponding to any core based on actual chip time synchronization requirements. For example, the preset processor core can be CORE1 in Figure 1, and the second preset timer can be the network card timer corresponding to CORE1 in CORE1 Dmain in Figure 1. Based on the time snapshot of the second preset timer and the time snapshot of the public timer, the time difference between the public timer and the second preset timer can be calculated as the second time difference between the public timer and the second preset timer. For example, the difference between the time snapshot of the public timer and the time snapshot of the second preset timer can be used as the second time difference.

[0106] In some optional examples, step 2031a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a first time difference determination unit in a preset chip.

[0107] Step 2032a: Based on the second time difference, the common timer is compensated to synchronize the time of the common timer with the second preset timer.

[0108] Among them, after obtaining the second time difference between the common timer and the second preset timer, the common timer can be time compensated based on the second time difference to eliminate or reduce the time difference between the common timer and the second preset timer, so that the time of the common timer is synchronized with the time of the second preset timer.

[0109] In some optional embodiments, if the second time difference is the difference between the time snapshot of the common timer and the time snapshot of the second preset timer, and the difference can be positive or negative, the time after subtracting the second time difference from the time of the common timer can be used as the time after compensation of the common timer. If the second time difference is the difference between the time snapshot of the second preset timer and the time snapshot of the common timer, the time after adding the second time difference to the time of the common timer can be used as the time after compensation of the common timer. For example, if the time snapshot of the common timer is 500 microseconds, the time snapshot of the second preset timer is 800 microseconds, and the second time difference is 300 microseconds, the real-time time of the common timer is compensated by 300 microseconds, so that the time of the common timer is synchronized with the time of the second preset timer. For example, when performing time compensation, the real-time time of the second preset timer is 1000 microseconds and the real-time time of the common timer is 700 microseconds. The real-time time of the common timer is compensated by 300 microseconds, so that the real-time time of the common timer becomes 1000 microseconds, so that the time of the common timer is synchronized with the time of the second preset timer. In actual applications, due to differences between the hardware circuits of the timers, the difference between the real-time of the public timer and the real-time of the second preset timer may vary from the difference between the time snapshots and the time compensation of the public timer. For example, when performing time compensation, the real-time time of the second preset timer is 1000 microseconds, and the real-time time of the public timer may be 650 microseconds. Then, in this time compensation, the public timer is compensated by 300 microseconds, so that the real-time time of the public timer becomes 950 microseconds, which can also reduce the difference between the public timer and the second preset timer. The remaining 50 microsecond difference can be continuously reduced through the next time synchronization and subsequent time synchronizations, thereby achieving time synchronization between the public timer and the second preset timer through multiple time synchronizations. In actual applications, the time snapshot can also be other time orders of magnitude such as nanoseconds, not limited to the above-mentioned microsecond order of magnitude.

[0110] In some optional examples, the step 2032a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a first time compensation unit in a preset chip.

[0111] Step 2033a: Time-compensate the time snapshot of the public timer based on the second time difference to obtain a compensated time snapshot of the public timer.

[0112] The time compensation principle for the public timer's time snapshot is similar to the compensation principle for real-time time described above and is not further elaborated here. For example, the sum of the public timer's time snapshot and the second time difference can be used as the compensated time snapshot of the public timer. Alternatively, the time snapshot of the second preset timer can be used as the compensated time snapshot of the public timer.

[0113] In some optional examples, step 2033a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a second time difference determination unit in a preset chip.

[0114] Step 2034a: Based on the time snapshots of other timers in the target chip except the second preset timer and the compensated time snapshot of the common timer, determine a third time difference between each other timer and the common timer.

[0115] For any other timer, based on the time snapshot of the other timer and the compensated time snapshot of the common timer, a third time difference (also referred to as a third compensated time difference) between the other timer and the compensated common timer can be directly determined. Each other timer can correspond to one third time difference.

[0116] In some optional examples, step 2034a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a second time difference determination unit in a preset chip.

[0117] Step 2035a: Based on the third time differences corresponding to the other timers, time compensation is performed on the other timers to synchronize the time of the other timers with the time-compensated common timer.

[0118] Among them, for any other timer, the specific operation of time compensating the other timer based on the third time difference corresponding to the other timer is similar to the specific operation of time compensating the public timer mentioned above, and will not be repeated here. For example, if the time snapshot of the public timer is 500 microseconds, the time snapshot of the second preset timer is 800 microseconds, and the second time difference is 300 microseconds, then the time snapshot of the public timer is compensated by 300 microseconds, and the compensated time snapshot is 800 microseconds. If the time snapshot of other timer B is 600 microseconds, and the third time difference between the time snapshot of the other timer B and the compensated time snapshot of the public timer is 200 microseconds, then the real-time time of the other timer is compensated by 200 microseconds to eliminate or reduce the time difference between the other timer and the compensated public timer, and further eliminate or reduce the time difference between the other timer and the second preset timer.

[0119] In some optional examples, the step 2035a may be executed by a processor calling corresponding instructions stored in a memory, or may be implemented by a second time compensation unit in a preset chip.

[0120] It should be noted that there is no particular order for steps 2033a to 2035a and step 2032a.

[0121] This embodiment uses the second time difference between the common timer and the second preset timer to compensate the common timer for time, thereby achieving time synchronization between the common timer and the second preset timer. Furthermore, the third time difference between the other timers and the common timer is determined by comparing the time snapshots of the other timers with the compensated time snapshot of the common timer. This is used to compensate the other timers, helping to eliminate or reduce the difference between the real-time time of the other timers and the real-time time of the compensated common timer, thereby reducing the difference between the real-time time of the other timers and the real-time time of the second preset timer. Time synchronization between the other timers and the second preset timer is achieved through the common timer, and time synchronization is achieved based on a time snapshot captured at the same moment by hardware, which is not easily affected by software delays and has high synchronization accuracy. Furthermore, this embodiment can also achieve accurate and effective time synchronization between timers corresponding to multiple cores of multiple chips through the common timer. Compared with the multi-level synchronization in related technologies that easily introduces large delays, this embodiment can greatly reduce the introduced delays and measurement errors.

[0122] FIG7 is a flowchart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0123] In some optional embodiments, as shown in FIG7 , step 203 of synchronizing the time of each timer in at least one chip based on the time snapshot of each timer may include:

[0124] Step 2031a: Determine a second time difference between the common timer and the second preset timer based on a time snapshot of a second preset timer corresponding to a preset processor core in the target chip and a time snapshot of the common timer.

[0125] Step 2032a: Based on the second time difference, the common timer is compensated to synchronize the time of the common timer with the second preset timer.

[0126] The specific operations of steps 2031a and 2032a in this embodiment can be referred to the above embodiments.

[0127] Step 2033b: Determine a third time difference between each of the other timers and the common timer based on the time snapshots of each of the other timers and the time snapshot of the common timer.

[0128] Among them, for any other timer, based on the time snapshot of the other timer and the time snapshot of the public timer, the difference between the time snapshot of the other timer and the time snapshot of the public timer can be used as the third time difference between the other timer and the public timer (which can be called the third snapshot time difference).

[0129] In some optional examples, step 2033b may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a second time difference determination unit in a preset chip.

[0130] Step 2034b: Based on the second time difference and the third time difference, time compensation is performed on each other timer to synchronize the time of each other timer with the time-compensated common timer.

[0131] Among them, the second time difference represents the difference between the time snapshot of the common timer and the time snapshot of the second preset timer, and for any other timer, the third time difference represents the difference between the time snapshot of the other timer and the time snapshot of the common timer. Based on the second time difference and the third time difference, time compensation is performed on the other timer, and the time difference between the other timer and the second preset timer can be compensated, so that the time of the other timer is synchronized with the time of the second preset timer. Exemplarily, the time snapshot of the common timer is 500 microseconds, the time snapshot of the second preset timer is 800 microseconds, the second time difference is 300 microseconds, the time snapshot of the other timer B is 600 microseconds, and the third time difference between the time snapshot of the other timer B and the time snapshot of the common timer is -100 microseconds. Then, the real-time time of the other timer is compensated by 200 (=300-100) microseconds, so that the difference between the real-time time of the other timer after compensation and the real-time time of the second preset timer is greatly reduced.

[0132] In some optional examples, step 2034b may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a second time compensation unit in a preset chip.

[0133] This embodiment calculates the third time difference between other timers and the common timer through the time snapshots of other timers and the time snapshots of the common timer, and performs time compensation on the other timers in combination with the second time difference between the common timer and the second preset timer, effectively eliminating or reducing the time difference between the other timers and the second preset timer, realizing time synchronization between the other timers and the second preset timer, and improving the accuracy of time synchronization.

[0134] In some optional embodiments, after determining the third time difference between each other timer and the common timer based on the time snapshots of each other timer and the time snapshot of the common timer, time compensation can be performed on the other timers based on the third time difference. In this way, in this time synchronization, only the difference between the other timers and the time snapshot of the common timer is compensated. If the second time difference between the common timer and the second preset timer is not compensated in this time, it can be compensated in the next time synchronization. Similarly, through periodic time synchronization, the difference between the other timers and the second preset timer can be continuously reduced. For example, if the time snapshot of the common timer is 600 microseconds, the time snapshot of the second preset timer is 800 microseconds, and the second time difference is 200 microseconds, the real-time time of the common timer is compensated by 200 microseconds. If the time snapshot of other timer B is 500 microseconds, the third time difference between the time snapshot of other timer B and the time snapshot of the common timer is 100 microseconds, and the time difference between other timer B and the time snapshot of the second preset timer is 300 microseconds. The real-time time of the other timer is compensated by 100 microseconds, which can reduce the difference between the real-time time of the other timer and the second preset timer by 100 microseconds. At the next time synchronization, the time snapshot of the second preset timer captured is, for example, 1800 microseconds. Since the public timer was compensated for in the previous time synchronization, the difference between the time snapshot of the public timer captured this time and the time snapshot of the second preset timer will be greatly reduced compared with the previous time. For example, the time snapshot of the public timer can be 1750 microseconds. The difference between the time snapshot of the other timer B and the time snapshot of the public timer will include the second time difference compensated by the previous public timer. Therefore, the difference between the other timer B and the public timer this time is The difference in the time snapshot may become larger than the previous one. For example, the time snapshot of other timer B is 1580. In this time synchronization, the second time difference between the public timer and the second preset timer is 50 microseconds, the third time difference between the time snapshot of other timer B and the time snapshot of the public timer is 170 microseconds, and the time difference between the time snapshot of other timer B and the second preset timer is 220 microseconds. The public timer is compensated by 50 microseconds, and the other timer B is compensated by 170 microseconds. It can be seen that the difference between the real-time time of other timer B and the second preset timer is constantly decreasing. Through multiple periodic time synchronizations, the time synchronization of other timer B and the second preset timer can be gradually achieved.

[0135] In some optional embodiments, FIG8 is a schematic diagram of the principle of a chip time synchronization method provided by an exemplary embodiment of the present disclosure. As shown in FIG8 , at least one chip includes two chips, SOC1 and SOC2, for example, and each chip includes two core domains, CORE1 Domain and CORE2 Domain, for example. Each core domain includes a core (not shown, see FIG1 ) and multiple timers corresponding to the core. If SOC1 is a preset chip, the network card timer corresponding to CORE1 (the preset core) of SOC1 (i.e., the network card timer in CORE1 Domain) is the second preset timer. SOC1 includes a common timer, which generates a pulse signal according to a preset period and transmits it to each timer corresponding to each core of SOC1 and each timer corresponding to each core of SOC2 through a transmission channel. The pulse signal can also be transmitted to the common timer itself, specifically to the time snapshot capture circuit of the common timer. When the pulse signal is in the preset state, it triggers each timer of each chip (including the common timer and the timer corresponding to each core) to capture the time snapshot of the timer. Each core of SOC1 can access a common timer to obtain a time snapshot of the common timer. Core1 of SOC1 can determine a second time difference between the common timer and the second preset timer based on the time snapshot of the common timer and a time snapshot of a second preset timer (network card timer). It can then compensate the common timer based on the second time difference to synchronize the common timer with the second preset timer. Core1 of SOC1 can synchronize its corresponding timers, except for the second preset timer, with the common timer, or it can synchronize the other timers directly with the second preset timer. Each core of Core2 of SOC1 can determine a third time difference between each other timer and the common timer based on the time snapshot of each timer corresponding to the core (also referred to as other timers) and the time snapshot of the common timer. It can then compensate the other timers based on the third time difference to synchronize the other timers with the common timer. Alternatively, Core1 can send the second time difference to Core2, which can then compensate the other timers corresponding to Core2 based on the second and third time differences to synchronize the other timers corresponding to Core2 with the second preset timer. Alternatively, CORE1 may send the compensated time snapshot of the common timer to CORE2. CORE2 may determine a third time difference based on the compensated time snapshot of the common timer and time snapshots of other timers corresponding to CORE2, and perform time compensation on other timers.After capturing the time snapshot, SOC1 can also transmit the time snapshot of the common timer or the compensated time snapshot of the common timer to SOC2 through the communication interface with SOC2. Each core of SOC2 can obtain the time snapshot of the common timer or the compensated time snapshot of the common timer through the communication interface, perform time compensation on the timer corresponding to the core, and realize time synchronization between the timer corresponding to the core and the common timer or the compensated common timer, so as to achieve the purpose of time synchronization with the second preset timer.

[0136] FIG9 is a flowchart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0137] In some optional embodiments, as shown in FIG9 , after capturing a time snapshot of at least one timer corresponding to at least one processor core in the target chip and a time snapshot of a common timer in step 202 a, the following steps may also be included:

[0138] Step 301: Transmit the compensated time snapshot of the common timer to other chips in at least one chip except the preset chip.

[0139] If the target chip is a preset chip, the target chip can transmit the compensated time snapshot of the common timer to other chips. The other chips are, for example, SOC2 in FIG8 . The target chip can transmit the compensated time snapshot of the common timer to other chips via a communication interface between the other chips.

[0140] In some optional examples, step 301 may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by the first transmission unit.

[0141] The step 202 of capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal may further include:

[0142] Step 202b, in response to the target chip not being the preset chip, the target chip captures a time snapshot of at least one timer corresponding to at least one processor core in the target chip in response to the pulse signal, and obtains a compensated time snapshot of a common timer from the preset chip.

[0143] If the target chip is not the pre-set chip, a pulse signal generated by the common timer in the pre-set chip is transmitted to each timer in the target chip. Each timer in the target chip captures a time snapshot of that timer in response to the pulse signal. The target chip can obtain the compensated time snapshot from the common timer in the pre-set chip via the communication interface.

[0144] In some optional examples, step 202b may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by the third capture unit and the first acquisition unit corresponding to each timer in other chips.

[0145] Step 203, synchronizing the time of each timer in at least one chip based on the time snapshot of each timer, may further include:

[0146] Step 2031c: Determine a fourth time difference between each timer and the common timer based on the time snapshot of each timer in the target chip and the compensated time snapshot of the common timer.

[0147] Among them, for any timer in the target chip, the specific operation of determining the fourth time difference between the timer and the common timer based on the time snapshot of the timer and the compensated time snapshot of the common timer can refer to the third time difference (third compensated time difference) of the aforementioned embodiment.

[0148] In some optional examples, step 2031c may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a third time difference determination unit in other chips.

[0149] Step 2032c: Based on the fourth time difference corresponding to each timer, time compensation is performed on each timer to synchronize the time of each timer with the time-compensated common timer.

[0150] The specific operation of time compensation can be found in the above embodiment and will not be described in detail here.

[0151] In some optional examples, step 2032c may be executed by the processor calling corresponding instructions stored in the memory, or may be implemented by a third time compensation unit in other chips.

[0152] For a target chip that is not a preset chip among multiple chips, this embodiment can obtain a compensated time snapshot of the common timer from the preset chip, and then synchronize the timer in the target chip with the compensated time of the common timer, thereby achieving the purpose of time synchronization between the target chip timer and the second preset timer of the preset chip, realizing time synchronization of timers corresponding to multiple cores of multiple chips, and improving the time synchronization accuracy.

[0153] FIG10 is a flowchart of a chip time synchronization method provided by yet another exemplary embodiment of the present disclosure.

[0154] In some optional embodiments, as shown in FIG10 , step 203 of synchronizing the time of each timer in at least one chip based on the time snapshot of each timer may include:

[0155] Step 2031d: Use each chip in the at least one chip as a target chip.

[0156] Step 2032d, in response to the target chip being a preset chip, transmitting a time snapshot of the third preset timer of the target chip to a first other chip in at least one chip other than the preset chip, and transmitting a time snapshot of the common timer of the target chip to a second other chip in at least one chip other than the preset chip; the third preset timer is a timer serving as a reference time; the preset chip is a chip including the third preset timer.

[0157] The preset chip and the third preset timer can be set as any timer in any chip in at least one chip. For example, in FIG8 , the preset chip can be SOC1, and the third preset timer can be a network card timer. The first other chip can include one or more other chips other than the preset chip. The first other chip can be a chip to be time-synchronized with the third preset timer. The second other chip can be a chip to be time-synchronized with the common timer. The second other chip can include one or more chips. The second other chip can be the same chip as the first other chip, or it can be different. Specific settings can be made based on time domain requirements. For example, the third preset timer is the network card timer in the CORE1 Domain of SOC1. The network card timers of each chip can be formed into one time domain, and the other timers and the common timer can be formed into another time domain. In this case, the first other chip is the other chip that includes the network card timer, and the second other chip is the other chip that includes the other timers. If each chip includes a network card timer and other timers, the first other chip and the second other chip are the same chip.

[0158] In some optional embodiments, if the target chip is a preset chip, the target chip can transmit a time snapshot of the third preset timer of the target chip to a first other chip, so that the first other chip can time-compensate an internal timer (fourth preset timer) to be synchronized with the time of the third preset timer, so that the fourth preset timer is synchronized with the time of the third preset timer. The target chip transmits a time snapshot of the common timer to a second other chip, so that the second other chip can time-compensate an internal timer (fifth preset timer) to be synchronized with the time of the common timer, so that the fifth preset timer is synchronized with the time of the common timer, thereby forming two time domains in multiple chips.

[0159] In some optional embodiments, the third preset timer and the common timer may be set in different chips.

[0160] In some optional embodiments, more time domains can be set according to actual needs.

[0161] In some optional embodiments, the target chip may further perform time compensation on other timers within the target chip that are to be time-synchronized with the third preset timer, thereby achieving time synchronization between these other timers and the third preset timer. The target chip may further perform time compensation on other timers within the target chip that are to be time-synchronized with the common timer, thereby achieving time synchronization between these other timers and the common timer. For example, the third preset timer is the network card timer in the CORE1 Domain of SOC1 in FIG8 . SOC1 may synchronize the network card timer in the CORE2 Domain of SOC1 with the third preset timer, and synchronize other timers in the CORE1 Domain and CORE2 Domain, except the network card timer, with the common timer.

[0162] Step 2033d, in response to the target chip being the first other chip, determining a fifth time difference between the fourth preset timer and the third preset timer based on a time snapshot of the third preset timer and a time snapshot of the fourth preset timer in the target chip; and performing time compensation on the fourth preset timer based on the fifth time difference so that the fourth preset timer is synchronized with the third preset timer.

[0163] The fourth preset timer may include one or more timers. For example, the fourth preset timer is a network card timer in each core domain of SOC2 in FIG8 . The specific operations for determining the fifth time difference and compensating the time of the fourth preset timer can be referred to in the aforementioned embodiment and are not further described here.

[0164] Step 2034d, in response to the target chip being the second other chip, determining the sixth time difference between the fifth preset timer and the common timer based on the time snapshot of the common timer and the time snapshot of the fifth preset timer in the target chip; based on the sixth time difference, performing time compensation on the fifth preset timer to synchronize the time of the fifth preset timer with the common timer.

[0165] The fifth preset timer may include one or more timers. For example, the fifth preset timer may include other timers in each core domain of SOC2 in FIG8 , excluding the network card timer. The specific operations for determining the sixth time difference and compensating the time of the fifth preset timer can be found in the aforementioned embodiments and are not further described here.

[0166] In some optional embodiments, one or more timers included in each core domain may be set within the core included in the core domain. That is, each core domain includes a core, and the core includes one or more timers corresponding to the core. For example, in Figure 8, the network card timer, PCIE timer, etc. in each domain may be a timer set within the core. The specific relationship between the core and the timer is not limited.

[0167] In some optional examples, the above steps 2031d to 2034d can be executed by the processor calling corresponding instructions stored in the memory, or can be implemented by corresponding units included in the time synchronization module 53.

[0168] This embodiment can achieve time synchronization of multiple time domains in at least one chip, which helps to meet different time synchronization requirements.

[0169] In some optional embodiments, FIG11 is a schematic diagram of the principle of a chip time synchronization method provided by another exemplary embodiment of the present disclosure. As shown in FIG11 , at least one chip includes three chips, SOC1, SOC2, and SOC3, SOC1 serves as a preset chip, and SOC2 and SOC3 serve as both the first other chip and the second other chip. SOC1 is connected to SOC2 and SOC3 respectively through a communication interface to realize the transmission of a time snapshot. SOC1 includes a common timer, and the pulse signal generated by the common timer can be transmitted to each timer corresponding to each core (not shown) in each core domain (e.g., CORE1 Domain, CORE2 Domain, CORE3 Domain) of each chip. In the preset state of the pulse signal, each timer can be triggered to capture the time snapshot of the timer. After capturing a time snapshot, SOC1 can transmit the time snapshot of the network card timer corresponding to CORE1 to SOC2 and SOC3. SOC2 and SOC3 then compensate their internal network card timers based on the time snapshot transmitted by SOC1, synchronizing each network card timer with the network card timer of CORE1 in SOC1, thus forming a network card time domain. SOC1 can also transmit the time snapshot of the public timer to SOC2 and SOC3. SOC2 and SOC3 then compensate their internal timers (excluding the network card timer) based on the time snapshot transmitted by SOC1, synchronizing all other timers with the public timer, thus forming a public time domain. This creates two time domains across the three chips.

[0170] In some optional embodiments, other chips besides the preset chip may also include a common timer (which may be referred to as another common timer). The pulse signal generated by the common timer of the preset chip may also be transmitted to the other common timers of the other chips, so that the other common timers of the other chips can capture a time snapshot, making it easier for the other chips to synchronize the other common timers with the common timer of the preset chip. For example, in Figure 11, SOC2 and SOC3 may each include another common timer (see the setting of the common timer of SOC1), and the pulse signal output end of the common timer of SOC1 is connected to the other common timers of SOC2 and SOC3.

[0171] In some optional embodiments, for any other chip other than the preset chip, if the other chip includes another common timer, the other chip can also synchronize its internal timers with the other common timers in the other chip to achieve time synchronization with the common timer of the preset chip, thereby achieving time synchronization with the preset timer in the preset chip. Alternatively, the other common timers in the other chip are used to synchronize the timers within the other chip. The specific synchronization principle can be found in the aforementioned embodiment and is not further described here.

[0172] The chip time synchronization method provided by the embodiment of the present disclosure supports the issuance of pulse signals by setting a common timer inside the chip. Each hardware timer inside the chip (including the common timer and other timers) can receive the pulse signal. Under the action of the pulse signal, the timer hardware can automatically record the time snapshot of the timer. According to the time snapshot, the common timer can be synchronized with any time inside the chip, and then the other timers inside the chip are synchronized with the common timer. This process does not require inter-core communication and can reduce communication time. Secondly, the pulse signal of the common timer can also be transmitted to other chips through the chip pin, triggering other chips to capture the time snapshot of the timer, and the time snapshot of the common timer can be transmitted to other chips through the communication interface between the chips, facilitating the time synchronization of the timers of other chips with the common timer. Thus, time synchronization can be achieved within the chip and between different chips. And the time difference measurement method of time synchronization between the chip and different chips is consistent, which helps to simplify the software architecture of time synchronization. Moreover, by triggering the capture of the time snapshot at the same moment by the pulse signal, the time difference is calculated by the time snapshot, and no delay compensation is required. Therefore, it is not affected by software processing delay, greatly improving the accuracy of the time difference. In addition, the communication interface between the chips of the method of the embodiment of the present disclosure can support any communication interface to transmit time snapshots, which helps to improve the adaptability of the method of the embodiment of the present disclosure.

[0173] The above-mentioned embodiments of the present disclosure may be implemented individually or in any combination without conflict. The specific configuration may be based on actual needs and is not limited by the embodiments of the present disclosure.

[0174] Any chip time synchronization method provided in the embodiments of the present disclosure can be executed by any appropriate device with data processing capabilities, including but not limited to terminal devices and servers. Alternatively, any chip time synchronization method provided in the embodiments of the present disclosure can be executed by a processor, such as by invoking corresponding instructions stored in a memory to execute any chip time synchronization method mentioned in the embodiments of the present disclosure. This will not be further described below.

[0175] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0176] Exemplary devices

[0177] FIG12 is a schematic diagram of the structure of a chip time synchronization device provided by an exemplary embodiment of the present disclosure. The chip time synchronization device of this embodiment can be used to implement the corresponding chip time synchronization method embodiment of the present disclosure. The device shown in FIG12 may include: a pulse signal generation module 51, a time snapshot capture module 52, and a time synchronization module 53.

[0178] The pulse signal generating module 51 is configured to generate a pulse signal according to a preset period.

[0179] The pulse signal generating module 51 may be a pulse signal generating circuit, such as a pulse signal generating circuit provided in a timer (such as a common timer), or a pulse signal generating circuit connected to a timer.

[0180] The time snapshot capturing module 52 is configured to capture a time snapshot of at least one timer in at least one chip in response to a pulse signal, where the time snapshot represents time information of the timer in a preset state of the pulse signal.

[0181] The time snapshot capture module 52 may include a time snapshot capture circuit (also referred to as a time snapshot capture unit or capture unit) distributed in each timer in at least one chip. Optionally, the time snapshot capture module is a hardware module that helps ensure the consistency of the capture time of the time snapshot of each timer.

[0182] The time synchronization module 53 is configured to synchronize the time of each timer in at least one chip based on the time snapshot of each timer.

[0183] The time synchronization module 53 may include a synchronization processing unit of each core of each chip. The synchronization processing unit may be a part of a processor or a core for running synchronization processing software, or may be a software program module.

[0184] FIG13 is a schematic structural diagram of a chip time synchronization device provided by another exemplary embodiment of the present disclosure.

[0185] In some optional embodiments, as shown in FIG. 13 , the time snapshot capturing module 52 may include: a pulse signal transmission unit 521 , a capturing unit 522 , a register 523 and a snapshot obtaining unit 524 .

[0186] The pulse signal transmission unit 521 is configured to transmit a pulse signal to each timer in at least one chip.

[0187] The pulse signal transmission unit 521 may be any transmission line for transmitting a pulse signal.

[0188] The capture units 522 corresponding to each timer in at least one chip are configured to write a time snapshot of the timer corresponding to the capture unit into a corresponding register in response to the pulse signal.

[0189] Each timer may have a corresponding capture unit 522 for capturing a time snapshot of the timer.

[0190] Register 523 is used to store a time snapshot.

[0191] Each timer may have a corresponding register 523 for storing a time snapshot of the timer.

[0192] In some optional embodiments, for any timer, the register corresponding to the timer can be set in the hardware circuit of the timer, or outside the timer, or outside the core where the timer is located, without specific limitation.

[0193] The snapshot obtaining unit 524 is configured to obtain a time snapshot of each timer from a register corresponding to each timer.

[0194] The snapshot acquisition unit 524 may be part of a synchronous processing unit of a processor or core of a chip.

[0195] In some optional embodiments, the snapshot obtaining unit 524 may also serve as a unit in the time synchronization module 53 .

[0196] In some optional embodiments, the snapshot acquisition unit 524 is specifically used to: detect an interrupt request, where the interrupt request is triggered based on a pulse signal or based on the register corresponding to each timer; in response to detecting the interrupt request, obtain a time snapshot of each timer from the register corresponding to each timer.

[0197] In some optional embodiments, the time synchronization module 53 may include: a time difference determination unit 531 and a time compensation unit 532 .

[0198] The time difference determining unit 531 is configured to determine a first time difference between other timers and the first preset timer based on a time snapshot of the first preset timer among the timers and time snapshots of other timers except the first preset timer among the timers.

[0199] The time compensation unit 532 is configured to perform time compensation on other timers based on the first time difference, so as to synchronize the time of the other timers with the time of the first preset timer.

[0200] In some optional embodiments, the time difference determining unit 531 is specifically configured to:

[0201] Each chip in at least one chip is respectively used as a target chip, and in response to the target chip including a first preset timer, based on the time snapshots of other timers in the target chip except the first preset timer, a first time difference between the other timers and the first preset timer is determined; and the time snapshot of the first preset timer is transmitted to other chips in the at least one chip except the target chip; in response to the target chip not including the first preset timer, a time snapshot of the first preset timer is received from the chip including the first preset timer, and based on the time snapshot of the first preset timer and the time snapshots of each timer in the target chip, a first time difference between each timer and the first preset timer is determined.

[0202] FIG14 is a schematic structural diagram of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure.

[0203] In some optional embodiments, each chip in the at least one chip may include at least one processor core; and each processor core may correspond to at least one timer.

[0204] As shown in FIG. 14 , the pulse signal generating module 51 may include: a common timer 511 in a preset chip in at least one chip, configured to generate a pulse signal according to a preset period.

[0205] The time snapshot capturing module 52 may include: a first capturing unit 521 a corresponding to each timer in the preset chip and a second capturing unit 522 a corresponding to the common timer in the preset chip.

[0206] The first capture unit 521a corresponding to each timer in the preset chip is used to capture a time snapshot of the timer in response to the pulse signal.

[0207] The second capturing unit 522a corresponding to the common timer in the preset chip is configured to capture a time snapshot of the common timer in response to the pulse signal.

[0208] The time synchronization module 53 may include:

[0209] The first time difference determining unit 531a in the preset chip is used to determine the second time difference between the common timer and the second preset timer based on the time snapshot of the second preset timer corresponding to the preset processor core in the preset chip and the time snapshot of the common timer.

[0210] The first time compensation unit 532a in the preset chip performs time compensation on the common timer based on the second time difference, so that the common timer is synchronized with the second preset timer.

[0211] The second time difference determination unit 533a in the preset chip is used to time compensate the time snapshot of the common timer based on the second time difference, obtain the compensated time snapshot of the common timer, and determine the third time difference between each other timer and the common timer based on the time snapshots of other timers except the second preset timer and the compensated time snapshot of the common timer.

[0212] The second time compensation unit 534a in the preset chip performs time compensation on each other timer based on the third time difference corresponding to each other timer, so that the time of each other timer is synchronized with the time-compensated common timer.

[0213] In some optional embodiments, the second time difference determining unit 533a in the preset chip is used to determine the third time difference between each other timer and the common timer based on the time snapshots of each other timer and the time snapshot of the common timer.

[0214] The second time compensation unit 534a in the preset chip is used to perform time compensation on each other timer based on the second time difference and the third time difference, so that the time of each other timer is synchronized with the time-compensated common timer.

[0215] In some optional embodiments, the time snapshot capturing module 52 may further include:

[0216] The first transmission unit 521b is configured to transmit the compensated time snapshot of the common timer to other chips except the preset chip in the at least one chip.

[0217] The third capture unit 522b corresponding to each timer in other chips is used to capture a time snapshot of the timer in response to the pulse signal.

[0218] The first acquiring unit 523b is configured to acquire a compensated time snapshot from a common timer of a preset chip.

[0219] The time synchronization module 53 may further include:

[0220] The third time difference determining unit 531b in the other chips is configured to determine a fourth time difference between each timer and the common timer based on the time snapshots of each timer in the other chips and the compensated time snapshot of the common timer.

[0221] The third time compensation unit 532b in other chips is used to perform time compensation on each timer based on the fourth time difference corresponding to each timer, so as to synchronize the time of each timer with the time-compensated common timer.

[0222] FIG15 is a schematic structural diagram of a chip time synchronization device provided by yet another exemplary embodiment of the present disclosure.

[0223] In some optional embodiments, as shown in FIG15 , the time synchronization module 53 may include:

[0224] The snapshot transmission unit 531c of the preset chip in at least one chip is used to transmit the time snapshot of the third preset timer of the preset chip to the first other chip in at least one chip other than the preset chip, and to transmit the time snapshot of the common timer of the preset chip to the second other chip in at least one chip other than the preset chip; the third preset timer is a timer serving as a reference time; the preset chip is a chip including the third preset timer.

[0225] The fourth time difference determining unit 532c in the first other chip is configured to determine a fifth time difference between the fourth preset timer and the third preset timer based on the time snapshot of the third preset timer and the time snapshot of the fourth preset timer in the first other chip.

[0226] The fourth time compensation unit 533c in the first other chip is configured to perform time compensation on the fourth preset timer based on the fifth time difference, so as to synchronize the fourth preset timer with the third preset timer.

[0227] The fifth time difference determining unit 534c in the second other chip is configured to determine a sixth time difference between the fifth preset timer and the common timer based on the time snapshot of the common timer and the time snapshot of the fifth preset timer in the second other chip.

[0228] The fifth time compensation unit 535c in the second other chip is configured to perform time compensation on the fifth preset timer based on the sixth time difference, so as to synchronize the fifth preset timer with the common timer.

[0229] It should be noted that the units of the modules of the embodiments of the present disclosure may be distributed in the same or different chips, or may be distributed in the same or different cores in the same or different chips.

[0230] In some optional embodiments, FIG16 is a schematic diagram of the structure of a chip time synchronization device provided in another exemplary embodiment of the present disclosure. As shown in FIG16 , for SOC1, which serves as a preset chip, the chip may include a common timer 511 and at least one core domain. The figure uses two core domains, CORE1 Domain and CORE2 Domain, as an example. Each core domain may include a core and multiple timers (such as a network card timer and a PCIE timer). Each timer may include a first capture unit 521a and a register 523. The common timer 511 may include a second capture unit 522a and a register 523. Each core may include a snapshot acquisition unit 524 for acquiring a time snapshot from the register 523. The preset core CORE1 in SOC1 includes a first time difference determination unit 531a and a first time compensation unit 532a. The non-preset core CORE2 in SOC1 includes a second time difference determination unit 533a and a second time compensation unit 534a. The specific functions of each unit can be found in the aforementioned embodiments.

[0231] In some optional embodiments, FIG17 is a schematic diagram of the structure of a chip time synchronization device provided by another exemplary embodiment of the present disclosure. As shown in FIG17 , for a non-preset SOC2, each timer in SOC2 may include a first capture unit 521a and a register 523. Each core in SOC2 may include a snapshot acquisition unit 524, a second time difference determination unit 533a, and a second time compensation unit 534a. The specific functions of each unit can be found in the aforementioned embodiments.

[0232] The beneficial technical effects corresponding to the exemplary embodiment of this device can be found in the corresponding beneficial technical effects of the above exemplary method part, which will not be repeated here.

[0233] Exemplary electronic devices

[0234] FIG18 is a structural diagram of an electronic device provided by an embodiment of the present disclosure, which includes at least one processor 11 and a memory 12 .

[0235] The processor 11 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0236] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute the one or more computer program instructions to implement the methods and / or other desired functions of the various embodiments of the present disclosure described above.

[0237] In one example, the electronic device 10 may further include an input device 13 and an output device 14 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0238] The input device 13 may also include, for example, a keyboard, a mouse, a touch screen, a microphone, various sensors, and the like. Sensors may include, for example, image sensors (such as cameras, webcams, etc.), laser radars, millimeter-wave radars, ultrasonic radars, positioning sensors, pressure sensors, air quality sensors, temperature sensors, and the like. Image sensors, laser radars, millimeter-wave radars, ultrasonic radars, and the like may be used to perceive the surrounding environment, i.e., to detect dynamic and static objects in the surrounding environment. Dynamic and static objects may include, for example, static objects such as lane lines, curbs, arrows, signs, trees, and buildings, as well as dynamic objects such as surrounding vehicles, pedestrians, and cyclists. Positioning sensors are used to achieve positioning of mobile devices (such as vehicles, robots, etc.) where electronic devices are located. Positioning sensors may include, for example, inertial measurement units (IMUs), global positioning systems (GPSs), and the like. Pressure sensors may be used to detect seat pressure. Temperature sensors may be used to detect the temperature in the vehicle cabin. Air quality sensors may be used to detect the air quality in the vehicle cabin.

[0239] The output device 14 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0240] Of course, for simplicity, FIG18 only shows some of the components of the electronic device 10 related to the present disclosure, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 10 may further include any other appropriate components depending on the specific application.

[0241] In addition, an embodiment of the present disclosure further provides an electronic device, which includes the chip time synchronization device provided by any of the above embodiments.

[0242] Exemplary computer program products and computer-readable storage media

[0243] In addition to the above methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to perform the steps in the methods of various embodiments of the present disclosure described in the above "Exemplary Method" section.

[0244] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0245] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps in the method of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0246] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or component comprising electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0247] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be considered as essential to each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0248] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A time synchronization method for a chip, comprising: Generating a pulse signal according to a preset period; In response to the pulse signal, capturing a time snapshot of at least one timer in at least one chip, the time snapshot representing the time information of the timer at a preset state of the pulse signal; Based on the time snapshots of the respective timers, performing time synchronization on the respective timers in the at least one chip.

2. The method according to claim 1, wherein, The performing time synchronization on the respective timers in the at least one chip based on the time snapshots of the respective timers includes: Based on the time snapshots of a first preset timer in each of the timers and the time snapshots of other timers in each of the timers except the first preset timer, determining a first time difference between the other timers and the first preset timer; Based on the first time difference, performing time compensation on the other timers so that the other timers are time-synchronized with the first preset timer.

3. The method according to claim 2, wherein The determining the first time difference between the other timers and the first preset timer based on the time snapshots of the first preset timer in each of the timers and the time snapshots of other timers in each of the timers except the first preset timer includes: Taking each chip in the at least one chip as a target chip respectively. In response to the target chip including the first preset timer, based on the time snapshots of other timers in the target chip except the first preset timer, determining the first time difference between the other timers and the first preset timer; and transmitting the time snapshot of the first preset timer to other chips in the at least one chip except the target chip; In response to the target chip not including the first preset timer, receiving the time snapshot of the first preset timer from a chip including the first preset timer, and based on the time snapshot of the first preset timer and the time snapshots of the respective timers in the target chip, determining the first time difference between the respective timers and the first preset timer.

4. The method according to claim 1, wherein The capturing a time snapshot of at least one timer in at least one chip in response to the pulse signal includes: Transmitting the pulse signal to the respective timers in the at least one chip so that the respective timers respond to the pulse signal respectively and write the time snapshots corresponding to the respective timers into corresponding registers; Obtaining the time snapshots of the respective timers from the registers corresponding to the respective timers.

5. The method according to claim 4, wherein The obtaining the time snapshots of the respective timers from the registers corresponding to the respective timers includes: Detecting an interrupt request, the interrupt request being triggered based on the pulse signal or based on the registers corresponding to the respective timers; In response to detecting the interrupt request, obtaining the time snapshots of the respective timers from the registers corresponding to the respective timers.

6. The method according to claim 1, wherein, Each chip in the at least one chip includes at least one processor core; Each of the processor cores corresponds to at least one of the timers; Generating a pulse signal according to a preset period, including: A common timer in a preset chip in the at least one chip generates the pulse signal according to the preset period; Responding to the pulse signal and capturing time snapshots of at least one timer in at least one chip, including: Taking each chip in the at least one chip as a target chip respectively. In response to the target chip being the preset chip, the target chip responds to the pulse signal and captures the time snapshots of at least one timer corresponding to at least one processor core in the target chip, as well as the time snapshot of the common timer; Based on the time snapshots of the respective timers, performing time synchronization on the respective timers in the at least one chip, including: Based on the time snapshot of a second preset timer corresponding to a preset processor core in the target chip and the time snapshot of the common timer, determining a second time difference between the common timer and the second preset timer; Based on the second time difference, performing time compensation on the common timer to synchronize the time of the common timer with that of the second preset timer; Performing time compensation on the time snapshot of the common timer based on the second time difference to obtain a compensated time snapshot of the common timer. Based on the time snapshots of the other timers in the target chip except the second preset timer and the compensated time snapshot of the common timer, determining third time differences between the respective other timers and the common timer; Based on the respective third time differences corresponding to the respective other timers, performing time compensation on the respective other timers to synchronize the time of the respective other timers with that of the common timer after time compensation; or, Based on the time snapshots of the respective other timers and the time snapshot of the common timer, determining third time differences between the respective other timers and the common timer; Based on the second time difference and the third time differences, performing time compensation on the respective other timers to synchronize the time of the respective other timers with that of the common timer after time compensation.

7. The method according to claim 6, wherein After capturing the time snapshots of at least one timer corresponding to at least one processor core in the target chip and the time snapshot of the common timer, further including: Transmitting the compensated time snapshot of the common timer to other chips in the at least one chip except the preset chip; Responding to the pulse signal and capturing time snapshots of at least one timer in at least one chip, further including: In response to the target chip not being the preset chip, the target chip responds to the pulse signal, captures the time snapshots of at least one timer corresponding to at least one processor core in the target chip, and obtains the compensated time snapshot of the common timer from the preset chip; Based on the time snapshots of the respective timers, performing time synchronization on the respective timers in the at least one chip, further including: Determine the fourth time differences between each of the timers and the common timer based on the time snapshots of each of the timers in the target chip and the compensated time snapshot of the common timer; Based on the fourth time differences respectively corresponding to each of the timers, perform time compensation on each of the timers so that the times of each of the timers are synchronized with the time of the common timer after time compensation. The time synchronization of each of the timers in the at least one chip based on the time snapshots of each of the timers includes:

8. The method according to claim 1, wherein Taking each of the at least one chip as a target chip respectively. In response to the target chip being a preset chip, transmit the time snapshot of the third preset timer of the target chip to a first other chip among the at least one chip other than the preset chip, and transmit the time snapshot of the common timer of the target chip to a second other chip among the at least one chip other than the preset chip; the third preset timer is a timer serving as a reference time; the preset chip is a chip including the third preset timer; In response to the target chip being the first other chip, determine the fifth time difference between the fourth preset timer and the third preset timer based on the time snapshot of the third preset timer and the time snapshot of the fourth preset timer in the target chip; based on the fifth time difference, perform time compensation on the fourth preset timer so that the time of the fourth preset timer is synchronized with the time of the third preset timer; In response to the target chip being the second other chip, determine the sixth time difference between the fifth preset timer and the common timer based on the time snapshot of the common timer and the time snapshot of the fifth preset timer in the target chip; based on the sixth time difference, perform time compensation on the fifth preset timer so that the time of the fifth preset timer is synchronized with the time of the common timer.

9. A time synchronization device for a chip, comprising: A pulse signal generation module, configured to generate a pulse signal according to a preset period; A time snapshot capture module, configured to capture the time snapshots of at least one timer in at least one chip in response to the pulse signal, where the time snapshot represents the time information of the timer at a preset state of the pulse signal; A time synchronization module, configured to synchronize the times of each of the timers in the at least one chip based on the time snapshots of each of the timers. The time snapshot capture module includes:

10. The apparatus according to claim 9, wherein, A pulse signal transmission unit, configured to transmit the pulse signal to each of the timers in the at least one chip; Capture units respectively corresponding to each of the timers in the at least one chip, configured to write the time snapshot of the timer corresponding to the capture unit into the corresponding register in response to the pulse signal; The register, configured to store the time snapshot; A snapshot acquisition unit, configured to acquire the time snapshots of each of the timers from the registers respectively corresponding to each of the timers. ​ 11. The device according to claim 9, wherein, Each of the at least one chip includes at least one processor core; Each of the processor cores corresponds to at least one of the timers; The pulse signal generation module includes: A common timer within a preset chip among the at least one chip, configured to generate the pulse signal according to the preset period; The time snapshot capture module includes: A first capture unit corresponding to each of the timers in the preset chip, configured to capture the time snapshot of the timer in response to the pulse signal; A second capture unit corresponding to the common timer in the preset chip, configured to capture the time snapshot of the common timer in response to the pulse signal; The time synchronization module includes: A first time difference determination unit within the preset chip, configured to determine a second time difference between the common timer and a second preset timer corresponding to a preset processor core within the preset chip based on the time snapshots of the second preset timer and the common timer; A first time compensation unit within the preset chip, configured to perform time compensation on the common timer based on the second time difference, so that the common timer is time-synchronized with the second preset timer; A second time difference determination unit within the preset chip, configured to perform time compensation on the time snapshot of the common timer based on the second time difference to obtain a compensated time snapshot of the common timer, and determine a third time difference between each of the other timers and the common timer based on the time snapshots of the other timers except the second preset timer and the compensated time snapshot of the common timer; A second time compensation unit within the preset chip, configured to perform time compensation on each of the other timers based on the third time difference corresponding to each of the other timers, so that each of the other timers is time-synchronized with the common timer after time compensation; or, The second time difference determination unit is configured to determine a third time difference between each of the other timers and the common timer based on the time snapshots of the other timers and the time snapshot of the common timer; The second time compensation unit is configured to perform time compensation on each of the other timers based on the second time difference and the third time difference, so that each of the other timers is time-synchronized with the common timer after time compensation.

12. A computer-readable storage medium storing a computer program for executing the time synchronization method of the chip according to any one of claims 1-8 above.

13. An electronic device, the electronic device includes: A processor; A memory for storing executable instructions of the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the time synchronization method of the chip according to any one of claims 1-8 above; or, The electronic device includes the time synchronization device of the chip according to any one of claims 9-11 above.

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