A physical unclonable function and a method for generating a key based on a physical unclonable function

Abstract

A method for generating a key based on a physical unclonable function is described including: generating a plurality of key elements of the key by operating each response structure of a plurality of response structures in accordance with a linked challenge / response operation. The linked challenge / response operation includes applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge. The linked challenge / response operation further includes applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge. The linked challenge / response operation includes causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, wherein the output is a function of the first challenge or the first response and of the second challenge or the second response.

Description

A PHYSICAL UNCLONABLE FUNCTION AND A METHOD FOR GENERATING A KEY BASED ON A PHYSICAL UNCLONABLE FUNCTIONTechnical Field

[0001] Various aspects relate to devices and methods for operating a physical unclonable function and generating a key based on a physical unclonable function.Background

[0002] In general, various data processing applications may rely on transistor technologies. However, it was found that resistor arrays may be useful for some data processing applications as well. Such resistorbased technologies were further developed to allow for a selective reconfiguration of an electric resistance of resistors. Such devices having a non-volatile, reconfigurable electric resistance, may be referred to as memristive devices or memristors, for example. Memristor crossbar arrays were developed to replace transistors and memory cells in some data processing and data storage applications. However, an occurrence of leakage currents in memristor based crossbar arrays may limit a scalability of such structures. Therefore, several types of memristors with nonlinear resistance behavior have been proposed to reduce leakage currents when reconfiguring and reading selective memristors over nonselective memristors. These include so-called complementary resistance switches, which include two memristive structures connected in series, wherein a disadvantage of this technology may be that the state of the complementary resistance can be only read out destructively and, therefore, the complementary resistance switch has to be rewritten after readout. An approach for a nondestructive readout of a state of a complementary resistive switch may be based on capacitance measurements. A complementary resistive switch may include a two-layer memristive structure with strong nonlinear resistive behavior and a single-layer memristive structure with strong nonlinear resistive behavior.Brief Description of the Drawings

[0003] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:FIG.1 schematically shows various aspects of a memristive structure;FIGS.2A to 2F show aspects of electric characteristics corresponding to barrier switching of a memristive structure and FIGS.2G to 2I each show measured IV-characteristics for different exemplary memristive structures;FIG.3A shows a respective schematic IV-characteristic of a memristive structure for three different memristive states and FIG.3B shows a respective IV-characteristic measured for five different memristive states of a memristive structure;FIGS.4A to 4E show various aspects of reading a memristive structure;FIGS.5A to 5E show various aspects of reading a memristive structure;FIGS.6A to 6C show various aspects of operating memristive structures in a physical unclonable functions technology;FIGS.7A to 7F show various aspects of operating response structures in a physical unclonable functions technology;FIGS.8A to 8F show various aspects of operating response structures based on a linked challenge / response operation in a physical unclonable functions technology;FIGS.9A to 9H show various aspects of operating memristive response structures based on a linked challenge / response operation in a physical unclonable functions technology;FIGS.10 and FIG.11 show various aspects of a method for generating a key in a physical unclonable functions technology in a schematic flow diagram;FIGS.12A to 12H show various aspects of operating response structures based on a linked challenge / response operation in a physical unclonable functions technology; andFIGS.13A to 13C show various aspects of operating response structures based on a linked challenge / response operation in a physical unclonable functions technology.Description

[0004] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details, and aspects in which the invention may be practiced. These aspects are described in sufficient detail to enable those skilled in the art to practice the invention. Other aspects may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various aspects are not necessarily mutually exclusive, as some aspects can be combined with one or more other aspects to form new aspects. Various aspects are described in connection with methods and various aspects are described in connection with devices (e.g., arrangements). However, it may be understood that aspects described in connection with methods may similarly apply to the devices, and vice versa.

[0005] The terms “at least one” and “one or more” may be understood to include any integer number greater than or equal to one, i.e. , one, two, three, four, [. . .], etc. The term “a plurality” may be understood to include any integer number greater than or equal to two, i.e., two, three, four, five, [. . .], etc. The phrase “at least one of’ with regard to a group of elements may be used herein to mean at least one element from the group consisting of the elements. For example, the phrase “at least one of” with regard to a group of elements may be used herein to mean a selection of: one of the listed elements, a plurality of one of the listed elements, a plurality of individual listed elements, or a plurality of a multiple of listed elements.

[0006] The phrase “unambiguously assigned” may be used herein to mean a one-to-one-assignment (e.g., allocation, e.g., correspondence) or a bijective assignment. As an example, a first element being unambiguously assigned to a second element may include that the second element is unambiguously assigned to the first element. As another example, a first group of elements being unambiguously assigned to a second group of element may include that each element of the first group of elements is unambiguously assigned to a corresponding element of the second group of elements and that that corresponding element of the second group of elements is unambiguously assigned to the element of the first group of elements.

[0007] The term “coupled” may be used herein with respect to nodes, circuit elements, and the like, to mean a, e.g. direct or indirect, connection and / or interaction. Several elements may, for example, be coupled together along an interaction chain (e.g., an electrically conductive path), along which the interaction (e.g., electrical charges) may be transmitted. For example, two elements coupled together may interact with each other.

[0008] The term “connected” or “connection” may be used herein with respect to nodes, circuit elements, and the like, to mean electrically connected, which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not influence the substantial functioning of the described circuit or device. The term “electrically conductively connected” that is used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc., may be understood as an electrically conductive connection with, for example, ohmic behavior, e.g., provided by a metal or degenerate semiconductor in absence of p-n junctions in the current path. The term “electrically conductively connected” may be also referred to as “galvanically connected.”

[0009] In some aspects, two physical and / or chemical properties (e.g., an electrical voltage, an electrical current, an electrical conductance, a thickness, an electrical conductivity, a doping concentration, as examples) may be compared with one another by relative terms such as “greater”, “higher”, “lower”, “less”, or “equal”, for example. It is understood that, in some aspects, a comparison may include a sign (positive or negative) of a value representing the physical and / or chemical properties or, in other aspects, the absolute values are considered for the comparison. However, a comparison of measurement values representing a physical and / or chemical property may usually include a measurement of such measurement values by the same measurement principle or at least by comparable measurement principles.

[0010] According to various aspects, a method for generating a key based on a physical unclonable function and various aspects of a physical unclonable function are described herein, wherein the randomness is generated by in-device variations of a memristive structure. Physical Unclonable Functions (also referred to as Physically Unclonable Functions or PUF) are hardware structures that serve to enable a clear identification of a device or to secure keys for cryptographic processes. Device including a PUF may be complete electronic chip cards or microprocessors, especially those with Hardware Security Modules (HSM) for cryptographic tasks. Like a fingerprint, the PUF is an individual characteristic tied to a physical object. PUFs are classified as physical primitives (based on a cryptographic primitive). The PUF is based on the fact that the smallest fluctuations in the production process cause certain assemblies to behave individually, even though the production process should produce absolutely identical parts. Devices with a PUF unit may be therefore manufactured using the same manufacturing process and do not undergo any individual processing - at least with regard to the PUF.

[0011] The PUF unit in the hardware may include elements that process an input (challenge) and generate a return value (response). Part of this challenge-response process is the PUF, which, through its behavior, causes a change in the return value that is unique to the component. In addition, the challengeresponse process can be secured using cryptographic hashes, for example, to such an extent that the behavior of the PUF cannot be inferred from the input and return value. There are a number of possibilities in hardware, some of which are presented below.

[0012] In order for PUF to be used in cryptographic applications, various properties may be beneficial, such as:I) Robustness: i.e., external influences may change only so slightly at the moment of reading (temperature, voltage, etc.) that, with reliable error correction measures, the response always delivers the same behavior or result to a challenge. For example, error correction methods are used for this purpose;II) Uncopyability: i.e., preventing, for example, a blank chip card from being made into a clone of another chip card. The PUF can no longer be changed, and if the production process is designed appropriately, the probability of two identically produced chip cards disappears;III) Unpredictability: i.e., the return (response) cannot be predicted from the input (challenge). This results in the expectation of a high entropy of the response even if the environmental conditions change. A cooling of the device (reduction of thermal entropy) should not be followed by a reduction of informational entropy;IV) Tamper evidence: i.e., the PUF reacts to invasive manipulation of the device and thereby reveals it or the response is no longer accepted.

[0013] In contrast to standard elements (transistors, SRAM elements, ring oscillators, as example) used in well known PUF technologies, memristors are more efficient to provide a randomness source for PUFs due to their appealing characteristics (e.g., inherent stochasticity and high density) and notable variation. With a compact crossbar array structure, the randomness in the conductance distribution, switching delay, and probabilistic switching can be used to produce highly random and reliable PUFs.

[0014] According to various aspects, a key element generated by a PUF may be referred to as a PUF bit, since a key is usually represented in a bit-sequence. Every key element can be derived from at least one PUF subunit or from several PUF subunits to reduce the error rate. According to various aspects, a PUF subunit as described herein may be realized by memristive structure including at least one memristive element. Typically, up to 5 PUF subunits may be used to represent one key element (e.g., one PUF bit). Nowadays PUFs may represent 128-bit or 256-bit keys and consists of up to 5*128 PUF subunits or of up to 5*256 PUF subunits, respectively.

[0015] A problem related to robustness may be, for example, caused by external influences (temperature, voltage, etc.) at the moment of determining the response of a PUF subunit to a challenge. External influences may increase the cycle-to-cycle variation of every PUF subunit and with that the error rate when extracting the key bit. The problem of too low unpredictability may be, for example, caused by too small and partially correlated fluctuations in the production process of PUF subunits. The problem of too low unpredictability may be caused also by a dependence of informational entropy on thermal entropy. The problem of tamper may be caused by using the device-to-device (PUF subunit-to-PUF subunit) variability of challenge-response of all PUF subunits forming the PUF, e.g. of all 5*128 PUF subunits or of up to 5*256 PUF subunits of the PUF representing a 128-bit or a 256-bit keys, respectively.

[0016] According to various aspects, the PUF described herein may be configured to represent a N- key-element key (also referred to as N-bit key) and is not subject to the device-to-device (D2D) variability of the PUF subunits. The PUF described herein exploits the uncorrelated fluctuations of the device-in-device (Di D) variability of each of the PUF subunits or of a set of PUF subunits. The PUF described herein exploits the device-in-device variability of single PUF subunits to extract every key element of the N-key-element key from the challenge-response of single PUF subunits or a set of PUF subunits.

[0017] According to various aspects, a PUF subunit may be characterized by a challenge response function with different l / V branches j. The PUF subunit may be realized by a memristive structure including one or more memristive elements. A memristive element and therefore, a memristive structure, may include a positive pair of branches (e.g., a positive LRS branch and a positive HRS branch or, in more detail, a positive write branch and one or more positive read branches) and / or negative pair of branches (e.g., a negative LRS branch and a negative HRS branch or, in more detail, a negative write branch and one or more negative read branches).

[0018] Various aspects related to a memristive structure and to a memristive element are described in the following. According to various aspects, a memristive structure in an array of memristive structures (e.g.,within a crossbar array) may be addressable, e.g. by being unambiguously assigned to a logic address. The addressability and the logic addresses may be provided by the architecture of the control lines connected to a respective memristive structure. In a crossbar array, two sets of control lines (e.g., a set of word-lines and a set of bit-lines) may be utilized to address an array of memristive structures. According to various aspects, an analog memristive structure may reside in one of various memristive states (also referred to as resistance states) associated therewith. As an example, the actual electrical resistance (or conductivity) associated with a memristive structure can be determined via a read operation to evaluate in which of the distinct memristive states the memristive structure is residing in. As another example, the actual electrical resistance (or conductivity) associated with a memristive structure can be utilized in a neuronal network configuration to influence a data or signal processing.

[0019] In some aspects, a plurality of memristive structures may be arranged in a crossbar configuration. In such a crossbar configuration, a memristive material portion (also referred to as memristor or memristive device) can be addressed by a corresponding cross-point formed by input-lines and outputlines of the crossbar arrangement. However, a plurality of memristive structures may be arranged in any other suitable configuration that allows for a desired electrical addressing to operate the of memristive structures.

[0020] FIG.1 shows various aspects of a memristive structure 100. A memristive structure 100 may include a first electrode 110 and a second electrode 120. The first electrode 110 and / or the second electrode 120 may include any suitable electrically conductive material, e.g., Al, Cu, Ti, AICu, TiN, W, Ta, only as examples. The memristive structure 100 may further include a memristive material portion 130 (e.g., a memristive element). The memristive material portion 130 may be disposed between the first electrode 110 and the second electrode 120. Illustratively, the region in which the first electrode 110 and the second electrode 120 overlap one another may be (e.g., partially or completely) filled with memristive material. According to various aspects, the memristive material portion 130 may be in electrical contact and in direct physical contact with both the first electrode 110 and the second electrode 120.

[0021] According to various aspects, the memristive structure 100 may be a memristive cross-point structure included in a memristive crossbar array. The first electrode 110 and the second electrode 120 may be each a portion of a corresponding crossbar control line. As an example, a crossbar array may include a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode110 may be a portion of a first control line 111 of the set of first control lines and the second electrode 120 may be a portion of a second control line 121 of the set of second control lines, as illustrated in FIG.1. In this example, the memristive material portion 130 may be in direct physical contact with both the first control line111 and the second control line 121 , and the memristive material portion 130 may be disposed between both the first control line 111 and the second control line 121 . Accordingly, a memristive structure 100 can be provided in each of various cross-point regions of the crossbar array.

[0022] In other aspects, the first electrode 110 may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a corresponding first control line (e.g., a first control line of a crossbar array) and the second electrode 120 may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a corresponding second control line (e.g., a second control line of a crossbar array). As an example, a crossbar array may include a set of first control lines and a set of second control lines in a crossbar configuration, and the first electrode 110 may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a first control line 111 of the set of first controllines and the second electrode 120 may be coupled to (e.g., electrically conductively connected to, e.g., in direct physical contact with) a second control line 121 of the set of second control lines. In this example, the memristive material portion 130 may not be in direct physical contact with the first control line 111 and the second control line 121. But the first electrode 110 may be in direct physical contact with the first control line 111 and the second electrode 120 may be in direct physical contact with the second control line 121. The first electrode 110, the second electrode 120, and the memristive material portion 130 may be disposed between the first control line 111 and the second control line 121 . Accordingly, a memristive structure 100 can be provided in each of various cross-point regions of a crossbar array.

[0023] As explained above, the first control line 111 and the second control line 121 may be in a crossbar configuration or in any other suitable configuration to allow for an electrical addressing of the memristive structure 100 (i.e., the memristive material portion 130) via the first control line 111 and the second control line 121. An electrical addressing of the memristive structure 100 may be used to read information stored in the memristive structure 100 and / or to write (e.g., store) information into the memristive structure 100. In other words, an electrical addressing of the memristive structure 100 may be used to determine a state (e.g., a memristive state) in which the memristive structure 100 is residing and / or to set (e.g., keep or change) a (e.g., a memristive) state of the memristive structure 100.

[0024] Possible materials that can be used to form the memristive material portion 130 may be, for example, a ternary oxide, a quaternary oxide, and / or a quinary oxide. Examples for ternary oxides are perovskite oxides with a base structure ABO3 or bixbyite with a base structure of A2O3 or B2O3 or mixtures thereof. Further, mixtures may include different impurities at the A or B site. Examples of elements for A may include La3+, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yp, Lu, Ca, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, Ba, Cr, Pu (e.g., all 3+ like La3+). Examples of elements for B may include AI3+, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn (e.g., all 3+ like AI3+). Examples of impurities at the A site may include Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr Pu, Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, e.g., with a different valence than 3+ Examples of impurities at the B site may include Al, Cr, Fe, Ga, In, Sc, V, Ti, Mn, Co, Ni, Sn, Ca, La, Ce, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Yb, Lu, Pr, Pm, Tm, Tl, Pb, Bi, Sr, Y, La, Ba, Cr, Pu, e.g., with a different valence than 3+ Perovskite oxides may be present in different phases like for example a rhombohedral alpha phase, an orthorhombic beta phase, a hexagonal phase, and / or a cubic bixbyite phase. Examples of suitable crystalline materials may include the ternary oxides CaTiO3, BaTiO 3, PbTiO3, LaNiO3, NdAIO3, and / or PrAIO3. The memristive material portion 130 may be or may include one or more of the following materials and / or material combinations: AI2O3 / TaOx, SiOx:Ag / TiOx, TaO, HfAlyOx / TaO, Pr0.7Ca0.3MnO3 (PCMO), Si-ln-Zn-O / ion gel, SilnZnO, SiN / TaN, SrFeO3, only as examples.

[0025] In some aspects, at least a portion of the memristive material portion 130 may be modified, e.g., to cause a vacancy doping V+ or V-. In some aspects, the memristive material portion 130 may include an n-type memristive material that has a positive vacancy doping V+, e.g. anion vacancy. In other aspects, the memristive material portion 130 may include a p-type memristive material that has a negative vacancy doping V-, e.g. cation vacancy. In the case that the memristive material that form the memristive material portion 130 is an oxide, e.g., BiFeyOx, the vacancy doping V+ may be cause by oxygen vacancies VO+. In some aspects, at least a portion of the memristive material portion 130 may be modified, e.g., to cause traps, T. Accordingly, the memristive material portion 130 may include traps T. As an example, the traps T may be caused by introduction of metal ions (e.g., titanium ions) into the memristive material. A function of the memristive material portion 130 may be understood in terms of movable vacancies V+ that can be locallytrapped in regions of the memristive material portion 130. The traps T may be introduced adjacent to the first electrode 110 and second electrode 120 and the movable vacancies V+ may selectively move either into the region adjacent to the first electrode 110 or into the region adjacent to the second electrode 120 and trapped there accordingly in an electric field. This may allow for generating selectively a Schottky-type diode either with maximum barrier height at the first electrode 110 or with maximum barrier height at the second electrode 120 such that the memristive structure 100 exhibit a nonlinear switching behavior and is selfrectifying.

[0026] A memristive structure (also referred to as memristive device, memristive element, resistive switch, memristor, memristor element, or memristor structure) may be regarded as an analog memristive structure in the case that the memristive structure exhibits a continuous change in current (e.g., in the read current Iread ) when (e.g., linearly) ramping the applied voltage (e.g., from 0 V to +Vmax and from +Vmax to 0 V and from 0 V to -Vmax and from -Vmax to 0 V), as illustrated, for example, in FIG.2A and FIG.2B. This current may be associated with a current through the memristive structure 100. In the following various aspects are described with reference to the memristive structure 100; it is noted th at this serves for illustration and that other memristive structures may be used accordingly.

[0027] Up to now, a memristive structure was set either into a high resistive state (HRS) or a low resistive state (LRS). This process of setting the memristive structure into the high resistive state (HRS) or the low resistive state (LRS) was often referred to as writing a memristive state of the memristive structure. However, according to various aspects, an applied write signal (e.g., a maximum applied voltage value or a maximum applied current value, a shape of the write signal, etc.) may define the memristive state into which the memristive structure is written in (e.g., in the case of a voltage signal, the memristive state after reducing the voltage to 0 V). This curve associated with changing the memristive states may be denoted as transition curve. It is found that this transition curve is common for all memristive states. Further, it is found that each memristive state is associated with a corresponding resistance-characteristic curve such that information about the resistance-characteristic curve allows to conclude the memristive state the memristive structure is in. Hence, each resistance-characteristic curve may be unambiguously assigned to a respective memristive state, and vice versa. This resistance-characteristic curve may be independent on how the memristive structure was set into the corresponding memristive state. It is understood that any memristive structure may be read using one or more reading schemes and that any kind of device which includes at least one memristive structure may employ any of the reading schemes. According to an example, the device may include a read / write circuit configured to read out and / or write the memristive state of the at least one memristive structure. According to another example, the device may be (e.g., for analysis) coupled to another device which is configured to apply a read / write signal to the memristive structure in order to read out and / or write the memristive state of the at least one memristive structure.

[0028] According to various aspects, a read / write signal may be applied to the memristive structure to set a memristive state and / or to read a prior set memristive state. The read / write signal may be, for example, a signal pulse. The memristive structure 100 may be addressed via a voltage-driven mode or a current- driven mode. In the case of the voltage-driven mode, a voltage signal (e.g., a voltage pulse) may be applied to the memristive structure 100 and an induced current through the memristive structure 100 may be determined (e.g., measured). In the case of the current-driven mode, a current signal (e.g., a current pulse) may be applied to the memristive structure 100 and an induced voltage may be determined (e.g., measured). Herein, various aspects of memristive structures and of various reading schemes are described for thevoltage-driven mode (e.g., in the case of the shown IV-characteristics). It is noted that this serves for illustration and that other modes, such as the current-driven mode, can be used accordingly.

[0029] FIG.2A shows a first exemplary ramping scheme 200a that can be used to set the memristive structure 100 into a high resistive state (HRS) and a second exemplary ramping schemes 200b that can be used to set the memristive structure 100 into a low resistive state (LRS). FIG.2B shows an exemplary current / voltage (l / V) characteristic of the memristive structure 100 obtained via the two exemplary ramping schemes 200a, 200b, according to various aspects. FIG.2C shows two equivalent circuits representing the electrical condition of a memristive structure for the HRS and the LRS. The memristive structure 100 may be in a self-rectifying configuration. The self-rectifying configuration and / or the desired switching behavior may be caused by a formation of a diode (e.g., a Schottky contact) and a resistor at the interfaces between the first electrode 110 and the memristive element 130 and between the second electrode 120 and the memristive element 130 (the memristive element 130 may be a memristive material portion). The diode and the resistor are coupled to one another in a series connection and provide the described HRS and LRS states for a defined polarity. The switching of the memristive structure 100 and therefore the presence of a diodecontact or a resistive contact at the respective electrode regions may be defined by the memristive material, e.g., by presence and / or absence of oxygen vacancies in the electrode regions.

[0030] It is understood that the IV-characteristics shown in FIG.2B are exemplary and schematically serving for illustration and that the IV-characteristic of a memristive structure may be different. In particular, many different types of IV-characteristics are possible for various kinds of memristive structures (e.g., depending on the material, the size, the thickness of the layers, etc.). FIG.2D to FIG.2F each show an exemplarily measured IV-characteristic of a respective memristive structure.

[0031] Up to now, the memristive structure 100 may be set into a well-defined memristive state by applying an initialization voltage, Vini , (in some aspects referred to as programming voltage or write voltage) and subsequently applying a desired write voltage scheme to set a memristive state in which the memristive structure 100 is residing in after the write voltage has been applied.

[0032] As shown in FIG.2A, the memristive structure 100 may be set into the low resistive state (LRS, branch 2) by ramping the voltage from 0 V to +|Vmax | (branch 1) and into low resistance state (LRS, branch 4) by ramping the voltage from 0V to -|Vmax| (branch 3). As shown in FIG.2B, the memristive structure 100 may be set into the low resistive state (LRS, branch 2) by ramping the voltage from 0 V to -|Vmax | (branch 1) and into low resistance state (LRS, branch 4) by ramping the voltage from 0V to +|Vmax| (branch 3). The resistance state in branch 2 and in branch 4 in FIG.2A can be determined by applying a read voltage that is less than the write voltage and has the same polarity as the write voltage, i.e. positive polarity in branch 2 and negative polarity in branch 4. The resistance state in branch 2 and in branch 4 in FIG.2B may be determined by applying a read voltage (value) that is smaller than the write voltage (value) and has the same polarity as the write voltage (value), i.e. a negative polarity in branch 2 and positive polarity in branch 4. In this case, the state of the memristive structure 100 may be read out by applying a positive read voltage having a voltage value between about 0 V and about +Vmax . Depending on the state of the memristive structure 100, the applied read voltage always causes a larger current flow associated with low resistance state in comparison to the small current flow flowing during application of the write voltage. Here, the voltage, V, may be ramped up to a maximum positive voltage value, +Vmax , and up to a maximum negative voltage value, -Vmax . In an example, the respective maximum voltage, |Vmax |, may be the highest voltage that can be applied such that no breakdown (e.g., of the diode described with reference to FIG.2C) occurs. In anotherexample, the respective maximum voltage, |Vmax |, may have any voltage value different from 0. However, as described above, these complex writing schemes may not be necessary by employing the findings that the high resistive state (HRS) is always associated with changing memristive states (branches 1 and 3 in FIG.2A and branches 1 and 3 in FIG.2B) and that each memristive state is associated with a corresponding resistance-characteristic curve (branches 2 and 4 in FIG.2A and branches 2 and 4 in FIG.2B).

[0033] FIG.3A shows a schematic IV-characteristic of the memristive structure 100 exemplarily for the first quadrant of the IV-diagram. The following description may apply similarly to the third quadrant. For example, the first quadrant and the third quadrant may be associated with a respective transition curve. Also, the first quadrant (i.e., positive applied voltages) may be associated with a plurality of (positive) memristive states and the third quadrant (i.e., negative applied voltages) may be associated with a plurality of (negative) memristive states. It is understood that, in some aspects, the described behavior may be only present in either the first quadrant or the third quadrant. FIG.3A also shows a voltage signal scheme including writing (dashed lines) as well as reading (solid lines) memristive states.

[0034] As exemplarily shown for the first quadrant, the transition curve 302 (branch 1) may be associated with changing the resistivity of the memristive structure 100 (e.g., via moving traps T), thereby changing the memristive state, ms. Each current-voltage (l-V) data point, l(V), on the transition curve 302 may be associated with a corresponding memristive state, 1 < ms< M (with M being any integer number equal to or greater than one (e.g., equal to or greater than 100, e.g., equal to or greater than 200, etc.), of the memristive structure 100. This transition curve 302 may be associated with the HRS state. As described herein, it is found that, when setting the memristive structure into a respective memristive state, this transition curve 302 is similar for all memristive states (since each data point of the transition curve 302 corresponds to a respective memristive state). Hence, a memristive structure 100 has one transition curve 302 (transitioning from a lowest memristive state, ms= 1 , over various intermediate memristive states to a highest memristive state, ms= M). For illustration, the transition curve 302 is herein shown (substantially) linearly. It is understood that the transition curve 302 may have any course depending the memristive structure. FIG.3B shows an IV-characteristic measured for a manufactured memristive structure illustrating that the transition curve 302 can have a substantially linear course. However, it is noted that there may be a highest memristive state, ms= M, associated with a corresponding voltage value. Within the same quadrant (e.g., the first or the third quadrant), the memristive states (from ms= 2 to ms= M-1) between the lowest memristive state, ms= 1, and the highest memristive state, ms= M, may be referred to as intermediate memristive states. When applying a voltage having a voltage value greater than the voltage value corresponding to the highest memristive state, ms= M, the memristive structure 100 may be set into the highest memristive state. In this case, the transition curve 302 may, at the voltage value corresponding to the highest memristive state, (e.g., slowly) change from the linear behavior into saturation (hence a substantially stable current). It is understood that by further increasing the voltage value beyond that saturation regime, the current value may increase significantly due to the diode character of the memristive structure 100 (hence, a breakthrough of the Schottky-type diode).

[0035] As described herein, each memristive state (thus, each data point, I (V)), on the transition curve 302) may be associated with (e.g., unambiguously assigned to) a corresponding resistance-characteristic curve (branch 2 in the case of the branch 1 transition curve or branch 4 in the case of the branch 3 transition curve) (as understood up to the highest memristive state). This resistance-characteristic curve may be characteristic for a corresponding memristive state (hence characteristic for the resistance corresponding tothe memristive state). A resistance-characteristic curve may be understood as a respective characteristic LRS curve for each memristive state. FIG.3A schematically shows a first resistance-characteristic curve 304 (e.g., a first LRS curve) corresponding to a first memristive state, a second resistance-characteristic curve 306 (e.g., a second LRS curve) corresponding to a second memristive state different from the first memristive state, and a third resistance-characteristic curve 308 (e.g., a third LRS curve) corresponding to a third memristive state different from both, the first memristive state and the second memristive state. FIG.3B shows the common transition curve 302 (HRS curve) and a corresponding (individual) resistancecharacteristic curve (hence, a respective LRS curve) for five different memristive states set via a respective programming voltage (6 V, 6,5 V, 7 V, 7,5 V, and 8 V).

[0036] Thus, depending on the memristive state the memristive structure resides in, the IV-characteristic may follow the transition curve 302 (in the case of changing the memristive state) or may follow the resistance-characteristic curve corresponding to a current memristive state (in the case of keeping (i.e., not changing) the memristive state). Hence, a measured IV-characteristic may depend on a current memristive state of the memristive structure 100. To program a memristive state and / or to determine the current memristive state of the memristive structure 100, a (e.g., measurement) signal may be applied to the memristive structure 100. For example, the measurement signal may be a measurement pulse (e.g., a voltage pulse or a current pulse).

[0037] As detailed above, herein the measurement source / input signal (short measurement signal) is described as voltage pulse for illustration and the measurement output signal is described as corresponding current pulse for illustration. Exemplary courses and shapes of one or more voltage pulses are shown in FIG.4A to FIG.4E. For simplicity, the voltage pulses are shown rising from and falling to 0 V as base voltage. It is understood that the base voltage may have any suitable voltage value. According to some aspects, the voltage may be applied to one of the first electrode 110 or the second electrode 120 and that the base voltage may be applied to the other one of the first electrode 110 or the second electrode 120. According to other aspects, a respective voltage (different from the base voltage) may be applied the first electrode 110 and to the second electrode 120. In this case, the voltage values of herein described voltages (e.g., the maximum positive read voltage value, +Vread,max , the maximum negative read voltage value, +Vread,max , etc.) may be voltage drops over the memristive structure 100 (hence a voltage difference between the voltage applied at the first electrode 110 and the voltage applied at the second electrode 120).

[0038] As shown, a voltage pulse may have a linear triangular course (see, for example, FIG.4A and FIG4B), a stepwise triangular course (see, for example, FIG.4C), a sinusoidal course (see, for example, FIG.4D), or an exponentially falling / rising course (see, for example, FIG.4E), as examples. It is understood that any other course and / or shape may be used. Even though these voltage pulses are described as read signals, it is understood that a write signal may have a similar course and / or shape. A voltage pulse may be characterized by a rising edge from the base voltage (e.g., 0 V) to a maximum read voltage value and a falling edge from the maximum read voltage value to the base voltage (e.g., 0 V). For example, a first voltage pulse may be characterized by a rising edge 402 from the base voltage (e.g., 0 V) to a maximum positive read voltage value, +Vread,max , and a falling edge 404 from the maximum positive read voltage value,+Vread,max , to the base voltage (e.g., 0 V). A second voltage pulse may be characterized by a rising edge 406 from the base voltage (e.g., 0 V) to a maximum negative read voltage value, -Vread.max , and a falling edge 408 from the maximum negative read voltage value, -Vread.max , to the base voltage (e.g., 0 V). A rising edge may be associated with (e.g., continuously) increasing (e.g., ramping) a voltage up to up to themaximum (positive or negative) voltage value (different from zero volts). According to various aspects, only one voltage pulse (e.g., the first voltage pulse or the second voltage pulse) may be applied. According to other aspects, the first voltage pulse and the second voltage pulse may be (in any order) applied subsequent to each other. In this case, the first voltage pulse and the second voltage pulse may be (in any order) applied directly subsequent to each other or there may be a time delay between them.

[0039] As described herein, a measured IV-characteristic (e.g., branch 2 and / or branch 4) depend on a current (i.e., an actual or present) memristive state of the memristive structure 100. This memristive state of the memristive structure 100 may depend on a prior applied measurement signal (in the present example a prior applied voltage signal). The memristive state may be set by applying a programming voltage pulse. For simplicity, in the following, the maximum voltage (in some aspects referred to as programming voltage) of the programming voltage pulse is considered as defining the memristive state the memristive structure 100 is set into. However, it is noted that the memristive state into which the memristive structure 100 is set by applying the programming voltage pulse may also depend on other aspects, such as the shape and / or course of the programming voltage pulse.

[0040] Hence, the curre nt / voltage (I Z) characteristic of the memristive structure 100 can depend on a prior applied voltage value, Vprior , associated with a prior applied voltage. FIG.5A to FIG.5E schematically show a respective IV-characteristic depending on the prior applied voltage value, Vprior , for the memristive structure 100 having the IV-characteristic shown in FIG.3A. In the case that a prior voltage has a negative voltage value (i.e., Vprior < 0), the memristive structure 100 resides either in a (negative) memristive state associated with the third quadrant (i.e., a negative voltage value and a negative current value) since the negative voltage would either write a (negative) memristive state associated with the third quadrant (e.g., in the case that the memristive structure 100 is in a memristive state associated with the first quadrant or in a memristive state associated with a negative voltage value having an absolute value less than the voltage value of the applied negative voltage) or would keep the (negative) memristive state in the case that the memristive structure 100 is in a (negative) memristive state associated with a negative voltage value having an absolute value greater than the voltage value of the applied negative voltage. When applying a first read voltage pulse (e.g., having a shape and / or course as shown in FIG.4A, FIG.4C, FIG.4D, or FIG.4E) with a first voltage value, Vi , as maximum positive read voltage value, +Vread,max , the rising edge 402 of the first read voltage pulse (continuously) changes the memristive state, ms, (over the memristive states starting from ms= 1) until setting the memristive structure 100 into the memristive state ms= ms(Vi ) associated with the first voltage value, Vi (see FIG.5A). Hence, the IV-characteristic follows the transition curve 302 during the rising edge 402 of the first read voltage pulse. The falling edge 404 of the first read voltage pulse keeps (i.e., does not change) the set (e.g., written) memristive state ms= ms(Vi ) since the voltage value is reduced (and not further increased). Hence, the IV-characteristic follows the first resistance-characteristic curve 304 associated with the first voltage value, Vi , during the falling edge 404 of the first read voltage pulse. When applying a (subsequent) second read voltage pulse (having the same polarity as the first read voltage pulse) with another voltage value, Vo , (being less than the first voltage value, Vi ,) as maximum positive read voltage value, +Vread,max , the rising edge 402 of the second read voltage pulse keeps (i.e., does not change) the memristive state ms= ms(Vi ) (see FIG.5B). Therefore, the rising edge 402 of the second read voltage pulse follows the first resistance-characteristic curve 304 associated with the first voltage value, Vi . When applying a third read voltage pulse (having the same polarity as the first read voltage pulse) with the first voltage value, Vi , as maximum positive read voltage value, +Vread,max , the rising edge 402 of the third read voltage pulsekeeps (i.e., does not change) the memristive state ms= ms(Vi ) up to the first voltage value, Vi (see FIG.5C). Therefore, the rising edge 402 of the third read voltage pulse follows the first resistance-characteristic curve 304 associated with the first voltage value, Vi , up to the first voltage value, Vi . When applying a fourth read voltage pulse (having the same polarity as the first read voltage pulse) with a second voltage value, V2 , (being greater than the first voltage value, Vi ,) as maximum positive read voltage value, +Vread,max , the rising edge 402 of the second read voltage pulse keeps (i.e., does not change) the memristive state ms= ms(Vi ) up to the first voltage value, Vi (see FIG.5D). Therefore, the rising edge 402 of the second read voltage pulse follows the first resistance-characteristic curve 304 associated with the first voltage value, Vi , up to the first voltage value, Vi . Once the voltage value of the rising edge 402 surpasses (hence, is greater than) the first voltage value, Vi , the memristive state msof the memristive structure 100 is (continuously) changed (starting from the memristive state ms= ms(Vi ) to the memristive state ms= ms(V2 ). Hence, from the first voltage value, Vi , to the second voltage value, V2 , the rising edge 402 of the fourth read voltage pulse follows the transition curve 302. The falling edge 404 of the fourth read voltage pulse keeps (i.e., does not change) the set (e.g., written) memristive state ms= ms(V2 ) since the voltage value is reduced. Hence, the IV-characteristic follows the second resistance-characteristic curve 306 associated with the second voltage value, V2 , during the falling edge 404 of the fourth read voltage pulse. This applies similar to applying any read voltage pulse having a greater voltage value (up to the highest voltage value) than a prior applied read voltage pulse. Hence, when applying a (subsequent) fifth read voltage pulse (having the same polarity as the second read voltage pulse) with a third voltage value, V3 , (being greater than the second voltage value, V2 ,) as maximum positive read voltage value, +Vread,max , the IV-characteristic of the memristive structure 100 follows the second resistance-characteristic curve 306 associated with the second voltage value, V2 , up to the second voltage value, V2 during the rising edge 402 of the fifth read voltage pulse and follows the transition curve 302 from the second voltage value, V2 , to the third voltage value, V3 . The falling edge 404 of the fifth read voltage pulse keeps the set memristive state ms= ms(V3 ) and the IV- characteristic, therefore, follows the third resistance-characteristic curve 308 associated with the third voltage value, V3 .

[0041] According to various aspects, a memristive state of the memristive structure 100 may be read either non-destructively (while keeping the memristive state) or destructively (which includes changing the memristive state).

[0042] In the case of a non-destructive read, the memristive structure 100 may reside in a memristive state, ms(+VProgram ), associated with a positive programming voltage value, +Vprogram , equal to or greater than the maximum read voltage value, +Vread,max , of the read voltage pulse. In this case, as described herein (e.g., regarding FIG.5A to FIG.5E), the rising edge 402 of the read voltage pulse causes a current through the memristive structure 100 according to the resistance-characteristic curve corresponding to the memristive state, ms(+Vprogram ). Hence, applying the read voltage pulse may keep the memristive state, ms(+Vpragram ), associated with the positive programming voltage. This allows, for example, to read the memristive state, ms(+VProgram ), of the memristive structure 100 multiple times as long as the respective maximum read voltage value, +Vread,max , of each read voltage pulse is equal to or lower than the positive programming voltage value, +VprOgram (and of course within the same quadrant, i.e., having the same polarity). When ramping the read voltage in a range between the base voltage (e.g., 0 V) and the maximum read voltage value, +Vread,max , less than the programming voltage value, +Vpragram , also the falling edge 404 of the read voltage pulse causes a current according to the resistance-characteristic curve corresponding to thememristive state, ms(+Vprogram ), (since the memristive state is not changed by the maximum read voltage value, +Vread,max ). It is understood that, in this example, no negative voltages may be applied since, as described herein, a negative voltage would write a memristive state in the third quadrant of the 1 / V characteristic.

[0043] In the case of a destructive read, the memristive structure 100 may reside in a memristive state, ms(+VProgram ), associated with a positive programming voltage value, +Vprogram , less than the maximum read voltage value, +V read, max , of the read voltage pulse. In this case, as described herein (e.g., regarding FIG.5A to FIG.5E), the rising edge 402 of the read voltage pulse causes, once the voltage value surpasses the positive programming voltage value, +VprOgram , a current through the memristive structure 100 according to the transition curve (e.g., transition curve 302). Hence, applying the read voltage pulse may change the memristive state from the memristive state, ms(+VprOgram ), associated with the positive programming voltage to the memristive state, ms(+Vread,max ), associated with the maximum read voltage value, +Vread,max .

[0044] FIG.6A to FIG.6C each show a device 600 according to various aspects. The device 600 may be a memory device or a storage device. For example, the device 600 may be an n -logic memory. The device 600 may include a plurality of memristive structures 602 (n = 2 to N). “N” may be any integer number equal to or greater than two. According to various aspects, “N” may be any integer number equal to or greater than twenty (e.g., equal to or greater than one hundred).

[0045] The device 600 may include an operation circuit 600c. As described herein, the operation circuit 600c may be configured to write and read out a respective logic state (of two or more logic states) of each memristive structure of the plurality of memristive structures 602(n = 2 to N) based on a challenge-response scheme as described herein. The device 600 may include one or more processors 604 (the one or more processors 604 may be a controller or part of a controller; the controller may be a PUF controller). The one or more processors 604 may be configured to determine a key 606. The key 606 may be, for example, a private key or an authentication key. According to some aspects, the one or more processors 604 may be configured to determine the key 606 based on the logic states determined for the plurality of memristive structures 602(n = 2 to N). According to various aspects, process variations or deviations among the plurality of memristive structures 602(n = 1 to N) may be employed to generate the key 606. Thereby, the plurality of memristive structures 602(n = 1 to N) may be a physical unclonable function (PUF). In particular, variations of the production process may induce variations of the plurality of memristive structures 602(n = 1 to N). The variations of the production process introduce randomness into the properties of the plurality of memristive structures 602(n = 1 to N) and can therefore provide the entropy for generating the key 606. Such variations in the properties of the plurality of memristive structures 602(n = 1 to N) may lead to differences in the IV- characteristics of the plurality of memristive structures 602(n = 1 to N).

[0046] According to various aspects, the device 600 may include a random number generator and the operation circuit 600c may be configured to select the memristive state into which a respective memristive element 602 of the plurality of memristive elements is to be written from the plurality of memristive states based on a random number generated by the random number generator. This may further increase the randomness and, thus, the security. The device 600 may be any device which may be used or may be employed to generate a key (e.g., a cryptographic key 608 derived from the key 606), a random number (e.g., a random number 610 derived from the key 606), etc. Thus, the device 600 may be or may be part of any suitable security device. For example, the device 600 may be or may be part of a hardware security module, a security key (e.g., a Universal Serial Bus (USB) security key), and / or a secure crypto-processor.

[0047] Various aspects described herein may be related to a memristive structure that can be configured and operated in such a way, that a physical unclonable function (PUF) can be realized with a high security level and a high reliability. A physical unclonable function, or PUF, may be understood as a physical object (e.g., a hardware device) that for a given input and conditions (referred to as a challenge), provides a physically defined output (referred to as a response) that serves as a unique identifier. The physical unclonable function described herein is based on unique physical variations occurring naturally during manufacturing. In contrast to a conventionally used PUF technology that is based on inter-devicevariations, the PUF described herein utilizes in-device-variations in each of the used memristive structures. The utilized in-device-variation of the novel PUF technology described herein generates a response for a memristive structure and at the same time a reference is provided from the same memristive structure to deriving the secret (e.g., to derive the key element, e.g., to derive whether the response represents a first or second logic state (usually referred to as “0” or “1”)) related to the memristive structure.

[0048] Various aspects of a method for generating a key based on a physical unclonable function and various aspects of a physical unclonable function are described in the following exemplarily for a memristive structure including one or more memristive elements. However, it is clear that any desired number of memristive structures can be included in a physical unclonable function or in a hardware device (e.g., in a security chip, in a device for identification and authentication in 5G / 6G network environment, etc.,) including the physical unclonable function.

[0049] The various aspects of the physical unclonable function described herein may address problems associated with conventional realizations of a physical unclonable function. Classical computers and quantum computers may only compute algebraic functions. Based on a memristive structure as described herein, transcendental functions (e.g., functions that can not be described by a polynomial equation, e.g., non-algebraic functions) can be implemented as a basis in the physical unclonable function. This allows for a development of a quantum-safe hardware solution for the implementation of zero trust principles, i.e. for a mutual confirmation of the identity and authenticity, for trusted exchange of information in unsecured networks, as an example. According to various aspects, the physical unclonable function physical unclonable function that utilizes, as described herein, a transcendental challenge input and key response approach provides quantum-safe random and unique secret keys.

[0050] According to various aspects, a cryptographic key generator (see device 600) is provided based on memristive structures as described herein. The memristive structures may have an electric characteristic (e.g., an I N characteristic) that allows for generating at least two different challenge / response pairs based on various l / V branches (see, for example, FIG.2B, FIG.2D, FIG.2E, and FIG.2F).

[0051] The memristive structures of the PUF described herein may be a passive electronic device with reconfigurable internal resistance states which has a transcendental challenge / key response function. Therefore, the generation of key response and generation of transcendental input / response function is merged in the PUF based on the memristive structures. This allows for a realization of a quantum-safe cryptographic key generator with memristive structures based PUFs which will provide quantum-safe random and unique secret keys. Even though memristive structures with one or more memristive elements may have some unique advantages for generating a key based thereon (for example, the response of a memristive structure can be transcendent, the memristive structure may include a multi-branch memristive element to implement more than one challenge / response via the same multi-branch memristive element, the memristive structure can be operated current driven and / or voltage driven such that the challenge can be a currentchallenge and / or a voltage challenge), as explained herein, any other suitable response structure with one or more response elements may be used on the same or in a similar way for generating a key (e.g., any response structure including one or more response elements that allows for a generation of entropy for generating a key via a PUF).

[0052] FIG.7A shows a schematic flow diagram of a method for generating a key based on a physical unclonable function 700. According to various aspects, the method may be implemented in the operation circuit 600c of the device 600 such that the device 600 is a physical unclonable function 700 or, in other aspects, the method may be implemented in any other suitable operation circuit 700c (the operation circuit may include a PUF controller) of a physical unclonable function device 700. According to various aspects, the method may include, in 710, generating a plurality of key elements 730e of a key 730 by operating each response structure 740m of a plurality of response structures 740 in accordance with a linked challenge / response operation 720. The linked challenge / response operation 720 is applied to each response structure 740m of the plurality of response structures 740 and includes a first challenge operation 720-1 that includes applying a first challenge to a respective response structure to cause a first response of the respective response structure as a function of the first challenge. The linked challenge / response operation further includes a second challenge operation 720-2 that includes applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge. The linked challenge / response operation 720 further includes a result determination operation 720-3 (also referred to as output determination operation) that includes causing a result (also referred to as output) representing a respective key element 730e of the key 730 corresponding to the respective response structure, wherein the result is a function I) of the first challenge or the first response and II) of the second challenge or the second response.

[0053] According to various aspects, the linked challenge / response operation 720 described herein includes that the output (e.g., based on the result of a comparison of the first challenge or the first response with the second challenge or the second response) of a response structure (illustratively the final response) in a PUF operation is a function of two challenge / response sub-operations that are linked with one another (e.g., referred to as linked challenge / response operation. The two challenge / response sub-operations can be applied to a same element of a response structure (in this case, for example, the response structure may be implemented via a single response element) or, alternatively, the two challenge / response suboperations can be applied to two distinct response elements of a same response structure (in this case, for example, the response structure may be implemented via two response elements).

[0054] The two challenge / response sub-operations may include a first sub-challenge / response operation and a second sub-challenge / response operation, the first sub-challenge / response operation includes the first challenge and the first response and the second sub-challenge / response operation includes the second challenge and the second response. According to various aspects, the first challenge may include a first challenge signal (CS1 (t, CS 1 max)) and the first response may include a first response signal (RS1 (t,RS1max)) caused by the first challenge signal (CS1 (t,CS1max)) as a function of a first electric characteristic of the response structure. Further, the second challenge may include a second challenge signal (CS2(t,CS2max)) and the second response may include a second response signal (RS2(t,RS2max)) caused by the second challenge signal (CS2(t,CS2max)) as a function of a second electric characteristic of the response structure different from the first electric characteristic of the response structure. According to various aspects, the first sub-challenge / response operation may include applying a first challenge signal(CS1 (t,CS1 max)) and thereby causing a first response signal (RS1 (t, RS1 max)) as a function of a first electric characteristic of the response structure. Further, the second sub-challenge / response operation may include applying a second challenge signal (CS2(t,CS2max)) and thereby causing a second response signal (RS2(t,RS2max)) as a function of a second electric characteristic of the response structure different from the first electric characteristic of the response structure. According to various aspects, in the case that the response structure includes a first response element and a second response element different from the first response element, the first electric characteristic of the response structure may be defined by the first response element and the second electric characteristic of the response structure may be defined by the second response element. According to various aspects, in the case that the response structure includes only a single response element, the first electric characteristic of the response structure may be defined by a first l / V-branch of the response element (e.g., the response element may be in this case a multi branch memristive element) and the second electric characteristic of the response structure may be defined by a second l / V-branch of the same response element (see branches 1 to 4 in FIGs.2A to 2F, for example).

[0055] According to various aspects, as illustrated in FIG.7B in a schematic overview, the physical unclonable function 700 may be configured to:• (in a first configuration 700-1) provide a relationship (e.g., referred to as a link) between the first challenge signal (CS1 (t,CS1 max)) and the second challenge signal (CS2(t,CS2max)) and determine the output based on a relationship between the first response signal (RS1 (t,RS1max)) and the second response signal (RS2(t,RS2 max )); or• (in a second configuration 700-2) provide a relationship (e.g., referred to as a link) between the first challenge signal (CS1 (t,CS1 max)) and the second response signal (RS2(t,RS2max)) and determine the output based on a relationship between the first response signal (RS1 (t,RS1max)) and the second challenge signal (CS2(t,CS2 max )); or• (in a third configuration 700-3) provide a relationship (e.g., referred to as a link) between the first response signal (RS1 (t,RS1max)) and the second challenge signal (CS2(t,CS2max)) and determine the output based on a relationship between the first challenge signal (CS1 (t,CS1max)) and the second response signal (RS2(t,RS2 max )); or• (in a fourth configuration 700-4) provide a relationship (e.g., referred to as a link) between the first response signal (RS1 (t,RS1max)) and the second response signal (RS2(t,RS2max)) and determine the output based on a relationship between the first challenge signal (CS1 (t,CS1max)) and the second challenge signal (CS2(t,CS2 max))-

[0056] According to various aspects, the response structure may be an electric response structure having one or more electric response elements and the electric response structure may receive an electric challenge signal and cause an electric response signal based on characteristic electric (referred to as l / V) properties of the electric response structure. In some aspects, the electric response structure may be a memristive structure including one or more memristive elements as the one or more response elements. A memristive element, for example, can be operated selectively in two distinct ways, either current driven or voltage driven. In this case, the electric response structure can selectively either receive a current signal as challenge signal and cause a voltage signal as response signal or receive a voltage signal as challenge signal and cause a current signal as response signal. In the case that the memristive structure includes more than one memristive element, the memristive structure can be configured to receive a current signalas challenge signal and cause a current signal as response signal or receive a voltage signal as challenge signal and cause a voltage signal as response signal, for example.

[0057] According to various aspects, the first challenge signal can be applied to a first response element of the response structure and the second challenge signal can be applied (e.g., in a same time interval) to a second response element of the response structure to receive the first response signal and the second response signal in the same time interval and to directly determine the output based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response in the same time interval. In this configuration, there may be no need to store information for a determination of the output. However, in another configuration, the first challenge signal can be applied to a response element of the response structure in a first time interval and the second challenge signal can be applied to the (very same) response element of the response structure in a second time interval different from the first time interval to receive the first response signal and the second response signal in different time intervals. Therefore, at least some data representing I) the first challenge or the first response and / or II) the second challenge or the second response have to be stored for determining the output based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response in the same time interval.

[0058] According to various aspects, in the case that the response structure is an electric response structure, as illustrated in FIG.7C to FIG.7F in a schematic view for each of the configurations 700-1 , 700-2, 700-3,700-4, the first challenge signal may be a first voltage signal (CV1 (t,CV1max)) and the first response signal may be a first current signal (RI1 (t.RHmax)); and the second challenge signal may be a second current signal (CI21 (t,CI2max)) and the second response signal may be a second voltage signal (RV2(t,RV2max)). According to other aspects, in the case that the response structure is an electric response structure, the first challenge signal may be a first current signal (CI1 (t, CI1 max)) and the first response signal may be a first voltage signal (RV1 (t,RV1max)); and the second challenge signal may be a second voltage signal (CV2(t,CV2max)) and the second response signal may be a second current signal (RI2(t,RI2max)). According to other aspects, in the case that the response structure is an electric response structure, the first challenge signal may be a first voltage signal (CV1 (t,CV1 max)) and the first response signal may be a first current signal (RI1 (t.RHmax)); and the second challenge signal may be a second voltage signal (CV2(t,CV2max)) and the second response signal may be a second current signal (RI2(t,RI2max)). According to other aspects, in the case that the response structure is an electric response structure, the first challenge signal may be a first current signal (CI1 (t, CI1 max)) and the first response signal may be a first voltage signal (RV1 (t, RV1 max)); and the second challenge signal may be a second current signal (CI21 (t,CI2 max)) and the second response signal may be a second voltage signal (RV2(t,RV2max)).

[0059] FIG.8A to FIG.8C shows a schematic circuit diagram of an electric response structure 800 (e.g., of a memristive structure) that allows for linking respectively two electric signals in hardware by use of two electric response elements 800e-1, 800e-2 (e.g., of two memristive elements). As shown in FIG.8A, two current signals (11 (t, 11 max)), (I2(t,l2max)) can be linked by a series connection of the electric response elements 800e-1 , 800e-2, since both electric response elements 800e-1 , 800e-2 see the same current provided by a current source. The respective voltage signals (V1 (t,V1 max)), (V2(t,V2max)) can be determined for each of the two electric response elements 800e-1, 800e-2 by a respective parallel connection of voltage determination means (e.g., by a voltage meter). As shown in FIG.8B, two voltage signals (V1 (t,V1 max)), (V2(t,V2max)) can be linked by a parallel connection of the electric response elements800e-1 , 800e-2, since both electric response elements 800e-1 , 800e-2 see the same voltage provided by a voltage source. The respective current signals (11 (t,Hmax)), (I2(t,l2max)) can be determined for each of the two electric response elements 800e-1, 800e-2 by a respective series connection of current determination means (e.g., by an ampere meter). As shown in FIG.8C, a voltage signal (V2(t,V2max)) and a current signal (11 (t,l1 max)) can be linked by use of a resistor in addition to the two electric response elements 800e-1 , 800e-2, since a voltage drop (V2(t,V2max)) over the resistor is linked to the current (11 (t, Umax)) provided by the current source through the first response element 800e-1 and, therefore, the voltage drop (V2(t,V2max)) over the resistor can be utilized as voltage source for the second response element 800e-2. The corresponding voltage signal (V1 (t,V1max)) can be determined for the first electric response element 800e-1 by a respective parallel connection of voltage determination means (e.g., by a voltage meter) and the respective current signal (I2(t, I2max)) can be determined for the second electric response element 800e-2 by a respective series connection of current determination means (e.g., by an ampere meter). According to various aspects, the resistor that is configured to link the voltage signal (V2(t,V2max)) and the current signal (11 (t,H max)) with one another may be a non-linear resistor, e.g., a memristor, to increase complexity of the electric response structure.

[0060] FIG.8D to FIG.8E shows a schematic circuit diagram for determining the output of the response structure based on a comparison of I) the first challenge or the first response with II) the second challenge or the second response. As shown in FIG.8D, two voltage signals (V1 (t,V1 max)), (V2(t,V2max))can be compared by any suitable voltage comparator 810, for example, by an analog operation amplifier comparator circuit. In the case that the two voltage signals may have opposite polarity, a converting operation amplifier comparator circuit can be used for the comparison. The output Vout of the operation amplifier comparator circuit 810 may represent, for example, a logic state (“0” or “1”, “high” or “low”) that may represent a respective key element 730e of the key 730 corresponding to the respective response structure.

[0061] As shown in FIG.8E, two current signals (11 (t, 11 max)), (I2(t,l2max))can be compared by any suitable current comparator 820, for example, by a CMOS current comparator circuit. The output of the suitable current comparator 820 can be either a voltage output Vout or a current output lout and may represent, for example, a logic state (“0” or “1”, “high” or “low”) that may represent a respective key element 730e of the key 730 corresponding to the respective response structure. Alternatively, as shown in FIG.8E, two current signals (11 (t, 11 max)), (I2(t,l2max)) can be compared by any combination of current integrators 830 (e.g., a operational amplifier integrator) and a voltage comparator 810 coupled to the outputs of the current integrators 830. This allows for a comparison of output voltages V1 out, V20Ut that represent the corresponding input currents (I1 (t,l1 max)) and (I2(t,l2max)) by a voltage comparator 810. The use of a current integrator 830 may also allow for a comparison of a voltage signal (V(t,Vmax)) with a current signal (l(t,lmax)), as illustrated in FIG.8F.

[0062] According to various aspects, the current signal (I (t,lmax)) can be integrated over a predefined time interval to cause a voltage representing a dynamic behavior of the current signal (l(t,lmax)) to increase complexity in generating an output of the electric response structure. Short integration times may be used to integrate quasi static current signals. According to various aspects, a response of the electric response structure can be determined dynamically, e.g., a dynamic measurement signal can be integrated over a predefined time interval to generate a final measurement result representing the dynamic response of the electric response structure caused by the dynamic measurement signal. According to various aspects, aresponse of the electric response structure can be determined dynamically, e.g., a dynamic challenge signal can be used to cause a dynamic response signal and the dynamic response signal can be integrated over a predefined time interval to generate a final response result representing the dynamic response of the electric response structure caused by the dynamic challenge signal.

[0063] According to various aspects, the response structure may be configured as a memristive response structure (also referred to herein as memristive structure) including one or more memristive response elements (also referred to herein as memristive elements). FIG.9A, and FIG.9C show a schematic view of a current response (Rl(t, Rlmax)) of a memristive element 900e caused by a voltage driven challenge (CV(t,CVmax)) based on an l / V-characteristic (shown as plot of current density on linear and logarithmic scale) of a memristive element and FIG.9B and FIG.9D show a schematic view of a voltage response (RV(t,RV max)) of a memristive element 900e caused by a current driven challenge (Cl (t, Clmax)) based on an l / V-characteristic (shown as plot of current density on linear and logarithmic scale) of a memristive element. Various aspects of an 1 / V characteristic of a memristive structure and a memristive element (e.g., memristive element 900e) is explained above, for example, with reference to FIGs.1 to 5E.

[0064] According to various aspects, the current response Rl caused by the voltage challenge CV, as exemplarily shown in FIG.9A, can be defined by a point (l / V) in the IV-characteristic. In this case, the current response is caused directly by the applied voltage challenge. According to various aspects, the voltage response RV caused by the current challenge Cl, as exemplarily shown in FIG.9B, can be defined by a point (V / l) in the IV-characteristic. In this case, the voltage response is caused directly by the applied current challenge.

[0065] According to various aspects, the current response Rl caused by the voltage challenge CV, as exemplarily shown in FIG.9C, can be defined by two distinct points C(l / V) and R(l / V) in the IV- characteristic. In this case, the current response Rl is caused indirectly by the applied voltage challenge CV, since the applied voltage challenge CV writes the memristive element 900e into a memristive state and the current response Rl is specific for the written memristive state. In this case, the voltage challenge CV can be a write voltage signal to write the memristive element 900e into a memristive state and the current response Rl can be a read current signal caused by a predefined read voltage VRead applied to the memristive element 900e. According to various aspects, the voltage response RV caused by the current challenge Cl, as exemplarily shown in FIG.9D, can be defined by two distinct points C(V / I) and R(V / I) in the IV-characteristic. In this case, the voltage response RV is caused indirectly by the applied current challenge Cl, since the applied current challenge Cl writes the memristive element 900e into a memristive state and the voltage response RV is specific for the written memristive state. In this case, the current challenge Cl can be a write current signal to write the memristive element 900e into a memristive state and the voltage response RV can be a read voltage signal caused by a predefined read current ead applied to the memristive element 900e.

[0066] Furthermore, as illustrated in more detail in FIG.9E, FIG.9F, FIG.9G, and FIG.9H, an l / V- characteristic of a memristive element may have a positive write branch (1) and corresponding positive read branches (2) as well as a negative write branch (3) and corresponding negative read branches (4), see also FIG.3A and FIG.3B, wherein the l / V-characteristic of the positive branches is different from the l / V-characteristic of the negative branches. Therefore, two distinct challenge / response sub-operations that are linked with one another can be carried out via a single memristive element.

[0067] According to various aspects, a first sub-challenge / response operation can be carried out in a first IV-operation range (e.g., in a positive voltage and / or positive current range) and a second sub- challenge / response operation can be carried out in a second IV-operation range (e.g., in a negative voltage and / or negative current range). According to various aspects, a positive write branch (1) and one or more corresponding positive read branches (2) may be used for carrying out the first sub-challenge / response operation (with first challenge C1 and first response R1) and a negative write branch (3) and one or more corresponding negative read branches (4) may be used for carrying out the second sub- challenge / response operation (with second challenge C2 and second response R2).

[0068] According to various aspects, a first current response R11 caused by a first voltage challenge C1V, as exemplarily shown in FIG.9E, can be defined by a first point 1 (IAZ) in the IV-characteristic, and furthermore, a second current response R2I caused by a second voltage challenge C2V can be defined by a second point 2(IAZ) in the IV-characteristic of the very same memristive element 900e. In this case, the respective current response is caused directly by the corresponding applied voltage challenge. According to various aspects, a first voltage response R1 V caused by a first current challenge C11, as exemplarily shown in FIG.9F, can be defined by a first point 1 (V / l) in the IV-characteristic, and furthermore, a second voltage response R2V caused by a second current challenge C2I can be defined by a second point 2(V / I) in the IV-characteristic of the very same memristive element 900e. In this case, the respective voltage response is caused directly by the corresponding applied current challenge.

[0069] According to various aspects, a first current response R11 caused by a first voltage challenge C1 V, as exemplarily shown in FIG.9G, can be defined by two distinct points C1 (IAZ) and R1 (l / V) in the IV- characteristic and a second current response R2I caused by a second voltage challenge C2Vcan be defined by two other distinct points C2(l / V) and R2(l / V) in the IV-characteristic of the very same memristive element 900e. In this case, the respective current response R11, R2I is caused indirectly by the applied corresponding voltage challenge C1 V, C2V, since the applied voltage challenge C1 V, C2V writes the memristive element 900e into a respective memristive state and the current response R11, R2I is specific for the respectively written memristive state. The first current response R11 is specific for the first memristive state and the second current response R2I is specific for the second memristive state. In this case, the first voltage challenge C1 V can be a first write voltage signal to write the memristive element 900e into a first memristive state and the second voltage challenge C2V can be a second write voltage signal to write the memristive element 900e into a second memristive state different from the first memristive state. The first current response R11 can be a first read current signal caused by a predefined first read voltage Vl Read applied to the memristive element 900e and the second current response R2I can be a second read current signal caused by a predefined second read voltage V2Read applied to the memristive element 900e.

[0070] According to various aspects, a first voltage response R1 V caused by a first current challenge C11, as exemplarily shown in FIG.9H, can be defined by two distinct points C1 (V / l) and R1 (V / l) in the IV- characteristic and a second voltage response R2V caused by a second current challenge C2I can be defined by two other distinct points C2(V / I) and R2(V / I) in the IV-characteristic of the very same memristive element 900e. In this case, the first voltage response R1 V is caused indirectly by the applied first current challenge C11, since the applied first current challenge C11 writes the memristive element 900e into a first memristive state and the second voltage response R2V is caused indirectly by the applied second current challenge C2I, since the applied second current challenge C2I writes the memristive element 900e into asecond memristive state different from the first memristive state. The first voltage response R1 V is specific for the written first memristive state and the second voltage response R2V is specific for the written second memristive state. In this case, the first current challenge C11 can be a first write current signal to write the memristive element 900e into a first memristive state and the first voltage response R1 V can be a first read voltage signal caused by a predefined first read current 11 Read applied to the memristive element 900e and the second current challenge C2I can be a second write current signal to write the memristive element 900e into a second memristive state and the second voltage response R2V can be a second read voltage signal caused by a predefined second read current l2Read applied to the memristive element 900e.

[0071] According to various aspects, two distinct challenge / response sub-operations that are linked with one another can be carried out via a single memristive element using distinct read / write branches. As illustrated exemplarily in FIGs.9E to 9H, the distinct read / write branches can be in regions of the l / V- characteristic with opposite polarities; however, in other aspects, the distinct read / write branches can be in regions of the l / V-characteristics with the same polarity using distinct memristive states of the memristive element for the two distinct challenge / response sub-operations.

[0072] According to various aspects, the respective response structure may be configured such that the second challenge is defined by a comparison of the first response and the second response with one another. Only as an example, the second challenge may be a controlled voltage signal (for example, a voltage increasing over time) and the controlled voltage signal is deactivated or the voltage of the controlled voltage signal is kept constant from a time on at which a comparison of the first response and the second response with one another fulfills a predefined requirement (e.g., the first response and the second response may be voltage signals with the same voltage, e.g., the first response and the second response may be current signals with the same current, e.g., the first response and the second response may be signals with a predefined relationship to one another). In this case, for example, the output representing the key element may be determined based on a comparison of the first challenge and the second challenge with one another.

[0073] According to various aspects, the respective response structure may be configured such that the second challenge is defined by a comparison of the first challenge and the second response with one another. Only as an example, the second challenge may be a controlled voltage signal (for example, a voltage increasing over time) and the controlled voltage signal is deactivated or the voltage of the controlled voltage signal is kept constant from a time on at which a comparison of the first challenge and the second response with one another fulfills a predefined requirement (e.g., the first challenge and the second response may be voltage signals with the same voltage, e.g., the first challenge and the second response may be current signals with the same current, e.g., the first challenge and the second response may be signals with a predefined relationship to one another). In this case, for example, the output representing the key element may be determined based on a comparison of the first response and the second challenge with one another.

[0074] According to various aspects, the output representing the key element may be determined, according to various aspects, based on a comparison of signals (for example, of challenge signals and / or response signals, see FIG.7A to 7F for example). According to various aspects, the comparison of signals can be any suitable comparison. As an example, two voltage signals may be compared with one another by comparing the voltage values of the two voltage signals at the same time or at predefined times. As an example, two current signals may be compared with one another by comparing the current values of thetwo current signals at the same time or at predefined times. As an example, a voltage signal and a current signal may be compared with one another by comparing the voltage value of the voltage signal with the current value of the current signal (e.g., related by ohm’s law) at the same time or at predefined times. As an example, a voltage signal and a current signal may be compared with one another by transforming the voltage signal into a transformed current signal representing the voltage signal (e.g., related by ohm’s law via a resistor) and comparing current values accordingly or by transforming the current signal into a transformed voltage signal representing the current signal (e.g., related by ohm’s law via a resistor) and comparing voltage values accordingly.

[0075] FIG.10 shows a schematic flow diagram of a method 1000 for generating a key based on a physical unclonable function, the method including, in 1010, generating a plurality of key elements of the key by operating each response structure of a plurality of response structures in accordance with a linked challenge / response operation 1020. The linked challenge / response operation 1020 applied to a respective response structure of the plurality of response structures includes, in 1022, applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge; in 1024, applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and, in 1026, causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, wherein the output is a function of the first challenge or the first response and of the second challenge or the second response.

[0076] FIG.11 shows a schematic flow diagram of a method 1100 for generating a key based on a physical unclonable function, the method including, in 1110, generating a first key element of the key by operating a first response structure in accordance with a linked challenge / response operation and, in 1120, generating a second key element of the key by operating a second response structure different from the first response structure in accordance with the linked challenge / response operation. The linked challenge / response operation applied to the response structure includes (see 1130) a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation includes a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation includes a second challenge to cause a second response by the response structure as a function of the second challenge; and wherein the linked challenge / response operation includes an output determination operation to determine an output representing the key element of the key, wherein the output determination includes a comparison of the first challenge or the first response with the second challenge or the second response.

[0077] According to various aspects, various aspects are related to a response structure in a challenge / response application of a PUF to cause a response of the respective response structure as a function of a challenge. The response structure may be any suitable entropy source (besides electric response structures various other types of response structures can be used such as optical response structures and / or ring oscillators). With ring oscillators PDFs, the respective challenge may be frequency and the corresponding response may be the amplitude of the oscillation. For ring oscillators PDFs, the challenge and the response cannot be interchanged as it is for example possible with memristor PDFs; in other words, the amplitude of the oscillation cannot be the challenge for the frequency as the response. With optical PDFs, the challenge may be the illumination of the PUF (for example, a scattering medium)and the response may be the intensity of the scattering. For optical PDFs, the challenge and the response cannot be interchanged as it is for example possible with memristor PDFs; in other words, the intensity of the scattering cannot be a challenge for the illumination of the PUF as a response.

[0078] According to various aspects, it may be beneficial from a security point of view, that the response structure is a non-linear response structure and, more preferably, the response structure may be a transcendent response structure as can be realized, for example, with memristive response elements as described herein.

[0079] FIG.12A to FIG.12H show various aspects of a realization of an electric response structure 1200 in a schematic circuit diagram. The electric response structure 1200 may have, e.g., in a first configuration 1200-1 , only a single resistive element 1200e (e.g., a memristor), or the electric response structure 1200 may have, e.g., in a second configuration 1200-2, only two resistive elements 1200e (e.g., two memristors). It is understood that the shown configurations include a minimal number of resistive elements 1200e for the respective configuration, wherein additional resistive element 1200e can be included in the electric response structure 1200. According to various aspects, resistive element 1200e may include a non-linear resistor such as a memristor. According to various aspects, resistive element 1200e may include a non-linear resistor with a transcendent non-linear l / V-characteristic, such as a memristor, as described herein.

[0080] According to various aspects, the electric response structure 1200 may include one or more current sources 1210 and / or one or more voltage sources 1220 to generate one or more electric signals (e.g., one or more time resolved current signals and / or one or more time resolved voltage signals) for the one or more current challenges 1210c and / or the one or more voltage challenges 1220c. According to various aspects, the electric response structure 1200 may include one or more current measurement entities 1230 (e.g., one or more ampere meter) and / or one or more voltage measurement entities 1240 (e.g., one or more voltage meter) to determine one or more electric signals (e.g., one or more time resolved current signals and / or one or more time resolved voltage signals) representing the one or more current responses 1230r and / or the one or more voltage responses 1240r.

[0081] According to various aspects, the electric response structure 1200 in the first configuration 1200-1 may be operated such that the second challenge is carried out after the first challenge and after the first response is determined. In other words, the second challenge / response suboperation may be carried out after the first challenge / response suboperation is finished. Therefore, in some aspects, a result of the determined first response may be stored to allow for a comparison with a result of the determined second response.

[0082] In other aspects, the electric response structure 1200 in the first configuration 1200-1 may be operated such that the first challenge and the second challenge are carried out stepwise alternati ngly. As an example, the first challenge and the second challenge may each have an electric signal with number of n-voltage or current steps defining the respective time dependent challenge, wherein the n-voltage or current steps of the first challenge and the second challenge are carried out alternatingly and the corresponding first response and the corresponding second response are determined alternatingly for each of the n-voltage or current steps. This allows for a comparison of the desired current and / or voltage signals after each of the steps. This allows for a comparison of the desired current and / or voltage values after each of the steps.

[0083] According to various aspects, the electric response structure 1200 in the second configuration 1200-2 may be operated such that the first challenge and the second challenge are carried out simultaneously such that the first response and the second response can be determined simultaneously as well. In other words, the second challenge / response suboperation may be carried at the same time as the first challenge / response suboperation. Therefore, in some aspects, a result of the determined first response can be compared with a result of the determined second response without storing any data representing the respective results.

[0084] According to various aspects, the electric response structure 1200 may be configured to link a first response (e.g., a current response) with a second challenge (e.g., a current challenge) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first challenge (e.g., a voltage challenge) corresponding to the first response and based on a second response (e.g., a voltage response) corresponding to the second challenge, as illustrated in FIG.12A, for example. In some aspects, the second challenge may be controlled based on the first response. The first response may be used to defined the second challenge. In one example, the first response signal may be directly used as the second challenge signal.

[0085] According to various aspects, the electric response structure 1200 may be configured to link a first challenge (e.g., a voltage challenge) with a second challenge (e.g., a voltage challenge) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first response (e.g., a current response) corresponding to the first challenge and based on a second response (e.g., a current response) corresponding to the second challenge, as illustrated in FIG.12B, for example. In some aspects, the first challenge and the second challenge may include the very same challenge signal. According to various aspects, the challenge signal may be a predefined challenge signal.

[0086] According to various aspects, the electric response structure 1200 may be configured to link a first response (e.g., a current response) with a second response (e.g., a current response) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first challenge (e.g., a voltage challenge) corresponding to the first response and based on a second challenge (e.g., a voltage challenge) corresponding to the second response, as illustrated in FIG.12C, for example. In some aspects, at least one of the first challenge and / or the second challenge may be controlled based on a predefined relation between the first response and the second response (e.g., the first challenge and / or the second challenge may stop at a present voltage value in the case that a predefined relation between the first response and the second response is fulfilled). The first challenge and / or the second challenge may be controlled via a closed loop control wherein the closed loop control is configured to reach a predefined relation between the first response and the second response by controlling the first challenge and / or the second challenge.

[0087] According to various aspects, the electric response structure 1200 may be configured to link a first challenge (e.g., a voltage challenge) with a second response (e.g., a voltage response) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first response (e.g., a current response) corresponding to the first challenge and based on a second challenge (e.g., a current challenge) corresponding to the second response, as illustrated in FIG.12D, for example. In some aspects, the first challenge may be controlled based on thesecond response (e.g., the first challenge may stop at a present voltage value in the case that the second response reaches a predefined voltage value).

[0088] According to various aspects, the electric response structure 1200 may be configured to link a first challenge (e.g., a current challenge) with a second challenge (e.g., a current challenge) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first response (e.g., a voltage response) corresponding to the first challenge and based on a second response (e.g., a voltage response) corresponding to the second challenge, as illustrated in FIG.12E, for example. In some aspects, the first challenge and the second challenge may include the very same challenge signal. According to various aspects, the challenge signal may be a predefined challenge signal.

[0089] According to various aspects, the electric response structure 1200 may be configured to link a first response (e.g., a voltage response) with a second challenge (e.g., a voltage challenge) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first challenge (e.g., a current challenge) corresponding to the first response and based on a second response (e.g., a current response) corresponding to the second challenge, as illustrated in FIG.12F, for example. In some aspects, the second challenge may be controlled based on the first response. The first response may be used to defined the second challenge. In one example, the first response signal may be directly used as the second challenge signal.

[0090] According to various aspects, the electric response structure 1200 may be configured to link a first challenge (e.g., a current challenge) with a second response (e.g., a current response) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first response (e.g., a voltage response) corresponding to the first challenge and based on a second challenge (e.g., a voltage challenge) corresponding to the second response, as illustrated in FIG.12G, for example. In some aspects, the first challenge may be controlled based on the second response (e.g., the first challenge may stop at a present current value in the case that the second response reaches a predefined current value).

[0091] According to various aspects, the electric response structure 1200 may be configured to link a first response (e.g., a voltage response) with a second response (e.g., a voltage response) and to determine an output of the electric response structure 1200 that represents a key element of a key based on a comparison of a first challenge (e.g., a current challenge) corresponding to the first response and based on a second challenge (e.g., a current challenge) corresponding to the second response, as illustrated in FIG.12H, for example. In some aspects, at least one of the first challenge and / or the second challenge may be controlled based on a predefined relation between the first response and the second response (e.g., the first challenge and / or the second challenge may stop at a present current value in the case that a predefined relation between the first response and the second response is fulfilled). The first challenge and / or the second challenge may be controlled via a closed loop control wherein the closed loop control is configured to reach a predefined relation between the first response and the second response by controlling the first challenge and / or the second challenge.

[0092] FIG.13A shows two c u rre nt / voltage time diagrams 1300a of a linked challenge / response operation, according to various aspects, to operate a response structure associated with a first response state 1300-1 and a second response state 1300-2. Only as an example, the first challenge / response suboperation may include a first challenge and a first response, in this exemplary case a first current challenge131 Oc-1 and a first voltage response 1340r-1 (of., the current challenge 1210c and voltage response 1240r in FIGs.12A to 12H, for example); and the second challenge / response sub-operation may include a second challenge and a second response, in this exemplary case a second current challenge 131 Oc-2 and a second voltage response 1340r-2 (cf., the current challenge 1210c and voltage response 1240r in FIGs.12A to 12H, for example). In some aspects, a comparison of the first voltage response 1340r-1 and the second voltage response 1340r-2 with one another may allow to identify a response state 1300-1 , 1300-2 (e.g., representing a key element such as a “0” or “1” of a binary key) of the response structure. As an example, in the case that a voltage value of the first voltage response 1340r-1 at the end of (after finishing) the first current challenge 1310c-1 is greater than a voltage value of the second voltage response 1340r-2 at the end of the second current challenge 131 Oc-2 it may be determined that the response structure is in the first response state 1300-1 (the key element may be determined as a “0” for example); and in the case that a voltage value of the first voltage response 1340r- 1 at the end of the first current challenge 1310c-1 is less than a voltage value of the second voltage response 1340r-2 at the end of the second current challenge 131 Oc-2 it may be determined that the response structure is in the second response state 1300-2 (the key element may be determined as a “1” for example). It is noted that other or similar comparison schemes may be used to determine the output of the response structure caused by a respective input and based on the linked challenge / response operation as described herein.

[0093] As exemplarily illustrated in FIG.13A, the respective response signals may be present at the same time, e.g., in the same time interval starting with the begin of the two challenges and ending with the end of the two challenges. In this case, comparing a voltage value or current value of the respective challenge and / or response signals may be possible at any time within the time interval, for example, at the end of the time interval or before the end of the two challenges. However, in the case that data representing the challenge and / or response signals are stored or in the case that voltage and / or current values of the challenge and / or response signals can be stored (e.g., preserved for a time longer than the time interval in which the first challenge is carried out) in hardware, the comparison of a voltage and / or current values of the respective challenge and / or response signals can be carried out at any time and the first challenge / response sub-operation can be carried out time-independent before and / or during the second challenge / response sub-operation is carried out.

[0094] FIG.13B shows two curre nt / voltage time diagrams 1300b of a linked challenge / response operation, according to various aspects, to operate a response structure associated with a first response state 1300-1 and a second response state 1300-2, wherein the first challenge / response sub-operation is carried out before the second challenge / response sub-operation is carried out. Only as an example, the first challenge / response sub-operation may include a first challenge and a first response, in this exemplary case a first current challenge 1310c-1 and a first voltage response 1340r-1 (cf., the current challenge 1210c and voltage response 1240r in FIGs.12A to 12H, for example) carried out in a first time interval T1 ; and the second challenge / response sub-operation may include a second challenge and a second response, in this exemplary case a second current challenge 131 Oc-2 and a second voltage response 1340r-2 (cf., the current challenge 1210c and voltage response 1240r in FIGs.12A to 12H, for example) carried out in a second time interval T2 after the first time interval T1 . A comparison of the first voltage response 1340r-1 and the second voltage response 1340r-2 with one another may allow to identify a response state 1300-1 , 1300-2 (e.g., representing a key element such as a “0” or “1 ” of a binary key) of the response structure as described above.

[0095] According to various aspects, instead of comparing a voltage value or current value of the respective response signals it may be useful to compare a time integral over a predefined time interval. A time integral may be more sensitive to variations in the respective response signals.

[0096] FIG.13C shows two curre nt / voltage time diagrams 1300b of a linked challenge / response operation, according to various aspects, to operate a response structure associated with a first response state 1300-1 and a second response state 1300-2, wherein the first challenge is carried out for a predefined time T and wherein the second challenge is carried out for a variable time t (for example t1 and t2) as a function of a comparison of the first response and the second response with one another. As an example, the second challenge is stopped at a time t1 , t2 as soon as the first response and the second response are in a predefined relation to one another (e.g., as soon as the voltage value of the first voltage response 1340r-1 is equal to the voltage value of the second voltage response 1340r-2). As another example, the time t2 of the second challenge is determined as soon as the first response and the second response are in a predefined relation to one another (e.g., as soon as the voltage value of the first voltage response 1340r-1 is equal to the voltage value of the second voltage response 1340r-2).

[0097] In the case that the time t1 , t2 of the second challenge is determined, the time t1 , t2 can be compared with a reference time tc to determine the identify a response state 1300-1, 1300-2 (e.g., representing a key element such as a “0” or “1 ” of a binary key) of the response structure as described above. In the case the time t1 , t2 is greater then the reference time tc the response state may be determined to be the first response state 1300-1 and in the case the time t1 , t2 is less then the reference time tc the response state may be determined to be the second response state 1300-2, as illustrated exemplarily in FIG.13C.

[0098] Various aspects include comparing one or more challenge and / or one or more responses to determine an output of the response structure. The output of the response structure may represent the secret (e.g., a key element) stored in the inherent properties of the response structure. According to various aspects, the comparison may include any suitable type of comparison, e.g., a greater than comparison, and / or a less than comparison, and / or an equal to comparison using the respective signals. In some aspects, the comparison may be based on a mathematical (e.g., arithmetic and / or logic) function linking a first comparison value and a second comparison value with one another. With an arithmetic function, the order in the addition / subtraction of the two response functions may be relevant, so that the arithmetic addition / subtraction operation may also return a number greater than zero (decision criterion for "0" or "1"). With an arithmetic function, the numerator / denominator assignment in the multiplication / division of the two response functions may be relevant, so that the arithmetic operation multiplication / division can also return a number with an absolute value greater than one (decision criterion for "0" or "1 "). With a logical function, the input may depend on the applied sequence. As an example, a logic “1” may be assigned to a first comparison value (e.g., to the larger value) and a logic “zero” may be assigned to a second comparison value (e.g., to the smaller value) and the output of the logic comparison (e.g., one or more of the possible 16 Boolean functions) may represent the secret (e.g., a logic "0" or a logic "1").

[0099] In the following, various examples are provided that may include one or more aspects described above with reference to a physical unclonable function and / or to method for generating a key based on a physical unclonable function as described herein.

[0100] Example 1 is a method for generating a key based on a physical unclonable function, the method including: generating a plurality of key elements of the key by operating each response structure ofa plurality of response structures in accordance with a linked challenge / response operation. The linked challenge / response operation applied to a respective response structure of the plurality of response structures includes: applying a first challenge to the respective response structure (any suitable entropy source, preferably a non-linear response structure, more preferably a transcendent response structure) to cause a first response of the respective response structure as a function of the first challenge; applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, wherein the output is a function I) of the first challenge or the first response and II) of the second challenge or the second response.

[0101] In Example 2, the method according to Example 1 may optionally further include that the second challenge and the first challenge are linked with one another in a predefined relation; or that the second challenge and the first response are linked with one another in a predefined relation; or that the second response and the first challenge are linked with one another in a predefined relation; or that the second response and the first response are linked with one another in a predefined relation.

[0102] In Example 3, the method according to Example 1 may optionally further include that the respective response structure is configured such that the first response defines the second challenge, and that the output representing the key element is determined based on a comparison of the first challenge and the second response with one another.

[0103] In Example 4, the method according to Example 1 may optionally further include that the respective response structure is configured such that the first challenge has a fixed relation to the second challenge, and that the output representing the key element is determined based on a comparison of the first response and the second response with one another.

[0104] In Example 5, the method according to Example 1 may optionally further include that the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with one another, and that the output representing the key element is determined based on a comparison of the first challenge and the second challenge with one another.

[0105] In Example 6, the method according to Example 1 may optionally further include that the respective response structure is configured such that the second challenge is defined by a comparison of the first challenge and the second response with one another, and that the output representing the key element is determined based on a comparison of the first response and the second challenge with one another.

[0106] In Example 7, the method according to any one of Examples 1 to 6 may optionally further include that the physical unclonable function is a hardware entity operated based on the linked challenge / response operation based on a feedback based determination of a challenge point at which a comparison condition is fulfilled or based on a comparison of responses at predefined challenge points.

[0107] In Example 8, the method according to any one of Examples 1 to 7 may optionally further include that the respective response structure is a respective electric response structure with an electric characteristic.

[0108] In Example 9, the method according to any one of Examples 1 to 8 may optionally further include that the first challenge is based on a first time dependent voltage signal (V(t)) or a first timedependent current signal (l(t)); and / or that the second challenge is based on a second time dependent voltage signal (V(t)) or a second time dependent current signal (l(t)).

[0109] In Example 10, the method according to any one of Examples 8 or 9 may optionally further include that the first challenge is based on a first maximum voltage (Vmax) of a first time dependent voltage signal (V(t)) or on a first maximum current (Imax) of a first time dependent current signal (l(t)); and / or that the second challenge is based on a second maximum voltage (Vmax) of a second time dependent voltage signal (V(t)) or on a second maximum current (Imax) of a second time dependent current signal (l(t)).

[0110] In Example 11 , the method according to any one of Examples 8 to 10 may optionally further include that the first challenge includes applying a first challenge signal (CS1 (t,CS1 max)); that the first response includes a first response signal (RS 1 (t,RS1 max)) caused by the first challenge signal (CS1 (t,CS1 max)) as a function of a first electric characteristic of the respective response structure; that the second challenge includes applying a second challenge signal (CS2(t,CS2max)); and that the second response includes a second response signal (RS2(t,RS2max)) caused by the second challenge signal (CS2(t,CS2max)) as a function of a second electric characteristic of the respective response structure different from the first electric characteristic of the respective response structure.

[0111] In Example 12, the method according to Example 11 may optionally further include that the first challenge signal includes a first voltage signal (CV1 (t, CV1 max)); that the first response signal includes a first current signal (RI1 (t,RI1 max)); that the second challenge signal includes a second current signal (CI21 (t,CI2 max)); and that the second response signal includes a second voltage signal (RV2(t,RV2max)).

[0112] In Example 13, the method according to Example 11 may optionally further include that the first challenge signal includes a first current signal (CI1 (t.CHmax)); that the first response signal includes a first voltage signal (RV1 (t,RV1max)); that the second challenge signal includes a second voltage signal (CV2(t,CV2max)); and that the second response signal includes a second current signal (RI2(t, RI2max)).

[0113] In Example 14, the method according to Example 11 may optionally further include that the first challenge signal includes a first voltage signal (CV1 (t, CV1 max)); that the first response signal includes a first current signal (RI1 (t,RI1 max)); that the second challenge signal includes a second voltage signal (CV2(t,CV2max)); and that the second response signal includes a second current signal (RI2(t, RI2max)).

[0114] In Example 15, the method according to Example 11 may optionally further include that the first challenge signal includes a first current signal (CI1 (t.CHmax)); that the first response signal includes a first voltage signal (RV1 (t,RV1max)); that the second challenge signal includes a second current signal (CI21 (t,CI2 max)); and that the second response signal includes a second voltage signal (RV2(t,RV2max)).

[0115] In Example 16, the method according to any one of Examples 11 to 15 may optionally further include that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and determine the output based on a relationship between the first response signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and determine the output based on a relationship between the first response signal and the second challenge signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and determine the output based on a relationship between the first challenge signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second response signaland determine the output based on a relationship between the first challenge signal and the second challenge signal.

[0116] In Example 17, the method according to any one of Examples 11 to 16 may optionally further include that the respective response structure includes a memristive structure with an electric characteristic, the electric characteristic of the memristive structure including a branch set with one or more distinct read branches and one or more distinct write branches, and wherein the first electric characteristic is associated with a branch of the branch set and wherein the second electric characteristic is associated with another branch of the branch set.

[0117] In Example 18, the method according to Example 17 may optionally further include that each of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied write signal.

[0118] In Example 19, the method according to Example 18 may optionally further include that an amplitude of the write signal defines the electric characteristic.

[0119] In Example 20, the method according to any one of Examples 17 to 19 may optionally further include that a positive read branch of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied positive write signal, wherein, preferably, a positive amplitude of the write signal defines the electric characteristic of the positive read branch; and / or that a negative read branch of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied negative write signal, wherein, preferably, a negative amplitude of the write signal defines the electric characteristic of the negative read branch.

[0120] In Example 21 , the method according to any one of Examples 17 to 20 may optionally further include that each of one or more distinct write branches has an electric characteristic as a function of a time dependent write signal.

[0121] In Example 22, the method according to Example 21 may optionally further include that a positive write branch of the one or more distinct write branches has an electric characteristic as a function of a corresponding applied positive write signal, wherein, preferably, a time dependence of the positive write signal defines the electric characteristic of the positive write branch; and / or that a negative write branch of the one or more distinct write branches has an electric characteristic as a function of a corresponding applied negative write signal, wherein, preferably, a time dependence of the negative write signal defines the electric characteristic of the negative write branch.

[0122] In Example 23, the method according to any one of Examples 19 to 22 may optionally further include that the write signal includes an initialization signal prior to a setting signal, wherein the setting signal is configured to bring the memristive structure from an initial state defined by the initialization signal into a written state defined by both the initialization signal and the setting signal.

[0123] In Example 24, the method according to any one of Examples 19 to 23 may optionally further include that the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with another read branch of the branch set; or that the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with a write branch of the branch set; or that the first electric characteristic is associated with a write branch of the branch set and wherein the second electric characteristic is associated with another write branch of the branch set; or that the first electric characteristic is associatedwith a write branch of the branch set and wherein the second electric characteristic is associated with a read branch of the branch set.

[0124] In Example 25, the method according to any one of Examples 1 to 24 may optionally further include that the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a characteristic of the first challenge or the first response and wherein the second comparison value is a representation of a characteristic of the second challenge or the second response.

[0125] In Example 26, the method according to Example 25 may optionally further include that the comparison includes a greater than comparison, and / or a less than comparison, and / or an equal to comparison; or that the comparison is based on a mathematical (e.g., arithmetic and / or logic) function linking the first comparison value and the second comparison value with one another.

[0126] In Example 25, the method according to any one of Examples 1 to 26 may optionally further include that the response structure includes a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; wherein, preferably, the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and stored in an analog memory or in a digital memory for the comparison with the second comparison value.

[0127] In Example 28, the method according to any one of Examples 1 to 27 may optionally further include that the memristive structure includes a memristive structure with a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; wherein, preferably, the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with one another.

[0128] In Example 29, the method according to any one of Examples 1 to 28 may optionally further include that the first challenge is carried out for a predefined time to define a reference value based on the first response; and that the second challenge is carried out for a variable time as a function of a comparison of the second response with the reference value; and that the output is determined based on a determination of the variable time.

[0129] Example 30 is a method for generating a key based on a physical unclonable function, the method including: generating a key element of the key by operating a response structure in accordance with a linked challenge / response operation, the linked challenge / response operation applied to the response structure includes a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation includes a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation includes a second challenge to cause a second response by the response structure as a function of the second challenge; and wherein the linked challenge / response operation includes an output determination operation to determine an output representing the key element of the key, wherein the output determination includes a comparison I) of the first challenge or the first response with II) the second challenge or the second response. According to various aspects, any of the Examples 2 to 29 can be applied to method 30 accordingly.

[0130] Example 31 is physical unclonable function for generating a key, the physical unclonable function, including: one or more response structures; and a controller configured to generate the key by operating each of the one or more response structures in accordance with a linked challenge / response operation, the linked challenge / response operation applied to a respective response structure of the one or more response structures includes a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation includes a first challenge to cause a first response by the respective response structure as a function of the first challenge; wherein the second challenge / response sub-operation includes a second challenge to cause a second response by the respective response structure as a function of the second challenge; and wherein the linked challenge / response operation includes an output determination operation to determine an output representing a key element of the key, wherein the output determination includes a comparison I) of the first challenge or the first response with II) the second challenge or the second response.

[0131] In Example 32, the physical unclonable function according to Example 31 may optionally further include that the second challenge and the first challenge are linked with one another in a predefined relation; or that the second challenge and the first response are linked with one another in a predefined relation; or that the second response and the first challenge are linked with one another in a predefined relation; or that the second response and the first response are linked with one another in a predefined relation.

[0132] In Example 33, the physical unclonable function according to Example 31 may optionally further include that the respective response structure is configured such that the first response defines the second challenge, and that the output representing the key element is determined based on a comparison of the first challenge and the second response with one another.

[0133] In Example 34, the physical unclonable function according to Example 31 may optionally further include that the respective response structure is configured such that the first challenge has a fixed relation to the second challenge, and that the output representing the key element is determined based on a comparison of the first response and the second response with one another.

[0134] In Example 35, the physical unclonable function according to Example 31 may optionally further include that the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with one another, and that the output representing the key element is determined based on a comparison of the first challenge and the second challenge with one another.

[0135] In Example 36, the physical unclonable function according to Example 31 may optionally further include that the respective response structure is configured such that the second challenge is defined by a comparison of the first challenge and the second response with one another, and that the output representing the key element is determined based on a comparison of the first response and the second challenge with one another.

[0136] In Example 37, the physical unclonable function according to any one of Examples 31 to 36 may optionally further include that the physical unclonable function is a hardware entity operated based on the linked challenge / response operation based on a feedback based determination of a challenge point at which a comparison condition is fulfilled or based on a comparison of responses at predefined challenge points.

[0137] In Example 38, the physical unclonable function according to any one of Examples 31 to 37 may optionally further include that the respective response structure is a respective electric response structure with an electric characteristic.

[0138] In Example 39, the physical unclonable function according to Example 38 may optionally further include that the first challenge includes a first time dependent voltage signal (V(t)) or a first time dependent current signal (l(t)); and / or that the second challenge includes a second time dependent voltage signal (V(t)) or a second time dependent current signal (l(t)).

[0139] In Example 40, the physical unclonable function according to any one of Examples 38 or 39 may optionally further include that the first challenge is defined by a first maximum voltage (Vmax) of a first time dependent voltage signal (V(t)) or on a first maximum current (Imax) of a first time dependent current signal (l(t)); and / or that the second challenge is defined by a second maximum voltage (Vmax) of a second time dependent voltage signal (V(t)) or on a second maximum current (Imax) of a second time dependent current signal (l(t)).

[0140] In Example 41 , the physical unclonable function according to any one of Examples 38 to 40 may optionally further include that the first challenge includes a first challenge signal (CS1 (t,CS1max)); that the first response includes a first response signal (RS1 (t,RS1max)) caused by the first challenge signal (CS1 (t, CS 1 max)) as a function of a first electric characteristic of the respective response structure; that the second challenge includes a second challenge signal (CS2(t,CS2max)); and that the second response includes a second response signal (RS2(t,RS2max)) caused by the second challenge signal (CS2(t,CS2max)) as a function of a second electric characteristic of the respective response structure different from the first electric characteristic of the respective response structure.

[0141] In Example 42, the physical unclonable function according to Example 41 may optionally further include that the first challenge signal includes a first voltage signal (CV1 (t, CV1 max)); that the first response signal includes a first current signal (RI1 (t.RHmax)); that the second challenge signal includes a second current signal (CI21 (t,CI2max)); and that the second response signal includes a second voltage signal (RV2(t,RV2 max))-

[0142] In Example 43, the physical unclonable function according to Example 41 may optionally further include that the first challenge signal includes a first current signal (Cl 1 (t, Cl 1 max)); that the first response signal includes a first voltage signal (RV1 (t,RV1max)); that the second challenge signal includes a second voltage signal (CV2(t,CV2max)); and that the second response signal includes a second current signal (RI2(t,RI2 max))-

[0143] In Example 44, the physical unclonable function according to Example 41 may optionally further include that the first challenge signal includes a first voltage signal (CV1 (t, CV1 max)); that the first response signal includes a first current signal (RI1 (t.RHmax)); that the second challenge signal includes a second voltage signal (CV2(t,CV2max)); and that the second response signal includes a second current signal (RI2(t,RI2 max))-

[0144] In Example 45, the physical unclonable function according to Example 41 may optionally further include that the first challenge signal includes a first current signal (Cl 1 (t, Cl 1 max)); that the first response signal includes a first voltage signal (RV1 (t,RV1max)); that the second challenge signal includes a second current signal (CI21 (t,CI2max)); and that the second response signal includes a second voltage signal (RV2(t,RV2 max))-

[0145] In Example 46, the physical unclonable function according to any one of Examples 41 to 45 may optionally further include that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and determine the output based on a relationship between the first response signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and determine the output based on a relationship between the first response signal and the second challenge signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and determine the output based on a relationship between the first challenge signal and the second response signal; or that the physical unclonable function is configured to provide a relationship between the first response signal and the second response signal and determine the output based on a relationship between the first challenge signal and the second challenge signal.

[0146] In Example 47, the physical unclonable function according to any one of Examples 41 to 46 may optionally further include that the respective response structure includes a memristive structure with an electric characteristic, the electric characteristic of the memristive structure including a branch set with one or more distinct read branches and one or more distinct write branches, and wherein the first electric characteristic is associated with a branch of the branch set and wherein the second electric characteristic is associated with another branch of the branch set.

[0147] In Example 48, the physical unclonable function according to Example 47 may optionally further include that each of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied write signal.

[0148] In Example 49, the physical unclonable function according to Example 47 or 48 may optionally further include that an amplitude of the write signal defines the electric characteristic.

[0149] In Example 50, the physical unclonable function according to any one of Examples 47 to 49 may optionally further include that a positive read branch of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied positive write signal, wherein, preferably, a positive amplitude of the write signal defines the electric characteristic of the positive read branch; and / or that a negative read branch of the one or more distinct read branches has an electric characteristic as a function of a corresponding applied negative write signal, wherein, preferably, a negative amplitude of the write signal defines the electric characteristic of the negative read branch.

[0150] In Example 51 , the physical unclonable function according to any one of Examples 47 to 50 may optionally further include that each of one or more distinct write branches has an electric characteristic as a function of a time dependent write signal.

[0151] In Example 52, the physical unclonable function according to Example 51 may optionally further include that a positive write branch of the one or more distinct write branches has an electric characteristic as a function of a corresponding applied positive write signal, wherein, preferably, a time dependence of the positive write signal defines the electric characteristic of the positive write branch; and / or that a negative write branch of the one or more distinct write branches has an electric characteristic as a function of a corresponding applied negative write signal, wherein, preferably, a time dependence of the negative write signal defines the electric characteristic of the negative write branch.

[0152] In Example 53, the physical unclonable function according to any one of Examples 49 to 52 may optionally further include that the write signal includes an initialization signal prior to a setting signal,wherein the setting signal is configured to bring the memristive structure from an initial state defined by the initialization signal into a written state defined by both the initialization signal and the setting signal.

[0153] In Example 54, the physical unclonable function according to any one of Examples 49 to 53 may optionally further include that the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with another read branch of the branch set; or that the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with a write branch of the branch set; or that the first electric characteristic is associated with a write branch of the branch set and wherein the second electric characteristic is associated with another write branch of the branch set; or that the first electric characteristic is associated with a write branch of the branch set and wherein the second electric characteristic is associated with a read branch of the branch set.

[0154] In Example 55, the physical unclonable function according to any one of Examples 31 to 54 may optionally further include that the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a characteristic of the first challenge or the first response and wherein the second comparison value is a representation of a characteristic of the second challenge or the second response.

[0155] In Example 56, the physical unclonable function according to Example 55 may optionally further include that the comparison includes a greater than comparison, and / or a less than comparison, and / or an equal to comparison; or that the comparison is based on a mathematical function linking the first comparison value and the second comparison value with one another.

[0156] In Example 57, the physical unclonable function according to any one of Examples 31 to 56 may optionally further include that the response structure includes a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; wherein, preferably, the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and stored in an analog memory or in a digital memory for the comparison with the second comparison value.

[0157] In Example 58, the physical unclonable function according to any one of Examples 31 to 56 may optionally further include that the memristive structure includes a memristive structure with a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; wherein, preferably, the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with one another.

[0158] In Example 59, the physical unclonable function according to any one of Examples 31 to 56 may optionally further include that the first challenge is carried out for a predefined time to define a reference value based on the first response; and that the second challenge is carried out for a variable time as a function of a comparison of the second response with the reference value; and that the output is determined based on a determination of the variable time.

[0159] According to various aspects, any of the Examples 2 to 29 can be applied to the physical unclonable function of Examples 31 to 59 accordingly. Any of the aspects described herein with reference to the method for generating a key based on a physical unclonable function can be implemented in thephysical unclonable function described herein, e.g., realized by a controller included in the physical unclonable function or connected to the physical unclonable function.

[0160] While the invention has been particularly shown and described with reference to specific aspects, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes, which come within the meaning and range of equivalency of the claims, are therefore intended to be embraced.

Claims

ClaimsWhat is claimed is:1 . A method for generating a key based on a physical unclonable function, the method comprising: generating a plurality of key elements of the key by operating each response structure of a plurality of response structures in accordance with a linked challenge / response operation, the linked challenge / response operation applied to a respective response structure of the plurality of response structures comprises: applying a first challenge to the respective response structure to cause a first response of the respective response structure as a function of the first challenge; applying a second challenge to the respective response structure to receive a second response of the respective response structure as a function of the second challenge; and causing an output representing a key element of the plurality of key elements of the key corresponding to the respective response structure, wherein the output is a functionI) of the first challenge or the first response andII) of the second challenge or the second response.

2. The method according to claim 1 , wherein the second challenge and the first challenge are linked with one another in a predefined relation; or wherein the second challenge and the first response are linked with one another in a predefined relation; or wherein the second response and the first challenge are linked with one another in a predefined relation; or wherein the second response and the first response are linked with one another in a predefined relation.

3. The method according to claim 1 , wherein the respective response structure is configured such that the first response defines the second challenge, and wherein the output representing the key element is determined based on a comparison of the first challenge and the second response with one another.

4. The method according to claim 1 , wherein the respective response structure is configured such that the first challenge has a fixed relation to the second challenge, and wherein the output representing the key element is determined based on a comparison of the first response and the second response with one another.

5. The method according to claim 1 , wherein the respective response structure is configured such that the second challenge is defined by a comparison of the first response and the second response with one another, andwherein the output representing the key element is determined based on a comparison of the first challenge and the second challenge with one another.

6. The method according to claim 1 , wherein the respective response structure is configured such that the second challenge is defined by a comparison of the first challenge and the second response with one another, and wherein the output representing the key element is determined based on a comparison of the first response and the second challenge with one another.

7. The method according to any one of claims 1 to 6, wherein the physical unclonable function is a hardware entity operated based on the linked challenge / response operation based on a feedback based determination of a challenge point at which a comparison condition is fulfilled or based on a comparison of responses at predefined challenge points.

8. The method according to any one of claims 1 to 7, wherein the respective response structure is a respective electric response structure with an electric characteristic.

9. The method according to claim 8, wherein the first challenge is based on a first time dependent voltage signal (V(t)) or a first time dependent current signal (l(t)); and / or wherein the second challenge is based on a second time dependent voltage signal (V(t)) or a second time dependent current signal (l(t)).

10. The method according to claims 8 or 9, wherein the first challenge comprises applying a first challenge signal (CS1 (t,CS1 max)); wherein the first response comprises a first response signal (RS1 (t,RS1 max)) caused by the first challenge signal (CS1 (t,CS1max)) as a function of a first electric characteristic of the respective response structure; wherein the second challenge comprises applying a second challenge signal (CS2(t,CS2max)); wherein the second response comprises a second response signal (RS2(t,RS2max)) caused by the second challenge signal (CS2(t,CS2max)) as a function of a second electric characteristic of the respective response structure different from the first electric characteristic of the respective response structure.11 . The method according to claim 10, wherein the physical unclonable function is configured to provide a relationship between the first challenge signal and the second challenge signal and determine the output based on a relationship between the first response signal and the second response signal; or wherein the physical unclonable function is configured to provide a relationship between the first challenge signal and the second response signal and determine the output based on a relationship between the first response signal and the second challenge signal; orwherein the physical unclonable function is configured to provide a relationship between the first response signal and the second challenge signal and determine the output based on a relationship between the first challenge signal and the second response signal; or wherein the physical unclonable function is configured to provide a relationship between the first response signal and the second response signal and determine the output based on a relationship between the first challenge signal and the second challenge signal.

12. The method according to any one of claims 1 to 11 , wherein the respective response structure comprises a memristive structure with an electric characteristic, the electric characteristic of the memristive structure comprising a branch set with one or more distinct read branches and one or more distinct write branches, and wherein the first electric characteristic is associated with a branch of the branch set and wherein the second electric characteristic is associated with another branch of the branch set.

13. The method according to claims 10 and 12, wherein the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with another read branch of the branch set; or wherein the first electric characteristic is associated with a read branch of the branch set and wherein the second electric characteristic is associated with a write branch of the branch set; or wherein the first electric characteristic is associated with a write branch of the branch set and wherein the second electric characteristic is associated with another write branch of the branch set; or wherein the first electric characteristic is associated with a write branch of the branch set and wherein the second electric characteristic is associated with a read branch of the branch set.

14. The method according to any one of claims 1 to 13, wherein the output is based on a comparison of a first comparison value and a second comparison value, wherein the first comparison value is a representation of a characteristic of the first challenge or the first response and wherein the second comparison value is a representation of a characteristic of the second challenge or the second response.

15. The method according to any one of claims 1 to 14, wherein the response structure comprises a memristive structure with a memristive element, and wherein the first challenge / response and the second challenge / response are applied to the memristive element; and wherein, preferably, the first comparison value is obtained from the memristive element before the second comparison value is obtained from the memristive element and stored in an analog memory or in a digital memory for the comparison with the second comparison value.

16. The method according to any one of claims 1 to 14, wherein the memristive structure comprises a memristive structure with a first memristive element and a second memristive element, and wherein the first challenge / response is applied to the first memristive element and the second challenge / response is applied to the second memristive element; andwherein, preferably, the first comparison value is obtained from the first memristive element and the second comparison value is obtained from the second memristive element at the same time to compare the first comparison value and the second comparison value with one another.

17. The method according to any one of claims 1 to 14, wherein the first challenge is carried out for a predefined time to define a reference value based on the first response; and wherein the second challenge is carried out for a variable time as a function of a comparison of the second response with the reference value; and wherein the output is determined based on a determination of the variable time.

18. A method for generating a key based on a physical unclonable function, the method comprising: generating a key element of the key by operating a response structure in accordance with a linked challenge / response operation, the linked challenge / response operation applied to the response structure comprises a first challenge / response sub-operation and a second challenge / response sub-operation, wherein the first challenge / response sub-operation comprises a first challenge to cause a first response by the response structure as a function of the first challenge; wherein the second challenge / response sub-operation comprises a second challenge to cause a second response by the response structure as a function of the second challenge; and wherein the linked challenge / response operation comprises an output determination operation to determine an output representing the key element of the key, wherein the output determination comprises a comparisonI) of the first challenge or the first response withII) the second challenge or the second response.

19. A physical unclonable function (700) for generating a key (730), the physical unclonable function, comprising: one or more response structures (740); and a controller (700c) configured to generate the key (730) by operating each of the one or more response structures (740) in accordance with a linked challenge / response operation (720), the linked challenge / response operation (720) applied to a respective response structure (740m) of the one or more response structures (740) comprises a first challenge / response sub-operation (720-1) and a second challenge / response sub-operation (720-2), wherein the first challenge / response sub-operation (720-1) comprises a first challenge to cause a first response by the respective response structure as a function of the first challenge; wherein the second challenge / response sub-operation (720-2) comprises a second challenge to cause a second response by the respective response structure as a function of the second challenge; and wherein the linked challenge / response operation (720) comprises an output determination operation (720-3) to determine an output representing a key element of the key, wherein the output determination comprises a comparisonI) of the first challenge or the first response withII) the second challenge or the second response.

20. The physical unclonable function according to claim 19, wherein the respective response structure (740m) comprises a memristive structure with an electric characteristic, the electric characteristic of the memristive structure comprising a branch set with one or more distinct read branches and one or more distinct write branches, and wherein the first electric characteristic is associated with a branch of the branch set and wherein the second electric characteristic is associated with another branch of the branch set.

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