Smart identification cable assembly

Abstract

Aspects of smart identification cable assemblies are described herein. An example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes signal wafer assemblies that are electrically coupled to cables in the cable bundle and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identifier for the cable assembly, such as a slot location for the connector. In other aspects, the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query. The identifier response can include a range of information, such as a unique identifier of a connector or a slot location, data related to a cable bundle, and other data related to an interconnect system used in a computing environment.

Description

SMART IDENTIFICATION CABEE ASSEMBEYBACKGROUND

[0001] Computing, network switching, telecommunications, and related systems and environments rely upon interconnect systems to provide data and power connectivity between different computing devices, switches, routers, and other equipment. A range of different input / output (I / O) connectors, cable assemblies, and interconnect systems are designed for those types of data, power, and data and power interconnection applications.

[0002] Example interconnect systems include board-to-board, wire-to-wire, and wire-to- board systems. A variety of designs exist for each type of connector, cable assembly, and interconnect system, depending on the requirements of the power and data communications environment in which the connectors, assemblies, and systems are used. As one example, a wire- to-board system includes a free-end connector attached to a cable bundle of wires and a fixed-end connector attached to a printed circuit board (PCB). As another example, a wire-to-wire system includes a first free-end connector attached to one end of cable bundle and a second free free-end connector attached to another end of the cable bundle.SUMMARY

[0003] Aspects of smart identification cable assemblies are described herein. An example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes signal wafer assemblies that are electrically coupled to cables in the cable bundle and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identifier for the cable assembly, such as a slot location for the connector. In other aspects, the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query. The identifier response can include a range of information, such as a unique identifier of a connector or a slot location, data related to a cable bundle, and other data related to an interconnect system used in a computing environment.

[0004] An example interconnect system includes a first cable assembly and a second cable assembly. The first cable assembly includes a first cable bundle and a first connector at one end of the first cable bundle. The first connector includes a first signal wafer assembly electricallycoupled to a cable in the first cable bundle, and a first identification wafer assembly. The first identification wafer assembly includes a first identification wafer module that stores a first unique identifier for the first cable assembly. The second cable assembly includes a second cable bundle and a second connector at one end of the second cable bundle. The second connector includes a second signal wafer assembly electrically coupled to a cable in the second cable bundle, and a second identification wafer assembly. The second identification wafer assembly includes a second identification wafer module that stores a second unique identifier for the second cable assembly.

[0005] Another example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes a signal wafer assembly electrically coupled to cables in the cable bundle and an identification wafer module. The identification wafer module stores a unique identifier for the cable assembly. The unique identifier includes a slot location identifier in a computing system in one example.

[0006] In other aspects of the embodiments, the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query on an identification coupling interface of the identification wafer module. The identifier response includes data related to the connector, the cable bundle, or both the connector and the cable bundle. In another example, the identifier response includes data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead, among other information.

[0007] An example connector includes a housing, a signal wafer assembly secured in the housing, and an identification wafer assembly secured in the housing. The identification wafer assembly includes an identification wafer module, and the identification wafer module stores a unique identifier for the connector. In one example, a plurality of signal wafer assemblies are arranged in a row within the housing, and the identification wafer assembly is positioned at one end of the row of the plurality of signal wafer assemblies. In other aspects, the signal wafer assembly includes a signal coupling interface, the identification wafer assembly includes an identification coupling interface, and the signal coupling interface is the same as the identification coupling interface.

[0008] An example identification wafer assembly for a connector includes a coupling interface and an identification wafer module. The coupling interface can include a number of conductors and at least one shield. The identification wafer module can include an integratedcircuit storing a unique identifier for the connector. In other aspects, the integrated circuit can include a data bus and power terminals coupled respectively to conductors in the coupling interface. The unique identifier can include a slot location identifier, data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead, and other information.

[0009] Another example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes a number of signal conductors electrically coupled to cables in the cable bundle and an identification module. The identification module stores a unique identifier for the cable assembly. The unique identifier can include a slot location identifier, data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead, and other information.

[0010] Another example connector includes a housing, a plurality of signal conductors, and an identification module secured in the housing. The identification module stores a unique identifier for the connector. The unique identifier can include a slot location identifier, data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead, and other information.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, with emphasis instead being placed upon clearly illustrating the principles of the disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

[0012] FIG. 1 illustrates an example computing environment with an interconnect system according to various aspects of the present disclosure.

[0013] FIG. 2 illustrates a perspective view of an example connector at a free end of a cable assembly in the interconnect system shown in FIG. 1 according to various aspects of the present disclosure.

[0014] FIG. 3A illustrates a perspective view of example wafer assemblies of the connector shown in FIG. 2, with the housing removed, according to various aspects of the present disclosure.

[0015] FIG. 3B illustrates a side view of the connector shown in FIG. 2, with the housing removed, according to various aspects of the present disclosure.

[0016] FIG. 4 illustrates a perspective view of a wafer assembly in a connector of the interconnect system shown in FIG. 1 according to various aspects of the present disclosure.

[0017] FIG. 5A illustrates a perspective view of an identification wafer assembly in a connector of the interconnect system shown in FIG. 1 according to various aspects of the present disclosure.

[0018] FIG. 5B illustrates a first-side plan view of a circuit module in the identification wafer assembly shown in FIG. 5A according to various aspects of the present disclosure.

[0019] FIG. 5C illustrates a second-side plan view of the circuit module shown in FIG. 5B according to various aspects of the present disclosure.DETAILED DESCRIPTION

[0020] As noted above, computing, network switching, telecommunications, and related systems and environments rely upon interconnect systems to provide data and power connectivity between different computing devices, switches, routers, and other equipment. A range of different input / output (I / O) connectors, cable assemblies, and interconnect systems are designed for those types of data, power, and data and power interconnection applications. Interconnect systems can include board-to-board, wire-to-wire, wire-to-board, and related systems. A variety of designs exist for each type of connector, cable assembly, and interconnect system, depending on the requirements of the power and data communications environment in which the connectors, assemblies, and systems are used.

[0021] High data rate connectors, cable assemblies, and interconnection systems often rely upon differentially coupled signal pairs in which two conductors are arranged in a pair to transmit a differential signal. The signal being transmitted is embodied by the electrical difference measured between the conductor pair. Differential signaling can be helpful to avoid spurious signals and crosstalk, and avoid inadvertent signaling modes among adjacent signals pairs. In connector interfaces, ground terminals can be relied upon to create a return path to electrical ground, provide shielding between differential pairs, and for other purposes.

[0022] Connectors used in high data rate applications are typically designed to meet a range of mechanical and electrical requirements. High data rate connectors, cable assemblies, and interconnection systems are often used in backplane applications, as one example, that require very high conductor density and data rates. To achieve the desired mechanical and electricalrequirements, the connectors used in such applications often incorporate one or more wafer assemblies.

[0023] In some interconnection systems, arrays of connectors can be arranged and secured to connector panels or bulkheads. A connector bulkhead can refer to a structure, such as a wall of a housing or a related barrier, to which one or more connectors of an interconnection system are mounted or otherwise secured. The connectors can extend through openings or apertures in the bulkhead in some cases. The connector bulkhead thus supports the connectors and secures them in place with respect to each other and the surrounding system. Connector bulkheads can be particularly helpful for wire-to-wire interconnection systems including multiple cable assemblies with free-end connectors at the ends of cable bundles. The bulkhead can support a group of the free-end connectors, and mating connectors can be mechanically and electrically connected to the group of the free-end connectors.

[0024] Aspects of smart identification cable assemblies are described herein. An example cable assembly includes a cable bundle and a connector at one end of the cable bundle. The connector includes signal wafer assemblies that are electrically coupled to cables in the cable bundle and an identification wafer assembly. The identification wafer assembly includes an identification wafer module. The identification wafer module stores a unique identifier for the cable assembly, such as a slot location for the connector. In other aspects, the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query. The identifier response can include a range of information, such as a unique identifier of a connector or a slot location, data related to a cable bundle, and other data related to an interconnect system used in a computing environment.

[0025] FIG. 1 illustrates an example computing environment 10 (also “environment 10”) with an interconnect system 100 according to various aspects of the present disclosure. Both the environment 10 and the interconnect system 100 are shown as a representative example in FIG. 1. The interconnect systems and concepts described herein can be extended to computing environments including any number of computing systems, cable assemblies, connectors, cables, cable bundles, and other components.

[0026] As shown in FIG. 1 , the environment 10 includes computing systems 20 and 40 and the interconnect system 100. The computing system 20 includes computing devices 30-39, among possibly others, and the computing system 40 includes computing devices 50-53, among possiblyothers. The computing devices 30-39 can be individual linecards of the computing system 20. Each of the computing devices 30-39 can be embodied as a computer or server including one or more general, specific-purpose, or general and specific-purpose processors and memory devices, a data communications device or system, a network storage device or system, a network switching, routing, or switching and routing system, a telecommunications system, or related computing system without limitation. The computing devices 50-53 can also be linecards of the computing system 40. Each of the computing devices 50-53 can be embodied as a computer or server including one or more general, specific-purpose, or general and specific-purpose processors and memory devices, a network storage device or system, a network switching, routing, or switching and routing system, a telecommunications system, or related computing system without limitation.

[0027] The interconnect system 100 provides a data interconnect system among the computing systems 20 and 40 in one example. In other cases, the interconnect system 100 can provide a power or a data and power interconnect system among the computing systems 20 and 40. The interconnect system 100 includes cable bundles 110-119 and free-end connectors 120- 129 at the ends of the cable bundles 110-119, respectively. The interconnect system 100 also includes cable bundles 130-133 and free-end connectors 140-143 at the ends of the cable bundles 130-133, respectively. Examples of the connectors 120-129 and 140-143 are described below with reference to FIG. 2, and examples of the wafer assemblies within the connectors 120-129 and MOMS are described below with reference to FIGS. 3A, 3B, 4, and 5A-5C.

[0028] The cable bundles 110-119 and 130-133 include cables extending between and among the connectors 120-129 and the connectors 140-143. The cables can be embodied as electrically- conductive twinaxial or twinax cables in one example, although other types of cables (e.g., shielded or unshielded twisted pair, coaxial cables, fiber optic cables, etc.) can be relied upon in the interconnect system 100. When embodied as twinax cables, each of the cables in the cable bundles 110-119 and 130-133 can include a pair of inner conductors, a dielectric insulator around the conductors, one or more shield or shielding layers around the dielectric insulator, one or more drain conductors, and a jacket. Twinax cables can be used in high-speed differential data signaling applications, and the interconnect system 100 can be relied upon in a range of data interconnection applications.

[0029] Each of the cable bundles 110-119 and 130-133 includes a number of cables. The number of cables in each cable bundle of the interconnect system 100 can depend on the type,style, number of wafer assemblies, and related characteristics of the free-end connector at the end of each cable bundle. In one example described herein, each of the cable bundles 110-119 includes sixty-four twinax cables. In other examples, each cable bundle among a first group of the cable bundles 110-119 includes a first number of cables, and each cable bundle among a second and different group of the cable bundles 110-119 includes a second and different number of cables. The embodiments are not limited to cable bundles of any particular number of cables, however, and each of the cable bundles 110-119 can include more or less than sixty-four twinax cables in other cases. Other examples include cable bundles of two (2), four (4), eight (8), sixteen (16), thirty-two (32), one-hundred twenty-eight (128), or other numbers of cables, without limitation. Each of the cable bundles 130-133 can also include more or less than sixty-four twinax cables.

[0030] In the example shown, each of the connectors 120-129 is secured to the bulkhead 22. The bulkhead 22 can be embodied as a wall of a housing, rack, case, or related structure of the computing system 20, as an example. The connectors 120-129 can extend through apertures or openings through the bulkhead 22, in one case, although the connectors 120-129 can also be secured to the bulkhead 22 in other arrangements or fashions using any suitable connectors, fasteners, or related means. The bulkhead 22 can facilitate alignment between the connectors 120- 129 of the interconnect system 100 and mating connectors of the computing devices 30-39, as described in further detail below. The connectors 120-129 can be arranged in a type of linear or matrix array using the bulkhead 22.

[0031] Each of the connectors 140-143 is secured to the bulkhead 42. The bulkhead 42 can be embodied as a wall of a housing, rack, case, or related structure of the computing system 40, as an example. The connectors 140-143 can extend through apertures or openings through the bulkhead 42, in one case, although the connectors 140-143 can also be secured to the bulkhead 42 in other arrangements or fashions using any suitable connectors, fasteners, or related means. The bulkhead 42 can facilitate alignment between the connectors 140-143 of the interconnect system 100 and mating connectors of the computing devices 50-53, as described in further detail below. The connectors 140-143 can be arranged in a type of linear or matrix array using the bulkhead 22.

[0032] As shown in FIG. 1, the computing devices 30-39 of the computing system 20 include connectors 60-69, respectively. The connectors 60-69 can be fixed-end connectors mounted to printed circuit boards (PCBs) of the computing devices 30-39 in the example shown in FIG. 1. Thus, the connector 60 facilitates electrical couplings or connections between the computingdevice 30 and the connector 120 of the interconnect system 100. Similarly, the connectors 61-69 facilitate electrical couplings or connections between the computing devices 31-39 and the connectors 121-129 of the interconnect system 100. As also shown in FIG. 1, the computing devices 50-53 of the computing system 40 include connectors 70-73, respectively. The connectors 70-73 can be fixed-end connectors mounted to PCBs of the computing devices 50-53. The connectors 70-73 facilitate electrical couplings or connections between the computing devices SO- 53 and the connectors 140-143 of the interconnect system 100. The fixed-end connectors 60-69 and 70-73 can also include aspects of the smart identification concepts described herein. For example, any of the fixed-end connectors 60-69 and 70-73 can also include the ID wafer assembly 220 described below with reference to FIGS. 5A-5C, or components thereof.

[0033] In the interconnect system 100, the cables in the cable bundles 110-119 and 130-133 can be routed among the connectors 120-129 and 140-143 in any suitable way depending on the interconnect needs in the environment 10. In other words, the cable bundles 110-119 and 130-133 can facilitate data communication among the linecards of the computing systems 20 and 40 in a variety of ways. As an example, the cable bundle 110 can include cables that extend between the computing device 30 and one or more of the computing devices 31-39 in the computing system 20. Additionally or alternatively, the cable bundle 110 can include cables that extend between the computing device 30 and one or more of the computing devices 50-53 in the computing system 40. Overall, each of the cable bundles 110-119 can include cables that extend among one or more of the computing devices 30-39 and 50-53, among others not shown. Similarly, the cable bundle 130 can include cables that extend between the computing device 50 and one or more of the computing devices 51-53 in the computing system 40. Additionally or alternatively, the cable bundle 130 can include cables that extend between the computing device 50 and one or more of the computing devices 30-39 in the computing system 20. Each of the cable bundles 130-133 can include cables that extend among the computing devices 30-39 and 50-53, among possibly others.

[0034] According to aspects of the embodiments, the interconnect system 100 incorporates one or more identifier or “ID” components. For example, one or more of the connectors 120-129 and 140-143 includes a part, element, or component configured to provide a unique identifier or ID (also an “ID response”). The ID response can be provided at any time, such as when power is applied to the ID components, in response to a query from one of the computing devices 30-39 and the computing devices 50-53, or in response to other conditions. The ID response can beprovided in the form of voltage potentials or logic levels on terminals of the connectors 120-129 and 140-143, serial or parallel data on the terminals, or in other suitable formats. An ID response provided from one of the connectors 120-129 and 140-143 can be, at least in part, unique as compared to any or all ID responses provided from other connectors 120-129 and 140-143 in one example.

[0035] The ID responses from the connectors 120-129 and 140-143 can include a range of information. The ID responses can include unique identifiers or codes, such as unique identifiers of the connectors 120-129 and 140-143. The ID responses can include physical or logical slot locations of the connectors 120-129 and 140-143. The ID responses can include data related to the type, style, or other characteristics of the connectors 120-129 and 140-143. The ID responses can include data related to the relative or absolute positions of the connectors 120-129 in the bulkhead 22. Similarly, the ID responses can include data related to the relative or absolute positions of the connectors 140-143 in the bulkhead 42. The ID responses can include data related to the cable bundles 110-119 and 130-133, the numbers and types (e.g., part number, conductor or fiber type, gauge, length, etc.) of cables in the cable bundles 110-119 and 130-133, the numbers of cable bundles in the interconnect system 100, and other information related to the cable bundles 110-119 and 130-133 and the interconnect system 100. The ID responses can include data related to the particular cable connections among the connectors 120-129 and 140-143. These and other types of ID responses are described below. As discussed in further detail below, the computing devices 30-39 and the computing devices 50-53 can tailor or adjust certain operating parameters, such as clock or skew timings, based on the ID responses.

[0036] Conventional interconnect systems do not provide any mechanism for computing devices to identify or determine the structural, electrical, and related characteristics of the interconnect systems between them. For example, if the interconnect system 100 did not incorporate the ID response concepts described herein, the computing device 30 could not identify that it was connected to the connector 120 as compared to any of the other connectors 121-129 and 140-143 in the environment 10. The computing device 30 could not identify that it was connected to the computing device 31, connected to the computing devices 31-33, or connected to any other particular combination of the computing devices in the environment 10. As another example, if the interconnect system 100 did not incorporate the ID response concepts described herein, the computing device 30 could not determine the position of the connector 120 with respect to theother connectors 121-129 on the bulkhead 22 or determine the physical or logical positions of (or connections with) the other computing devices 31-39 in the computing system 20. The computing device 30 also could not determine any characteristics about the cable bundle 110 or the interconnect system 100, and the computing device 30 could not tailor or adjust any operating parameters. These and other aspects of the embodiments are described below.

[0037] FIG. 2 illustrates a perspective view of the connector 120 at the free end of a cable bundle 110 in the interconnect system 100 shown in FIG. 1. The connector 120 is illustrated as a representative example and is not drawn to any particular scale or size. The shape, size, style, proportion, and other characteristics of the connector 120 can vary as compared to that shown. Additionally, while the connector 120 and other connectors discussed herein are described for use in high speed backplane and related interconnect applications, the concepts are not limited to use with such interconnect applications or systems. The concepts can be extended to use in other types of connectors and in other types of interconnect systems and applications.

[0038] The connector 120 includes a housing 200. The housing 200 has a mating interface 202 and a cable interface 204. Another mating connector, such as the connector 60 of the computing device 30 shown in FIG. 1, can be mated and electrically coupled to the connector 120 at the mating interface 202. In other examples, the free end of another interconnect system cable can be mated and electrically coupled to the connector 120 at the mating interface 202. In the example shown, the connector 120 is a hermaphroditic or genderless type of connector. In other words, a duplicate of the connector 120 could be rotated and mated to the connector 120 (i.e., to itself) at the mating interface 202. The concepts are not limited to use with hermaphroditic connectors, and other types or styles of connectors can be relied upon in the interconnect system 100.

[0039] The housing 200 can be formed from a plastic or polymer, such as liquid crystal polymer (LCP), polyethylene (PE), polytetrafluoroethylene (PTFE), fluoropolymer, or other plastic or insulating material(s). The housing 200 can be formed using any suitable additive or subtractive manufacturing techniques, including molding, injection molding, printing, and other techniques. In some cases, the outer surfaces of the housing 200 can be plated with a plating metal or metals for conductivity, and the housing 200 can be embodied as a plated plastic component. The surfaces can be etched in some cases and metalized or plated in a bath, barrel plated, plated by physical vapor deposition (PVD), plated by electroless plating, electroplating, sputter plating,ion plating, or other plating techniques or a combination thereof. The surfaces of the housing 200 can be metalized or plated with copper, nickel, tin, silver, another other plating metal, or a combination of such plating metals.

[0040] The cable bundle 110 extends into the cable interface 204 of the connector 120. As described in further detail below, the distal ends of the cables in the cable bundle 110 are mechanically and electrically terminated to wafer assemblies, which are positioned in a side-by- side arrangement within the housing 200. The wafer assemblies include signal conductors or terminals and ground shields, among other components, and the conductors in the cable bundle 110 are electrically coupled to the signal conductors of the wafer assemblies. Any wafer assembly that is electrically coupled to cables in the cable bundle 110 can be referred to herein as a signal wafer assembly. An identification or ID wafer assembly is also positioned within the housing 200, among the other signal wafer assemblies. The housing 200 is positioned over and secures the wafer assemblies in the connector 120.

[0041] As described below, the connector 120 includes sixteen signal wafer assemblies and an additional ID wafer assembly, for a total of seventeen wafer assemblies. However, the connector 120 can include other numbers of signal and ID wafer assemblies in other cases, including fewer or greater numbers of wafer assemblies. Each of the signal wafer assemblies, which are described in further detail below with reference to FIG. 4, includes pairs of signal conductors and a channel shield for each pair of signal conductors. Each of the signal wafer assemblies includes four pairs of signal conductors and four channel shields in the examples shown. Each pair of signal conductors extends within a channel of a respective channel shield, and the channel shield provides a common ground and shield for the pair of signal conductors. The ID wafer assembly, which is described in further detail below with reference to FIGS. 5A-5D, also includes four pairs of signal conductors and four channel shields in the examples shown.

[0042] FIG. 3A illustrates a perspective view and FIG. 3B illustrates a side view of the wafer assemblies of the connector 120 shown in FIG. 2. The housing 200 of the connector 120 is omitted from view in FIGS. 3 A and 3B so that the wafer assemblies are visible. The wafer assemblies shown in FIGS. 3 A and 3B are illustrated as a representative example and are not drawn to any particular scale or size. The shape, size, proportion, and other characteristics of the wafer assemblies can vary as compared to that shown. Each of the connectors 120-129 and 140-143 caninclude an arrangement of wafer assemblies similar to that shown in FIGS. 3A and 3B, including both signal wafer assemblies and an ID wafer assembly.

[0043] As shown, the connector 120 includes a number of wafer assemblies, including the wafer assemblies 210A, 210B, 210C, 210D, and 210P, among others (collectively “wafer assemblies 210”). The wafer assemblies 210 are positioned in a side-by-side arrangement in the connector 120. Each of the wafer assemblies 210 is a signal wafer assembly, as cables from the cable bundle 110 are terminated to the wafer assemblies 210. For example, the cables 110A-110D are terminated to the wafer assembly 210A, and other cables from the cable bundle 110 are terminated to the wafer assemblies 210B, 210C, 210D, and 210P, among others. The connector 120 includes sixteen wafer assemblies 210 in the example shown. The connector 120 can include other numbers of wafer assemblies in other cases, however, including fewer or greater numbers of wafer assemblies.

[0044] The connector 120 also includes an ID wafer assembly 220, which is an example of an ID component in the interconnect system 100. In one example, each of the connectors 120-129 and 140-143 in the interconnect system 100 can include an ID wafer assembly similar to the ID wafer assembly 220. In other cases, however, a subset of the connectors 120-129 and 140-143 in the interconnect system 100 include an ID wafer assembly. Notably, no cables from the cable bundle 110 are terminated to the ID wafer assembly 220, and the ID wafer assembly 220 can be referred to as a “dead-end” wafer assembly for that reason. In the example shown in FIGS. 3A and 3B, the ID wafer assembly 220 is positioned at one end (e.g., at the right end) of the signal wafer assemblies 210 in the connector 120. In other cases, the ID wafer assembly 220 can be positioned at the other end (e.g., at the left end) of the signal wafer assemblies 210. The ID wafer assembly 220 is not limited to being positioned at an end of a side-by-side arrangement of signal wafers, however, and the ID wafer assembly 220 can also be positioned at any location among the wafer assemblies 210 (e.g., in the middle of or between the wafer assemblies 210) in other cases.

[0045] Each of the wafer assemblies 210 includes a signal coupling interface. For example, the wafer assemblies 210A, 210B, 210C, 210D, and 21 OP include signal coupling interfaces 212A, 212B, 212C, 212D, and 212P, respectively. The signal coupling interface 212A of the wafer assembly 210A is described in further detail below with reference to FIG. 4 and includes electrical contacts for signal conductors and ground shields. The signal coupling interfaces of each of theother wafer assemblies 21 OB, 21 OC, 210D, and 21 OP is the same as the signal coupling interface 212A of the wafer assembly 21 OA in the example shown.

[0046] The ID wafer assembly 220 includes an identification or ID coupling interface 222. The ID coupling interface 222 of the ID wafer assembly 220 is described in further detail below with reference to FIGS. 5A-5C and includes electrical contacts for signal conductors and ground shields. The ID coupling interface 222 of the ID wafer assembly 220 can be the same as the signal coupling interfaces of the wafer assemblies 210, as described in further detail below. In other cases, the ID coupling interface 222 of the ID wafer assembly 220 can be different than the signal coupling interfaces of the wafer assemblies 210. The coupling interfaces of the wafer assemblies 210 and the ID wafer assembly 220 can be electrically coupled with the connector 60 of the computing device 30 (see FIG. 1), to make electrical connections with the computing device 30.

[0047] The ID wafer assembly 220 includes wiring and / or circuitry for storing a unique identifier, among other data, associated with the connector 120, the cable bundle 110, the interconnect system 100, or some combination thereof. More particularly, FIG. 3B illustrates an ID circuit module 280 of the ID wafer assembly 220. Referring to FIG. 3A, the ID wafer assembly 220 includes a wafer insert 270, and the ID circuit module 280 is positioned within the wafer insert 270. The wafer insert 270 is omitted from view in FIG. 3B, so that the ID circuit module 280 is visible.

[0048] The ID circuit module 280 can store and provide a unique identifier or ID in response to a query from the computing device 30. The ID response can be provided in the form of voltage potentials or logic levels on the coupling interface 222 of the ID wafer assembly 220, serial or parallel data on the coupling interface 222, or data in other suitable formats. An ID response from the ID circuit module 280 can be, at least in part, unique as compared to any or all ID responses provided from other ID wafer assemblies in the connectors 121-129 and 140-143. Additional aspects of the ID circuit module 280 are described in greater detail below with reference to FIGS. 5B and 5C.

[0049] The wafer assemblies of the connector 120, as shown in FIGS. 3 A and 3B, are representative of the wafer assemblies in the other connectors 121-129 and 140-143 in the interconnect system 100. More particularly, the connectors 121-129 and 140-143 also include signal wafer assemblies and an ID wafer assembly. In some cases, each of the connectors 121-129 and 140-143 includes an ID wafer assembly. In other cases, a subset of the connectors 120- 129 and 140-143 in the interconnect system 100 include an ID wafer assembly.

[0050] Consistent with the concepts described herein, the ID wafer assembly in each (or in any) of the connectors 120-129 and 140-143 can be queried or interrogated by the computing devices 30-30 and 50-53, respectively, to receive ID responses from the connectors 120-129 and 140-143. The ID responses from the connectors 120-129 and 140-143 can include a range of information. The ID responses can include unique identifiers or codes, such as unique identifiers of the connectors 120-129 and 140-143. The ID responses can include data related to the type, style, or other characteristics of the connectors 120-129 and 140-143. The ID responses can include data related to the relative or absolute positions of the connectors 120-129 in the bulkhead 22. Similarly, the ID responses can include data related to the relative or absolute positions of the connectors 140-143 in the bulkhead 42. The ID responses can include data related to the cable bundles 110-119 and 130-133, the numbers and types (e.g., part number, conductor or fiber type, gauge, length, etc.) of cables in the cable bundles 110-119 and 130-133, the numbers of cable bundles in the interconnect system 100, and other information related to the cable bundles 110- 119 and 130-133 and the interconnect system 100. The computing devices 30-39 and the computing devices 50-53 can tailor or adjust certain operating parameters, such as clock or skew timings, based on the ID responses.

[0051] FIG. 4 illustrates a perspective view of the wafer assembly 210A in the connector 120 shown in FIG. 1. The wafer assembly 210A is illustrated as a representative example and is not drawn to any particular scale or size. The shape, size, proportion, and other characteristics of the wafer assembly 210A can vary as compared to that shown. Each of the wafer assemblies 210 in the connector 120 can be similar to, and include the same components and features as, the wafer assembly 210A.

[0052] The wafer assembly 210A includes channel shields 231-234, a wafer insert 240, and signal conductors 251-258. The signal conductors 251-258 are electrical terminals for the communication of data signals through the wafer assembly 210A and the connector 120. The channel shields 231-234 are common or ground shields in the wafer assembly 210A and the connector 120. At one end, the channel shields 231-234 and the signal conductors 251-258 form the signal coupling interface 212A of the wafer assembly 210A.

[0053] The channel shields 231-234 are formed as U-shaped shields in the example shown, although the channel shields 231-234 can be formed in other shapes. Each of the channel shields 231-234 includes a pair of sidewalls which extend substantially orthogonal to a back wall, to form a U-shaped shield. Pairs of the signal conductors 251-258 extend within channels of the channel shields 231-234. Particularly, the signal conductors 251 and 252 extend within a channel of the channel shield 231, the signal conductors 253 and 254 extend within a channel of the channel shield 232, the signal conductors 255 and 256 extend within a channel of the channel shield 233, and the signal conductors 257 and 258 extend within a channel of the channel shield 234.

[0054] The signal conductors 251-258 can be formed from (e.g., stamped, sheared, or otherwise formed out of) a flat sheet of metal, such as a lead frame. In some cases, the sheet of metal or lead frame can be plated with one or more plating metals. The shapes of the signal conductors 251-258 can be formed by bending, pressing, or stamping. The channel shields 231- 234 can be separately formed from (e.g., stamped, sheared, or otherwise formed out of) a flat sheet of metal material. The shapes of the channel shields 231-234 can be formed by bending, pressing, or stamping.

[0055] The wafer insert 240 can be formed from a plastic or polymer, such as LCP, PE, PTFE, fluoropolymer, or other plastic or insulating material(s). The wafer insert 240 can be molded around the signal conductors 251-258 and the channel shields 231-234. The wafer insert 240 secures and positions the signal conductors 251-258 and the channel shields 231-234 with respect to each other and with respect to the other components of the wafer assembly 210A.

[0056] As also shown in FIG. 4, the cables 110A-110D are terminated to the wafer assembly 210A. More particularly, the cable 110A includes the conductors 151 and 152, and the conductors 151 and 152 are electrically coupled to the signal conductors 251 and 252 within the wafer assembly 210A. Further, the cable HOB includes the conductors 153 and 154, which are electrically coupled to the signal conductors 253 and 254 within the wafer assembly 210A. The cable HOC includes the conductors 155 and 156, which are electrically coupled to the signal conductors 255 and 256, and the cable HOD includes the conductors 157 and 158, which are electrically coupled to the signal conductors 257 and 258. Thus, the conductors 151-158 of the cables 110A-110D are electrically coupled to the signal conductors 251-258. Data signals carried over the conductors 151-158 are coupled to the signal conductors 251-258 by the wafer assembly 210A. The other wafer assemblies 210 in the connector 120 are also designed to conduct datasignals from other cables in the cable bundle 110 to signal conductors in a similar way. Drain conductors in the cables 110A-110D are also electrically coupled to the channel shields 231-234 in the wafer assembly 21 OA.

[0057] FIG. 5A illustrates a perspective view of the ID wafer assembly 220 in the connector 120 of the interconnect system 100 shown in FIG. 1. The ID wafer assembly 220 is illustrated as a representative example and is not drawn to any particular scale or size. The shape, size, proportion, and other characteristics of the ID wafer assembly 220 can vary as compared to that shown.

[0058] The ID wafer assembly 220 includes channel shields 261-264, a wafer insert 270, and conductors 281-288. The conductors 281-288 and channel shields 231-234 form the ID coupling interface 222 of the ID wafer assembly 220. The ID wafer assembly 220 also includes the ID circuit module 280, which is secured within the wafer insert 270. As described below with reference to FIGS. 5B and 5C, the ID circuit module 280 is configured to generate an ID response in response to a query presented on the ID coupling interface 222 of the ID circuit module 280 by the computing device 30.

[0059] Comparing FIG. 5A with FIG. 4, the ID coupling interface 222 of the ID wafer assembly 220 is the same (e.g., having the same number, position, and arrangement of conductors / terminals, same lead style, etc.) as the signal coupling interface 212A of the wafer assembly 210A. Further, the ID coupling interface 222 of the ID wafer assembly 220 is also the same as the signal coupling interfaces of all the other wafer assemblies 210 in the connector 120 in the example shown (see also FIGS. 3 A and 3B). Thus, the mating connector 60 of the computing device 30 (see FIG. 1) does not need to be modified or adjusted for connection to the connector 120 in the example shown. In other cases, however, the ID coupling interface 222 of the ID wafer assembly 220 can be different than the signal coupling interfaces of the wafer assemblies 210 in the connector 120.

[0060] The channel shields 261-264 of the ID wafer assembly 220 shown in FIG. 5 A are formed as U-shaped shields, although the channel shields 261-264 can be formed in other shapes. Each of the channel shields 261-264 includes a pair of sidewalls which extend substantially orthogonal to a back wall, to form a U-shaped shield. Pairs of the signal conductors 281-288 extend within channels of the channel shields 261-264. The conductors 281-288 can be formed from (e.g., stamped, sheared, or otherwise formed out of) a flat sheet of metal, such as a lead frame.In some cases, the sheet of metal or lead frame can be plated with one or more plating metals. The shapes of the signal conductors 281-288 can be formed by bending, pressing, or stamping. The channel shields 261-264 can be separately formed from (e.g., stamped, sheared, or otherwise formed out of) a flat sheet of metal material. The shapes of the channel shields 261-264 can be formed by bending, pressing, or stamping.

[0061] The wafer insert 270 can be formed from a plastic or polymer, such as LCP, PE, PTFE, fluoropolymer, or other plastic or insulating material(s). The wafer insert 270 can be molded around the conductors 281-288 and the channel shields 261-264. The wafer insert 270 secures and positions the conductors 281-288 and the channel shields 261-264 with respect to each other and with respect to the other components of the ID wafer assembly 220. The wafer insert 270 is also molded around the ID circuit module 280. Thus, the wafer insert 270 secures and positions the conductors 281-288, the channel shields 261-264, and the ID circuit module 280 with respect to each other.

[0062] FIG. 5B illustrates a first-side plan view of the ID circuit module 280 in the ID wafer assembly 220 shown in FIG. 5A, and FIG. 5C illustrates a second-side plan view of ID circuit module 280. The ID circuit module 280 is illustrated as an example in FIGS. 5 A and 5B, and the ID circuit module 280 can vary as compared to that shown in practice. In the example shown, the ID circuit module 280 includes a PCB 300 and circuit components or elements on the PCB 300. As shown in FIG. 5C, the ID circuit module 280 includes a circuit 330 and the resistor 340 on the PCB 300, among possibly other active integrated circuits and passive components. The PCB 300 includes a ground plane 310 and conductive traces 320-324. The PCB 300 can include other ground planes, conductive traces, conductive pads, and related features among the embodiments. The channel shields 261-264 and the conductors 281-288 of the ID wafer assembly 220 are electrically coupled to conductive pads of the PCB 300, for electrical connections to the ground plane 310 and the conductive traces 320-324 of the PCB 300.

[0063] The circuit 330 can be embodied as a range of different discrete and integrated circuit components among the embodiments. As one example, the circuit 330 can be embodied as an electrically erasable and programmable read-only memory (EEPROM) with a serial bus interface. Thus, the ID circuit module 280 includes a memory circuit or device in the example shown. The circuit 330 can also be embodied as other types of integrated circuits, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices(PLDs), and other integrated circuits. The circuit 330 can include any suitable interface, such as a serial, parallel, or related bus interface among the embodiments. The circuit 330 can also be embodied as one or more discrete components, other integrated components, or a combination thereof in other cases.

[0064] The circuit 330 includes an inter-integrated circuit or FC serial bus interface in the example shown, including clock or SCL and data or SDA pins. The circuit 330 also includes a write protect or WP pin, as well as pins for power or VDC, ground or GND, and possibly other interfaces. The VDC pin of the circuit 330 is electrically coupled to the conductor 288 of the ID wafer assembly 220 by the trace 321 on the PCB 300. The SCL and SDA pins of the circuit 330 are electrically coupled to the conductors 287 and 285 of the ID wafer assembly 220 by the traces 322 and 323, respectively. The WP pin of the circuit 330 is coupled to the conductor 284 by the trace 324, and the GND pin of the circuit 330 is coupled to the ground plane 310 of the PCB 300. The ground plane 310 of the PCB 300 is also coupled to the conductor 283 through the resistor 340 and the trace 320. The connections between the circuit 330 and the conductors 281-288 is provided as an example in FIG. 5C. In other examples, the circuit 330 can be electrically coupled to the conductors 281-288 in other ways depending on the type and format of the circuit 330. In some cases, all of the conductors 281-288 can be coupled to the circuit 330, for example, if more pins are needed for a different type of data bus.

[0065] The circuit 330 can be powered by and communicate data over the ID coupling interface 222. For example, when the connector 120 is mated with the connector 60 of the computing device 30, the computing device 30 can provide power to and receive data from the circuit 330 of the ID wafer assembly 220. More particularly, the computing device 30 can provide power to the circuit 330 over the conductor 288, and the computing device 30 can query the data stored on the circuit 330 using the conductors 287 and 285 coupled to the SCL and SDA pins of the circuit 330. Any data received by the computing device 30 from the circuit 330 can be referred to herein as an ID response from the ID wafer assembly 220.

[0066] The circuit 330 of the ID wafer assembly 220 can store data related to the connector 120, the cable bundle 110, the interconnect system 100, and other information. Data can be defined or programmed in the circuit 330 when the circuit module 280 is manufactured, when the connector 120 is installed in the environment 10, or at any other suitable time. As examples, the circuit 330 can store a unique identifier of the connector 120, a physical or logical slot location or identifierfor the connector 120, data related to the type, style, or other characteristics of the connector 120, data related to the relative or absolute position of the connector 120 in the bulkhead 22, data related to the relative or absolute position of the other connectors 121-129 in the bulkhead 22, data related to the relative or absolute positions of the connectors 140-143 in the bulkhead 42, data related to the cable bundle 110 or the other cable bundles 111-119 and 130-133, data related to the numbers and types (e.g., part number, conductor or fiber type, gauge, length, etc.) of the cables in the cable bundles 110-119 and 130-133, data related to the numbers of cable bundles or cable assemblies in the interconnect system 100, data related to the cable interconnections among the individual cables in the interconnect system 100, and other information. The circuit 330 can communicate any or all of the data described above to the computing device 30 over the ID coupling interface 222, when the connector 120 is mated with the connector 60 of the computing device 30 as shown in FIG. 1.

[0067] The computing device 30 can determine its slot location in the computing system 20, for example, based on an ID response from the ID wafer assembly 220 in the connector 120. The slot location can be defined as a physical or logical location as compared to the other computing devices 31-39 in the computing system 20. The computing device 30 can also tailor or adjust certain operating parameters based on the slot location, such as clock or skew timings. The computing device 30 can also identify that it is connected to the connector 120 as compared to any of the other connectors 121-129 and 140-143 in the environment 10. The computing device 30 can also identify that it is connected to the computing device 31 at another slot location, for example, or connected to another computing device or devices in the environment 10. The computing device 30 can also determine the position of the connector 120 with respect to the other connectors 121-129 on the bulkhead 22 or determine the physical or logical positions of (or connections with) the other computing devices 31-39 in the computing system 20. The computing device 30 also could not determine any characteristics about the cable bundle 110 or the interconnect system 100, and the computing device 30 could not tailor or adjust any operating parameters. These and other aspects of the embodiments are described below.

[0068] In a similar way, the computing devices 31-39 can determine slot locations in the computing system 20 based on ID responses from ID wafer assemblies in the connectors 121-129. For example, the computing device 30 can determine a first slot location identifier from the connector 120, and the computing device 31 can determine a second and different slot locationidentifier from the connector 121. Additionally, the computing devices 50-53 can determine slot locations in the computing system 40 based on ID responses from ID wafer assemblies in the connectors 140-143. The ID wafer assemblies in the connectors 120-129 and 140-143 can each include unique data, such as unique data related to the connectors 120-129 and 140-143, the cable bundles 110-119 and 130-133, and the interconnect system 100.

[0069] Terms such as “top,” “bottom,” “side,” “front,” “back,” “right,” and “left” are not intended to provide an absolute frame of reference. Rather, the terms are relative and are intended to identify certain features in relation to each other, as the orientation of structures described herein can vary. The terms “comprising,” “including,” “having,” and the like are synonymous, are used in an open-ended fashion, and do not exclude additional elements, features, acts, operations, and so forth. Also, the term “or” is used in its inclusive sense, and not in its exclusive sense, so that when used, for example, to connect a list of elements, the term “or” means one, some, or all of the elements in the list.

[0070] Combinatorial language, such as “at least one of X, Y, and Z” or “at least one of X, Y, or Z,” unless indicated otherwise, is used in general to identify one, a combination of any two, or all three (or more if a larger group is identified) thereof, such as X and only X, Y and only Y, and Z and only Z, the combinations of X and Y, X and Z, and Y and Z, and all of X, Y, and Z. Such combinatorial language is not generally intended to, and unless specified does not, identify or require at least one of X, at least one of Y, and at least one of Z to be included. The terms “about” and “substantially,” unless otherwise defined herein to be associated with a particular range, percentage, or related metric of deviation, account for at least some manufacturing tolerances between a theoretical design and manufactured product or assembly, such as the geometric dimensioning and tolerancing criteria described in the American Society of Mechanical Engineers (ASME®) Y14.5 and the related International Organization for Standardization (ISO®) standards. Such manufacturing tolerances are still contemplated, as one of ordinary skill in the art would appreciate, although “about,” “substantially,” or related terms are not expressly referenced, even in connection with the use of theoretical terms, such as the geometric “perpendicular,” “orthogonal,” “vertex,” “collinear,” “coplanar,” and other terms.

[0071] The above-described embodiments of the present disclosure are merely examples of implementations to provide a clear understanding of the principles of the present disclosure. Many variations and modifications can be made to the above-described embodiments without departingsubstantially from the spirit and principles of the disclosure. In addition, components and features described with respect to one embodiment can be included in another embodiment. All such modifications and variations are intended to be included herein within the scope of this disclosure.

Claims

CLAIMSWhat is claimed is:

1. A cable assembly, comprising: a cable bundle; a connector at one end of the cable bundle, the connector comprising: a plurality of signal wafer assemblies electrically coupled to cables in the cable bundle; and an identification wafer assembly comprising an identification wafer module, the identification wafer module storing a unique identifier for the cable assembly.

2. The cable assembly according to claim 1, wherein: the connector further comprises a housing; the plurality of signal wafer assemblies are arranged in a row within the housing; and the identification wafer assembly is positioned at one end of the row of the plurality of signal wafer assemblies.

3. The cable assembly according to claim 1, wherein: each of the plurality of signal wafer assemblies comprises a signal coupling interface; the identification wafer assembly comprises an identification coupling interface; and the signal coupling interface is the same as the identification coupling interface.

4. The cable assembly according to claim 3, wherein the identification coupling interface comprises a data bus and power terminals.

5. The cable assembly according to claim 3, wherein the identification coupling interface comprises a serial data bus and power terminals.

6. The cable assembly according to claim 3, wherein: each signal coupling interface of the plurality of signal wafer assemblies is electrically coupled to conductors of cables among the cable bundle; andthe identification wafer assembly is not electrically coupled to any conductor of any cable in the cable bundle.

7. The cable assembly according to claim 1, wherein the unique identifier comprises a slot location identifier.

8. The cable assembly according to claim 1, wherein the identification wafer module is configured to communicate the unique identifier for the cable assembly in response to a query on an identification coupling interface of the identification wafer assembly.

9. The cable assembly according to claim 1, wherein the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query on an identification coupling interface of the identification wafer assembly.

10. The cable assembly according to claim 9, wherein the identifier response comprises a unique identifier of the connector at the one end of the cable bundle.

11. The cable assembly according to claim 9, wherein the identifier response comprises data related to the connector, the cable bundle, or both the connector and the cable bundle.

12. The cable assembly according to claim 9, wherein the identifier response comprises data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead.

13. An interconnect system, comprising: a first cable assembly comprising: a first cable bundle; a first connector at one end of the first cable bundle, the first connector comprising: a first signal wafer assembly electrically coupled to a cable in the first cable bundle; anda first identification wafer assembly comprising a first identification wafer module, the first identification wafer module storing a first unique identifier for the first cable assembly; and a second cable assembly comprising: a second cable bundle; a second connector at one end of the second cable bundle, the second connector comprising: a second signal wafer assembly electrically coupled to a cable in the second cable bundle; and a second identification wafer assembly comprising a second identification wafer module, the second identification wafer module storing a second unique identifier for the second cable assembly.

14. The interconnect system according to claim 13, wherein: the first signal wafer assembly comprises a signal coupling interface; the first identification wafer assembly comprises an identification coupling interface; and the signal coupling interface is the same as the identification coupling interface.

15. The interconnect system according to claim 14, wherein the identification coupling interface comprises a serial data bus and power terminals.

16. The interconnect system according to claim 13, wherein: the first unique identifier comprises a first slot location identifier; and the second unique identifier comprises a second slot location identifier.

17. A cable assembly, comprising: a cable bundle; a connector at one end of the cable bundle, the connector comprising: a signal wafer assembly electrically coupled to cables in the cable bundle; and an identification wafer module, the identification wafer module storing a unique identifier for the cable assembly.

18. The cable assembly according to claim 17, wherein the unique identifier comprises a slot location identifier.

19. The cable assembly according to claim 17, wherein the identification wafer module is configured to communicate an identifier response for the cable assembly in response to a query on an identification coupling interface of the identification wafer module.

20. The cable assembly according to claim 19, wherein the identifier response comprises data related to the connector, the cable bundle, or both the connector and the cable bundle.

21. A connector, comprising: a housing; a signal wafer assembly secured in the housing; and an identification wafer assembly secured in the housing, the identification wafer assembly comprising an identification wafer module, the identification wafer module storing a unique identifier for the connector.

22. The connector according to claim 21, wherein: the signal wafer assembly comprises a plurality of signal wafer assemblies arranged in a row within the housing; and the identification wafer assembly is positioned at one end of the row of the plurality of signal wafer assemblies.

23. The connector according to claim 21, wherein: the signal wafer assembly comprises a signal coupling interface; the identification wafer assembly comprises an identification coupling interface; and the signal coupling interface is the same as the identification coupling interface.

24. The connector according to claim 23, wherein the identification coupling interface comprises a data bus and power terminals.

25. The connector according to claim 21 , wherein the unique identifier comprises a slot location identifier.

26. The connector according to claim 21, wherein the unique identifier comprises data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead.

27. An identification wafer assembly for a connector, comprising: a coupling interface, the coupling interface comprising a plurality of conductors and at least one shield; and an identification wafer module, the identification wafer module comprising an integrated circuit storing a unique identifier for the connector.

28. The identification wafer assembly according to claim 27, wherein the integrated circuit comprises a data bus and power terminals coupled respectively to conductors among the plurality of conductors.

29. The identification wafer assembly according to claim 27, wherein the unique identifier comprises a slot location identifier.

30. The identification wafer assembly according to claim 27, wherein the unique identifier comprises data related to a position of the connector and at least one other connector in an arrangement of connectors of a bulkhead.

31. A cable assembly, comprising: a cable bundle; a connector at one end of the cable bundle, the connector comprising:a plurality of signal conductors electrically coupled to cables in the cable bundle; and an identification module, the identification module storing a unique identifier for the cable assembly.

32. The cable assembly according to claim 31, wherein: the identification module is electrically coupled to an identification coupling interface; and the identification coupling interface comprises a data bus and power terminals.

33. The cable assembly according to claim 31 , wherein the unique identifier comprises a slot location identifier.

34. A connector, comprising: a housing; a plurality of signal conductors; and an identification module secured in the housing, the identification module storing a unique identifier for the connector.

35. The connector according to claim 34, wherein: the identification module is electrically coupled to an identification coupling interface of the connector; and the identification coupling interface comprises a data bus and power terminals.

36. The connector according to claim 34, wherein the unique identifier comprises a slot location identifier.

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