Techniques for managing noise decoding

Abstract

Various aspects of the present disclosure relate to techniques for guessing random additive noise decoding. An apparatus is configured to receive a signal via a channel, demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or a low-density parity check (LDPC) codeword from an LDPC codebook, and decode the codeword according to a guessing random additive noise decoding (GRAND) scheme.

Description

TECHNIQUES FOR MANAGING NOISE DECODING TECHNICAL FIELD

[0001] The present disclosure relates to wireless communications, and more specifically to techniques for managing noise decoding, including techniques for guessing random additive noise decoding (GRAND). BACKGROUND

[0002] A wireless communications system may include one or multiple network communication devices, such as base stations (BSs), which may support wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE), or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers, or the like). Additionally, the wireless communications system may support wireless communications across various radio access technologies including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., sixth generation (6G)). SUMMARY

[0003] An article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of”) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall beconstrued in the same manner as the phrase “based at least in part on.” Further, as used herein, including in the claims, a “set” may include one or more elements.

[0004] In one embodiment, an apparatus may be configured to support a means to receive a signal via a channel, demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or a low-density parity check (LDPC) codeword from an LDPC codebook, and decode the codeword according to a GRAND scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 illustrates an example of a wireless communications system in accordance with aspects of the present disclosure.

[0006] Figure 2 illustrates an example transmission chain using a GRAND decoder, in accordance with aspects of the present disclosure.

[0007] Figure 3 illustrates an example of polar code decoding using soft and hard detection GRAND decoding, in accordance with aspects of the present disclosure.

[0008] Figure 4 illustrates an example performance of polar codes, in accordance with aspects of the present disclosure.

[0009] Figure 5 illustrates an example transmission chain illustrating interleaving and deinterleaving, in accordance with the present disclosure.

[0010] Figure 6 illustrates an example of the performance of polar codes, in accordance with aspects of the present disclosure.

[0011] Figure 7 illustrates an example of the performance of LDPC codes, in accordance with aspects of the present disclosure.

[0012] Figure 8 illustrates an example of a UE in accordance with aspects of the present disclosure.

[0013] Figure 9 illustrates an example of a processor in accordance with aspects of the present disclosure.

[0014] Figure 10 illustrates an example of a network equipment (NE) in accordance with aspects of the present disclosure.

[0015] Figure 11 illustrates a flowchart of a method performed by a device in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0016] Some wireless communication networks include various service requirements. For instance, 6G use cases that use enhanced ultra-reliable low-latency communications (URLLC), enhanced mobile broadband (eMBB), and enhanced massive machine-type communications (mMTC) are aimed at services with stringent requirements for high throughput, low end-to-end transmission latency, ultra-reliability, packet size flexibility, and availability. 6G URLLC plays a role in providing connectivity for the new services and applications from vertical domains, such as, for example, factory automation, tactile internet, autonomous driving, and so on.

[0017] Current 5G new radio (NR) standardization has adopted polar codes for control channels and LDPC codes for data channels due to their capacity-achieving performance and low-complexity encoding and decoding schemes. However, legacy decoding algorithms are typically designed with particular codebook structures in mind and are heuristically aimed to approximately identify a maximum likelihood (ML) decoding candidate. This applies to polar codes designed to be decoded using the cyclic redundancy check (CRC) aided successive cancellation list (CA-SCL) decoder and LDPC codes designed to be decoded using the belief propagation (BP) decoder or sum- product algorithms (SPA).

[0018] An exception to this is the GRAND framework, which works with any block-code. GRAND identifies an ML decoding, while GRAND with Abandonment (GRANDAB), a variant with reduced computational complexity, either identifies an ML decoding or reports a decoding failure. Both have been theoretically proven to be capacity-achieving when used with random codebooks. In contrast to codebook-oriented algorithms, GRAND and GRANDAB are noise-centric, and aim to infer the noise that has occurred on the channel from which the ML decoding can be deduced.

[0019] The subject matter herein presents solutions and procedures that enable the decoding of different 5G NR channel codes using a code agnostic GRANDAB decoder. The solutions allow for better hardware efficiency and low implementation complexity by enabling different channel codes, at different block lengths and different rates to be decoded using the same capacity-achieving decoding algorithm. The solutions improvethe area efficiency and chip area of legacy 5G NR channel coding techniques, which improves the reliability, power usage, efficiency, latency, and / or the like of UEs and other network equipment devices. Simulation results for LDPC codes and polar codes using GRANDAB and for different code rates and code block lengths are also described and compared with legacy decoding techniques, e.g., CA-SCL for polar codes and iterative decoding for LDPC codes.

[0020] Aspects of the present disclosure are described in the context of a wireless communications system.

[0021] Figure 1 illustrates an example of a wireless communications system 100 in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more NE 102, one or more UE 104, and a core network (CN) 106. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, such as an LTE network or an LTE-Advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a NR network, such as a 5G network, a 5G-Advanced (5G-A) network, or a 5G ultrawideband (5G-UWB) network. In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology including Institute of Electrical and Electronics Engineers (IEEE) 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G, for example, 6G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA), frequency division multiple access (FDMA), or code division multiple access (CDMA), etc.

[0022] The one or more NE 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the NE 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a network function, a network entity, a radio access network (RAN), a NodeB, an eNodeB (eNB), a next-generation NodeB (gNB), or other suitable terminology. An NE 102 and a UE 104 may communicate via a communication link, which may be a wireless or wired connection. For example, an NE 102 and a UE 104may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

[0023] An NE 102 may provide a geographic coverage area for which the NE 102 may support services for one or more UEs 104 within the geographic coverage area. For example, an NE 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc.) according to one or multiple radio access technologies. In some implementations, an NE 102 may be moveable, for example, a satellite associated with a non-terrestrial network (NTN). In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies may overlap, but the different geographic coverage areas may be associated with different NE 102.

[0024] The one or more UE 104 may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a remote unit, a mobile device, a wireless device, a remote device, a subscriber device, a transmitter device, a receiver device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an Internet-of-Things (IoT) device, an Internet-of-Everything (IoE) device, or machine-type communication (MTC) device, among other examples.

[0025] A UE 104 may be able to support wireless communication directly with other UEs 104 over a communication link. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link 114 may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

[0026] An NE 102 may support communications with the CN 106, or with another NE 102, or both. For example, an NE 102 may interface with other NE 102 or the CN 106 through one or more backhaul links (e.g., S1, N2, N2, or network interface). In some implementations, the NE 102 may communicate with each other directly. In some other implementations, the NE 102 may communicate with each other or indirectly(e.g., via the CN 106. In some implementations, one or more NE 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC). An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmit-receive points (TRPs).

[0027] The CN 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The CN 106 may be an evolved packet core (EPC), or a 5G core (5GC), which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME), an access and mobility management functions (AMF)) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW), a Packet Data Network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc.) for the one or more UEs 104 served by the one or more NE 102 associated with the CN 106.

[0028] The CN 106 may communicate with a packet data network over one or more backhaul links (e.g., via an S1, N2, N2, or another network interface). The packet data network may include an application server. In some implementations, one or more UEs 104 may communicate with the application server. A UE 104 may establish a session (e.g., a protocol data unit (PDU) session, or the like) with the CN 106 via an NE 102. The CN 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server using the established session (e.g., the established PDU session). The PDU session may be an example of a logical connection between the UE 104 and the CN 106 (e.g., one or more network functions of the CN 106).

[0029] In the wireless communications system 100, the NEs 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communications). In some implementations, the NEs 102 and the UEs 104 may support different resource structures. For example, the NEs 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the NEs 102 and the UEs 104 maysupport a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the NEs 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures). The NEs 102 and the UEs 104 may support various frame structures based on one or more numerologies.

[0030] One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., ^=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., ^=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., ^=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., ^=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., ^=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., ^=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

[0031] A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames). Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, each frame may include multiple subframes. For example, each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

[0032] Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., ^=0, ^=1, ^=2, ^=3, ^=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively. Each slot may include a number (e.g., quantity) ofsymbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing), a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., ^=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

[0033] In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz – 7.125 GHz), FR2 (24.25 GHz – 52.6 GHz), FR3 (7.125 GHz – 24.25 GHz), FR4 (52.6 GHz – 114.25 GHz), FR4a or FR4-1 (52.6 GHz – 71 GHz), and FR5 (114.25 GHz – 300 GHz). In some implementations, the NEs 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the NEs 102 and the UEs 104, among other equipment or devices for cellular communications traffic (e.g., control information, data). In some implementations, FR2 may be used by the NEs 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

[0034] FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies). For example, FR1 may be associated with a first numerology (e.g., ^=0), which includes 15 kHz subcarrier spacing; a second numerology (e.g., ^=1), which includes 30 kHz subcarrier spacing; and a third numerology (e.g., ^=2), which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies). For example, FR2 may be associated with a third numerology (e.g., ^=2), which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., ^=3), which includes 120 kHz subcarrier spacing.

[0035] As background, the third-generation partnership project (3GPP) has defined URLLC as a critical communication scenario for beyond 5G and 6G networks. URLLCin 6G requires a significantly lower end-to-end latency (= 1 ms) compared to 5G NR, and a high level of transmission reliability, requiring a block error rate (BLER) of less than 10^^. URLLC will enable emerging applications, such as future factory applications, tactile internet, distributed utility grid, and metaverse, as well as mission- critical applications, such as telesurgery, autonomous driving and factory automation. Table 1 depicts target requirements of some of these use cases. Table 1: Examples of URLLC use cases and their target requirements

[0036] On the other hand, short block-length codes with strong error-correction capabilities are essential in URLLC to meet the stringent latency and reliability requirements. However, the use of short block-length codes could degrade the transmission reliability. According to the normal approximation (NA) bound for the finite block-length regime, the theoretical maximum ratio of information bits to coded bits that can be correctly transmitted over a noisy channel significantly drops as the block-length decreases.

[0037] Polar codes have been the subject of active research in recent times, mainly since they are the first ever provably capacity achieving codes, with explicit construction and very low complexity of encoding and decoding. As a preliminary, we write W: X → Y to denote a generic B-DMC with input alphabet X, output alphabet Y, and transition probabilities W (y|x) , x ∈ X , y ∈ Y. The input alphabet X will always be {0,1}, the output alphabet and the transition probabilities may be arbitrary. We write^^to denote the channel corresponding to N uses of W; thus,^^: ^^→ ^^with^ ^ ^| ^ ∏^^ ^^ ^^ ) = ^^^ ^^^^|^^) .there are two channel parameters of primary interest:the symmetric capacity: ^^^) = ∑ ^^^ ^ %∈&∑#∈$^ ^^^|^) log^^^^ !^^^^0^" !^^^^1^)

[0039] and the^^) ≜ ( )^^^|0)^^^|1)

[0040] Theseand reliability, respectively. I (W) is the highest rate at which reliable communication is possible across W using the inputs of W with equal frequency. Z (W) is an upper bound on the probability of maximum-likelihood (ML) decision error when W is used only once to transmit a 0 or 1. It is easy to see that Z (W) takes values in [0 ,1], whereby a 0 indicates a null probability of error in ML-sense, and respectively, a 1 indicates a certain probability of error in ML-sense.

[0041] Channel polarization is an operation by which one manufactures out of N independent copies of a given B-DMC W, a second set of N channels {^^^)^ : 1 ≤ i ≤ N} that show a polarization effect in the sense that, as N becomescapacity terms {I(^^^)^ )} tend towards 0 or 1 for all but a vanishing fraction of indices i. Thisof a channel combining phase and a channel splitting phase.

[0042] Channel combining: This phase combines copies of a given B-DMC W in a recursive manner to produce a vector channel ^^: ^^→ ^^, where N can be any powerof two, * = 2,, n ≥ 0. The recursion begins at the 0-th level (n = 0) with only one copyof W and we set ^^ ≜ ^. The first level (n = 1) of the recursion combines twoindependent copies of ^^as shown in Fig.3 and obtains the channel ^^: ^^→ ^^with the transition^^^^^, ^^|.^, .^) = ^^^^|.^ ⊕ .^) ^^^^| .^)

[0043] Channel Splitting: Having synthesized the vector channel ^^out of ^^, the next step of channel polarization is to split ^^back into a set of N binary-inputcoordinate channels ^^^)^ : ^ → ^^ × ^^^^, 1 ≤ i ≤ N, defined by the transitionprobabilities^^^)^ ^^^, .^^^^. ∑ ^5367 ∈ $ ^34 ^ ^| ^^ ^ ^) ≜ 346 ^^ ^^ .^ )

[0044] To gain anintuitive understanding of the channels {^^^)^ a genie-aided successivecancellation decoder in which the ith element estimates .^after observing ^^^past channel inputs .^^^and the^by the genie regardless ofdecision errors at earlier stages). If .^^is a-priori uniform on ^^, then ^^^)^ is the effective channel seen by the ith element in this scenario.

[0045] It is a known result that for any B-DMC W, the channels {^^^)^ } polarize in the sense that, for any fixed δ ∈ (0, 1), as N goes to infinity of two, thefraction of indices i ∈ {1, ... , N} for which I(^^^)^ ) ∈ (1 − δ, 1] goes to I(W) and the fraction for which I(^^^)^ ) ∈ [0, δ) goes to 1−I(W).

[0046] A purpose of polar codes encoding is the splitting of data sequence indexes into two different sets before transmission. The first set includes the indexes of the data to be transmitted on the noise-free channels. The other set includes the indexes corresponding to the known frozen bits to be transmitted on the pure-noise channel. Many techniques have been introduced to construct polar codes, with varying complexities, e.g., based on Bhattacharyya parameter bounds, Monte-Carlo estimation, density evolution (DE), and Gauss approximation.

[0047] Various techniques have been introduced to decode polar codes. Three main techniques are considered for decoding: successive cancellation (SC), successive cancellation list (SCL) and log-likelihood ratio (LLR) based SCL. As SC decoding is sub-optimal for finite length polar codes, SCL decoding was introduced to achieve the ML bound for a sufficiently large list size L, at the cost of increased complexity due to the list decoding nature. Further enhancement of the code was conducted via concatenating a high-rate outer code such as CRC and parity-check (PC) codes. Under SCL decoding, these CRC-aided polar codes and parity-check concatenated polar codes were shown to outperform the state-of-the-art LDPC codes. An extension of polarcodes, namely Polar Subcodes, have been proposed, outperforming the above- mentioned code constructions.

[0048] However, the SCL decoder is characterized by a high complexity and an inherently serial decoding nature, which in turn reduces the decoding throughput and causes high decoding latency. In addition, SCL decoding may not be a good match to iterative detection and decoding due to its hard decision output nature (i.e., not a soft- in / soft-out decoder). Iterative decoding of polar codes based on message passing over the encoding graph has been possible through BP decoders. The BP algorithm has some advantages over SC-based decoding, as it can be easily parallelized, thus high throughput / low latency implementations are possible, and it inherently enables soft- in / soft-out decoding, facilitating joint iterative detection and decoding. Thus, BP decoding is a promising candidate for high data rate and low latency demanding applications. A belief propagation list (BPL) decoder with comparable performance to the successive cancellation list (SCL) decoder of polar codes, which already achieves the maximum likelihood (ML) bound of polar codes for sufficiently large list size L, also exists.

[0049] LDPC codes provide high performance with iterative decoding. Quasi cycle QC-LDPC (quasi-cyclic LDPC) codes have been adopted for data channels in 5Gnetworks due to their low complexity implementation. An ^8, 9) − LDPC code is alinear block code for which the parity-check matrix ; has a low density of 1s. ; is an^8 − 9) × 8 parity-check matrix whose rows are vectors {ℎ^}. The parity-check matrixperforms ? = 8 − 9 separate parity-checks on a received word. A regular LDPC codeis a linear block code whose parity-check matrix ; contains exactly @A1’s in eachcolumn and exactly @B = @A^8⁄ ? ) 1’s in each row, where @A ≪ ? (and equivalently@ ≪ ? ). The code rate E = F is related to these pa @AB , rameters via ^E = 1 − G @B )which assumes ; is full rank. If ; is low density, but the number of 1’s in each column or row is not constant, then the code is an irregular LDPC code. It is easiest to see the sense in which an LDPC code is regular or irregular through its graphical representation.

[0050] 5G NR QC-LDPC are codes that can be put into quasi-cyclic form. Its parity check matrix can be put into the form of a block matrix consisting of either circulant permutation sub-matrices or the zero sub-matrix. Such codes are often constructed bylifting certain protographs into such block matrices. Their simple structure makes them useful for several wireless communication standards.

[0051] The bit sequence input for a given code block to channel coding is denoted byc0,c1,c2,c3 ,...,cK ^ 1, whereKis the number of bits that could be calculated at the output of the CB segmentation and CRC attachment.

[0052] After encoding the bits are denoted byd0,d1,d2 ,...,dN ^ 1, whereN ^ 66Z cfor LDPC base graph 1 andN ^ 50Z cfor LDPCsizeZ cis given in TS 38.212 section 5 (incorporated herein by reference). LDPC encoder is based on the determination of a parity check matrix H. Parity check matrices could be determined based on chosen base graphs and lifting sizesIA. For LDPC base graph 1, a matrix ofH BGhas 46 rows with row indicesi^0,1,2,..., 45and 68 columns with column indices j ^0,1,2,..., 67. For LDPC base graph 2, a matrix ofH BG has 42 rows with row indices i^0,1,2,..., 41 and 52 columns with column indicesj ^0,1,2,..., 51. The elements in H BG with row and column indices given in TS 38.2123 (for LDPC base graph 2) are of value 1, and all other elements inH BGare of value 0.

[0054] Once the parity check matrix is calculated, theN^2Z c ^ Kparity bitsw^ ^w0,w1,w2 ,...,w TN^2Z ^K ^ 1 ^ H^ c ^ ^ ^ ^w ^ ^ 0^ , whereto 0. The encoding isperformed in GF(2).

[0055] In natural message-passing iterative decoding algorithms, messages are exchanged between the variable and check nodes in discrete time steps. Initially, eachvariable node JK 1 ≤ M ≤ 8, has an associated received value NK , which is a randomvariable taking values in the channel output alphabet Y. Based on this, each variable sends a message belong to some message alphabet M. A common choice for this initial message is simply the received value NK, or perhaps some quantized version of NKfor continuous output channels such as BIAWGN. Now, each check node c processes the messages it receives from its neighbors and sends back a suitable message in M to eachof its neighboring variable nodes. Upon receipt of the messages from the check nodes, each variable node JKuses these together with its own received value NKto produce new messages that are sent to its neighboring check nodes. This process continues for many time steps, till a certain cap on the number of iterations is reached. In the analysis, we are interested in the probability of incorrect decoding, such as the bit-error probability.For every time step O, O ∈ ℕ , the i’th iteration consists of a round check-to-variable nodemessages, followed by the variable nodes responding with their messages to the check nodes. The 0’th iteration consists of dummy messages from the check nodes, followed by the variable nodes sending their received values to the check nodes.

[0056] A condition in the determination of the next message based on the messages received from the neighbors is that message sent by . along an edge e does not depend on the message just received along edge Q. This is important so that only “extrinsic” information is passed along from a node to its neighbor in each step. It is exactly this restriction that leads to the independence condition that makes analysis of the decoding possible.

[0057] GRAND is an algorithm for realizing ML decoding in discrete channels with or without memory. It belongs to the family of code-agnostic decoding algorithms. In it, the receiver rank orders noise sequences from most likely to least likely. Subtracting noise from the received signal in that order, the first instance that results in a member of the codebook is the ML decoding. GRAND has proved to be capacity-achieving when used with random codebooks. For rates below capacity, we identify error exponents, and for rates beyond capacity we identify success exponents.

[0058] As described herein, the scheme’s complexity is determined in terms of the number of computations the receiver performs. For rates beyond capacity, this reveals thresholds for the number of guesses by which if a member of the codebook is identified it is likely to be the transmitted codeword. An approximate ML decoding scheme is introduced where the receiver abandons the search after a fixed number of queries, an approach called GRANDAB. While not an ML decoder, it is established that the algorithm GRANDAB is also capacity-achieving for an appropriate choice of abandonment threshold, and its complexity, error, and success exponents are characterized below. Worked examples are presented for Markovian noise that indicatethat these decoding schemes substantially outperform the brute force decoding approach.

[0059] GRAND algorithmic variants differ in their order of querying putative noise effects. When putative noise effects are ordered in decreasing likelihood from a noise model matched to the channel, it provably produces an ML decoding even for channels with memory in the absence of interleaving. The original algorithm assumed the decoder obtained only hard decision demodulated symbols from the receiver. The simplicity of its operation and the evident parallelizability of code-book querying has resulted in the proposal of efficient circuit implementations.

[0060] The solution detailed in this disclosure describes mechanisms and procedures to enable the decoding of 5G NR channel codes using a universal, code- agnostic decoder mainly the GRANDAB decoder. Both polar codes and LDPC codes are decoded using the same decoding algorithm. BLER performance for both channel coding techniques are provided for different code rates and block lengths and compared with legacy decoding techniques e.g., CA-SCL for polar codes and iterative sum- product (SP) decoder for LDPC codes. This method enables more efficient and less complex hardware implementation and is useful for devices with reduced chip areas and where area efficiency should be high.

[0061] The solution presented herein is valid for different transmission channels including memoryless and channels with memory as opposed to legacy decoders that assume memoryless channels. Raw communication channels are seldom memoryless. Channel fading, inter-symbol interference, multi-user interference, and external noise sources all have inherent timescales that result in time-dependent correlations in instantaneous Signal to Interference plus Noise Ratio (SINR). Essentially, forward error correction decoders assume, however, that channels are memoryless and, as we shall demonstrate, their performance degrades significantly if they are not. The engineering solution to this mismatch is to employ interleaving. In the transmitter, the interleaver permutes the location of bits across the code-words prior to their transmission. At the receiver, the de-interleaver recovers the original bit order, and the resulting signals are passed to a decoder for error correction. In this manner, clumped errors are separated and distributed across multiple code-words, giving noise the appearance of being uncorrelated. Indeed, interleaving can be viewed as another layer of encoding over alarger scale of information bits. It is noted that the transmission channel described herein is an additive white Gaussian noise (AWGN) channel unless noted otherwise.

[0062] Figure 2 illustrates an example transmission chain 200 using a GRAND decoder, in accordance with aspects of the present disclosure. According to a first embodiment, 5G NR legacy channel codes e.g., polar codes 202 and LDPC codes 204, could be decoded using the same universal code-agnostic decoder 206 e.g., GRANDAB or any of its variants, for example, ordered reliability bit GRAND (ORBGRAND), line- 1 ORBGRAND, or the like. In one embodiment, this is beneficial for devices that require low-complexity hardware implementation while preserving good BLER performance as well as code length and code rate flexibility.

[0063] In one embodiment, the encoder could encode the information bits using any channel code, for example, polar code or LDPC code. The information bits size and the code rate could be chosen to have any value e.g., information bits InfoBitsYZ[\could be tens, hundreds or thousands of bits according to the application and use case requirements of the corresponding device. The code rate E could be chosen such that low redundancy or high redundancy are allowed. In this case, in order to allow good decoding performance, low-redundancy codes are privileged, which could be translatedto rates E][0.8, 0.95].

[0064] Figure 3 illustrates an example of CA-polar codes decoding using soft 300 and hard 310 detection GRAND decoding, in accordance with aspects of the present disclosure. In another embodiment, hard detection GRANDAB could be used for both 5G NR polar and LDPC codes, in this case, channel hard output ^defgdis fed to the GRAND decoder. Better BLER performance could be gained when using soft decoding using two GRAND’s variants (ORBGRAND and line-1 ORBGRAND). In this case, soft inputs e.g., log-likelihood ratios (LLRs) are fed to the decoders.

[0065] Encoding and decoding theoretical work assumes memoryless channels, e.g., the AWGN. Raw transmission channels are seldom memoryless due to the channel fading, inter-symbol interference, multi-user interference, and external noise sources. This mismatch between theory and real communication channels impacts the channel coding performance.

[0066] Figure 4 illustrates an example performance of 5G NR CA-polar codes 400over an AWGN channel h^0, i^), where i^ is the noise variance, in accordance withaspects of the present disclosure. In one embodiment, polar codes and LDPC codes are transmitted over memoryless channels such as binary symmetric channels (BSC) as well as over channels with memory such as Markovian channels. In both cases, GRAND decoding preserves channel coding performance. The noise guesswork is based in the case of BSC channels on the Hamming weights of the noise.

[0067] Figure 5 illustrates an example transmission chain 500 illustrating interleaving and deinterleaving, in accordance with the present disclosure. In the transmitter, the interleaver 502 permutes the location of bits across the codewords prior to their transmission. At the receiver, the de-interleaver 504 recovers the original bit order, and the resulting signals are passed to a decoder for error correction. In this way, clumped errors are separated and distributed across multiple code-words, giving noise the appearance of being uncorrelated. According to a second embodiment, the polar and LDPC encoders could disable the interleaving and / or de-interleaving procedure. In such case, the encoded bits could be transmitted over the channel 506 without being interleaved at the transmitter and without being de-interleaved at the receiver. An illustration of the new transmission chain for both LDPC and polar codes is shown in Figure 5. In this case, encoding and decoding latency could be reduced for both polar and LDPC codes.

[0068] In a third embodiment, noise patterns could be identified using, for example, Monte Carlo simulations based on channel statistical data or on channel state information (CSI) at transmitter. The noise patterns for each of the channel codes could be used to enhance decoding latency gains. Correlations and inter-dependencies between the noise patterns could be used as well. For example, look-up tables could be used to store jklmempirically observed error-patterns with highest likelihood occurrence. In this case, the GRAND algorithm or one of its variants, could start by decoding the received codeword using these jklmerror-patterns and the remaining^jno − jklm ) (where jnois the number of iterations until abandonment) patterns aregenerated according to the preferred schedule, excluding the intersection with the set of the already selected patterns are generated according to the preferred schedule, excluding the intersection with the set of the already selected jklmpatterns.

[0069] Figure 6 illustrates an example performance of polar codes at high SNR, in accordance with the present disclosure. The abandonment threshold or maximumnumber of noise guesses jnois function of the channel noise entropy and alphabet. The choice of jnois critical for allowing capacity-achieving decoding performance as well as low decoding latency. At high SNR, it can be seen in Figure 6 that the number of guesses jnoneeded for polar codes decoding using GRAND decoder is relatively low and the decoded bits could be determined in less decoding iterations. In a first implementation, the maximum number of noise guesses jnocould be determined along with noise patterns and tabulated within the same look-up tables. The corresponding jnovalue could then be signaled to the decoder and allows higher performance gains in terms of latency and BLER.

[0070] Figure 7 illustrates an example performance of LDPC codes 700, 710, in accordance with aspects of the present disclosure. When compared with state-of-art decoding schemes for legacy 5G NR channel codes, soft-detection ORBGRAND is shown to provide similar block error performance in the case of LDPC codes with low complexity compared with the SPA or BP algorithm, while providing better block error rate performance than CA-SCL, a state-of-the-art soft detection CA-Polar decoder. This is shown in Figure 7 for LDPC codes and in Figure 3 for polar codes. The universal GRAND algorithm only requires as input the parity check matrix of the code (LDPC or polar), the maximum number of queries (or allowed noise guesses), the demodulated received codeword and optionally the channel’s noise statistical information (in our case AWGN channel).

[0071] In a second embodiment, the area efficiency and hardware implementation of the decoder could be enhanced when using universal decoder GRAND for decoding both LDPC and polar codes. In legacy channel coding, decoders are designed to match the coding procedure for example for polar codes the reliability of the bit-channels and the identification of the frozen set are designed so that near-ML performance could be achieved when CA-SCL decoding is used. The BLER performance may be worse when another decoder is used to decode the polar sequence. This impacts the hardware implementation and area efficiency of the decoders, making hardware implementation more complex and less efficient.

[0072] GRAND and by extension its variants such as ORBGRAND algorithms are entirely parallelizable and suitable for implementation in circuits. It avails of a codebook independent quantization of soft information, the decreasing rank order of thereliability of each bit in a received block to map a fixed, pre-determined, series of putative noise queries to their appropriate locations in the received block. If the a posteriori bit flip probabilities match a member of a broad parametric class of models it provides ML decoding, and approximate-ML decoding otherwise. The best case are efficiency and chips are given for legacy decoders and compared with GRAND decoder in Table 2. Channel Code Area Efficiency Chips Area LDPC / SPA decoder19.1 Gps / ??^4.55 ??^Polar / SCL Decoder 3.17 Gps / ??^1.48 ??^LDPC / Polar GRAND 19.56 Gps / ??^4.05 ??^Decoding Table 2: Hardware implementation of different decoders

[0073] In one embodiment, the interleaving and de-interleaving hardware blocks could be removed from the hardware implementation. In this case, GRAND Markovian decoder, a variant of GRAND, could be used to decode the received polar and LDPC codewords without impacts on the decoding performance.

[0074] Figure 8 illustrates an example of a UE 800 in accordance with aspects of the present disclosure. The UE 800 may include a processor 802, a memory 804, a controller 806, and a transceiver 808. The processor 802, the memory 804, the controller 806, or the transceiver 808, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

[0075] The processor 802, the memory 804, the controller 806, or the transceiver 808, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

[0076] The UE 800 may be configured to support a means to receive a signal via a channel, demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or an LDPC codeword from an LDPC codebook, and decode the codeword according to a GRAND scheme.

[0077] In one embodiment, to decode the codeword, the UE 800 is configured to decode the codeword according to the GRAND scheme using a decoder of the device and based on a coding rate associated with the signal satisfying a coding rate threshold or a code block length associated with the signal satisfying a code block length threshold, wherein the decoder comprises a GRAND decoder.

[0078] In one embodiment, to decode the codeword, the UE 800 is configured to decode the codeword according to the GRAND scheme using a decoder of the device, wherein an input to the decoder of the device comprises a set of one or more parameters including one or more of the codeword, an indication of a parity-check matrix associated with the signal, or channel noise information associated with the channel, and wherein the decoder comprises a GRAND decoder.

[0079] In one embodiment, the UE 800 is configured to determine a block error rate of a decoder of the device to determine an efficiency of the decoder of the device as compared with other decoders, wherein the decoder comprises a GRAND decoder. In one embodiment, the UE 800 includes a decoder for decoding the codeword according to the GRAND scheme, wherein the decoder comprises a soft-input GRAND decoder, the soft-input GRAND decoder comprising an ordered reliability bit (ORBGRAND) decoder or a line-1 ORBGRAND decoder.

[0080] In one embodiment, the GRAND decoder satisfies a block error rate threshold for polar short codes or LDPC short codes with low redundancy and high code rate. In one embodiment, the UE 800 is configured to combine transmission chains of the polar codeword and the LDPC codeword using a decoder of the device that is configured to decode polar codewords and LDPC codewords. In one embodiment, the UE 800 is configured to disable one or more of an interleaving operation or deinterleaving operation in response to using a GRAND decoder for decoding the codeword.

[0081] The processor 802 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combinationthereof). In some implementations, the processor 802 may be configured to operate the memory 804. In some other implementations, the memory 804 may be integrated into the processor 802. The processor 802 may be configured to execute computer-readable instructions stored in the memory 804 to cause the UE 800 to perform various functions of the present disclosure.

[0082] The memory 804 may include volatile or non-volatile memory. The memory 804 may store computer-readable, computer-executable code including instructions when executed by the processor 802 cause the UE 800 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 804 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0083] In some implementations, the processor 802 and the memory 804 coupled with the processor 802 may be configured to cause the UE 800 to perform one or more of the functions described herein (e.g., executing, by the processor 802, instructions stored in the memory 804). For example, the processor 802 may support wireless communication at the UE 800 in accordance with examples as disclosed herein.

[0084] The controller 806 may manage input and output signals for the UE 800. The controller 806 may also manage peripherals not integrated into the UE 800. In some implementations, the controller 806 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 806 may be implemented as part of the processor 802.

[0085] In some implementations, the UE 800 may include at least one transceiver 808. In some other implementations, the UE 800 may have more than one transceiver 808. The transceiver 808 may represent a wireless transceiver. The transceiver 808 may include one or more receiver chains 810, one or more transmitter chains 812, or a combination thereof.

[0086] A receiver chain 810 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 810 may include one or more antennas for receiving the signal over the air or wirelessmedium. The receiver chain 810 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 810 may include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 810 may include at least one decoder for decoding and processing the demodulated signal to receive the transmitted data.

[0087] A transmitter chain 812 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 812 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 812 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 812 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

[0088] Figure 9 illustrates an example of a processor 900 in accordance with aspects of the present disclosure. The processor 900 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 900 may include a controller 902 configured to perform various operations in accordance with examples as described herein. The processor 900 may optionally include at least one memory 904, which may be, for example, an L1 / L2 / L3 cache. Additionally, or alternatively, the processor 900 may optionally include one or more arithmetic-logic units (ALUs) 906. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses).

[0089] The processor 900 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or morecaches (e.g., memory local to or included in the processor chipset (e.g., the processor 900) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others).

[0090] The controller 902 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 900 to cause the processor 900 to support various operations in accordance with examples as described herein. For example, the controller 902 may operate as a control unit of the processor 900, generating control signals that manage the operation of various components of the processor 900. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

[0091] The controller 902 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 904 and determine subsequent instruction(s) to be executed to cause the processor 900 to support various operations in accordance with examples as described herein. The controller 902 may be configured to track memory address of instructions associated with the memory 904. The controller 902 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 902 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 900 to cause the processor 900 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 902 may be configured to manage flow of data within the processor 900. The controller 902 may be configured to control transfer of data between registers, arithmetic logic units (ALUs), and other functional units of the processor 900.

[0092] The memory 904 may include one or more caches (e.g., memory local to or included in the processor 900 or other memory, such RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc. In some implementations, the memory 904 may reside within or on a processor chipset (e.g., local to the processor 900). In some otherimplementations, the memory 904 may reside external to the processor chipset (e.g., remote to the processor 900).

[0093] The memory 904 may store computer-readable, computer-executable code including instructions that, when executed by the processor 900, cause the processor 900 to perform various functions described herein. The code may be stored in a non- transitory computer-readable medium such as system memory or another type of memory. The controller 902 and / or the processor 900 may be configured to execute computer-readable instructions stored in the memory 904 to cause the processor 900 to perform various functions. For example, the processor 900 and / or the controller 902 may be coupled with or to the memory 904, the processor 900, the controller 902, and the memory 904 may be configured to perform various functions described herein. In some examples, the processor 900 may include multiple processors and the memory 904 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

[0094] The one or more ALUs 906 may be configured to support various operations in accordance with examples as described herein. In some implementations, the one or more ALUs 906 may reside within or on a processor chipset (e.g., the processor 900). In some other implementations, the one or more ALUs 906 may reside external to the processor chipset (e.g., the processor 900). One or more ALUs 906 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 906 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 906 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 906 may support logical operations such as AND, OR, exclusive-OR (XOR), not-OR (NOR), and not-AND (NAND), enabling the one or more ALUs 906 to handle conditional operations, comparisons, and bitwise operations.

[0095] The processor 900 may support wireless communication in accordance with examples as disclosed herein. In one embodiment, the processor 900 may be configured to or operable to support a means to receive a signal via a channel, demodulate thesignal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or an LDPC codeword from an LDPC codebook, and decode the codeword according to a GRAND scheme.

[0096] In one embodiment, to decode the codeword, the processor 900 is configured to decode the codeword according to the GRAND scheme using a decoder of the device and based on a coding rate associated with the signal satisfying a coding rate threshold or a code block length associated with the signal satisfying a code block length threshold, wherein the decoder comprises a GRAND decoder.

[0097] In one embodiment, to decode the codeword, the processor 900 is configured to decode the codeword according to the GRAND scheme using a decoder of the device, wherein an input to the decoder of the device comprises a set of one or more parameters including one or more of the codeword, an indication of a parity-check matrix associated with the signal, or channel noise information associated with the channel, and wherein the decoder comprises a GRAND decoder.

[0098] In one embodiment, the processor 900 is configured to determine a block error rate of a decoder of the device to determine an efficiency of the decoder of the device as compared with other decoders, wherein the decoder comprises a GRAND decoder. In one embodiment, the processor 900 includes a decoder for decoding the codeword according to the GRAND scheme, wherein the decoder comprises a soft-input GRAND decoder, the soft-input GRAND decoder comprising an ordered reliability bit (ORBGRAND) decoder or a line-1 ORBGRAND decoder.

[0099] In one embodiment, the GRAND decoder satisfies a block error rate threshold for polar short codes or LDPC short codes with low redundancy and high code rate. In one embodiment, the processor 900 is configured to combine transmission chains of the polar codeword and the LDPC codeword using a decoder of the device that is configured to decode polar codewords and LDPC codewords. In one embodiment, the processor 900 is configured to disable one or more of an interleaving operation or deinterleaving operation in response to using a GRAND decoder for decoding the codeword.

[0100] Figure 10 illustrates an example of a NE 1000 in accordance with aspects of the present disclosure. The NE 1000 may include a processor 1002, a memory 1004, a controller 1006, and a transceiver 1008. The processor 1002, the memory 1004, thecontroller 1006, or the transceiver 1008, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

[0101] The processor 1002, the memory 1004, the controller 1006, or the transceiver 1008, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

[0102] The NE 1000 may be configured to support a means to receive a signal via a channel, demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or an LDPC codeword from an LDPC codebook, and decode the codeword according to a GRAND scheme.

[0103] In one embodiment, to decode the codeword, the NE 1000 is configured to decode the codeword according to the GRAND scheme using a decoder of the device and based on a coding rate associated with the signal satisfying a coding rate threshold or a code block length associated with the signal satisfying a code block length threshold, wherein the decoder comprises a GRAND decoder.

[0104] In one embodiment, to decode the codeword, the NE 1000 is configured to decode the codeword according to the GRAND scheme using a decoder of the device, wherein an input to the decoder of the device comprises a set of one or more parameters including one or more of the codeword, an indication of a parity-check matrix associated with the signal, or channel noise information associated with the channel, and wherein the decoder comprises a GRAND decoder.

[0105] In one embodiment, the NE 1000 is configured to determine a block error rate of a decoder of the device to determine an efficiency of the decoder of the device as compared with other decoders, wherein the decoder comprises a GRAND decoder. In one embodiment, the NE 1000 includes a decoder for decoding the codeword according to the GRAND scheme, wherein the decoder comprises a soft-input GRAND decoder,the soft-input GRAND decoder comprising an ordered reliability bit (ORBGRAND) decoder or a line-1 ORBGRAND decoder.

[0106] In one embodiment, the GRAND decoder satisfies a block error rate threshold for polar short codes or LDPC short codes with low redundancy and high code rate. In one embodiment, the NE 1000 is configured to combine transmission chains of the polar codeword and the LDPC codeword using a decoder of the device that is configured to decode polar codewords and LDPC codewords. In one embodiment, the NE 1000 is configured to disable one or more of an interleaving operation or deinterleaving operation in response to using a GRAND decoder for decoding the codeword.

[0107] The processor 1002 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof). In some implementations, the processor 1002 may be configured to operate the memory 1004. In some other implementations, the memory 1004 may be integrated into the processor 1002. The processor 1002 may be configured to execute computer- readable instructions stored in the memory 1004 to cause the NE 1000 to perform various functions of the present disclosure.

[0108] The memory 1004 may include volatile or non-volatile memory. The memory 1004 may store computer-readable, computer-executable code including instructions when executed by the processor 1002 causes the NE 1000 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 1004 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0109] In some implementations, the processor 1002 and the memory 1004 coupled with the processor 1002 may be configured to cause the NE 1000 to perform one or more of the functions described herein (e.g., executing, by the processor 1002, instructions stored in the memory 1004). For example, the processor 1002 may supportwireless communication at the NE 1000 in accordance with examples as disclosed herein.

[0110] The controller 1006 may manage input and output signals for the NE 1000. The controller 1006 may also manage peripherals not integrated into the NE 1000. In some implementations, the controller 1006 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 1006 may be implemented as part of the processor 1002.

[0111] In some implementations, the NE 1000 may include at least one transceiver 1008. In some other implementations, the NE 1000 may have more than one transceiver 1008. The transceiver 1008 may represent a wireless transceiver. The transceiver 1008 may include one or more receiver chains 1010, one or more transmitter chains 1012, or a combination thereof.

[0112] A receiver chain 1010 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 1010 may include one or more antennas for receiving the signal over the air or wireless medium. The receiver chain 1010 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 1010 may include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 1010 may include at least one decoder for decoding and processing the demodulated signal to receive the transmitted data.

[0113] A transmitter chain 1012 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 1012 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 1012 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 1012 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

[0114] Figure 11 illustrates a flowchart of a method in accordance with aspects of the present disclosure. The operations of the method may be implemented by a UE or NE as described herein. In some implementations, the UE or NE may execute a set of instructions to control the function elements of the UE or NE to perform the described functions.

[0115] At 1102, the method may receive a signal via a channel. The operations of 1102 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1102 may be performed by a UE as described with reference to Figure 8 or the NE as described with reference to Figure 10.

[0116] At 1104, the method may demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or an LDPC codeword from an LDPC codebook. The operations of 1104 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1104 may be performed by a UE as described with reference to Figure 8 or the NE as described with reference to Figure 10.

[0117] At 1106, the method may decode the codeword according to GRAND scheme. The operations of 1106 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of 1106 may be performed by a UE as described with reference to Figure 8 or the NE as described with reference to Figure 10.

[0118] It should be noted that the method described herein describes a possible implementation, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible.

[0119] The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

CLAIMS What is claimed is:

1. A device for wireless communication, comprising: at least one memory; and at least one processor coupled with the at least one memory and configured to cause the device to: receive a signal via a channel; demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or a low-density parity check (LDPC) codeword from an LDPC codebook; and decode the codeword according to a guessing random additive noise decoding (GRAND) scheme.

2. The device of claim 1, wherein, to decode the codeword, the at least one processor is configured to cause the device to: decode the codeword according to the GRAND scheme using a decoder of the device and based on a coding rate associated with the signal satisfying a coding rate threshold or a code block length associated with the signal satisfying a code block length threshold, wherein the decoder comprises a GRAND decoder.

3. The device of claim 1, wherein, to decode the codeword, the at least one processor is configured to cause the device to: decode the codeword according to the GRAND scheme using a decoder of the device, wherein an input to the decoder of the device comprises a set of one or more parameters including one or more of the codeword, an indication of a parity-check matrix associated with the signal, or channel noise information associated with the channel, and wherein the decoder comprises a GRAND decoder.

4. The device of claim 1, wherein the at least one processor is configured to cause the device to determine a block error rate of a decoder of the device to determinean efficiency of the decoder of the device as compared with other decoders, wherein the decoder comprises a GRAND decoder.

5. The device of claim 1, further comprising: a decoder for decoding the codeword according to the GRAND scheme, wherein the decoder comprises a soft-input GRAND decoder, the soft-input GRAND decoder comprising an ordered reliability bit (ORBGRAND) decoder or a line-1 ORBGRAND decoder.

6. The device of claim 5, wherein the GRAND decoder satisfies a block error rate threshold for polar short codes or LDPC short codes with low redundancy and high code rate.

7. The device of claim 1, wherein the at least one processor is configured to cause the device to combine transmission chains of the polar codeword and the LDPC codeword using a decoder of the device that is configured to decode polar codewords and LDPC codewords.

8. The device of claim 1, wherein the at least one processor is configured to cause the device to disable one or more of an interleaving operation or deinterleaving operation in response to using a GRAND decoder for decoding the codeword.

9. The device of claim 1, wherein the device comprises a user equipment (UE), a base station, or a network entity.

10. A processor for wireless communication, comprising: at least one controller coupled with at least one memory and configured to cause the processor to: receive a signal via a channel; demodulate the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or a low-density parity check (LDPC) codeword from an LDPC codebook; and decode the codeword according to a guessing random additive noise decoding (GRAND) scheme.

11. The processor of claim 10, wherein, to decode the codeword, the at least one controller is configured to cause the processor to:decode the codeword according to the GRAND scheme using a decoder and based on a coding rate associated with the signal satisfying a coding rate threshold or a code block length associated with the signal satisfying a code block length threshold, wherein the decoder comprises a GRAND decoder.

12. The processor of claim 10, wherein, to decode the codeword, the at least one controller is configured to cause the processor to: decode the codeword according to the GRAND scheme using a decoder, wherein an input to the decoder comprises a set of one or more parameters including one or more of the codeword, an indication of a parity-check matrix associated with the signal, or channel noise information associated with the channel, and wherein the decoder comprises a GRAND decoder.

13. The processor of claim 10, wherein the at least one controller is configured to cause the processor to determine a block error rate of a decoder to determine an efficiency of the decoder as compared with other decoders, wherein the decoder comprises a GRAND decoder.

14. The processor of claim 13, further comprising: a decoder for decoding the codeword according to the GRAND scheme, wherein the decoder comprises a soft-input GRAND decoder, the soft-input GRAND decoder comprising an ordered reliability bit (ORBGRAND) decoder or a line-1 ORBGRAND decoder.

15. The processor of claim 10, wherein the GRAND decoder satisfies a block error rate threshold for polar short codes or LDPC short codes with low redundancy and high code rate.

16. The processor of claim 10, wherein the at least one controller is configured to cause the processor to combine transmission chains of the polar codeword and the LDPC codeword using a decoder that is configured to decode polar codewords and LDPC codewords.

17. The processor of claim 10, wherein the at least one controller is configured to cause the processor to disable one or more of an interleaving operation or deinterleaving operation in response to using a GRAND decoder for decoding the codeword.

18. The processor of claim 10, wherein the processor is in a user equipment (UE), a base station, or a network entity.

19. A method performed by a device, the method comprising: receiving a signal via a channel; demodulating the signal for a codeword, the codeword corresponding to a polar codeword from a polar codebook or a low-density parity check (LDPC) codeword from an LDPC codebook; and decoding the codeword according to a guessing random additive noise decoding (GRAND) scheme.

20. The method of claim 19, wherein the device comprises a user equipment (UE), a base station, or a network entity.

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