Method for manufacturing wiring board

Abstract

Provided is a method for manufacturing a wiring board, the method comprising: preparing an intermediate structure that has a base material having a main surface, an insulating resin layer, and a seed layer, the insulating resin layer forming a via hole that exposes the main surface of the base material; pre-treating the surface of the seed layer so that the contact angle of an electrolytic plating solution with respect to the surface is 40° or less; and forming, on the seed layer by electrolytic plating in the electrolytic plating solution, an electrolytic plating layer that includes a via portion for filling the via hole.

Description

Method for manufacturing a wiring board

[0001] The present disclosure relates to a method for manufacturing a wiring substrate.

[0002] A wiring board having multiple built-up wiring layers may be formed by a method such as a semi-additive process (SAP) or a modified semi-additive process (MSAP). In the manufacture of a wiring board, vias (filled vias) for electrical connection between upper and lower wiring layers are generally formed in via holes of an insulating resin layer (interlayer insulating layer) by electroplating (see, for example, Patent Document 1).

[0003] JP 2015-28973 A

[0004] When vias (filled vias) are formed in via holes in an insulating resin layer by electroplating, depressions may occur on the surface of the vias. Large depressions in the vias may prevent electrical continuity between wiring layers.

[0005] The present disclosure relates to suppressing recesses in via portions when manufacturing a wiring board, which includes forming an electrolytic plating layer including a via portion that fills a via hole.

[0006] The present disclosure includes the following: [1] A method for manufacturing a wiring substrate, comprising: preparing an intermediate structure having a substrate having a main surface, an insulating resin layer, and a seed layer, the insulating resin layer being provided on the substrate in contact with the main surface, the insulating resin layer forming a via hole through which the main surface is exposed, and the seed layer having a portion of the main surface of the substrate exposed in the via hole and a portion of the surface of the insulating resin layer that is continuously formed so as to cover the portion that forms the via hole; pretreating the surface of the seed layer so that a contact angle of an electrolytic plating solution with the surface is 40° or less; and forming an electrolytic plated layer on the seed layer by electroplating in the electrolytic plating solution, the electrolytic plated layer including a via portion that fills the via hole. [2] The method described in [1], wherein the surface of the seed layer is pretreated with plasma so that the contact angle of an electrolytic plating solution with the surface is 40° or less. [3] The method according to [1] or [2], wherein the intermediate structure further comprises a resist layer provided on a surface of the insulating resin layer opposite the substrate, the resist layer having a pattern including openings through which the via holes are exposed. [4] The method according to [3], wherein the surface of the seed layer is pretreated, and the surface of the resist layer is pretreated so that the contact angle of the electrolytic plating solution with the surface is 50° or less. [5] The method according to any of [1] to [4], wherein the maximum width of the via holes is 30 to 60 μm. [6] The method according to any of [1] to [5], wherein a filling rate calculated by the following formula: Filling rate [%] = (h2 / h1) × 100, where h1 is the maximum height of the electrolytic plating layer from the substrate and h2 is the minimum height of the via portion from the substrate, is 90% or more. [7] The method according to any of [1] to [6], wherein the substrate is a wiring structure including a core substrate and an insulating resin layer and a wiring layer provided on the core substrate.

[0007] In the case of manufacturing a wiring board, which includes forming an electrolytic plating layer including a via portion that fills a via hole, depressions in the via portion are suppressed.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.It is to be understood that the following detailed description is exemplary and explanatory and is not restrictive of the invention.

[0009] The present disclosure is not limited to the following examples.

[0010] 1 and 2 are process diagrams illustrating an example of a method for manufacturing a wiring board according to the present disclosure. In this method, as shown in FIG. 1( a), an intermediate structure 10 including a substrate 1 having a main surface 1S, an insulating resin layer 2, and a seed layer 3 is prepared.

[0011] The insulating resin layer 2 is provided on the substrate 1 so as to contact the main surface 1S. The insulating resin layer 2 forms a via hole 5 through which the main surface 1S is exposed. The seed layer 3 has a portion of the main surface 1S of the substrate 1 exposed in the via hole 5, a portion of the surface of the insulating resin layer 2 that forms the via hole 5 (the wall surface of the via hole 5), and a portion of the surface of the insulating resin layer 2 that is formed continuously so as to cover the surface opposite the substrate 1. In other words, the seed layer 3 is provided continuously so as to cover the entire surface of the laminated structure including the substrate 1 and the insulating resin layer 2 on the insulating resin layer 2 side.

[0012] The substrate 1 may be, for example, a structure including a core substrate that constitutes a wiring board, or may be a wiring structure including a core substrate and an insulating resin layer and a wiring layer provided below (on the core substrate side of) the insulating resin layer 2. The core substrate may be a laminate formed from a plurality of prepregs for printed wiring boards. A plurality of lower insulating resin layers may be provided on the core substrate side of the insulating resin layer 2. A wiring layer may be provided between adjacent insulating resin layers.

[0013] The insulating resin layer 2 can be formed, for example, from a typical build-up film used for manufacturing wiring boards. The via holes 5 can be formed by a typical method such as laser processing or photolithography. The thickness of the insulating resin layer 2 can be, for example, 10 μm or more and 30 μm or less.

[0014] The seed layer 3 may be, for example, a metal plating layer formed by electroless plating, a metal foil such as copper foil, a layer formed by vapor deposition such as sputtering, or a metal sintered layer. The metal sintered layer is a layer formed by heating a coating film containing metal particles to sinter the metal particles. The seed layer 3 may contain, for example, at least one metal selected from the group consisting of copper, gold, silver, tungsten, molybdenum, tin, cobalt, chromium, iron, and zinc. The seed layer 3 may be a single layer or may be composed of two or more layers. The thickness of the seed layer 3 may be, for example, 0.1 to 2.0 μm.

[0015] 1(b), a resist layer 4 may be provided on the surface of the seed layer 3 opposite to the substrate 1, outside the via hole 5. The resist layer 4 has a pattern including an opening 4a through which the via hole 5 is exposed. The pattern of the resist layer 4 may further include an opening 4b for forming a wiring layer. The opening 4b is arranged at a position where the portion of the seed layer 3 covering the surface of the insulating resin layer 2 opposite to the substrate 1 is exposed. The thickness of the resist layer 4 may be, for example, 10 to 50 μm.

[0016] The resist layer 4 can be formed of a photosensitive resist material that is commonly used to form wiring. The resist material for forming the resist layer 4 may be selected so that the contact angle of the resist layer 4 with the electrolytic plating solution described below falls within a predetermined range.

[0017] The resist layer 4 having a pattern including openings 4a can be formed by a method including providing a photosensitive layer on the seed layer 3, exposing portions of the photosensitive layer, and developing the exposed photosensitive layer. The exposure and development can be performed by conventional methods known to those skilled in the art. For example, exposure through a photomask forms a fine pattern including openings that expose the metal layer. The developer for development may be an alkaline aqueous solution such as an aqueous sodium carbonate solution. To form the photosensitive layer, a photosensitive resist film may be laminated on the seed layer 3, or a resist material containing a solvent may be applied to the seed layer 3 and the solvent may be removed from the coating.

[0018] The photosensitive layer for forming the resist layer 4 is formed from a conventional resist material. The resist material may be, for example, a photosensitive resin composition containing a binder polymer, a photopolymerizable compound having an ethylenically unsaturated bond, and a photopolymerization initiator.

[0019] The binder polymer may be, for example, a copolymer containing benzyl (meth)acrylate or a derivative thereof, styrene or a styrene derivative, a (meth)acrylic acid alkyl ester, and (meth)acrylic acid as monomer units.

[0020] Examples of the benzyl (meth)acrylate derivative that constitutes the binder polymer include 4-methylbenzyl (meth)acrylate, 4-ethylbenzyl (meth)acrylate, 4-tert-butylbenzyl (meth)acrylate, 4-methoxybenzyl (meth)acrylate, 4-ethoxybenzyl (meth)acrylate, 4-hydroxybenzyl (meth)acrylate, and 4-chlorobenzyl (meth)acrylate.

[0021] Examples of the styrene derivative that constitutes the binder polymer include vinyltoluene, p-methylstyrene, and p-chlorostyrene.

[0022] The (meth)acrylic acid alkyl ester constituting the binder polymer may be an ester compound formed from (meth)acrylic acid and a linear or branched aliphatic alcohol having 1 to 12 carbon atoms. The aliphatic alcohol may have 1 to 8 or 1 to 4 carbon atoms. Examples of the (meth)acrylic acid alkyl ester include methyl (meth)acrylate, ethyl (meth)acrylate, propyl (meth)acrylate, isopropyl (meth)acrylate, butyl (meth)acrylate, tert-butyl (meth)acrylate, pentyl (meth)acrylate, hexyl (meth)acrylate, heptyl (meth)acrylate, octyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate.

[0023] The weight average molecular weight (Mw) of the binder polymer may be 20,000 to 150,000, 30,000 to 100,000, 40,000 to 80,000, or 40,000 to 60,000. The weight average molecular weight here refers to a value calculated in terms of standard polystyrene determined by gel permeation chromatography (GPC).

[0024] The photopolymerizable compound having an ethylenically unsaturated bond may be, for example, one or more compounds selected from a bisphenol A (meth)acrylate compound, a hydrogenated bisphenol A (meth)acrylate compound, a polyalkylene glycol (meth)acrylate, a urethane monomer, pentaerythritol (meth)acrylate, and trimethylolpropane (meth)acrylate.

[0025] Examples of photopolymerization initiators include benzophenone, N,N,N',N'-tetramethyl-4,4'-diaminobenzophenone (Michler's ketone), N,N,N',N'-tetraethyl-4,4'-diaminobenzophenone, 4-methoxy-4'-dimethylaminobenzophenone, 2-benzyl-2-dimethylamino-1-(4-morpholinophenyl)-butanone-1, and 2-methyl-1-[4-(methylthio)phenyl]-2-morpholino-propanone-1. aromatic ketones such as 2-ethylanthraquinone, phenanthrenequinone, 2-tert-butylanthraquinone, octamethylanthraquinone, 1,2-benzanthraquinone, 2,3-benzanthraquinone, 2-phenylanthraquinone, 2,3-diphenylanthraquinone, 1-chloroanthraquinone, 2-methylanthraquinone, 1,4-naphthoquinone, 9,10-phenanthraquinone, 2-methyl-1,4-naphthoquinone, and 2,3-dimethylanthraquinone. benzoin ether compounds such as benzoin methyl ether, benzoin ethyl ether, and benzoin phenyl ether; benzoin compounds such as benzoin, methylbenzoin, and ethylbenzoin; benzyl derivatives such as benzil dimethyl ketal; 2,4,5-triarylimidazole dimers such as 2-(o-chlorophenyl)-4,5-diphenylimidazole dimer, 2-(o-chlorophenyl)-4,5-di(methoxyphenyl)imidazole dimer, 2-(o-fluorophenyl)-4,5-diphenylimidazole dimer, 2-(o-methoxyphenyl)-4,5-diphenylimidazole dimer, and 2-(p-methoxyphenyl)-4,5-diphenylimidazole dimer; acridine derivatives such as 9-phenylacridine and 1,7-bis(9,9′-acridinyl)heptane; N-phenylglycine; N-phenylglycine derivatives; and coumarin compounds. These may be used alone or in combination of two or more.

[0026] The content of the binder polymer in the photosensitive resin composition may be 40 to 80 parts by mass, 45 to 75 parts by mass, or 50 to 70 parts by mass, relative to 100 parts by mass of the total amount of the binder polymer and the photopolymerizable compound. The content of the photopolymerization initiator in the photosensitive resin composition may be 0.01 to 5 parts by mass, 0.1 to 4.5 parts by mass, or 1 to 4 parts by mass, relative to 100 parts by mass of the total amount of the binder polymer and the photopolymerizable compound.

[0027] The photosensitive resin composition may contain other components as needed. Examples of other components include a photopolymerizable compound having a cationically polymerizable cyclic ether group, a cationic polymerization initiator, a sensitizer, a dye such as malachite green, a photocoloring agent such as tribromomethylphenyl sulfone or leucocrystal violet, a thermal color-developing inhibitor, a plasticizer such as p-toluenesulfonamide, a pigment, a filler, an antifoaming agent, a flame retardant, a stabilizer, an adhesion promoter, a leveling agent, a release accelerator, an antioxidant, a fragrance, an imaging agent, and a thermal crosslinking agent. The content of each of the other components may be about 0.01 to 20 parts by mass per 100 parts by mass of the combined amount of the binder polymer and the photopolymerizable compound.

[0028] After the intermediate structure 10 is prepared, the surface 3S of the seed layer 3 opposite the substrate 1 is pretreated so that the contact angle of an electrolytic plating solution with respect to the surface 3S is 40° or less. The electrolytic plating solution used here is used to form an electrolytic plating layer on the seed layer 3. Following the pretreatment of the surface 3S, as shown in FIG. 2( a), an electrolytic plating layer 6 including a via portion 6A (filled via) that fills the via hole 5 is formed on the seed layer 3 by electroplating in the electrolytic plating solution. The via portion 6A is formed within the opening 4a of the resist layer 4. The electrolytic plating layer 6 may further include a wiring layer 6B that is a portion formed within the opening 4b. The electrolytic plating layer 6 may be an electrolytic copper plating layer.

[0029] The contact angle of the electrolytic plating solution with respect to the surface 3S of the seed layer 3 after pretreatment being 40° or less means that the electrolytic plating solution has high wettability with respect to the surface of the seed layer 3. According to the findings of the present inventors, high wettability of the electrolytic plating solution with respect to the surface of the seed layer 3 contributes to suppressing the occurrence of depressions in the via portion 6A to be formed. If the wettability of the electrolytic plating solution with respect to the surface of the seed layer 3 is low, it takes a relatively long time for the voids in the via hole 5 to be completely removed during electroplating, which may delay the start of plating growth in the via hole 5. If the plating growth in the via hole 5 is delayed, a large depression in the via portion 6A may occur. It is believed that high wettability of the electrolytic plating solution with respect to the surface of the seed layer 3 makes it less likely that plating growth will be delayed in the via hole 5, which contributes to suppressing depressions. From a similar viewpoint, the contact angle of the electroplating solution on the surface 3S after pretreatment may be 35° or less, 30° or less, 25° or less, 20° or less, 15° or less, 10° or less, 6° or less, 5° or less, 4° or less, 3° or less, or 2° or less. This contact angle may be 0° or more, or 1° or more.

[0030] In the present disclosure, the contact angle of the electrolytic plating solution with respect to the surface of the seed layer is measured by the sessile drop method at 25° C. and refers to the angle formed by a 1 μL droplet of the electrolytic plating solution with the surface of the seed layer 1 second after it lands on the surface of the seed layer. The contact angle of the electrolytic plating solution with respect to the surface of the resist layer is defined similarly.

[0031] The method for pretreating the surface 3S of the seed layer 3 may include treatment by irradiating the surface 3S with plasma 15 as schematically shown in FIG. 1C. The plasma 15 may be, for example, oxygen plasma. The irradiation conditions, such as the time for irradiating the surface 3S with the plasma 15, are adjusted so that the contact angle of the electrolytic plating solution with respect to the surface 3S is 40° or less or in another desired range. For example, the irradiation time for the plasma 15 may be 30 seconds to 3 minutes.

[0032] FIG. 3 is a cross-sectional view showing an example of a portion near a via portion. A via hole 5 is filled with a via portion 6A, which is a part of the electroplated layer 6, and a part of the seed layer 3. A recess 8 may form on the surface of the via portion 6A opposite the seed layer 3 above the via hole 5. When the maximum height of the electroplated layer 6 from the substrate 1 is h1 and the minimum height of the via portion 6A from the substrate 1 is h2, a high filling rate calculated using the following formula: Filling rate [%] = (h2 / h1) × 100 indicates a small recess in the electroplated layer 6. This filling rate may be 90% or more or 100% or less. In the example of FIG. 3, the width of the via hole 5 increases with increasing distance from the substrate 1, reaching a maximum width w at the position farthest from the substrate 1. The maximum width w of the via hole 5 may be 30 to 60 μm. If the width of the via hole 5 is large, a large depression 8 is likely to form, but by pretreating the surface of the seed layer 3 before electroplating as in the method disclosed herein, the depression 8 in the via portion 6A can be effectively suppressed.

[0033] While the surface 3S of the seed layer 3 is pretreated, the surface of the resist layer 4 may also be pretreated so that the contact angle of the electrolytic plating solution with respect to that surface is 50° or less. For example, for the pretreatment, the surface 3S of the seed layer 3 and the surface of the resist layer 4 may be irradiated with plasma. The pretreatment of the surface of the resist layer 4 may also contribute to suppressing depressions in the via portion 6A. The contact angle of the electrolytic plating solution with respect to the surface 3S after pretreatment may be 0° or more, 1° or more, 10° or more, 20° or more, 30° or more, or 40° or more.

[0034] The electrolytic plating solution may be a conventional plating solution used to form a metal layer by electrolytic plating, or may be an aqueous solution containing a copper-containing compound (e.g., copper sulfate).

[0035] After the electrolytic plating layer 6 is formed, the resist layer 4 is removed as shown in Fig. 2(b) . Removal of the resist layer 4 exposes a portion of the seed layer 3 in the opening of the electrolytic plating layer 6. Next, as shown in Fig. 2(c) , the portion of the seed layer 3 that is not covered by the electrolytic plating layer 6 is removed by etching.

[0036] The wiring board 20 manufactured by the above steps has a base material 1, an insulating resin layer 2, and an electrolytic plated layer 6 (including via portions 6A and wiring layers 6B). A multilayer wiring board can also be manufactured by further forming an insulating resin layer, via portions, wiring layers, etc. on the electrolytic plated layer 6. In a multilayer wiring board, the via portions ensure electrical continuity between the wiring layers.

[0037] The present invention is not limited to the following examples. 1. Materials (1) Copper-clad laminate (substrate): A copper-clad laminate for printed wiring boards having a size of 50 mm x 50 mm and a thickness of 0.45 mm (manufactured by Resonac Co., Ltd.) (2) Interlayer insulating material: An interlayer insulating material having a support film, a curable resin film provided on the support film, and a protective film (Ajinomoto Build-up Film GX-92, manufactured by Ajinomoto Fine-Techno Co., Ltd.) (3) Resist film: A photosensitive film for forming a package substrate circuit having a photosensitive layer and a support film (dry film resist manufactured by Resonac Co., Ltd.)

[0038] 2. Formation of an insulating resin layer on a wiring board The protective film was peeled off from the interlayer insulating material, and the exposed curable resin film was placed on a copper-clad laminate. The placed curable resin film was pressed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho) to be pressure-bonded to the copper-clad laminate. The pressing conditions were a press hot plate temperature of 80°C, a vacuum time of 20 seconds, a pressing time of 60 seconds, an atmospheric pressure of 4 kPa or less, and a pressure of 0.4 MPa. The curable resin film was then cured in an oven by heating at 180°C for 30 minutes and then at 190°C for 60 minutes, forming an insulating resin layer on the copper foil of the copper-clad laminate. CO was applied to the insulating resin layer. ２ By irradiating the support film with a laser, via holes having a diameter of 30 to 60 μm were formed, which penetrated the insulating resin layer and exposed the copper foil of the copper-clad laminate.

[0039] Next, after removing the support film, the laminate including the insulating resin layer and the copper-clad laminate was immersed in the following order: a mixed aqueous solution of 500 mL / L of wetting solution (Swelling Securigant, manufactured by Atotech) and 3 g / L of NaOH at 80°C for 15 minutes, pure water at room temperature for 2 minutes, a mixed aqueous solution of 640 mL / L of desmear solution (Compact CP, manufactured by Atotech) and 40 g / L of NaOH at 80°C for 20 minutes, pure water at 50°C for 2 minutes, a mixed aqueous solution of 100 mL / L of acidic solution (Reduction Securigant, manufactured by Atotech) and 50 mL / L of 98% sulfuric acid at 40°C for 5 minutes, and pure water at room temperature for 1 minute. The surface of the insulating resin layer was roughened by immersion in the desmear solution.

[0040] Formation of seed layer The laminate consisting of the roughened insulating resin layer and the copper-clad laminate was immersed in a 50 mL / L aqueous solution of an acid pretreatment reagent for electroless plating (manufactured by Uemura, trade name: MCD-PL) at 40 ° C. for 5 minutes, in pure water at 40 ° C. for 1 minute, in pure water at room temperature for 1 minute, in a 10% aqueous sulfuric acid solution at room temperature for 1 minute, in pure water at room temperature for 1 minute, in a mixed aqueous solution of a pre-dip reagent (manufactured by Uemura, trade name: MDP-2) and sulfuric acid (MDP-2 concentration: 10 mL / L, 95% sulfuric acid: 1 mL / L) at room temperature for 2 minutes, in a mixed solution of an activator reagent (manufactured by Uemura, trade name: MAT-SP) and NaOH (MAT-SP concentration: 50 mL / L, NaOH: 1.6 g / L) at 40 ° C. for 5 minutes, in pure water at room temperature for 1 minute, and in a reducer reagent (manufactured by Uemura, trade name: MRD-2-C, MAB-4-C, MAB-4-A) for 1 minute. ) (MRD-2-C concentration: 10 mL / L, MAB-4-C concentration: 50 mL / L, MAB-4-A concentration: 10 mL / L) at 35°C for 3 minutes, purified water for 1 minute, accelerator reagent (manufactured by Uemura, trade name: MEL-3A) 50 mL / L aqueous solution for 1 minute at room temperature, electroless plating reagent (manufactured by Uemura, trade name: PEA-6A, PEA-6-B-2X, PEA-6- The substrate was immersed in a mixed solution of PEA-6A (PEA-6A concentration: 100 mL / L, PEA-6-B-2X concentration: 50 mL / L, PEA-6-C concentration: 14 mL / L, PEA-6-D concentration: 15 mL / L, PEA-6-E concentration: 50 mL / L, formaldehyde concentration: 5 mL / L) at 36 ° C. for 15 minutes, and then in pure water for 1 minute. By electroless plating including these immersion treatments, a copper plating layer continuously covering the surface of the insulating resin layer and the copper foil exposed in the via hole was formed as a seed layer. The formed seed layer was annealed by heating in an oven at 150 ° C. for 30 minutes.

[0041] Formation of Resist Layer The photosensitive layer and support film of the resist film were laminated onto the seed layer using a laminator (GK-13DX, manufactured by Lamy Corporation) at a temperature of 110°C, a speed of 1.4 m / min, and a pressure of 0.5 MPa, with the photosensitive layer facing the seed layer. The laminated resist film was left for 30 minutes. The resist film was then exposed using a stepper (S6Ck, manufactured by Therma Precision Co., Ltd.) and a photomask. The exposure dose was 130 mJ / cm. ２ The resist film after exposure was left for 30 minutes. The support film was peeled off, and a resist layer having a pattern including openings exposing via holes was formed by development using a 1.0% aqueous sodium carbonate solution. Development was performed using an ultra-high pressure spin developer (manufactured by Blue Ocean Technology) by spraying the developer for 100 seconds, followed by pure water as a rinse for 110 seconds. The development temperature was 30°C, the rotation speed was 500 rpm, the spray pressure was 0.18 MPa, the spray nozzle head travel distance was 7.2 cm, and the spray nozzle head travel speed was 10 cm / s.

[0042] Pretreatment The surface of the resist layer and the portion of the surface of the seed layer that was not covered with the resist layer were treated with plasma using a plasma asher (March, AP-1000) under the following conditions: RD output 500 W, base pressure 150 mTorr, process pressure 200 mTorr, pressure range 200 mTorr, oxygen flow rate 100 sccm, and irradiation time 1 minute.

[0043] Contact Angle of Electrolytic Plating Solution The contact angle immediately after 1 mL of electrolytic plating solution was dropped onto the seed layer and resist layer after plasma pretreatment was measured using a contact angle meter (DMo-501, manufactured by Kyowa Interface Science Co., Ltd.).

[0044] The electrolytic plating solution was a mixed solution containing a mixed aqueous solution containing 60 g / L of copper sulfate pentahydrate, 60 g / L of 96% sulfuric acid, and 50 mg / L of hydrochloric acid, and an electrolytic plating additive.

[0045] Electrolytic plating: The pretreated laminate was immersed in the same electrolytic plating solution as that used in the contact angle measurement, at 25°C and a current density of 4.5 A / dm2 An electrolytic copper plating layer was formed on the seed layer for 40 minutes under the conditions of 1. Electrolytic plating yielded a wiring substrate of the example having a copper-clad laminate, a seed layer, an electrolytic plating layer including vias for filling the via holes, and a resist layer. After electrolytic plating, the wiring substrate was immersed in pure water at room temperature for 1 minute.

[0046] For comparison, a laminate was prepared in the same manner as above, except that the surfaces of the seed layer and resist layer were not pretreated with plasma. An electrolytic copper plating layer was formed on the seed layer of the laminate by electrolytic plating in the same manner as above, thereby obtaining a wiring board for the comparative example.

[0047] 3. Evaluation In the wiring board, the height of the electrolytic copper plating layer from the copper-clad laminate (substrate) was measured using a film thickness measuring device (DektakXT-S, manufactured by Bruker). The filling rate of the via part was calculated using the following formula: h1 is the maximum height of the electrolytic copper plating layer from the copper-clad laminate, and h2 is the minimum height of the via part from the copper-clad laminate. Filling rate [%] = (h2 / h1) × 100

[0048] The evaluation results are shown in Table 1. The contact angle of the electrolytic plating solution with respect to the surface of the seed layer changed from 65° to 2°. The contact angle of the electrolytic plating solution with respect to the surface of the resist layer changed from 63° to 45°. In the case of the examples, the filling rate was 90% or more, and it was confirmed that the depressions in the via portions of the electrolytic plating layer were small.

[0049]

[0050] 1...substrate, 1S...main surface of substrate, 2...insulating resin layer, 3...seed layer, 3S...surface of seed layer, 4...resist layer, 4a, 4b...opening, 5...via hole, 6...electroplated layer, 6A...via portion (filled via), 6B...wiring layer, 10...intermediate structure, 15...plasma, 20...wiring board, w...maximum width of via hole

Claims

1. A method for manufacturing a wiring board, comprising: preparing an intermediate structure having a base material with a main surface, an insulating resin layer, and a seed layer, wherein the insulating resin layer is provided on the base material so as to be in contact with the main surface, the insulating resin layer forms via holes through which the main surface is exposed, and the seed layer has a portion that continuously covers a portion of the main surface of the base material exposed within the via holes and a portion of the surface of the insulating resin layer where the via holes are formed; pretreating the surface of the seed layer so that the contact angle of an electrolytic plating solution with respect to the surface is 40° or less; and forming an electrolytic plating layer including via portions that fill the via holes by electrolytic plating in the electrolytic plating solution on the seed layer.

2. The method according to claim 1, wherein the surface of the seed layer is pretreated by plasma so that the contact angle of the electrolytic plating solution with respect to the surface is 40° or less.

3. The method according to claim 1, wherein the intermediate structure further has a resist layer provided on a surface of the insulating resin layer opposite to the base material, and the resist layer has a pattern including an opening through which the via holes are exposed.

4. The method according to claim 3, wherein the surface of the seed layer is pretreated, and the surface of the resist layer is pretreated so that the contact angle of the electrolytic plating solution with respect to the surface is 50° or less.

5. The method according to claim 1, wherein the maximum width of the via holes is 30 to 60 μm.

6. The method according to claim 1, wherein when the maximum value of the height of the electrolytic plating layer from the base material is h1 and the minimum value of the height of the via portions from the base material is h2, the filling rate calculated by the following formula: filling rate [%] = (h2 / h1) × 100 is 90% or more.

7. The method according to claim 1, wherein the base material is a wiring structure including a core substrate, an insulating resin layer provided on the core substrate, and a wiring layer.

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