Storage device, information processing system, and information processing method

Abstract

In this information processing system provided with a storage device and a processing device, the storage device is provided with: a storage unit that stores a data structure for holding data in a randomized physical address; a conversion unit that converts a key value for data search into the physical address in the data structure; and a transfer unit that transfers the data read from the storage unit to the processing device.

Description

Storage device, information processing system, and information processing method

[0001] The present invention relates to a countermeasure against side channel attacks that applies Oblivious RAM (hereinafter referred to as ORAM).

[0002] In a typical conventional computer model, the CPU is responsible for controlling all program instructions. In contrast, a technology called the Memory Centric Model is being studied, in which memory is the main driver of program instruction control, without the intervention of the CPU. While this technology is expected to significantly improve computational speed compared to conventional computer models, it also has the drawback of enabling effective side-channel attacks by externally observing the timing of memory reads and writes and the positions of cells.

[0003] As a countermeasure against side channel attacks, ORAM, which conceals access patterns, is known (for example, Non-Patent Documents 1 and 2).

[0004] Oded Goldreich and Rafail Ostrovsky. Software protection and simulation on oblivious rams. J. ACM, Vol. 43, No. 3, pp. 431-473, 1996.Emil Stefanov, Marten van Dijk, Elaine Shi, Christopher Fletcher, Ling Ren,XiangyaoYu, and Srinivas Devadas. Path oram: An extremely simple oblivious ram protocol. In CCS, pp. 299-310, 2013.

[0005] As described above, side channel attacks are effective in the Memory Centric Model, and ORAM exists as a technology for countering side channel attacks.

[0006] However, ORAM is a technology based on a CPU-centric computer model, and it is difficult to simply apply it to a memory-centric model.

[0007] The present invention has been made in view of the above points, and has an object to provide a technique for applying ORAM to a Memory Centric Model.

[0008] According to the disclosed technology, there is provided a storage device in an information processing system comprising a storage device and a processing device, the storage device comprising: a storage unit that stores a data structure that holds data at randomized physical addresses; a conversion unit that converts a key value for data search into the physical address in the data structure; and a transfer unit that transfers the data read from the storage unit to the processing device.

[0009] According to the disclosed technology, it becomes possible to apply ORAM to the Memory Centric Model.

[0010] 1 is a diagram illustrating a terminal configuration comprising a CPU, a GPU, and a memory. FIG. 2 is a diagram illustrating a terminal configuration hash-based ORAM comprising a CPU, a GPU, and a memory. FIG. 3 is a diagram illustrating a tree-based ORAM. FIG. 4 is a diagram illustrating an example of the configuration of an information processing system. FIG. 5 is a diagram illustrating an example of the configuration of a memory 100 in a first embodiment. FIG. 6 is a flowchart illustrating the operation in the first embodiment. FIG. 7 is a diagram illustrating an example of the configuration of a memory 100 in a second embodiment. FIG. 8 is a flowchart illustrating the operation in the second embodiment. FIG. 9 is a diagram illustrating an example of the configuration of a memory 100 in a third embodiment. FIG. 10 is a flowchart illustrating the operation in the third embodiment. FIG. 11 is a diagram illustrating an example of the functional configuration of a storage device 100. FIG. 12 is a diagram illustrating an example of the hardware configuration of a device.

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is merely an example, and the embodiment to which the present invention is applied is not limited to the following embodiment.

[0012] In this embodiment, ORAM is used as a method for randomizing access patterns to data, but the technology according to the present invention can also be applied to methods for randomizing access patterns to data other than ORAM.

[0013] In the following, first, the conventional technology and its problems will be described in more detail, and then the technology according to this embodiment will be described using Examples 1 to 3.

[0014] (Regarding the Prior Art) A computational model (or architecture) known as the Memory Centric Model is disclosed, for example, in "Anteneh Gebregiorgis, Hoang Anh Du Nguyen, Jintao Yu, Rajendra Bishnoi, Mottaqiallah Taouil, Francky Catthoor, and Said Hamdioui. A survey on memory-centric computer architectures. Vol. 18, No. 4, 2022."

[0015] The Memory Centric Model differs from conventional computer architectures in which all processing and information transmission is controlled by the CPU. Instead, memory is at the center of processing, reducing the time required for data transfer and reducing the load on the CPU, thereby improving calculation speed.

[0016] For example, in a terminal configuration consisting of a CPU, a GPU, and a memory as shown in Figure 1, in a conventional CPU-centric architecture, even when executing a calculation using the GPU, the CPU first obtains a program instruction related to data transfer from the memory (S1 in Figure 1), and then performs processing to transfer the data in the memory to the GPU based on this instruction (S2). In this way, in a conventional CPU-centric architecture, the CPU is responsible for controlling all program instructions.

[0017] In contrast, in the Memory Centric Model, memory is the main controller of these transfer commands. For example, as shown in Figure 2, program commands that use the GPU are sent directly to the GPU without going through the CPU, thereby reducing the CPU load. While this technology is expected to significantly improve computational speed compared to conventional computers, it also raises concerns that side-channel attacks, which involve externally observing the timing of memory reads and writes and the location of cells, could be effectively used to steal data from within the computer. For example, as disclosed in "ZiyuWang, Fan Hsuan Meng, Yongmo Park, Jason K. Eshraghian, and Wei D. Lu. Side-channel attack analysis on in-memory computing architectures. IEEE Transactions on Emerging Topics in Computing, pp. 1-13, 2023," a side-channel attack that can extract machine learning models is known in the Memory Centric Model.

[0018] On the other hand, ORAM is an algorithm that allows a client, who is the owner of data, to safely access a server that is the recipient of the data, and is realized by the methods shown in Non-Patent Documents 1 and 2, for example.

[0019] One of the applications of ORAM is to counter side-channel attacks by concealing access patterns, which stems from the fact that ORAM is a secure computing technology that safely simulates a computational model called a RAM (Random Access Machine) and allows RAM program execution between a client and a server.

[0020] RAM is a computer model that can be said to be the basis of the CPU-centric architecture mentioned above, in which the CPU that executes instructions (programs) accesses the memory that stores the instructions as appropriate to read and write data and execute instructions.

[0021] ORAM replaces the CPU with the client (the data owner / program executor) and the memory with the server (the data recipient), and uses an algorithm that conceals access patterns to make the data read / write locations appear random to an attacker (server), while still ensuring that the client can correctly load the desired data. This property of concealing access patterns can be used not only in client-server bilateral protocols, but also in data transfers between the CPU and memory on a single computer, making it a countermeasure against side-channel attacks.

[0022] (Regarding the Issues) As described above, it is known that side channel attacks are effective in the Memory Centric Model, and that ORAM can be used as a countermeasure against side channel attacks on memory.

[0023] However, ORAM is a technology based on RAM (i.e., a CPU-centric model), and it is difficult to simply apply it to a memory-centric model.

[0024] Specifically, in the Memory Centric Model, memory is equipped with circuits that independently execute some processing (such as transfer control) (hence the term In-Memory Computing), and the advantage of the Memory Centric Model is that it effectively utilizes the circuits within this memory. In other words, the Memory Centric Model is a computational model that is fundamentally different from the conventional RAM model, in which memory is simply a data pool and the CPU is responsible for all processing. Therefore, there is the issue that it is difficult to apply conventional ORAM, which is based on the conventional RAM model, to the Memory Centric Model.

[0025] (Outline of the embodiment) In order to solve the above problem, in this embodiment, a new system (framework) is described in which the part of the ORAM algorithm that corresponds to the framework that spans many methods is modified for the Memory Centric Model, and data can be transferred from memory to any instruction processing circuit while keeping the access pattern randomized.

[0026] In this embodiment, the process that spans most of the existing ORAM implementation methods will be considered as the ORAM framework and will be described. Existing ORAM frameworks are broadly divided into two types: hash-based ORAM and tree-based ORAM. First, hash-based ORAM and tree-based ORAM will be described below.

[0027] (Hash-based ORAM) In hash-based ORAM (e.g., Non-Patent Document 1), the location of each piece of data is concealed using a hash table. Specifically, as shown in FIG. 3, each piece of data is represented as a pair consisting of a logical address (the address value of the data in memory) k and the data body v, and is stored at a physical address indicated by a hash value h(k). In this case, if the hash function h has sufficient randomness like a cryptographic hash function, the correlation between h(k) and k becomes computationally difficult to identify, and randomization of the access location is realized. Note that there are two types of hash-based ORAM: a method that uses only one hash table and a method that uses multiple hash tables.

[0028] However, if a physical address h(k) that has been accessed once is accessed again, the access pattern information that "the same data has been accessed twice" will be leaked regardless of the original k. To prevent this, hash-based ORAM provides a separate data evacuation area called a "stash," and copies accessed data to the stash as appropriate, and when the stash area becomes full, it rebuilds the hash table (re-randomizes addresses).

[0029] More specifically, after a set number of accesses (= stash size), the stash and hash table (or some of them if there are multiple stashes) are completely rebuilt and rerandomized.

[0030] In a conventional hash-based ORAM, a client (a data owner or program executor) has a hash function h, and a server (a data recipient) has a hash table and a stash. When a conventional hash-based ORAM is applied inside a computer, the client is, for example, a CPU, and the server is a memory.

[0031] (Tree-based ORAM) In tree-based ORAM (e.g., Non-Patent Document 2), each piece of data is distributed in a binary tree-like data structure. Each node in the binary tree can hold O(1) pieces of data, and the number of leaf nodes is equal to or greater than the total number of pieces of data to be stored. Each piece of data is associated with one of the randomly selected leaf nodes, and an algorithm controls so that the data associated with the leaf always exists "on the path from the root to the leaf in question."

[0032] When reading or writing data, the path where the desired data resides is traced from the root to the leaves to obtain the data. To prevent the access pattern from being leaked on a second access, once accessed data is linked to a new random leaf and re-stored in the binary tree so that it exists "on the path from the root to the relevant leaf." A table (called a Position Map) is created to store pairs of the logical address k of each piece of data and the associated leaf l, allowing information to be retained so that the appropriate path can be traced when retrieving any data. Many tree-based ORAMs also provide a data backup area called a "stash" that serves as a temporary data storage location in case the binary tree or some of its nodes exceed their capacity.

[0033] An example of a binary tree and a position map is shown in FIG. 4. In the example of FIG. 4, data v at logical address k is ｋ The data is linked to the leaf identified by ｋIt is stored at one of the nodes on the path to

[0034] In a conventional tree-based ORAM, a client (a data owner / program executor) has a Position Map and a stash, and a server (a data entrusted party) has a binary tree. When a conventional tree-based ORAM is applied inside a computer, the client is, for example, a CPU, and the server is a memory.

[0035] (Recursive Tree-Based ORAM) As a variation of the tree-based ORAM, a technique is known in which the above-mentioned position map is recursively stored in a tree-based ORAM (Non-Patent Document 2). Specifically, each pair (k, l) saved in the position map is grouped into a set of multiple pairs and stored in a binary tree smaller than the original tree. Then, for a new position map that is generated, another pair is created and stored in a smaller binary tree. By recursively storing the position map in the tree-based ORAM in this manner, the space and time computational complexity required for storing and searching the position map is reduced.

[0036] Examples 1 to 3 will be described below as examples of the technology according to this embodiment.

[0037] First Embodiment First, a description will be given of a first embodiment. In the first embodiment, a description will be given of an information processing system in which the framework of a hash-based ORAM is modified to conform to a Memory Centric Model.

[0038] FIG. 5 shows an example of the configuration of an information processing system according to the first embodiment. As shown in FIG. 5, the information processing system includes a memory 100 and an instruction processing circuit 200. The memory 100 and the instruction processing circuit 200 are connected by a communication line, enabling communication between the memory 100 and the instruction processing circuit 200. The instruction processing circuit 200 may be a CPU, a GPU, or other circuit. Furthermore, the information processing system may include a plurality of memories 100 and a plurality of instruction processing circuits 200.

[0039] The configuration having the memory 100 and the instruction processing circuit 200 is, for example, the internal configuration of one computer. However, this is not limiting, and the memory 100 may be the memory of one computer, and the instruction processing circuit 200 may be the instruction processing circuit of another computer. Also, the memory 100 may be a server, and the instruction processing circuit 200 may be a client.

[0040] The memory 100 may be referred to as the "storage device 100" and the instruction processing circuit 200 may be referred to as the "processing device 200".

[0041] As described above, in existing hash-based ORAM, the client has a hash function h, and the server has a hash table and a stash. On the other hand, due to the characteristics of the Memory Centric Model and the assumed attack being a side-channel attack, in Example 1, the memory 100 has a hash function, a hash table, and a stash, as shown in Fig. 6. Note that the memory 100 may be provided with multiple hash functions, multiple hash tables, or multiple stashes.

[0042] (First Embodiment: Processing Procedure) In the information processing system having the above configuration, the processing procedure when transferring data from the memory 100 to the instruction processing circuit 200 will be described with reference to the flowchart of FIG.

[0043] <S101> In S101 (step 101), the memory 100 acquires a logical address value k of data to be transferred to the instruction processing circuit 200. This may be a value calculated by the memory 100 during a series of program execution processes, or may be a value provided by the instruction processing circuit 200 or another instruction processing circuit.

[0044] <S102> In S102, the memory 100 checks all data stored in the stash against k, and stores a data pool (k', v') and a flag f.

[0045] In the above process, if the desired data (k, v) is in the stash, then (k', v') = (k, v) and f = 1; if the desired data (k, v) is not in the stash, then (k', v') is a dummy value and f = 0.

[0046] <S103> The memory 100 sets k to a dummy value only when f=1. However, this dummy value must be different from any value used for past accesses. For example, this dummy value may be a value that is incremented for each access.

[0047] The memory 100 calculates h(k), retrieves the pair (k, v) from the hash table that corresponds to the address value, and moves it to the stash. That is, the memory 100 reads the pair (k, v) from the hash table and stores the pair (k, v) in the stash. In this process, when f=1 (when k is a dummy value), the pair (k, v) corresponding to h(k) based on the dummy value k is read from the hash table and stored in the stash, and when f=0 (when k is not a dummy value), the data (k, v) to be transferred to the instruction processing circuit 200 is read from the hash table and stored in the stash.

[0048] Furthermore, when f=0, the memory 100 sets (k', v')=(k, v).

[0049] The above process is for the case where only one hash table is used. In the case where multiple hash tables (here, m tables) are used, the memory 100 executes the following processes 1 and 2 in a predetermined order i=1,...,m.

[0050] Process 1: The memory 100 calculates h_i(k) and stores the pair (k_i, v_i) corresponding to the address value. At this time, if f = 0 and k_i = k, set f = 1, set k to a dummy value, and set (k', v') = (k_i, v_i).

[0051] Process 2: After searching all the hash tables, the memory 100 moves only the data for which k_i=k to the stash, and returns the other read data to its original position in the hash table.

[0052] <S104> In S104, the memory 100 transfers the data (k', v') to the instruction processing circuit 200.

[0053] This concludes the description of S101 to S104. Each time the logical address value k of the data to be transferred to the instruction processing circuit 200 is acquired, the processing of S101 to S104 is carried out.

[0054] By the above process, access to the hash table is randomized in the memory 100, so that the access pattern to the hash table can be kept secret.

[0055] When the memory 100 detects that the stash is full, it executes a hash table reconstruction process in the following step S105.

[0056] <S105> The memory 100 extracts non-dummy data from all hash tables to be disassembled according to the existing hash-based ORAM algorithm, and stores all the data together with the stash data in new hash tables.

[0057] Note that one or both of the stash full search in S102 and the calculation of the hash value in S103 may be outsourced to the instruction processing circuit 200 instead of being processed by the memory 100.

[0058] (Example 2) Next, Example 2 will be described. In Example 2, an information processing system in which the framework of the tree-based ORAM is modified to conform to the Memory Centric Model will be described. The configuration of the information processing system in Example 2 is the same as the configuration of the information processing system in Example 1, and is as described in Example 1 using FIG. 5.

[0059] In existing tree-based ORAMs (non-recursive variations), the client has a position map and a stash, and the server has a binary tree. In contrast, in Example 2, as shown in Fig. 8, memory 100 has a position map, a stash, and a binary tree. Note that memory 100 may be provided with multiple position maps, multiple binary trees, or multiple stashes.

[0060] (Second Embodiment: Processing Procedure) A processing procedure for transferring data from the memory 100 to the instruction processing circuit 200 in the information processing system of the second embodiment will be described with reference to the flowchart of FIG.

[0061] <S201> In S201, the memory 100 acquires a logical address value k of data to be transferred to the instruction processing circuit 200. This may be a value calculated by the memory 100 during a series of program execution processes, or may be a value provided by the instruction processing circuit 200 or another instruction processing circuit.

[0062] <S202> In S202, in the case of a non-recursive variation, the memory 100 checks all data in the Position Map against k and obtains the leaf address value 1 associated with it. In the case of a recursive variation, the memory 100 searches using k in order from the smallest binary trees and similarly obtains the leaf address value 1 of the largest tree.

[0063] <S203> The memory 100 searches all data in all nodes and stashes on the path from the root to the leaf l, and acquires data (k, v).

[0064] <S204> The memory 100 transfers the data (k, v) to the instruction processing circuit 200.

[0065] <S205> The memory 100 randomly selects a new leaf l' for the logical address value k from the binary tree, and restores the data (k, v) to the binary tree according to the existing tree-based ORAM algorithm. Also, in the Position Map, the address value of the leaf corresponding to the logical address value k is updated to the address value of the new leaf l'.

[0066] In addition, any one, any two, or all of the full search of the Position Map in S202, the search of the path stash in S203, and the random leaf selection in S205 may be delegated to the instruction processing circuit 200 instead of being processed in the memory 100.

[0067] By the above process, access to the binary tree is randomized in the memory 100, so that the access pattern to the binary tree can be kept secret.

[0068] Next, a third embodiment will be described as a processing mode of ORAM common to hash-based ORAM and tree-based ORAM. In the third embodiment, a method of extending the processing mode common to ORAM to a memory-centric model will be described as a method encompassing the first and second embodiments.

[0069] First, the processing of existing ORAMs, which is common to hash-based ORAMs and tree-based ORAMs, will be described.

[0070] Generally, ORAM consists of two elements: a "data structure" that stores data and a "position map" that converts queries. In the data structure, each piece of data is stored in a random location (physical address), and the storage location is re-randomized based on a period (trigger) determined by the ORAM algorithm.

[0071] The Position Map is a function that converts a query (i.e., a key value for searching data) into a physical address corresponding to the data to be searched. In hash-based ORAM, the hash function corresponds to the Position Map.

[0072] In existing ORAM, a trusted client (the original owner of the data) holds the Position Map, and the server holds the data structure. When accessing data, the client converts its desired search key (query) using the Position Map and sends it to the server, and the server returns the data (or data sets) indicated by the sent address to the client. The data structure is then re-randomized as needed by the algorithm as a two-way protocol between the client and the server.

[0073] (Embodiment 3: System Configuration) The configuration of the information processing system in embodiment 3 is the same as the configuration of the information processing system in embodiment 1, and is as described in embodiment 1 using Fig. 5. The instruction execution circuit 200 is not limited to a CPU, and may be a GPU, FPGA, or the like.

[0074] As mentioned above, in the Memory Centric Model, unlike the client-server model (or CPU-memory model) assumed in conventional ORAM, the memory 100 has a certain degree of computing power. Also, the instruction execution circuit 200 can communicate directly with the memory 100 without going through the CPU.

[0075] Based on the above, in the third embodiment, as shown in FIG. 10, the data structure is stored in the memory 100, and part or all of the position map is also stored in the memory 100.

[0076] If there is a portion of the Position Map that is not stored in the memory 100, that portion is shared with one or more instruction execution circuits 200 and is synchronized with each other by any means.

[0077] Third Embodiment: Processing Procedure A processing procedure for transferring data from the memory 100 to the instruction processing circuit 200 in the information processing system of the third embodiment will be described with reference to the flowchart of FIG.

[0078] <S301> In S301, the memory 100 acquires a logical address value k or a value similar thereto of the data to be transferred to the instruction processing circuit 200. This may be a value calculated by the memory 100 during a series of program execution processes, or may be specified by the instruction execution circuit 200. If the instruction execution circuit 200 has a part of a position map, k may be a value obtained by converting the logical address value.

[0079] <S302> In S302, the memory 100 obtains the physical address corresponding to k from its own Position Map and transfers the data at that position in the data structure to the instruction execution circuit 200. Based on the underlying ORAM algorithm, S301 to S302 can be executed recursively. Also, in S302, some processing may be delegated to the instruction execution circuit 200 as necessary.

[0080] <S303> After the instruction execution circuit 200 acquires the desired data (k, v), the memory 100 updates the data and data structure based on the existing ORAM algorithm. In S303, the memory 100 may delegate some of the processing to the instruction execution circuit 200 as needed. This delegation is performed especially when part of the Position Map is stored in the instruction execution circuit 200.

[0081] (Example of functional configuration of storage device 100) As described above, the memory 100 may be called the storage device 100. Furthermore, the storage device 100 is not limited to a component within a computer, but may be one or more computers. An example of the functional configuration of the storage device 100 common to Examples 1 to 3 is shown in FIG. 12.

[0082] 12, the storage device 100 includes a storage unit 110, a conversion unit 120, a transfer unit 130, and an update unit 140. In the first and second embodiments, the storage device 100 may further include a memory area for storing a stash. The storage unit 110 may include an area for the stash.

[0083] The storage unit 110 stores a data structure that holds data at randomized physical addresses, and the conversion unit 120 converts a key value for data search into a physical address in the data structure.

[0084] Furthermore, the transfer unit 130 reads data from the storage unit 110 and transfers the data to the processing device 200. After the data has been transferred to the processing device 200, the update unit 140 updates the data structure.

[0085] It should be noted that in each of the conversion unit 120, the transfer unit 130, and the update unit 140, all or part of the processing may be outsourced to the processing device 200. Even in such cases where outsourcing is performed, the function of the processing device 200 to execute the outsourced processing may be interpreted as being included in the storage device 100.

[0086] In the first embodiment, the above data structure is a hash table having hash values ​​of key values ​​for data search as physical addresses, and the conversion unit 120 is a hash function that calculates hash values.

[0087] In the second embodiment, the data structure is a binary tree consisting of multiple nodes, each capable of holding data. In the binary tree, identification information of the leaf of the path where data is stored corresponds to a physical address. The conversion unit 120 has correspondence information between the leaves in the binary tree and the data.

[0088] (Hardware Configuration Example) Any of the devices described in this embodiment (memory, storage device, instruction processing circuit, processing device, information processing system, etc.) can be realized, for example, by causing a computer to execute a program. This computer may be a physical computer or a virtual machine on the cloud.

[0089] That is, the device can be realized by executing a program corresponding to the processing performed by the device using hardware resources such as a CPU and memory built into a computer. The program can be recorded on a computer-readable recording medium (such as a portable memory) and stored or distributed. The program can also be provided via a network such as the Internet or email.

[0090] Fig. 13 is a diagram showing an example of the hardware configuration of the computer. The computer in Fig. 13 includes a drive device 1000, an auxiliary storage device 1002, a memory device 1003, a CPU 1004, an interface device 1005, a display device 1006, an input device 1007, an output device 1008, a GPU 1009, and the like, all of which are interconnected via a bus B.

[0091] The program that realizes the processing on the computer is provided by a recording medium 1001, such as a CD-ROM or a memory card. When the recording medium 1001 storing the program is set in the drive device 1000, the program is installed from the recording medium 1001 to the auxiliary storage device 1002 via the drive device 1000. However, the program does not necessarily have to be installed from the recording medium 1001, but may be downloaded from another computer via a network. The auxiliary storage device 1002 stores the installed program as well as necessary files, data, etc.

[0092] The memory device 1003 reads and stores the program from the auxiliary storage device 1002 when an instruction to start the program is received. The CPU 1004, memory device 1003, etc. realizes the functions related to the device in accordance with the program. The interface device 1005 is used as an interface for connecting to a network, etc. The display device 1006 displays a GUI (Graphical User Interface) based on the program, etc. The input device 1007 is composed of a keyboard, mouse, buttons, touch panel, etc., and is used to input various operation instructions. The output device 1008 outputs the results of calculations.

[0093] The processes described in the first to third embodiments are performed, for example, between a memory device 1003 and a GPU 1009 in a computer shown in Fig. 13. In this case, the memory device 1003 has the computing power to perform the processes described in the first to third embodiments.

[0094] In addition, the computer shown in Figure 13 may perform the processing of the memory 100 (also called the storage device 100) in Examples 1 to 3, and the computer shown in Figure 12 may perform the processing of the instruction processing circuit 200 (also called the processing device 200) described in Examples 1 to 3.

[0095] (Effects of the Embodiment) As described above, the technology described in the present embodiment makes it possible to apply ORAM to the Memory Centric Model.

[0096] The following additional notes are provided regarding the above-described embodiments.

[0097] <Additional Notes> (Additional Item 1) An information processing system including a storage device and a processing device, the storage device comprising: a storage unit that stores a data structure that holds data at randomized physical addresses; a conversion unit that converts a key value for data search into the physical address in the data structure; and a transfer unit that transfers the data read from the storage unit to the processing device. (Additional Item 2) The storage device according to Additional Item 1, further comprising: an update unit that updates the data structure after the data is transferred to the processing device. (Additional Item 3) The storage device according to Additional Item 1, wherein the data structure is a hash table that has hash values ​​of the key values ​​as physical addresses, and the conversion unit calculates the hash values. (Additional Item 4) The storage device according to Additional Item 1, wherein the data structure is a binary tree made up of a plurality of nodes each capable of holding data, and the conversion unit has correspondence information between leaves in the binary tree and data. (Supplementary Item 5) An information processing system comprising the storage device according to any one of Supplementary Items 1 to 4, and a processing device to which data is transferred from the storage device. (Supplementary Item 6) An information processing method executed by a storage device in an information processing system comprising a storage device and a processing device, wherein the storage device comprises a storage unit that stores a data structure that holds data at randomized physical addresses, and the information processing method comprises: a conversion step of converting a key value for data search into the physical address in the data structure; and a transfer step of transferring the data read from the storage unit to the processing device.

[0098] Although the present embodiment has been described above, the present invention is not limited to such a specific embodiment, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0099] 100 Memory, storage device 110 Storage unit 120 Conversion unit 130 Transfer unit 140 Update unit 200 Instruction processing circuit, processing device 1000 Drive device 1001 Recording medium 1002 Auxiliary storage device 1003 Memory device 1004 CPU 1005 Interface device 1006 Display device 1007 Input device 1008 Output device 1009 GPU

Claims

1. A storage device in an information processing system including a storage device and a processing device, the storage device comprising: a storage unit that stores a data structure for holding data at a randomized physical address; a conversion unit that converts a key value for data search into the physical address in the data structure; and a transfer unit that transfers the data read from the storage unit to the processing device.

2. The storage device according to claim 1, further comprising an update unit that updates the data structure after the data is transferred to the processing device.

3. The data structure is a hash table having a hash value of the key value as a physical address, and the conversion unit calculates the hash value. The storage device according to claim 1.

4. The data structure is a binary tree composed of a plurality of nodes each capable of holding data, and the conversion unit has correspondence information between a leaf and data in the binary tree. The storage device according to claim 1.

5. An information processing system including the storage device according to any one of claims 1 to 4 and a processing device that is a transfer destination of data from the storage device.

6. An information processing method executed by the storage device in an information processing system including a storage device and a processing device, the storage device including a storage unit that stores a data structure for holding data at a randomized physical address, the information processing method comprising: a conversion step of converting a key value for data search into the physical address in the data structure; and a transfer step of transferring the data read from the storage unit to the processing device.

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