Semiconductor device and method for manufacturing semiconductor device

Abstract

This semiconductor device comprises: a support; a first semiconductor element supported by the support; a first signal terminal that is electrically connected to the first semiconductor element; and a sealing resin that covers the first semiconductor element. The first signal terminal includes a rod-like part protruding from the sealing resin, and an extension part extending from the rod-like part when viewed in the center axis direction of the rod-like part. The extension part is directly bonded to the support.

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) have been known. Such semiconductor devices are installed in a wide variety of electronic devices, from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 (Patent Document 1) discloses a conventional semiconductor device (power module). The semiconductor device described in Patent Document 1 includes a semiconductor element, a main substrate, and a substrate. The main substrate has a metal layer. The semiconductor element is conductively joined to the metal layer. The sub-substrate is supported by the main substrate. The semiconductor element is provided with a gate terminal.

[0003] Japanese Patent Application Laid-Open No. 2021-190505

[0004] [Summary] If the attachment of the gate terminal is unstable, it may cause problems in the operation of the semiconductor device.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that can more appropriately fix signal terminals.

[0006] The present disclosure provides a semiconductor device comprising: a support body, a first semiconductor element supported by the support body, a first signal terminal electrically connected to the first semiconductor element, and a sealing resin covering the first semiconductor element. The first signal terminal includes a rod-shaped portion protruding from the sealing resin and an extension portion extending from the rod-shaped portion when viewed in the direction of the central axis of the rod-shaped portion. The extension portion is directly bonded to the support body.

[0007] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 3 is a partial perspective view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 4 is a plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 5 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 6 is a partial side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 7 is a partial enlarged plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 8 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 9 is a partial plan view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 10 is a side view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 11 is a bottom view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 14 is a partial enlarged cross-sectional view showing a semiconductor device according to a first embodiment of the present disclosure. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5 . FIG. 17 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 18 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 19 is a partially enlarged plan view showing the semiconductor device according to the first embodiment of the present disclosure. FIG. 20 is a partially enlarged cross-sectional view taken along line XX-XX in FIG. 19 . FIG. 21 is a configuration diagram showing a vehicle according to the first embodiment of the present disclosure. FIG. 22 is a partially enlarged cross-sectional view showing a method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. FIG. 23 is a partially enlarged cross-sectional view showing a method for manufacturing a first modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 24 is a partially enlarged plan view showing another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure. FIG. 25 is a partially enlarged plan view showing yet another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure. FIG. 26 is a partially enlarged plan view showing yet another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure. FIG. 27 is a partially enlarged plan view showing yet another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure.FIG. 28 is a partial enlarged plan view showing yet another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure. FIG. 29 is a partial enlarged plan view showing yet another example of a signal terminal of the semiconductor device according to the first embodiment of the present disclosure. FIG. 30 is a partial enlarged cross-sectional view showing a second modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 31 is a partial enlarged cross-sectional view showing a third modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 32 is a partial enlarged cross-sectional view showing a fourth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 33 is a partial enlarged cross-sectional view showing a fifth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 34 is a perspective view showing a sixth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 35 is a plan view showing the sixth modified example of the semiconductor device according to the first embodiment of the present disclosure. FIG. 36 is a partial enlarged cross-sectional view taken along line XXXVI-XXXVI in FIG. 35. FIG. 37 is a partial perspective view showing the semiconductor device according to the second embodiment of the present disclosure. FIG. 38 is a partial plan view showing the semiconductor device according to the second embodiment of the present disclosure. FIG. 39 is a partial enlarged cross-sectional view showing the semiconductor device according to the second embodiment of the present disclosure.

[0009] DETAILED DESCRIPTION Preferred embodiments of the present disclosure will now be described in detail with reference to the drawings.

[0010] The terms "first," "second," "third," etc. in this disclosure are used for identification purposes only and are not intended to impose any ranking on their objects.

[0011] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on a certain object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on a certain object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on a certain object B" includes "a certain object A is located on a certain object B with a certain object A in contact with the certain object B" and "a certain object A is located on a certain object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, the phrase "an object A overlaps an object B when viewed in a certain direction" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, in the present disclosure, "a surface A faces in (one side or the other side of) direction B" is not limited to the case where the angle of surface A with respect to direction B is 90°, but also includes the case where surface A is tilted with respect to direction B.

[0012] 1 to 20 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device A1 of this embodiment includes a support 1, one or more first semiconductor elements 10A, one or more signal terminals 45, and a sealing resin 8. The semiconductor device A1 may include a plurality of first semiconductor elements 10A, a plurality of second semiconductor elements 10B, a first terminal 41, a second terminal 42, a plurality of third terminals 43, a fourth terminal 44, a plurality of signal terminals 45, a first conductive member 5, and a second conductive member 6.

[0013] FIG. 1 is a perspective view showing the semiconductor device A1. FIG. 2 is a partial perspective view showing the semiconductor device A1. FIG. 3 is a partial perspective view showing the semiconductor device A1. FIG. 4 is a plan view showing the semiconductor device A1. FIG. 5 is a partial plan view showing the semiconductor device A1. FIG. 6 is a partial side view showing the semiconductor device A1. FIG. 7 is a partial enlarged plan view showing the semiconductor device A1. FIG. 8 is a partial plan view showing the semiconductor device A1. FIG. 9 is a partial plan view showing the semiconductor device A1. FIG. 10 is a side view showing the semiconductor device A1. FIG. 11 is a bottom view showing the semiconductor device A1. FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 5. FIG. 13 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 14 is a partial enlarged cross-sectional view showing the semiconductor device A1. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 5. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 5. FIG. 17 is a partial enlarged plan view showing the semiconductor device A1. FIG. 18 is a partial enlarged plan view showing the semiconductor device A1. Fig. 19 is a partially enlarged plan view showing the semiconductor device A1. Fig. 20 is a partially enlarged cross-sectional view taken along line XX-XX in Fig. 19. For ease of understanding, the sealing resin 8 is omitted from Figs. 2, 3, 5 to 9, and 17 to 19.

[0014] In these figures, for example, the thickness direction z is an example of the thickness direction of the support 1. The first direction x is an example of a direction perpendicular to the thickness direction z. The second direction y is an example of a direction perpendicular to the thickness direction z and the first direction x. Furthermore, for example, one side of the first direction x will be referred to as the x1 side of the first direction x, and the other side of the first direction x will be referred to as the x2 side of the first direction x. Furthermore, for example, one side of the second direction y will be referred to as the y1 side of the second direction y, and the other side of the second direction y will be referred to as the y2 side of the second direction y. Furthermore, for example, one side of the thickness direction z will be referred to as the z1 side of the thickness direction z, and the other side of the thickness direction z will be referred to as the z2 side of the thickness direction z.

[0015] First semiconductor element 10A, second semiconductor element 10B: The first semiconductor elements 10A and the second semiconductor elements 10B are electronic components that are the core of the semiconductor device A1. The first semiconductor elements 10A and the second semiconductor elements 10B are made of a semiconductor material primarily composed of, for example, silicon carbide (SiC). This semiconductor material is not limited to silicon carbide (SiC) and may be silicon (Si), gallium nitride (GaN), diamond (C), or other suitable materials. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is a power semiconductor chip with switching functionality, such as a metal oxide semiconductor field effect transistor (MOSFET). While this embodiment illustrates a case in which the first semiconductor elements 10A and the second semiconductor elements 10B are MOSFETs, they are not limited thereto and may be other transistors, such as insulated gate bipolar transistors (IGBTs). The first semiconductor elements 10A and the second semiconductor elements 10B may have different configurations or may have the same configuration. In the following description, the first semiconductor elements 10A and the second semiconductor elements 10B are all the same element. Each of the first semiconductor elements 10A and the second semiconductor elements 10B is, for example, an n-channel MOSFET, but may also be a p-channel MOSFET.

[0016] 13 and 14 , the first semiconductor element 10A and the second semiconductor element 10B each have an element main surface 101 and an element back surface 102. In each of the first semiconductor elements 10A and the second semiconductor elements 10B, the element main surface 101 and the element back surface 102 are spaced apart in the thickness direction z. The element main surface 101 faces the z1 side in the thickness direction z, and the element back surface 102 faces the z2 side in the thickness direction z.

[0017] The number of first semiconductor elements 10A and the number of second semiconductor elements 10B are changed as appropriate depending on the required performance, such as the current capacity handled by the semiconductor device A1. In this embodiment, as shown in Figures 8 and 9, four first semiconductor elements 10A and four second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and four second semiconductor elements 10B may be two or three, or may be five or more. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal to or different from each other.

[0018] The semiconductor device A1 can be configured, for example, as a half-bridge switching circuit. In this case, a plurality of first semiconductor elements 10A form an upper arm circuit of the semiconductor device A1, and a plurality of second semiconductor elements 10B form a lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are connected in series to form a bridge layer.

[0019] As shown in Figures 8, 9, and 16, each of the multiple first semiconductor elements 10A is mounted on a first conductive portion 32A of the main substrate 3, which will be described later. In the example shown in Figures 8 and 9, the multiple first semiconductor elements 10A are lined up, for example, in the second direction y and spaced apart from one another. Each first semiconductor element 10A is conductively bonded to the first conductive portion 32A via a first conductive bonding material 19A. The element back surface 102 faces the first conductive portion 32A.

[0020] As shown in Figures 8, 9, and 15, each of the multiple second semiconductor elements 10B is mounted on a second conductive portion 32B of the main substrate 3 (described later). In the example shown in Figures 8 and 9, the multiple second semiconductor elements 10B are aligned, for example, in the second direction y and spaced apart from one another. Each second semiconductor element 10B is conductively bonded to the second conductive portion 32B via a second conductive bonding material 19B. The element back surface 102 faces the second conductive portion 32B. As can be seen from Figure 9, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap when viewed in the first direction x, but they do not have to overlap.

[0021] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B each have a first principal surface electrode 11, a second principal surface electrode 12, a third principal surface electrode 13, and a back surface electrode 15. The configurations of the first principal surface electrode 11, the second principal surface electrode 12, the third principal surface electrode 13, and the back surface electrode 15 described below are common to each of the first semiconductor elements 10A and each of the second semiconductor elements 10B. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are provided on the element main surface 101. The first principal surface electrode 11, the second principal surface electrode 12, and the third principal surface electrode 13 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0022] The first principal surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the first semiconductor element 10A (second semiconductor element 10B) is input. In the first semiconductor element 10A (second semiconductor element 10B), the second principal surface electrode 12 is, for example, a source electrode, through which a source current flows. The third principal surface electrode 13 is, for example, a source sense electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire area of ​​the element back surface 102. The back surface electrode 15 is, for example, formed by Ag (silver) plating.

[0023] When a drive signal (gate voltage) is input to the first principal surface electrode 11 (gate electrode), each first semiconductor element 10A (each second semiconductor element 10B) switches between a conductive state and a non-conductive state in response to the drive signal. In the conductive state, current flows from the back surface electrode 15 (drain electrode) to the second principal surface electrode 12 (source electrode), and in the non-conductive state, current does not flow. In other words, each first semiconductor element 10A (each second semiconductor element 10B) performs a switching operation. The semiconductor device A1 converts a DC voltage input between the single fourth terminal 44 and the two first and second terminals 41 and 42 into, for example, an AC voltage, and outputs the AC voltage from the third terminal 43, using the switching functions of the multiple first semiconductor elements 10A and multiple second semiconductor elements 10B.

[0024] Support 1: The support 1 supports the first semiconductor element 10A, the second semiconductor element 10B, and a plurality of signal terminals 45. There are no limitations on the specific configuration of the support 1. In this embodiment, the support 1 may include a main substrate 3, a first sub-substrate 48A, and a second sub-substrate 48B.

[0025] Main substrate 3: The main substrate 3 supports a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The specific configuration of the main substrate 3 is not limited, and may be, for example, a direct bonded copper (DBC) substrate or an active metal brazing (AMB) substrate. The main substrate 3 may include a main insulating layer 31, a first main metal layer 32, and a second main metal layer 33. The first main metal layer 32 includes a first conductive portion 32A and a second conductive portion 32B. The dimension of the main substrate 3 in the thickness direction z is not limited, and may be, for example, 0.4 mm to 3.0 mm. In the illustrated example, the first main metal layer 32 may be a single layer without a plating layer or may be a multi-layer structure including a plating layer of Ni or the like.

[0026] The constituent material of the main insulating layer 31 may include, for example, ceramics with excellent thermal conductivity. Examples of such ceramics include SiN (silicon nitride). The constituent material of the main insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The main insulating layer 31 has, for example, a rectangular shape in a plan view. The dimension of the main insulating layer 31 in the thickness direction z is not limited in any way and may be, for example, 0.05 mm or more and 1.0 mm or less.

[0027] As shown in FIGS. 8 , 9 , and 12 , the first conductive portion 32A can support multiple first semiconductor elements 10A, and the second conductive portion 32B can support multiple second semiconductor elements 10B. The first conductive portion 32A and the second conductive portion 32B can be formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the main insulating layer 31. The constituent material of the first conductive portion 32A and the second conductive portion 32B can include, for example, Cu (copper). The constituent material can include, for example, Al (aluminum) other than Cu (copper). The first conductive portion 32A and the second conductive portion 32B are spaced apart in the first direction x. The first conductive portion 32A is located on the x1 side of the second conductive portion 32B in the first direction x. The first conductive portion 32A and the second conductive portion 32B can each have, for example, a rectangular shape in a plan view. The first conductive portion 32A and the second conductive portion 32B, together with the first conductive member 5 and the second conductive member 6, can form a path of a main circuit current that is switched by the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B.

[0028] The first conductive portion 32A has a first main surface 301A. The first main surface 301A may be a flat surface facing the z1 side in the thickness direction z. A plurality of first semiconductor elements 10A may be bonded to the first main surface 301A of the first conductive portion 32A via a first conductive bonding material 19A. The second conductive portion 32B has a second main surface 301B. The second main surface 301B is a flat surface facing the z1 side in the thickness direction z. A plurality of second semiconductor elements 10B may be bonded to the second main surface 301B of the second conductive portion 32B via a second conductive bonding material 19B. The constituent materials of the first conductive bonding material 19A and the second conductive bonding material 19B are not particularly limited and may be, for example, solder, a metal paste material containing a metal such as Ag (silver), or a sintered metal containing a metal such as Ag (silver). The dimensions of first conductive portion 32A and second conductive portion 32B in thickness direction z are not limited in any way and may be, for example, 0.1 mm or more and 1.5 mm or less.

[0029] The second main metal layer 33 may be formed on the lower surface (surface facing the z2 side in the thickness direction z) of the main insulating layer 31. The constituent material of the second main metal layer 33 may be, for example, the same as the constituent material of the first main metal layer 32. The second main metal layer 33 has a back surface 302. The back surface 302 may be a flat surface facing the z2 side in the thickness direction z. In the example shown in FIG. 11 , the back surface 302 may be exposed from the sealing resin 8. A heat dissipation member (e.g., a heat sink) (not shown) may be attached to the back surface 302. The back surface 302 may not be exposed from the sealing resin 8 and may be covered by the sealing resin 8. The second main metal layer 33 may overlap both the first conductive portion 32A and the second conductive portion 32B in a plan view.

[0030] First terminal 41, second terminal 42, third terminal 43, fourth terminal 44: The specific configurations of the first terminal 41, second terminal 42, the plurality of third terminals 43, and fourth terminal 44 are not limited in any way, and in this embodiment, they may be made of a plate-shaped metal plate. This metal plate may contain, for example, Cu (copper) or a Cu (copper) alloy. In the examples shown in Figures 1 to 6, 8, 9, and 11, the semiconductor device A1 includes one each of the first terminal 41, second terminal 42, and fourth terminal 44, and two third terminals 43, but the number of each terminal is not limited in any way.

[0031] A DC voltage to be converted into power may be input to the first terminal 41, the second terminal 42, and the fourth terminal 44. For example, the fourth terminal 44 may be a positive electrode (P terminal), and the first terminal 41 and the second terminal 42 may each be a negative electrode (N terminal). An AC voltage converted into power by the first semiconductor element 10A and the second semiconductor element 10B may be output from the plurality of third terminals 43. The first terminal 41, the second terminal 42, the plurality of third terminals 43, and the fourth terminal 44 may each include a portion covered by the sealing resin 8 and a portion exposed from the sealing resin 8.

[0032] As shown in FIG. 12 , the fourth terminal 44 may be conductively bonded to the first conductive portion 32A. The conductive bonding method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc. may be appropriately adopted. The fourth terminal 44 may be integrally formed with the first conductive portion 32A. As shown in FIGS. 8 and 9 , the fourth terminal 44 may be located on the x1 side in the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The fourth terminal 44 may be conductively connected to the first conductive portion 32A and to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A via the first conductive portion 32A.

[0033] As shown in FIG. 5 , the first terminal 41 and the second terminal 42 may be conductively joined to the second conductive member 6. The conductive joining method is not limited, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately adopted. The first terminal 41 and the second terminal 42 may be integrally formed with the second conductive member 6. As shown in FIGS. 5 , 8 , etc., the first terminal 41 and the second terminal 42 are each located on the x1 side of the first direction x with respect to the multiple first semiconductor elements 10A and the first conductive portions 32A. The first terminal 41 and the second terminal 42 are each conductively connected to the second conductive member 6 and may be conductively connected to the second principal surface electrodes 12 (source electrodes) of each second semiconductor element 10B via the second conductive member 6.

[0034] As shown in FIGS. 1 to 5 and 11 , the first terminal 41, the second terminal 42, and the fourth terminal 44 may each protrude from the sealing resin 8 toward the x1 side in the first direction x in the semiconductor device A1. The first terminal 41, the second terminal 42, and the fourth terminal 44 may be spaced apart from one another. The first terminal 41 and the second terminal 42 may be located on opposite sides of the fourth terminal 44 in the second direction y. The first terminal 41 may be located on the y1 side of the fourth terminal 44 in the second direction y, and the second terminal 42 may be located on the y2 side of the fourth terminal 44 in the second direction y. The first terminal 41, the second terminal 42, and the fourth terminal 44 may overlap one another when viewed in the second direction y.

[0035] As can be seen from FIGS. 8 , 9 , and 12 , the two third terminals 43 may each be conductively bonded to the second conductive portion 32B. The conductive bonding method is not limited to any particular method, and methods such as ultrasonic bonding, laser bonding, and welding, or methods using solder, metal paste, silver sintered body, etc., may be appropriately employed. As shown in FIG. 8 and other figures, the two third terminals 43 may each be located on the x2 side of the second semiconductor elements 10B and the second conductive portions 32B in the first direction x. Each third terminal 43 may be conductively connected to the second conductive portion 32B and, via the second conductive portion 32B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The number of third terminals 43 is not limited to two and may be, for example, one or three or more. For example, when there is one third terminal 43, it is preferably connected to the center portion of the second conductive portion 32B in the second direction y.

[0036] First sub-substrate 48A, second sub-substrate 48B: The first sub-substrate 48A and the second sub-substrate 48B can support a plurality of signal terminals 45. The first sub-substrate 48A and the second sub-substrate 48B can be interposed between the first main surface 301A and the second main surface 301B and the plurality of signal terminals 45 in the thickness direction z. The first sub-substrate 48A and the second sub-substrate 48B can have different configurations or can have a common configuration. The first sub-substrate 48A is disposed on the first conductive portion 32A. The second sub-substrate 48B can be disposed on the second conductive portion 32B. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B can have a common configuration and can be rotated 180 degrees relative to the other when viewed in the thickness direction z.

[0037] The specific configuration of the first sub-substrate 48A and the second sub-substrate 48B is not limited in any way. Specific examples of the first sub-substrate 48A and the second sub-substrate 48B include an IMS (Insulated Metal Substrate) substrate, a glass epoxy resin substrate, and a metal substrate. In this embodiment, the first sub-substrate 48A and the second sub-substrate 48B may be an IMS substrate. As shown in FIG. 20 , the first sub-substrate 48A and the second sub-substrate 48B may have a sub-insulation layer 481, a first sub-metal layer 482, and a second sub-metal layer 483 stacked on top of each other.

[0038] The sub-insulating layer 481 may be made of, for example, ceramics. The sub-insulating layer 481 may have, for example, a rectangular shape in plan view. The thickness of the sub-insulating layer 481 is not particularly limited and may be, for example, 0.05 mm or more and 1.0 mm or less.

[0039] The first sub-metal layer 482 may be formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the sub-insulating layer 481. The first sub-metal layer 482 may include, for example, Cu (copper) or a Cu (copper) alloy. The specific configuration of the first sub-metal layer 482 is not limited in any way. The thickness of the first sub-metal layer 482 is not limited in any way and may be, for example, 0.035 mm or more and 2.0 mm or less.

[0040] 17 and 18, the first sub-metal layer 482 may include a plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F. The plurality of regions 482A, 482B, 482C, 482D, 482E, and 482F may be spaced apart and insulated from one another.

[0041] The region 482A may include a connection portion 4821A and a terminal portion 4822A. In the first sub-substrate 48A, the connection portion 4821A may be located on the x2 side in the first direction x, and the terminal portion 4822A may be located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821A may be located on the x1 side in the first direction x, and the terminal portion 4822A may be located on the x2 side in the first direction x. The connection portion 4821A may have a shape that extends elongatedly in the second direction y. The terminal portion 4822A may be substantially circular.

[0042] A plurality of wires 71 can be bonded to the connection portion 4821A. In this embodiment, the wires 71 can be bonded to a surface metal layer 4829 of the connection portion 4821A. The constituent material of the wires 71 is not limited in any way and can include, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482A can be electrically connected to the first main surface electrodes 11 (gate electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 71.

[0043] The region 482B may include a connection portion 4821B and a terminal portion 4822B. In the first sub-substrate 48A, the connection portion 4821B may be located on the x2 side in the first direction x, and the terminal portion 4822B may be located on the x1 side in the first direction x. In the second sub-substrate 48B, the connection portion 4821B may be located on the x1 side in the first direction x, and the terminal portion 4822B may be located on the x2 side in the first direction x. In the first sub-substrate 48A, the region 482B may be located on the x1 side in the first direction x of the connection portion 4821A. In the second sub-substrate 48B, the region 482B may be located on the x2 side in the first direction x of the connection portion 4821A. The connection portion 4821B has a shape that extends elongated in the second direction y. The terminal portion 4822B may be approximately semicircular. In the first sub-substrate 48A, the terminal portion 4822B may be located on the y2 side of the terminal portion 4822A in the second direction y. In the second sub-substrate 48B, the terminal portion 4822B may be located on the y1 side of the terminal portion 4822A in the second direction y.

[0044] A plurality of wires 72 may be joined to the connection portion 4821B. In this embodiment, the wires 72 may be joined to a surface metal layer 4829 of the connection portion 4821B. The constituent material of the wires 72 is not limited in any way and may include, for example, Al (aluminum) or an Al (aluminum) alloy. The region 482B may be electrically connected to the third principal surface electrodes 13 (source sense electrodes) of the plurality of first semiconductor elements 10A (the plurality of second semiconductor elements 10B) via the plurality of wires 72.

[0045] The region 482C may include a connecting portion 4821C and a terminal portion 4822C. In the first sub-substrate 48A, the connecting portion 4821C may be located on the y2 side in the second direction y, and the terminal portion 4822C may be located on the y1 side in the second direction y. In the second sub-substrate 48B, the connecting portion 4821C may be located on the y1 side in the second direction y, and the terminal portion 4822C may be located on the y2 side in the second direction y. The connecting portion 4821C may have a curved shape extending in the second direction y. The terminal portion 4822C has a substantially circular shape. In the first sub-substrate 48A, the terminal portion 4822C may be located on the x1 side in the first direction x of the connecting portion 4821A, and on the y2 side in the second direction y of the terminal portion 4822B. On the second sub-substrate 48B, the connecting portion 4821A may be located on the x2 side in the first direction x, and the terminal portion 4822C may be located on the y1 side in the second direction y of the terminal portion 4822B.

[0046] The region 482D may include a connection portion 4821D and a terminal portion 4822D. In the first sub-substrate 48A, the connection portion 4821D may be located on the y2 side in the second direction y, and the terminal portion 4822D may be located on the y1 side in the second direction y. The connection portion 4821D may be, for example, rectangular, and the terminal portion 4822D may be, for example, approximately circular. In the first sub-substrate 48A, the connection portion 4821D may be located on the x1 side in the first direction x of the connection portion 4821C. In the second sub-substrate 48B, the connection portion 4821D may be located on the x2 side in the first direction x of the connection portion 4821C. In the first sub-substrate 48A, the terminal portion 4822D may be located on the y2 side in the second direction y of the terminal portion 4822C. In the second sub-substrate 48B, the terminal portion 4822D can be located on the y1 side in the second direction y of the terminal portion 4822C.

[0047] In the first sub-substrate 48A, the region 482E may be located on the y2 side in the second direction y of the connecting portion 4821A and on the x2 side in the first direction x of the connecting portion 4821C. In the second sub-substrate 48B, the region 482E may be located on the y1 side in the second direction y of the connecting portion 4821A and on the x1 side in the first direction x of the connecting portion 4821C. The region 482E may have a shape that extends in the second direction y.

[0048] The multiple regions 482F may be arranged alternately in the second direction y with the terminal portion 4822A, the terminal portion 4822B, the terminal portion 4822C, and the terminal portion 4822D. The shape of the multiple regions 482F is not limited in any way and may be rectangular, circular, or the like, and in the illustrated example, may be rectangular.

[0049] 13, 14, 20, etc., the second sub-metal layer 483 may be formed on the lower surface (the surface on the z2 side in the thickness direction z) of the sub-insulating layer 481. The constituent material of the second sub-metal layer 483 may include, for example, Cu (copper) or a Cu (copper) alloy. The thickness of the second sub-metal layer 483 is not particularly limited and may be, for example, 0.035 mm or more and 3.0 mm or less.

[0050] The second sub-metal layer 483 of the first sub-substrate 48A can be conductively bonded to the first conductive portion 32A. The second sub-metal layer 483 of the second sub-substrate 48B can be conductively bonded to the second conductive portion 32B. The method for conductively bonding the second sub-metal layer 483 to the first conductive portion 32A or the second conductive portion 32B is not limited in any way. Examples of conductive bonding methods include a method using a conductive bonding material, a laser bonding method, an ultrasonic bonding method, and a solid-state bonding method. In this embodiment, the second sub-metal layers 483 of the first sub-substrate 48A and the second sub-substrate 48B can be conductively bonded to the first conductive portion 32A and the second conductive portion 32B via a conductive bonding material 49, as shown in FIG. 20 . The conductive bonding material 49 can be, for example, solder.

[0051] 20 , on the first sub-substrate 48A, a wire 73 can be connected to the connection portion 4821D and the first conductive portion 32A. There are no limitations on the material of the wire 73, and it can include, for example, Al (aluminum) or an Al (aluminum) alloy. This allows the region 482D to be electrically connected to the first conductive portion 32A.

[0052] 18 , a thermistor 17 may be connected to the connection portion 4821C and the connection portion 4821D of the second sub-substrate 48B. The thermistor 17 may be used as a temperature detection sensor. In addition to the thermistor 17, a temperature-sensitive diode or the like may be included, or the thermistor 17 or the like may not be included.

[0053] The wire 71, the wire 72, and the wire 73 may not be connected to the first main metal layer 32. In other words, the first main metal layer 32 may be separated from the plurality of wires 71, 72, and 73.

[0054] Signal terminals 45: Each of the multiple signal terminals 45 may be, for example, a terminal for controlling each first semiconductor element 10A and each second semiconductor element 10B. The multiple signal terminals 45 may include multiple first signal terminals 46A, 46B, 46E and multiple second signal terminals 47A to 47D. The multiple first signal terminals 46A, 46B, 46E may be used to control each first semiconductor element 10A, etc. The multiple second signal terminals 47A to 47D may be used to control each second semiconductor element 10B, etc. The multiple first signal terminals 46A, 46B, 46E and the multiple second signal terminals 47A to 47D are supported by the support body 1 and directly bonded to the support body 1.

[0055] The multiple first signal terminals 46A, 46B, 46E may be arranged at intervals in the second direction y. The multiple first signal terminals 46A, 46B, 46E may be supported by the first conductive portion 32A via a first sub-substrate 48A, as shown in Figures 2, 3, 5, 6, 8, 17, etc. The multiple first signal terminals 46A, 46B, 46E may be located between the multiple first semiconductor elements 10A and the first terminal 41, the second terminal 42, and the fourth terminal 44 in the first direction x, as shown in Figure 5.

[0056] 17 , the first signal terminal 46A may be disposed on the terminal portion 4822A. The first signal terminal 46A may be a terminal (gate terminal) for inputting drive signals to the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A may be input to the first signal terminal 46A (for example, a gate voltage may be applied).

[0057] The first signal terminal 46B may be disposed on the terminal portion 4822B. The first signal terminal 46B may be a terminal for detecting source signals (source sense terminal) of the multiple first semiconductor elements 10A. The first signal terminal 46B can detect a voltage (voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple first semiconductor elements 10A.

[0058] The first signal terminal 46E may be disposed on the terminal portion 4822D. The first signal terminal 46E may be a terminal (drain sense terminal) for detecting drain signals of the multiple first semiconductor elements 10A. The first signal terminal 46E can detect a voltage (a voltage corresponding to a drain current) applied to each back surface electrode 15 (drain electrode) of the multiple first semiconductor elements 10A.

[0059] The second signal terminals 47A to 47D may be arranged at intervals in the second direction y. The second signal terminals 47A to 47D may be supported by the second conductive portion 32B via the second sub-substrate 48B, as shown in Figures 2, 3, 5, 6, 8, 18, etc. The second signal terminals 47A to 47D may be located between the second semiconductor elements 10B and the third terminals 43 in the first direction x, as shown in Figure 5.

[0060] 18 , the second signal terminal 47A may be disposed on the terminal portion 4822A. The second signal terminal 47A may be a terminal (gate terminal) for inputting drive signals to the plurality of second semiconductor elements 10B. A drive signal for driving the plurality of second semiconductor elements 10B may be input to the second signal terminal 47A (for example, a gate voltage may be applied).

[0061] The second signal terminal 47B may be disposed on the terminal portion 4822B. The second signal terminal 47B may be a terminal for detecting source signals (source sense terminal) of the multiple second semiconductor elements 10B. The second signal terminal 47B can detect a voltage (a voltage corresponding to a source current) applied to each second main surface electrode 12 (source electrode) of the multiple second semiconductor elements 10B.

[0062] The second signal terminal 47C may be disposed on the terminal portion 4822C. The second signal terminal 47D may be disposed on the terminal portion 4822D. The second signal terminals 47C and 47D may be terminals that are electrically connected to the thermistor 17.

[0063] 12 and 17 to 20, each of the plurality of signal terminals 45 (the plurality of first signal terminals 46A, 46B, and 46E and the plurality of second signal terminals 47A to 47D) includes an extending portion 451 and a rod-shaped portion 452. The signal terminals 45 may include a conductive material typified by metals such as Cu (copper), Fe (iron), and Ni (nickel).

[0064] The rod-shaped portion 452 is a rod-shaped portion extending in the thickness direction z. As shown in FIGS. 1 and 12 , the rod-shaped portion 452 protrudes from the sealing resin 8 toward the z1 side in the thickness direction z. In the illustrated example, the rod-shaped portion 452 may include a thick-diameter portion 4521. The thick-diameter portion 4521 may be provided near an end of the rod-shaped portion 452 on the z1 side in the thickness direction z. The thick-diameter portion 4521 has a larger dimension in a direction perpendicular to the thickness direction z than other portions of the rod-shaped portion 452. The thick-diameter portion 4521 may be press-fitted into a through-hole provided in a control board (not shown) external to the semiconductor device A1 when the signal terminal 45 is connected to the control board.

[0065] The extension portion 451 extends from the rod-shaped portion 452 when viewed in the z direction, which is the direction of the central axis of the rod-shaped portion 452. As shown in Fig. 20 , the extension portion 451 is directly bonded to the first sub-metal layer 482. There are no particular limitations on the method for directly bonding the extension portion 451 to the first sub-metal layer 482, and ultrasonic bonding, laser bonding, solid-state diffusion bonding, or the like may be used as appropriate. In this example, ultrasonic bonding may be used.

[0066] As shown in FIGS. 19 and 20 , the extension portion 451 may have a thick portion 4511 and a thin portion 4512. The thick portion 4511 is connected to the rod-shaped portion 452. The thin portion 4512 includes a portion located on the opposite side of the thick portion 4511 from the rod-shaped portion 452. The thickness of the thick portion 4511 is thinner than the thickness of the thin portion 4512. In the illustrated example, both the thick portion 4511 and the thin portion 4512 are annular. When ultrasonic bonding is used as the bonding method for the extension portion 451, the extension portion 451 is likely to include the thick portion 4511 and the thin portion 4512. Furthermore, the thin portion 4512 may mainly contribute to the bonding between the extension portion 451 and the first sub-metal layer 482.

[0067] 20, the extending portion 451 and a part of the rod-shaped portion 452 can be housed in a through-hole 85 of the sealing resin 8. The signal terminal 45 may be separated from the sealing resin 8.

[0068] First Conductive Member 5, Second Conductive Member 6: The first conductive member 5 and the second conductive member 6, together with the first conductive portion 32A and the second conductive portion 32B, can form a path for a main circuit current switched by the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B. The first conductive member 5 and the second conductive member 6 can be spaced apart from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z and can overlap the first main surface 301A and the second main surface 301B in a plan view. In this embodiment, the first conductive member 5 and the second conductive member 6 can each be made of a metal plate material. The metal can include, for example, Cu (copper) or a Cu (copper) alloy. Specifically, the first conductive member 5 and the second conductive member 6 can be made of an appropriately bent metal plate material.

[0069] The first conductive member 5 is connected to the second principal surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 32B, and can electrically connect the second principal surface electrode 12 of each first semiconductor element 10A and the second conductive portion 32B. The first conductive member 5 can form a path for a main circuit current switched by the multiple first semiconductor elements 10A. As shown in FIGS. 7 and 8 , the first conductive member 5 can include a main portion 51, multiple first bonding portions 52, and multiple second bonding portions 53.

[0070] The main portion 51 may be a strip-shaped portion located between the plurality of first semiconductor elements 10A and the second conductive portion 32B in the first direction x and extending in the second direction y in a plan view. The main portion 51 may overlap both the first conductive portion 32A and the second conductive portion 32B in a plan view and be spaced apart in the thickness direction z from the first main surface 301A and the second main surface 301B on the z1 side in the thickness direction z. As shown in FIG. 16 and other figures, the main portion 51 may be located on the z2 side in the thickness direction z with respect to a third path portion 66 and a fourth path portion 67 of the second conductive member 6 described later and closer to the first main surface 301A and the second main surface 301B than the third path portion 66 and the fourth path portion 67.

[0071] In this embodiment, the main portion 51 can be disposed parallel (or approximately parallel) to the first main surface 301A and the second main surface 301B.

[0072] As shown in FIG. 8 and other figures, the main portion 51 may extend continuously in the second direction y to correspond to the region in which the multiple first semiconductor elements 10A are arranged. In this embodiment, as shown in FIGS. 7 , 8 , 12 , and other figures, multiple first openings 514 are formed in the main portion 51. Each of the multiple first openings 514 may be a through hole penetrating in the thickness direction z (the plate thickness direction of the main portion 51), for example. The multiple first openings 514 may be arranged at intervals in the second direction y. The multiple first openings 514 may be provided corresponding to each of the multiple first semiconductor elements 10A. In this embodiment, four first openings 514 are provided in the main portion 51, and these first openings 514 and the multiple (four) first semiconductor elements 10A may be positioned at the same position in the second direction y.

[0073] 8, 12, etc., in the present embodiment, each first opening 514 can overlap a gap between the first conductive portion 32A and the second conductive portion 32B in a plan view. The multiple first openings 514 can be formed to facilitate the flow of a resin material between an upper side (the z1 side in the thickness direction z) and a lower side (the z2 side in the thickness direction z) near the main portion 51 (first conductive member 5) when injecting the flowable resin material to form the sealing resin 8.

[0074] As shown in FIG. 8 and other figures, the multiple first bonding portions 52 and the multiple second bonding portions 53 are connected to the main portion 51 and may be arranged corresponding to the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B. Specifically, each first bonding portion 52 may be located on the x1 side of the main portion 51 in the first direction x. Each second bonding portion 53 is located on the x2 side of the main portion 51 in the first direction x. As shown in FIG. 13 , the multiple first bonding portions 52 may be individually bonded to the second principal surface electrodes 12 of the multiple first semiconductor elements 10A via conductive bonding materials 59. The multiple second bonding portions 53 and the second conductive portion 32B may be bonded to each other via the conductive bonding material 59. The material of the conductive bonding material 59 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the first bonding portion 52 may have two portions spaced apart in the second direction y.

[0075] The second conductive member 6 can electrically connect the second main surface electrode 12 (source electrode) of each second semiconductor element 10B to the first terminal 41 and the second terminal 42. The second conductive member 6 can be formed integrally with the first terminal 41 and the second terminal 42. The second conductive member 6 can constitute a path of a main circuit current switched by the plurality of second semiconductor elements 10B. As shown in FIGS. 2 and 5 to 7 , the second conductive member 6 can include a plurality of third joint portions 61, a first path portion 64, a second path portion 65, a plurality of third path portions 66, and a fourth path portion 67.

[0076] The multiple third bonding portions 61 may be portions that are individually bonded to the multiple second semiconductor elements 10B. Each third bonding portion 61 and the second principal surface electrode 12 of each second semiconductor element 10B may be bonded via a conductive bonding material 69. The constituent material of the conductive bonding material 69 is not particularly limited and may be, for example, solder, a metal paste material, or a sintered metal. In this embodiment, the third bonding portion 61 may have two flat portions 611 and two first inclined portions 612.

[0077] The two flat portions 611 may be aligned in the second direction y. The two flat portions 611 may be spaced apart from each other in the second direction y. The shape of the flat portions 611 is not limited in any way and may be rectangular in the illustrated example. The two flat portions may be joined to the second principal surface electrode 12 on both sides in the second direction y.

[0078] The two first inclined portions 612 may be connected to the outer sides of the two flat portions 611 in the second direction y. That is, the first inclined portion 612 located on the y1 side in the second direction y may be connected to the y1 side in the second direction y of the flat portion 611 located on the y1 side in the second direction y. Furthermore, the first inclined portion 612 located on the y2 side in the second direction y may be connected to the y2 side in the second direction y of the flat portion 611 located on the y2 side in the second direction y. The first inclined portion 612 may be inclined to be located closer to the z1 side in the thickness direction z as it becomes farther away from the flat portion 611 in the second direction y.

[0079] The first path portion 64 may be interposed between the plurality of third joint portions 61 and the first terminal 41. In the illustrated example, the first path portion 64 may be connected to the first terminal 41 via a first step portion 602. The first path portion 64 may overlap the first conductive portion 32A in a plan view. The first path portion 64 may have a shape that extends as a whole in the first direction x.

[0080] The first path portion 64 may include a first band-shaped portion 641 and a first extending portion 643. The first band-shaped portion 641 may be located on the x2 side in the first direction x with respect to the first terminal 41, and may be substantially parallel to the first main surface 301A. The first band-shaped portion 641 may have a shape that extends as a whole in the first direction x.

[0081] The first extending portion 643 may extend from a side end of the first strip portion 641 on the y1 side in the second direction y to the z2 side in the thickness direction z. The first extending portion 643 is spaced apart from the first conductive portion 32A. In the illustrated example, the first extending portion 643 may have a shape that follows the thickness direction z and is an elongated rectangle with the first direction x as its longitudinal direction. The first path portion 64 may not have the first extending portion 643.

[0082] The second path portion 65 may be interposed between the plurality of third joint portions 61 and the second terminal 42. In the illustrated example, the second path portion 65 may be connected to the second terminal 42 via a second step portion 603. The second path portion 65 overlaps the first conductive portion 32A in a plan view. The second path portion 65 may have a shape that extends as a whole in the first direction x.

[0083] The second path portion 65 may include a second band portion 651 and a second extending portion 653. The second band portion 651 may be located on the x2 side in the first direction x with respect to the second terminal 42, and may be substantially parallel to the first main surface 301A. The second band portion 651 may have a shape that extends in the first direction x as a whole.

[0084] The second extending portion 653 may extend from the side end of the second strip portion 651 on the y2 side in the second direction y to the z2 side in the thickness direction z. The second extending portion 653 is spaced apart from the first conductive portion 32A. In the illustrated example, the second extending portion 653 may have a shape that follows the thickness direction z and is an elongated rectangle with the first direction x as its longitudinal direction. Note that the second path portion 65 may not have the second extending portion 653.

[0085] The multiple third path portions 66 may be individually connected to the multiple third joint portions 61. Each third path portion 66 may have a shape extending in the first direction x and be arranged spaced apart from one another in the second direction y. The number of the multiple third path portions 66 is not limited in any way, and in the illustrated example, five third path portions 66 may be arranged. Each third path portion 66 may be arranged so as to be located between the multiple second semiconductor elements 10B in the second direction y, or so as to be located outward of the multiple second semiconductor elements 10B in the second direction y.

[0086] In the present embodiment, one third joint 61 may be disposed between two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y1 side in the second direction y may be connected to the third path portion 66 located on the y1 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y. In one third joint 61, the first inclined portion 612 located on the y2 side in the second direction y may be connected to the third path portion 66 located on the y2 side in the second direction y, of the two third path portions 66 adjacent to each other in the second direction y.

[0087] The fourth path portion 67 may be connected to ends of the plurality of third path portions 66 on the x1 side in the first direction x. The fourth path portion 67 may have a shape that extends elongatedly in the second direction y. The fourth path portion 67 may be connected to ends of the first band portion 641 of the first path portion 64 and the second band portion 651 of the second path portion 65 on the x2 side in the first direction x. In the illustrated example, the first path portion 64 may be connected to an end of the fourth path portion 67 on the y1 side in the second direction y. Furthermore, the second path portion 65 may be connected to an end of the fourth path portion 67 on the y2 side in the second direction y.

[0088] Sealing resin 8: The sealing resin 8 may cover the multiple first semiconductor elements 10A, the multiple second semiconductor elements 10B, the main substrate 3 (excluding the back surface 302), portions of the first terminal 41, the second terminal 42, the multiple third terminals 43, and the multiple fourth terminals 44, portions of the multiple signal terminals 45, the first sub-substrate 48A and the second sub-substrate 48B, the first conductive member 5, the second conductive member 6, and the multiple wires 71 to 73. The sealing resin 8 may be composed of, for example, a black epoxy resin. The sealing resin 8 may be formed, for example, by molding. The size of the sealing resin 8 is not limited in any way, and may be, for example, approximately 35 mm to 60 mm in the first direction x, approximately 35 mm to 50 mm in the second direction y, and approximately 4 mm to 15 mm in the thickness direction z. These dimensions may be the size of the largest portion along each direction. The sealing resin 8 can have a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0089] The resin main surface 81 and the resin back surface 82 may be spaced apart in the thickness direction z, as shown in FIGS. 10 , 12 , and 15 . The resin main surface 81 may face the z1 side in the thickness direction z, and the resin back surface 82 may face the z2 side in the thickness direction z. A plurality of signal terminals 45 (a plurality of first signal terminals 46A, 46B, and 46E and a plurality of second signal terminals 47A to 47D) may protrude from the resin main surface 81. As shown in FIG. 11 , the resin back surface 82 may have a frame shape surrounding the back surface 302 (the lower surface of the second main metal layer 33) of the main substrate 3 in a plan view. The back surface 302 of the main substrate 3 may be exposed from the resin back surface 82 and may be flush with the resin back surface 82, for example.

[0090] Each of the multiple resin side surfaces 831 to 834 may be connected to both the resin main surface 81 and the resin back surface 82 and may be sandwiched between them in the thickness direction z. As shown in FIG. 4 and other figures, the resin side surface 831 and the resin side surface 832 may be spaced apart in the first direction x. The resin side surface 831 may face the x2 side of the first direction x, and the resin side surface 832 may face the x1 side of the first direction x. Two third terminals 43 may protrude from the resin side surface 831, and the first terminal 41, the second terminal 42, and the fourth terminal 44 may protrude from the resin side surface 832. As shown in FIG. 4 and other figures, the resin side surface 833 and the resin side surface 834 may be spaced apart in the second direction y. The resin side surface 833 may face the y2 side of the second direction y, and the resin side surface 834 may face the y1 side of the second direction y.

[0091] 4 , a plurality of recesses 832a may be formed in the resin side surface 832. Each recess 832a may be a portion recessed in the first direction x in a plan view. The plurality of recesses 832a may include one formed between the first terminal 41 and the fourth terminal 44 and one formed between the second terminal 42 and the fourth terminal 44 in a plan view. The plurality of recesses 832a may be provided to increase the creepage distance along the resin side surface 832 between the first terminal 41 and the fourth terminal 44 and the creepage distance along the resin side surface 832 between the second terminal 42 and the fourth terminal 44.

[0092] The sealing resin 8 may have a plurality of through holes 85. Each of the plurality of through holes 85 opens to the resin main surface 81 and reaches the support body 1. Each through hole 85 may accommodate a portion of the signal terminal 45.

[0093] Next, a vehicle B1 equipped with the semiconductor device A1 will be described with reference to Fig. 21. The vehicle B1 is, for example, an electric vehicle (EV).

[0094] As shown in Fig. 21 , vehicle B1 includes an on-board charger 91, a storage battery 92, and a drive system 93. Power is supplied to the on-board charger 91 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power may be supplied from the power supply facility to the on-board charger 91 via a wired connection. The on-board charger 91 is configured with a step-up DC-DC converter. The voltage of the power supplied to the on-board charger 91 is stepped up by the converter and then supplied to the storage battery 92. The stepped-up voltage is, for example, 600 V.

[0095] The drive system 93 drives the vehicle B1. The drive system 93 has an inverter 931 and a drive source 932. The semiconductor device A1 constitutes part of the inverter 931. Power stored in the storage battery 92 is supplied to the inverter 931. The power supplied from the storage battery 92 to the inverter 931 is DC power. In addition, unlike the power system shown in FIG. 20 , a step-up DC-DC converter may be further provided between the storage battery 92 and the inverter 931. The inverter 931 converts DC power into AC power. The inverter 931 including the semiconductor device A1 is electrically connected to the drive source 932.

[0096] The drive source 932 includes an AC motor and a transmission. When AC power converted by the inverter 931 is supplied to the drive source 932, the AC motor rotates and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and then rotates the drive shaft of the vehicle B1. This drives the vehicle B1. To drive the vehicle B1, it is necessary to freely control the rotation speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. The semiconductor device A1 in the inverter 931 is required to output AC power whose frequency has been appropriately changed to correspond to the required rotation speed of the AC motor.

[0097] Next, a method for manufacturing the semiconductor device A1 will be described below with reference to FIG.

[0098] First, prepare the support body 1. In this embodiment, the support body 1 may have a configuration in which a first sub-substrate 48A and a second sub-substrate 48B are joined to a main substrate 3 with a conductive bonding material 49.

[0099] Next, the first semiconductor element 10A and the second semiconductor element 10B are mounted, the wires 71, 72, and 73 are bonded, and the first terminal 41, the second terminal 42, the third terminal 43, the fourth terminal 44, the first conductive member 5, and the second conductive member 6 are attached as appropriate. Then, the sealing resin 8 is formed. The sealing resin 8 may have a through hole 85 formed therein.

[0100] Next, the multiple signal terminals 45 are joined. The first signal terminal 46A will be described as an example of joining the multiple signal terminals 45, but a similar method may be used for the other signal terminals 45. The extending portion 451 of the first signal terminal 46A is placed on the first sub-metal layer 482 of the first sub-substrate 48A.

[0101] Next, the tool TL is pressed against the extension portion 451 from the z1 side in the thickness direction z. The tool TL is connected to, for example, an ultrasonic generator or the like and can transmit ultrasonic waves. With the tool TL pressed against the extension portion 451 with a predetermined pressing force, ultrasonic waves are applied from the tool TL to the extension portion 451. As a result, a portion of the extension portion 451 is thinned by the pressing, and can become a thin-walled portion 4512. Furthermore, the thin-walled portion 4512 can be ultrasonically bonded to the first sub-metal layer 482 and directly bonded to the first sub-metal layer 482. In the illustrated example, the tool TL is cylindrical and can accommodate the rod-shaped portion 452.

[0102] Through the above steps, the semiconductor device A1 is obtained.

[0103] Next, the operation of the semiconductor device A1 will be described.

[0104] In this embodiment, the extension portion 451 is directly bonded to the support body 1. This reduces the possibility of the extension portion 451 becoming misaligned when the solder melts during soldering. Furthermore, while there is concern that the mechanical bond strength and electrical conductivity of the extension portion 451 may be inadequate if the soldering is insufficient, this embodiment reduces such concerns. Therefore, the signal terminal 45 can be more appropriately fixed.

[0105] The support body 1 includes the first signal terminals 46A and 46B, and the extending portions 451 of the plurality of signal terminals 45 are directly bonded to the first signal terminals 46A and 46B. The first signal terminals 46A and 46B are easier to pattern into finer conductive portions than the main substrate 3. This allows for improved electrical functionality and miniaturization.

[0106] The through-hole 85 provided in the sealing resin 8 allows, for example, a tool TL for joining the extension portion 451 to come into contact with the extension portion 451 .

[0107] 23 to 39 show modified examples and other embodiments of the present disclosure. In these figures, elements that are the same as or similar to those in the above-described embodiment are given the same reference numerals. Furthermore, the configurations of the various parts in each modified example and each embodiment can be combined with each other as appropriate within the scope of not causing technical contradictions.

[0108] First Modification of First Embodiment: Figure 23 shows a first modification of the manufacturing method of the semiconductor device A1. In this modification, laser bonding is used to bond the extension portion 451 to the support 1 (first sub-metal layer 482). In this case, the extension portion 451 of the semiconductor device A11 of this modification may be configured without the thin portion 4512. This modification also allows the signal terminal 45 to be more appropriately fixed.

[0109] 24 to 29 show other examples of the extension portion 451. FIG.

[0110] 24 , the extension portion 451 may include a plurality of band-shaped portions 4513. The plurality of band-shaped portions 4513 may extend radially from the rod-shaped portion 452. In this example, the extension portion 451 may have four band-shaped portions 4513, and the angles formed between the band-shaped portions 4513 may be approximately 90°.

[0111] 25, the extension portion 451 has two band-shaped portions 4513. The two band-shaped portions 4513 may extend in opposite directions with the rod-shaped portion 452 in between.

[0112] 26, the extension portion 451 has three band-shaped portions 4513. The angle formed by each of the three band-shaped portions 4513 may be approximately 60°.

[0113] 27, the extension portion 451 has one strip-shaped portion 4513. The strip-shaped portion 4513 may extend from the rod-shaped portion 452 in the second direction y.

[0114] In the example shown in FIG. 28, two thick portions 4511 may be provided on the inside and outside with a thin portion 4512 sandwiched therebetween.

[0115] 29, there may be provided a plurality of thinned portions 4512. In the illustrated example, four thinned portions 4512 may be arranged on a circle centered on the rod-shaped portion 452. The angles formed by each of the four thinned portions 4512 are approximately 90°.

[0116] As can be seen from the examples shown in FIGS. 24 to 29, the shape of the extension portion 451 is not limited in any way.

[0117] 30 shows a second modification of the semiconductor device A1. In the semiconductor device A12 of this modification, the thickness of the first sub-metal layer 482 may be thicker than the thickness of the second sub-metal layer 483. This configuration is advantageous for increasing the bonding strength when the extension portion 451 is directly bonded to the first sub-metal layer 482 using ultrasonic bonding, laser bonding, or the like.

[0118] Third Modification of First Embodiment: FIG. 31 shows a third modification of the semiconductor device A1. In a semiconductor device A13 of this embodiment, the first sub-substrate 48A may further include a spacer 489. The spacer 489 may be disposed on the first sub-metal layer 482. The spacer 489 may include a metal such as Cu (copper). The spacer 489 may be bonded to the first sub-metal layer 482 by, for example, solder bonding, ultrasonic bonding, or the like. In the illustrated example, the spacer 489 may be bonded to the first sub-metal layer 482 via a conductive bonding material 4899 such as solder. The extension portion 451 may be bonded to the spacer 489 by, for example, laser bonding.

[0119] According to this modified example, even if the thickness of the first sub-metal layer 482 is not sufficient when the extension portion 451 is joined to the first sub-metal layer 482 by laser joining, the spacer 489 can ensure the thickness of the metal portion required for laser joining.

[0120] 32 shows a fourth modification of the semiconductor device A1. The through-hole 85 of the semiconductor device A14 of this modification may be tapered or stepped, for example.

[0121] According to this modification, the through-hole 85 has a tapered shape, which makes it easy to position the tool TL inside the through-hole 85. In addition, there is an advantage that, when performing laser joining, it is easy to irradiate the extending portion 451 with laser light from an oblique angle.

[0122] Fifth Modification of First Embodiment: Figure 33 shows a fifth modification of the semiconductor device A1. In the semiconductor device A15 of this modification, the through-holes 85 may be filled with a filled resin 89. The filled resin 89 may be formed, for example, by filling the through-holes 85 with a liquid resin material and curing the resin material in the configuration shown in Figure 20. There are no particular limitations on the material of the filled resin 89, and it may be, for example, epoxy resin, silicone resin, or the like.

[0123] This modification allows the signal terminal 45 to be more appropriately fixed. The provision of the filling resin 89 more reliably achieves insulation from the outside of the semiconductor device A15. Furthermore, the filling resin 89 allows the first signal terminal 46A (signal terminal 45) to be more firmly supported.

[0124] 34 to 36 show a sixth modification of the semiconductor device A1. In the semiconductor device A16 of this modification, the configurations of the through holes 85 and the signal terminals 45 may differ from those in the above-described examples.

[0125] The through hole 85 may have a first surface 851 and a second surface 852. The first surface 851 and the second surface 852 may be located on opposite sides in the x direction across the signal terminal 45. The distance between the rod-shaped portion 452 and the second surface 852 may be greater than the distance between the rod-shaped portion 452 and the first surface 851 as it moves from the extending portion 451 toward the tip of the rod-shaped portion 452.

[0126] The second surface 852 may be inclined with respect to the rod-shaped portion 452. The second surface 852 may be a flat surface. The first surface 851 may be along the thickness direction z. The first surface 851 may be a concave curved surface.

[0127] The signal terminals 45 and the through holes 85 are aligned in the second direction y. The second surface 852 extends from the signal terminals 45 in the first direction x that intersects with the second direction y.

[0128] The rod-shaped portion 452 is connected to a portion of the extending portion 451 that is closer to the first surface 851 in the x direction than the second surface 852. In other words, the rod-shaped portion 452 is closer to the second surface 852 and the first surface 851.

[0129] This modification makes it possible to more appropriately fix the signal terminal 45. The through hole 85 having the second surface 852 has the advantage that the tool TL and laser light can be more easily applied to the extending portion 451 when joining the extending portion 451. The multiple through holes 85 are aligned in the second direction y, and the second surfaces 852 extend in the first direction x, thereby reducing interference between the second surfaces 852 of one of the adjacent through holes 85 and the other through hole 85.

[0130] 37 to 39 show a semiconductor device according to a second embodiment of the present disclosure. In the semiconductor device A2 of this embodiment, the support body 1 is formed by the main substrate 3, and does not include a first sub-substrate 48A or a second sub-substrate 48B. The extending portions 451 of the multiple signal terminals 45 can be directly bonded to the support body 1.

[0131] 38 , the first conductive portion 32A may have a first portion 320A, a second portion 321A, and a third portion 322A. A plurality of first semiconductor elements 10A may be mounted on the first portion 320A. An extending portion 451 of the first signal terminal 46E may be directly joined to the first portion 320A.

[0132] The second portion 321A may be directly joined to the extending portion 451 of the first signal terminal 46A, and may be connected to a plurality of wires 71. The third portion 322A may be directly joined to the extending portion 451 of the first signal terminal 46B, and may be connected to a plurality of wires 72.

[0133] The second conductive portion 32B can have a first portion 320B, a second portion 321B, a third portion 322B, a fourth portion 323B, and a fifth portion 324B. A plurality of second semiconductor elements 10B may be mounted on the first portion 320B.

[0134] The second portion 321B may be directly joined to the extending portion 451 of the second signal terminal 47A, and may be connected to a plurality of wires 71. The third portion 322B may be directly joined to the extending portion 451 of the second signal terminal 47B, and may be connected to a plurality of wires 72.

[0135] The fourth portion 323B may be directly joined to the extending portion 451 of the second signal terminal 47C, and may be connected to the thermistor 17. The fifth portion 324B may be directly joined to the extending portion 451 of the second signal terminal 47D, and may be connected to the thermistor 17.

[0136] 39 , the extending portion 451 may be directly bonded to the first conductive portion 32A (first main metal layer 32) of the main substrate 3. There are no particular limitations on the method for directly bonding the extending portion 451, and ultrasonic bonding, laser bonding, solid-state diffusion bonding, or the like may be used as appropriate. When ultrasonic bonding is used, the extending portion 451 may have a thick portion 4511 and a thin portion 4512.

[0137] This embodiment makes it possible to more appropriately fix the signal terminals 45. Since the support 1 is composed only of the main substrate 3, it is possible to reduce the number of parts and the dimension of the semiconductor device A2 in the thickness direction z.

[0138] The semiconductor device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of the semiconductor device according to the present disclosure can be freely modified in various ways. The present disclosure includes the embodiments described in the following appendices.

[0139] Supplementary Note 1. A semiconductor device (A1) comprising: a support (1); a first semiconductor element (10A) supported by the support (1); a first signal terminal (46A) electrically connected to the first semiconductor element (10A); and a sealing resin (8) covering the first semiconductor element (10A), wherein the first signal terminal (46A) includes a rod-shaped portion (452) protruding from the sealing resin (8) and an extension portion (451) extending from the rod-shaped portion (452) when viewed in the direction of the central axis of the rod-shaped portion (452), and the extension portion (451) is directly bonded to the support (1). Supplementary Note 2. The semiconductor device (A1) according to Supplementary Note 1, wherein the extending portion (451) includes a thick portion (4511) connected to the rod-shaped portion (452) and a thin portion (4512) including a portion of the thick portion (4511) located on the opposite side of the rod-shaped portion (452) from the rod-shaped portion (452). Supplementary Note 3. The semiconductor device (A12) according to Supplementary Note 1 or 2, wherein the sealing resin (8) has a through hole (85), and at least a portion of the first signal terminal (46A) is accommodated in the through hole (85) and is separated from the sealing resin (8). Supplementary Note 4. The semiconductor device (A1) according to any of Supplements 1 to 3, wherein the extending portion (451) is circular. Supplementary Note 5. The semiconductor device (A1) according to any of Supplements 1 to 3, wherein the extending portion (451) includes one or more strip-shaped portions (4513). Supplementary Note 6. The semiconductor device (A1) according to Supplementary Note 5, wherein the extension portion (451) includes a plurality of the strip-shaped portions (4513). Supplementary Note 7. The semiconductor device (A1) according to Supplementary Note 6, wherein the plurality of strip-shaped portions (4513) are arranged radially. Supplementary Note 8. The semiconductor device (A1) according to any one of Supplements 1 to 7, wherein the support (1) includes a main substrate (3) and a first sub-substrate (48A) mounted on the main substrate (3), and the extension portion (451) is directly bonded to the first sub-substrate (48A). Supplementary Note 9. The semiconductor device (A1) according to Supplementary Note 8, wherein the first sub-substrate (48A) includes a sub-insulating layer (481), a first sub-metal layer (482), and a second sub-metal layer (483) located on the opposite side of the sub-insulating layer (481) from the first sub-metal layer (482), and the extension portion (451) is directly bonded to the first sub-metal layer (482).Appendix 10. The semiconductor device (A11) according to Appendix 9, wherein the first auxiliary metal layer (482) is thicker than the second auxiliary metal layer (483). Appendix 11. The semiconductor device (A1) according to Appendix 9 or 10, wherein the main substrate (3) includes a main insulating layer (31), a first main metal layer (32), and a second main metal layer (33) located on the opposite side of the main insulating layer (31) from the first main metal layer (32), and the first auxiliary substrate (48A) is bonded to the first main metal layer (32). Appendix 12. The semiconductor device (A2) according to any one of Supplementary Notes 1 to 7, wherein the support (1) includes a main substrate (3), the main substrate (3) including a main insulating layer (31), a first main metal layer (32), and a second main metal layer (33) located on the opposite side of the first main metal layer (32) with the main insulating layer (31) sandwiched therebetween, and the extension portion (451) is directly bonded to the first main metal layer (32).Supplementary Note 13. The semiconductor device (A2) according to Supplementary Note 3, wherein the through hole (85) includes a first surface (851) and a second surface (852) located on opposite sides in a first direction with the first signal terminal (46A) sandwiched therebetween, and the distance between the rod-shaped portion (452) and the second surface (852) is greater from the extension portion (451) toward the tip of the rod-shaped portion (452).Supplementary Note 14. The semiconductor device (A2) according to Appendix 13, wherein the second surface (852) is inclined with respect to the rod-shaped portion (452). Appendix 15. The semiconductor device (A2) according to Appendix 13 or 14, wherein the rod-shaped portion (452) is connected to a portion of the extending portion (451) that is closer to the first surface (851) than the second surface (852) in the x-direction. Appendix 16. The semiconductor device (A2) according to any one of Appendixes 13 to 15, comprising a plurality of the first signal terminals (46A), wherein the sealing resin (8) has a plurality of the through holes (85), and wherein the plurality of first signal terminals (46A) and the plurality of through holes (85) are aligned in a second direction (y) intersecting the first direction (x). Appendix 17. The semiconductor device (A14) according to Appendix 3, wherein the through holes (85) are tapered.Appendix 18. The semiconductor device (A15) according to Appendix 3, further comprising a filled resin (89) filled in the through hole (85) and in contact with the first signal terminal (46A). Appendix 19. The semiconductor device (A13) according to any one of claims 1 to 18, wherein the support (1) includes a spacer (489) to which the extension portion (451) is joined.

[0140] A1, A11, A12, A13, A14, A15, A16, A2: semiconductor device 1: support 3: main substrate 5: first conductive member 6: second conductive member 8: sealing resin 10A: first semiconductor element 10B: second semiconductor element 11: first principal surface electrode 12: second principal surface electrode 13: third principal surface electrode 15: back surface electrode 17: thermistor 19A: first conductive bonding material 19B: second conductive bonding material 31: main insulating layer 32: first main metal layer 32A: first conductive portion 32B: second conductive portion 33: second main metal layer 41: first terminal 42: second terminal 43: third terminal 44: fourth terminal 45: signal terminal 46A, 46B: first signal terminal 47A, 47B, 47C, 47D: Second signal terminal 48A: First sub-board 48B: Second sub-board 49: Conductive bonding material 51: Main portion 52: First joint portion 53: Second joint portion 59: Conductive bonding material 61: Third joint portion 64: First path portion 65: Second path portion 66: Third path portion 67: Fourth path portion 69: Conductive bonding material 71: Wire 72: Wire 73: Wire 81: Resin main surface 82: Resin back surface 85: Through hole 89: Filled resin 91: On-board charger 92: Storage battery 93: Drive system 101: Element main surface 102: Element back surface 301A: First main surface 301B: Second main surface 302: Back surface 320A, 320B: First portion 321A, 321B: Second portion 322A, 322B: Third portion 323B: Fourth portion 324B: Fifth portion 451: Extension portion 452: Rod-shaped portion 481: Sub-insulation layer 482: First sub-metal layer 482A, 482B, 482C, 482D, 482E, 482F: Region 483: Second sub-metal layer 489: Spacer 514: First opening 602: First step portion 603: Second step portion 611: Flat portion 612: First inclined portion 641: First strip-shaped portion 643: First extension portion 651: Second strip-shaped portion 653: Second extension portion 831, 832: Resin side surface 832a: Recessed portion 833, 834: Resin side surface 851: First surface 852: Second surface 931: Inverter 932: Driving source 4511: Thick portion 4512: Thin portion 4513: Belt-shaped portion 4521: Large diameter portion 4821A, 4821B, 4821C, 4821D: Connection portion 4822A, 4822B,4822C, 4822D: Terminal portion 4829: Surface metal layer 4899: Conductive bonding material B1: Vehicle TL: Tool x: First direction y: Second direction z: Thickness direction

Claims

1. A semiconductor device comprising a support, a first semiconductor element supported by the support, a first signal terminal electrically connected to the first semiconductor element, and a sealing resin covering the first semiconductor element, wherein the first signal terminal includes a rod-shaped portion protruding from the sealing resin and an extending portion extending from the rod-shaped portion when viewed in the central axis direction of the rod-shaped portion, and the extending portion is directly bonded to the support.

2. The semiconductor device according to claim 1, wherein the extending portion includes a thick portion connected to the rod-shaped portion and a thin portion located on the side opposite to the rod-shaped portion with respect to at least a part of the thick portion.

3. The semiconductor device according to claim 1 or 2, wherein the sealing resin has a through hole, and at least a part of the first signal terminal is accommodated in the through hole and is separated from the sealing resin.

4. The semiconductor device according to any one of claims 1 to 3, wherein the extending portion is circular.

5. The semiconductor device according to any one of claims 1 to 3, wherein the extending portion includes one or more strip-shaped portions.

6. The semiconductor device according to claim 5, wherein the extending portion includes a plurality of the strip-shaped portions.

7. The semiconductor device according to claim 6, wherein the plurality of strip-shaped portions are arranged radially.

8. The semiconductor device according to any one of claims 1 to 7, wherein the support includes a main substrate and a first sub-substrate mounted on the main substrate, and the extending portion is directly bonded to the first sub-substrate.

9. The semiconductor device according to claim 8, wherein the first sub-substrate includes a sub-insulating layer, a first sub-metal layer, and a second sub-metal layer located on the side opposite to the first sub-metal layer with the sub-insulating layer interposed therebetween, and the extending portion is directly bonded to the first sub-metal layer.

10. The semiconductor device according to claim 9, wherein the first sub-metal layer is thicker than the second sub-metal layer.

11. The semiconductor device according to claim 9 or 10, wherein the main substrate includes a main insulating layer, a first main metal layer, and a second main metal layer located on the side opposite to the first main metal layer with the main insulating layer interposed therebetween, and the first sub-substrate is bonded to the first main metal layer.

12. The semiconductor device according to any one of claims 1 to 7, wherein the support includes a main substrate, the main substrate includes a main insulating layer, a first main metal layer, and a second main metal layer located on the side opposite to the first main metal layer with the main insulating layer interposed therebetween, and the extending portion is directly bonded to the first main metal layer.

13. The through hole includes a first surface and a second surface that are respectively located on opposite sides in a first direction with the first signal terminal interposed therebetween. The distance between the rod-shaped portion and the second surface is greater than the distance between the rod-shaped portion and the first surface as going from the extending portion toward the tip of the rod-shaped portion. The semiconductor device according to claim 3.

14. The second surface is inclined with respect to the rod-shaped portion. The semiconductor device according to claim 13.

15. The rod-shaped portion is connected to a portion of the extending portion that is closer to the first surface than the second surface in the first direction. The semiconductor device according to claim 13 or 14.

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