Solid-state imaging device

Abstract

The present disclosure relates to a solid-state imaging device configured so that the power consumption thereof is reduced. Provided is a solid-state imaging device comprising a pixel array unit in which a plurality of pixels are arranged. The pixels include: a photoelectric conversion unit that converts incident light into an electric charge; a charge-to-voltage conversion unit that accumulates the electric charge obtained by photoelectric conversion; a conversion efficiency switching unit that is provided to the charge-to-voltage conversion unit and switches conversion efficiency; and a conversion efficiency switching control unit that controls the switching of conversion efficiency by the conversion efficiency switching unit, on the basis of the potential of the charge-to-voltage conversion unit. The present disclosure can be applied to, for example, a CMOS-type image sensor.

Description

solid-state imaging device

[0001] The present disclosure relates to a solid-state imaging device, and more particularly to a solid-state imaging device that is capable of reducing power consumption.

[0002] In a CMOS (Complementary Metal Oxide Semiconductor) image sensor, a DCG (Dual Conversion Gain) method is known as a technology for achieving both low noise due to high conversion efficiency and an expanded dynamic range due to low conversion efficiency (see, for example, Patent Document 1).

[0003] In the conventional DCG method, a conversion efficiency transistor is formed for the floating diffusion (FD), and the following operation is performed when reading out the charge stored in the photodiode (PD): First, the conversion efficiency transistor is turned off to read out at high conversion efficiency, and then the conversion efficiency transistor is turned on to read out at low conversion efficiency. By combining these two readout signals, both of the above are achieved.

[0004] Japanese Patent Application Publication No. 2017-216513

[0005] However, when reading out pixel output, it was necessary to read out both high conversion efficiency data and low conversion efficiency data separately, which took a long time to read out, making it impossible to increase the frame rate and potentially increasing power consumption.

[0006] The present disclosure has been made in light of these circumstances, and aims to make it possible to reduce power consumption.

[0007] A solid-state imaging device according to one aspect of the present disclosure includes a pixel array section in which a plurality of pixels are arranged, and the pixels each include a photoelectric conversion section that converts incident light into an electric charge, a charge-voltage conversion section that accumulates the electric charge obtained by the photoelectric conversion, a conversion efficiency switching section that is provided for the charge-voltage conversion section and switches the conversion efficiency, and a conversion efficiency switching control section that controls the switching of the conversion efficiency by the conversion efficiency switching section based on the potential of the charge-voltage conversion section.

[0008] A solid-state imaging device according to one aspect of the present disclosure includes a pixel array unit having a plurality of pixels arranged therein, and each pixel includes a photoelectric conversion unit that converts incident light into electric charges, a charge-voltage conversion unit that accumulates the electric charges obtained by the photoelectric conversion, a conversion efficiency switching unit that is provided for the charge-voltage conversion unit and switches conversion efficiencies, and a conversion efficiency switching control unit that controls switching of the conversion efficiency by the conversion efficiency switching unit based on a potential of the charge-voltage conversion unit.

[0009] The solid-state imaging device according to one aspect of the present disclosure may be an independent device or an internal block constituting a single device.

[0010] 1 is a diagram showing an example configuration of an embodiment of a solid-state imaging device to which the present disclosure is applied. FIG. 1 is a circuit diagram showing an example configuration of a pixel in a first embodiment. FIG. 2 is a timing chart showing operation in the circuit configuration of the pixel in FIG. 2. FIG. 3 is a circuit diagram showing another example configuration of the pixel in FIG. 2. FIG. 4 is a circuit diagram showing an example configuration of a pixel in a second embodiment. FIG. 5 is a timing chart showing operation in the circuit configuration of the pixel in FIG. 5. FIG. 6 is a circuit diagram showing an example configuration of a pixel in a third embodiment. FIG. 7 is a timing chart showing operation in the circuit configuration of the pixel in FIG. 7. FIG. 8 is a circuit diagram showing an example configuration of a pixel in a fourth embodiment. FIG. 9 is a timing chart showing operation in the circuit configuration of the pixel in FIG. 9. FIG. 10 is a cross-sectional view showing an example structure of a pixel in a fifth embodiment. FIG. 11 is a cross-sectional view showing an example structure of a pixel in a sixth embodiment. FIG. 12 is a cross-sectional view showing an example structure of a pixel in a seventh embodiment. FIG. 13 is a cross-sectional view showing an example structure of a pixel in an eighth embodiment. FIG. 14 is a diagram showing an example configuration of an electronic device equipped with a solid-state imaging device to which the present disclosure is applied.

[0011] <Device Configuration> FIG. 1 is a diagram showing an example of the configuration of an embodiment of a solid-state imaging device to which the present disclosure is applied.

[0012] 1, the solid-state imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and is composed of a pixel array section 11, a vertical driving section 12, a column signal processing section 13, a horizontal driving section 14, an output section 15, and a control section 16.

[0013] The pixel array unit 11 has a plurality of pixels 21 arranged two-dimensionally in a matrix on a semiconductor substrate made of silicon (Si) or the like. Each pixel 21 has a photodiode, a plurality of pixel transistors, etc. In the pixel array unit 11, for the plurality of pixels 21 arranged two-dimensionally in a matrix, a pixel drive line 31 is formed for each row and connected to the vertical drive unit 12, and a vertical signal line 32 is formed for each column and connected to the column signal processing unit 13.

[0014] The vertical drive unit 12 is composed of a shift register, an address decoder, etc., and drives each pixel 21 arranged in the pixel array unit 11. Signals output from the pixels 21 selected and scanned by the vertical drive unit 12 are supplied to the column signal processing unit 13 through vertical signal lines 32. The column signal processing unit 13 performs predetermined signal processing (e.g., noise removal processing, sampling processing, etc.) on signals output from each pixel 21 in a selected row through the vertical signal lines 32 for each pixel column in the pixel array unit 11, and temporarily stores the processed signals.

[0015] The horizontal drive unit 14 is composed of a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns of the column signal processing unit 13. By selective scanning by the horizontal drive unit 14, signals processed by the column signal processing unit 13 are output to the output unit 15 via horizontal signal lines 33. The output unit 15 performs predetermined signal processing on signals sequentially input via the horizontal signal lines 33 from each of the column signal processing units 13, and outputs the resulting signals.

[0016] The control unit 16 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 12, the column signal processing unit 13, the horizontal driving unit 14, etc. based on the various timing signals generated by the timing generator.

[0017] 2 is a circuit diagram showing an example of the configuration of a pixel in Embodiment 1. As shown in Fig. 2, the pixel 21 includes a photodiode PD, a transfer transistor TRG, a conversion efficiency transistor FDG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0018] The photodiode PD is a photoelectric conversion unit that converts incident light into electric charges and accumulates the photoelectrically converted charges. One of the source and drain of the transfer transistor TRG is connected to the photodiode PD, and the other is connected to the floating diffusion FD1. The transfer transistor TRG transfers the electric charges accumulated in the photodiode PD to the floating diffusion FD1 in response to a drive signal applied to its gate. The floating diffusion FD1 is a charge-voltage conversion unit that accumulates the electric charges. The floating diffusion FD1 is connected to the gate of the amplification transistor AMP, and the electric charges from the photodiode PD are converted into a voltage signal.

[0019] The conversion efficiency transistor FDG is a transistor that switches the conversion efficiency. One of the source and drain of the conversion efficiency transistor FDG is connected to the floating diffusion FD1, and the other is connected to the floating diffusion FD2. One of the source and drain of the reset transistor RST is connected to the floating diffusion FD2, and the other is connected to the power supply voltage VDD. The reset transistor RST resets the floating diffusions FD1 and FD2 in response to a drive signal applied to its gate.

[0020] One of the source or drain of the amplification transistor AMP is connected to the selection transistor SEL, and the other is connected to a power supply voltage VDD. One of the source or drain of the selection transistor SEL is connected to a vertical signal line (VSL) 32, and the other is connected to the amplification transistor AMP. The selection transistor SEL outputs a voltage signal from the amplification transistor AMP to the vertical signal line (VSL) 32 in response to a drive signal applied to its gate.

[0021] The pixel 21 further includes a conversion efficiency switching control circuit 51 that controls switching of the conversion efficiency by the conversion efficiency transistor FDG. The conversion efficiency switching control circuit 51 includes a transistor RSC, a transistor RSD, a transistor SWD, a capacitor C1, and an inverter INV.

[0022] One of the source or drain of the transistor RSC is connected to the power supply voltage VSS, and the other is connected to the transistor RSD. One of the source or drain of the transistor RSD is connected to the transistor RSC, and the other is connected to the source of the amplifier transistor AMP. The transistor RSD is connected to the source of the amplifier transistor AMP at node A, so that the potential of the floating diffusion FD1 can be read out.

[0023] One of the source and drain of transistor SWD is connected between transistors RSC and RSD, and the other is connected to inverter INV. Capacitor C1 is connected between transistors RSC, RSD, and transistor SWD. Inverter INV is a CMOS inverter consisting of a PMOS transistor on the VDD side and an NMOS transistor on the VSS side. Inverter INV inverts the potential input through transistor SWD and outputs it to the gate of conversion efficiency transistor FDG.

[0024] That is, the conversion efficiency switching control circuit 51 is a conversion efficiency switching control section that controls the on / off of the conversion efficiency transistor FDG by controlling the voltage applied to the gate of the conversion efficiency transistor FDG as a conversion efficiency switching section in accordance with the potential of the node A. Here, for example, if the capacitance value of the floating diffusion FD1 is C FD1 The capacitance of the floating diffusion FD2 is C FD2 When the conversion efficiency transistor FDG is turned on, the capacitance C is C FD1 +C FD2 On the other hand, when the conversion efficiency transistor FDG is turned off, the capacitance value C is C FD1 This means that the amount of change in voltage relative to the amount of change in charge (FD conversion efficiency) increases. Note that a signal line VFDG is connected between the inverter INV and the gate of the conversion efficiency transistor FDG, and a signal indicating the conversion efficiency at which the data was read is output to the peripheral circuitry via the signal line VFDG.

[0025] In the pixel 21 configured as described above, when the transfer transistor TRG is turned on with the conversion efficiency transistor FDG turned off during readout, if the floating diffusion FD1 is saturated with charge flowing from the photodiode PD into the floating diffusion FD1, the conversion efficiency switching control circuit 51 turns on the conversion efficiency transistor FDG. As a result, when the charge accumulated in the photodiode PD is small, the conversion efficiency transistor FDG remains off and readout is performed at high conversion efficiency (HCG: High Conversion Gain). When the charge accumulated in the photodiode PD is large, the conversion efficiency transistor FDG is turned on and readout is performed at low conversion efficiency (LCG: Low Conversion Gain). This makes it possible to achieve both low noise due to high conversion efficiency and an expanded dynamic range by ensuring the charge (Qs) of the FD at low conversion efficiency.

[0026] 3 is a timing chart showing the operation of the circuit configuration of pixel 21 in FIG. 2. FIG. 3 shows a timing chart of the select transistor SEL, reset transistor RST, transfer transistor TRG, transistor RSC, transistor RSD, transistor SWD, floating diffusion FD1, and conversion efficiency transistor FDG. In the timing chart of floating diffusion FD1 and conversion efficiency transistor FDG, the dotted line after time T6 indicates the level during HCG readout (low light intensity), and the dashed-dotted line indicates the level during LCG readout (high light intensity). Each transistor is turned on when the voltage (potential) applied to its gate is at H (High) level, and turned off when it is at L (Low) level.

[0027] At time T1, the transfer transistor TRG is turned on, which discharges the charge accumulated in the photodiode PD and starts the shutter operation. At time T2, the transfer transistor TRG is turned off, which completes the shutter operation and starts exposure. At time T3, the reset transistor RST is turned off, and the reset level of the LCG is output to the vertical signal line VSL. Here, the reset level is referred to as the P phase.

[0028] At time T4, transistor RSC is turned off and transistor RSD is turned on. At this time, transistor SWD is on, so the high potential, which is the reset potential of floating diffusion FD1, is also output to node A, converted to a low potential by inverter INV, and applied to the gate of conversion efficiency transistor FDG. This turns off conversion efficiency transistor FDG, and the potential of floating diffusion FD1 at this time is output to vertical signal line VSL as the reset level (P phase) of HCG.

[0029] At time T5, the transistor SWD is turned off, fixing the conversion efficiency transistor FDG in the off state. At time T6, the transfer transistor TRG is turned on, reading out the charge accumulated in the photodiode PD.

[0030] At time T7, the transistor RSD is turned off to hold the potential of the floating diffusion FD1 (hereinafter also referred to as the FD1 potential). At this time, if the amount of charge photoelectrically converted by the photodiode PD is small and the FD1 potential is not saturated, a high potential is held in the capacitor C1, and if the amount of charge photoelectrically converted is large and the FD1 potential is saturated, a low potential is held in the capacitor C1.

[0031] At time T8, the transistor SWD is turned on. At this time, only when the FD1 potential is saturated, the low potential held in the capacitor C1 is converted to a high potential by the inverter INV and applied to the gate of the conversion efficiency transistor FDG. This turns on the conversion efficiency transistor FDG.

[0032] At time T9, the selection transistor SEL is turned on to output a signal level to the vertical signal line VSL. Here, the signal level is referred to as the D-phase. At time T6, if the FD1 potential is not saturated after the charge stored in the photodiode PD is read, the conversion efficiency transistor FDG remains off and the signal level (D-phase) is read by the HCG. On the other hand, if the FD1 potential is saturated after the charge stored in the photodiode PD is read at time T6, the conversion efficiency transistor FDG is turned on and the signal level (D-phase) is read by the LCG. Therefore, the readout of the signal level (D-phase) can be completed in one go. At this time, a signal indicating whether the data was read at the high conversion efficiency (HCG) or the low conversion efficiency (LCG) is output to the peripheral circuit via the signal line VFDG. For example, the column signal processing unit 13 can perform correlated double sampling (CDS) based on the reset level and signal level read by the HCG or LCG.

[0033] As described above, in the solid-state imaging device 1, when the DCG (Dual Conversion Gain) method is adopted, by providing a conversion efficiency switching control circuit 51 in each pixel 21 arranged in the pixel array section 11 and controlling the on / off of the conversion efficiency transistor FDG, reading of the signal level (D phase) can be completed in one go, thereby shortening the readout time, increasing the frame rate, and reducing power consumption.

[0034] 2, the conversion efficiency switching control circuit 51 is configured to read out the potential of the floating diffusion FD1 (FD1 potential) from node A connected to the source of the amplification transistor AMP, but node A may be connected to the floating diffusion FD1 and the potential of the floating diffusion FD1 may be read out directly. However, in a configuration in which the FD1 potential is read out directly, the wiring connected to node A and the source-drain diffusion layer capacitance of the transistor RSD are added as capacitance of the floating diffusion FD1, which may result in a decrease in the high conversion efficiency (HCG).

[0035] Fig. 4 is a circuit diagram showing another example of the configuration of the pixel 21 of Fig. 2. In the pixel 21 of Fig. 4, parts corresponding to those of the pixel 21 of Fig. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0036] 4, pixel 21 may have a configuration in which two photodiodes PD, photodiode PD1 and photodiode PD2, share a floating diffusion FD1. A transfer transistor TRG1 is provided between photodiode PD1 and floating diffusion FD1. A transfer transistor TRG2 is provided between photodiode PD2 and floating diffusion FD1.

[0037] In the pixel 21 of Fig. 4, after charge is accumulated in the two photodiodes PD, the charge accumulated in the photodiode PD1 is read out, the floating diffusion FD1 is reset, and then the charge accumulated in the photodiode PD2 is read out. In the pixel 21 of Fig. 4, the configuration after the floating diffusion FD1 is the same as the configuration of the pixel 21 of Fig. 2. In the pixel 21 of Fig. 4, it is only necessary to fit the pixel transistors after the floating diffusion FD1 into an area equivalent to two pixels, thereby improving area efficiency.

[0038] <<Second Embodiment>> Fig. 5 is a circuit diagram showing an example of the configuration of a pixel in Embodiment 2. In the pixel 21 in Fig. 5, parts corresponding to those in the pixel 21 in Fig. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0039] 5, the pixel 21 has a conversion efficiency switching control circuit 51 that controls switching of the conversion efficiency by the conversion efficiency transistor FCG. The conversion efficiency switching control circuit 51 is composed of a transistor RSC, a transistor RSD, a capacitor C1, and an inverter INV.

[0040] One of the source and drain of transistor RSC is connected to the power supply voltage VSS, and the other is connected to transistor RSD. One of the source and drain of transistor RSD is connected to transistor RSC, and the other is connected to the source of the amplifier transistor AMP. An inverter INV is connected between transistors RSC and RSD, and a capacitor C1 is also connected between them. The inverter INV inverts the input potential and outputs it to the gate of the conversion efficiency transistor FCG.

[0041] That is, the conversion efficiency switching control circuit 51 is a conversion efficiency switching control unit that controls the on / off of the conversion efficiency transistor FCG as a conversion efficiency switching unit by controlling the voltage applied to the gate of the conversion efficiency transistor FCG in accordance with the potential of the node A. Note that a signal line VFCG is connected between the inverter INV and the gate of the conversion efficiency transistor FCG, and a signal indicating at which conversion efficiency the data was read is output to a peripheral circuit via the signal line VFCG.

[0042] One of the source or drain of the conversion efficiency transistor FCG is connected to the floating diffusion FD1, and the other is connected to the floating diffusion FD3. One of the source or drain of the reset transistor RST is connected to the floating diffusion FD3, and the other is connected to the power supply voltage VDD. The reset transistor RST resets the floating diffusions FD1 and FD3 in response to a drive signal applied to its gate.

[0043] The floating diffusion FD3 is provided with a capacitance MIM configured with, for example, an MIM (Metal Insulator Metal) capacitance element. The capacitance MIM accumulates the charge that overflows from the photodiode PD to the floating diffusion FD1. The capacitance MIM can be configured with a lateral overflow integration capacitor (LOFIC). For example, if the capacitance value of the floating diffusion FD1 is C FD1The capacitance of the floating diffusion FD3 is C LOFIC When the conversion efficiency transistor FCG is turned on, the capacitance C is C FD1 +C LOFIC When the conversion efficiency transistor FCG is turned off, the capacitance C is C FD1 Therefore, the conversion efficiency can be changed by controlling the on / off of the conversion efficiency transistor FCG.

[0044] In the pixel 21 configured as described above, while charge is being stored in the photodiode PD, the charge that overflows from the photodiode PD to the floating diffusion FD1 is stored in the floating diffusion FD3, and this charge can be combined with the charge in the photodiode PD and read out with low conversion efficiency (LCG).

[0045] Fig. 6 is a timing chart showing the operation of the circuit configuration of pixel 21 in Fig. 5. Fig. 6 shows a timing chart of the select transistor SEL, reset transistor RST, transfer transistor TRG, transistor RSC, transistor RSD, floating diffusion FD1, and conversion efficiency transistor FCG. In the timing chart of the floating diffusion FD1 and conversion efficiency transistor FCG, the dotted line after time T2 indicates the level during HCG readout (low light intensity), and the dashed-dotted line indicates the level during LCG readout (high light intensity).

[0046] At time T1, the reset transistor RST is turned on to reset the floating diffusions FD1 and FD3. Also, the transfer transistor TRG is turned on to discharge the charge accumulated in the photodiode PD. This starts the shutter operation.

[0047] At time T2, the reset transistor RST is turned off. Furthermore, by turning off the transistor RSC and turning on the transistor RSD, the high potential (reset potential) of the floating diffusion FD1 is inverted to a low potential by the inverter INV, and the conversion efficiency transistor FCG is turned off. Furthermore, by turning off the transfer transistor TRG, the shutter operation is completed and exposure begins.

[0048] At time T3, the selection transistor SEL is turned on, and the reset level (P phase) of the HCG is output to the vertical signal line VSL. Note that during the exposure period, if the photodiode PD saturates and overflows the transfer transistor TRG, causing charge to accumulate in the floating diffusion FD1, the potential of node A becomes low and is inverted to a high potential by the inverter INV, turning on the conversion efficiency transistor FCG. Therefore, the node becomes LCG, and the reset level (P phase) of the HCG is not output, but this does not pose a problem because HCG readout is not used at this time.

[0049] At time T4, transistor RSD is turned off. Here, during the exposure period when transistor RSD is turned on, if the photodiode PD is not saturated, the potential of node A is high and is inverted to a low potential by the inverter INV, and the conversion efficiency transistor FCG is turned off. Therefore, by turning off transistor RSD, the conversion efficiency transistor FCG is maintained in an off state. On the other hand, during the exposure period when transistor RSD is turned on, if the photodiode PD is saturated and charge is accumulated in the floating diffusion FD1, the potential of node A is low and is inverted to a high potential by the inverter INV, and the conversion efficiency transistor FCG is turned on. Therefore, by turning off transistor RSD, the conversion efficiency transistor FCG is maintained in an on state.

[0050] At time T5, the transfer transistor TRG is turned on to read out the charge from the photodiode PD.

[0051] At time T6, the selection transistor SEL is turned on, and the signal level (D phase) is output to the vertical signal line VSL. As described above at time T4, if the photodiode PD is not saturated during the exposure period, the conversion efficiency transistor FCG is turned off, and the signal level is output at HCG. On the other hand, if the photodiode PD is saturated during the exposure period and charge is accumulated in the floating diffusion FD1, the conversion efficiency transistor FCG is turned on, and the signal level is output at LCG. Therefore, reading of the signal level (D phase) can be completed in one go.

[0052] At time T7, the reset transistor RST and transistor RSC are turned on, turning on the conversion efficiency transistor FCG and resetting the floating diffusions FD1 and FD3. At time T8, the reset transistor RST is turned off. At time T9, the selection transistor SEL is turned on, outputting the reset level (P phase) of LCG to the vertical signal line VSL. A signal indicating the conversion efficiency at which the data was read is output to the peripheral circuitry via the signal line VFCG.

[0053] As described above, in the solid-state imaging device 1, when an overflow driving method with LOFIC is adopted, by providing a conversion efficiency switching control circuit 51 in each pixel 21 arranged in the pixel array section 11 and controlling the on / off of the conversion efficiency transistor FCG, reading of the signal level (D phase) can be completed in one go, thereby shortening the readout time, increasing the frame rate, and reducing power consumption.

[0054] <<Third Embodiment>> Fig. 7 is a circuit diagram showing an example of the configuration of a pixel according to the third embodiment. In the pixel 21 in Fig. 7, parts corresponding to those in the pixel 21 in Fig. 2 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0055] 7, the pixel 21 has a conversion efficiency switching control circuit 51 that controls switching of the conversion efficiency by the conversion efficiency transistor FDG. The conversion efficiency switching control circuit 51 is composed of transistors RSC, RSD, and SWD, a capacitor C1, and an inverter INV. The conversion efficiency switching control circuit 51 controls the on / off of the conversion efficiency transistor FDG in accordance with the potential of node A.

[0056] One of the source or drain of the conversion efficiency transistor FDG is connected to the floating diffusion FD1, and the other is connected to the floating diffusion FD2. One of the source or drain of the conversion efficiency transistor FCG is connected to the floating diffusion FD2, and the other is connected to the floating diffusion FD3. One of the source or drain of the reset transistor RST is connected to the floating diffusion FD3, and the other is connected to the power supply voltage VDD. The reset transistor RST resets the floating diffusions FD1, FD2, and FD3 in response to a drive signal applied to its gate. The floating diffusion FD3 is provided with a capacitor MIM that accumulates charge that overflows from the photodiode PD to the floating diffusion FD1. The capacitor MIM is composed of an MIM capacitance element or the like, and can be configured using LOFIC.

[0057] In the pixel 21 configured as described above, when a combination of the DCG method and the overflow driving method provided with LOFIC is adopted, the conversion efficiency transistor FDG and the conversion efficiency transistor FCG serving as the conversion efficiency switching unit are used, and by controlling the voltage applied to the gate of the conversion efficiency transistor FDG, the conversion efficiency transistor FDG is turned on / off in accordance with the potential of node A. This makes it possible to read out the signal level (D phase) only in the DCG method readout only once, and as a result, the number of times the signal level (D phase) is read out can be reduced from three to two.

[0058] 8 is a timing chart showing the operation of the circuit configuration of pixel 21 in FIG. 8. This timing chart shows the select transistor SEL, reset transistor RST, transfer transistor TRG, conversion efficiency transistor FCG, transistor RSC, transistor RSD, transistor SWD, floating diffusion FD1, and conversion efficiency transistor FDG. In the timing chart for floating diffusion FD1 and conversion efficiency transistor FDG, the dotted line after time T3 indicates the level during HCG readout (low light intensity), the dashed line indicates the level during MCG (Middle Conversion Gain) readout (medium light intensity), and the dashed-dotted line indicates the level during LCG readout (high light intensity).

[0059] At time T1, the reset transistor RST is turned on to reset the floating diffusions FD1, FD2, and FD3. Also, the transfer transistor TRG is turned on to discharge the charge accumulated in the photodiode PD. This starts the shutter operation.

[0060] At time T2, the reset transistor RST and the conversion efficiency transistor FCG are turned off. Furthermore, by turning off the transistor RSC and turning on the transistor RSD, the high potential (reset potential) of the floating diffusion FD1 is inverted to a low potential by the inverter INV, and the conversion efficiency transistor FDG is turned off. Furthermore, by turning off the transfer transistor TRG, the shutter operation is completed and exposure begins.

[0061] At time T3, the transistor SWD is turned off to maintain the off state of the conversion efficiency transistor FDG. During the exposure period, if the photodiode PD becomes saturated, the transfer transistor TRG overflows, and charge accumulates in the floating diffusion FD1, causing the FD1 potential to become low, and this low potential is held in the capacitor C1.

[0062] At time T4, the transistor RSD is turned off, and the transistors RSC and SWD are turned on. At time T5, the selection transistor SEL is turned on, thereby outputting the reset level (P phase) of MCG to the vertical signal line VSL.

[0063] At time T6, by turning off the transistor RSC and turning on the transistor RSD, if the photodiode PD is not saturated during the exposure period, the floating diffusion FD1 becomes high potential (the potential of node A becomes high), so it is inverted to low potential by the inverter INV, and the conversion efficiency transistor FDG is turned off. As a result, the reset level (P phase) of HCG is output to the vertical signal line VSL.

[0064] During the exposure period, if the photodiode PD saturates and overflows the transfer transistor TRG, causing charge to accumulate in the floating diffusion FD1, the potential at node A drops and is inverted to a high potential by the inverter INV, turning on the conversion efficiency transistor FDG. As a result, the MCG is generated and the HCG reset level (P phase) is not output, but this does not pose a problem because HCG readout is not used at this time.

[0065] At time T7, the transistor SWD is turned off, and the charge stored in the photodiode PD is read out by turning on the transfer transistor TRG while keeping the gate potential of the conversion efficiency transistor FDG fixed. At this time, the potential of the floating diffusion FD1 is held in the capacitor C1.

[0066] At time T8, transistor RSD is turned off and transistor SWD is turned on. Here, if the floating diffusion FD1 is not saturated, the potential of capacitor C1 is high and is inverted to low potential by inverter INV, turning off the conversion efficiency transistor FDG. This results in the HCG readout state. On the other hand, if the floating diffusion FD1 is saturated, the potential of capacitor C1 is low and is inverted to high potential by inverter INV, turning on the conversion efficiency transistor FDG. This results in the MCG readout state.

[0067] At time T9, the selection transistor SEL is turned on to output the signal level (D phase) to the vertical signal line VSL. At this time, as described above at time T8, the readout states of HCG and MCG are appropriately selected, and the readout of the signal levels (D phase) of HCG and MCG can be completed in one go.

[0068] At time T10, the conversion efficiency transistor FCG is turned on to perform LCG readout. This readout is used as an image when the photodiode PD is saturated during the exposure period and overflows the transfer transistor TRG. In this case, the floating diffusion FD1 is saturated at time T7, and the conversion efficiency transistor FDG is turned on, enabling LCG readout. By turning on the transfer transistor TRG, all charges remaining in the photodiode PD are read out, and the selection transistor SEL is turned on to output the LCG signal level (D phase) to the vertical signal line VSL.

[0069] At time T11, the transistor RSC is turned on, and with the conversion efficiency transistor FDG fixed on, the reset transistor RST is turned on to reset the entire floating diffusions FD1, FD2, and FD3. At time T12, the reset transistor RST is turned off. At time T13, the selection transistor SEL is turned on, and the reset level (P phase) of LCG is output to the vertical signal line VSL. A signal indicating the conversion efficiency at which the data was read is output to the peripheral circuitry via the signal line VFDG.

[0070] As described above, in the solid-state imaging device 1, when a combination of the DCG system and the overflow driving system provided with LOFIC is adopted, by providing the conversion efficiency switching control circuit 51 in each pixel 21 arranged in the pixel array unit 11 and controlling the on / off of the conversion efficiency transistor FDG, the readout of the signal level (D phase) of the DCG system (readout of HCG and MCG) is completed in one go, and together with the LCG readout, the readout of the signal level (D phase) is completed in two goes. Therefore, the readout of the signal level (D phase) is reduced from three goes to two, the readout time is shortened, the frame rate is increased, and power consumption can be reduced.

[0071] <<Fourth Embodiment>> Fig. 9 is a circuit diagram showing an example of the configuration of a pixel according to the fourth embodiment. In the pixel 21 in Fig. 9, parts corresponding to those in the pixel 21 in Fig. 2 are denoted by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0072] 9, the pixel 21 has a conversion efficiency switching control circuit 51 that controls switching of the conversion efficiency by the conversion efficiency transistor FDG and the conversion efficiency transistor FCG. The conversion efficiency switching control circuit 51 is composed of a transistor RSC, a transistor RSD, a capacitor C2, a transistor SWD, an inverter INV2, a transistor SWC, a capacitor C1, and an inverter INV1.

[0073] One of the source and drain of the transistor RSC is connected to the power supply voltage VSS, and the other is connected to the transistor RSD. One of the source and drain of the transistor RSD is connected to the transistor RSC, and the other is connected to the source of the amplifier transistor AMP.

[0074] One of the source and drain of transistor SWD is connected between transistors RSC and RSD, and the other is connected to inverter INV2. Capacitor C2 is connected between transistors RSC, RSD, and transistor SWD. Inverter INV2 inverts the input potential and outputs it to the gate of conversion efficiency transistor FDG.

[0075] One of the source and drain of transistor SWC is connected between transistors RSC and RSD, and the other is connected to inverter INV1. Capacitor C1 is connected between transistor SWC and inverter INV1. Inverter INV1 inverts the input potential and outputs it to the gate of conversion efficiency transistor FCG.

[0076] That is, the conversion efficiency switching control circuit 51 controls the on / off of the conversion efficiency transistor FDG and the conversion efficiency transistor FCG by controlling the voltage applied to the gates of the conversion efficiency transistor FDG and the conversion efficiency transistor FCG according to the potential of the node A. A signal line VFDG is connected between the inverter INV2 and the gate of the conversion efficiency transistor FDG, and a signal indicating the conversion efficiency at which the data was read is output via the signal line VFDG. A signal line VFCG is connected between the inverter INV1 and the gate of the conversion efficiency transistor FCG, and a signal indicating the conversion efficiency at which the data was read is output via the signal line VFCG.

[0077] One of the source or drain of the conversion efficiency transistor FDG is connected to the floating diffusion FD1, and the other is connected to the floating diffusion FD2. One of the source or drain of the conversion efficiency transistor FCG is connected to the floating diffusion FD2, and the other is connected to the floating diffusion FD3. One of the source or drain of the reset transistor RST is connected to the floating diffusion FD3, and the other is connected to the power supply voltage VDD. The reset transistor RST resets the floating diffusions FD1, FD2, and FD3 in response to a drive signal applied to its gate. The floating diffusion FD3 is provided with a capacitor MIM that accumulates charge that overflows from the photodiode PD to the floating diffusion FD1. The capacitor MIM is composed of an MIM capacitance element or the like, and can be configured using LOFIC.

[0078] In the pixel 21 configured as described above, when a combination of the DCG system and the overflow driving system with LOFIC is adopted, the voltages applied to the gates of the conversion efficiency transistor FDG and the conversion efficiency transistor FCG, which serve as a conversion efficiency switching unit, are controlled to respectively control the on / off of the conversion efficiency transistor FDG and the on / off of the conversion efficiency transistor FCG according to the potential of node A. This allows the signal level (D phase) to be read out only once when the DCG system and the overflow driving system with LOFIC are combined. In other words, the number of times the signal level (D phase) is read out can be reduced from three to one.

[0079] Figure 10 is a timing chart showing the operation of the circuit configuration of pixel 21 in Figure 9. Figure 10 shows a timing chart of the select transistor SEL, reset transistor RST, transfer transistor TRG, transistor RSC, transistor SWC, transistor RSD, transistor SWD, floating diffusion FD1, conversion efficiency transistor FCG, and conversion efficiency transistor FDG. For floating diffusion FD1, conversion efficiency transistor FCG, and conversion efficiency transistor FDG, the dotted lines after time T3 indicate the levels during HCG readout (low light intensity), the dashed lines indicate the levels during MCG readout (medium light intensity), and the dashed-dotted lines indicate the levels during LCG readout (high light intensity).

[0080] At time T1, the reset transistor RST is turned on. At this time, the transistors RSC, SWC, and SWD are on, so the conversion efficiency transistors FCG and FDG are on, and the floating diffusions FD1, FD2, and FD3 are reset. Furthermore, the transfer transistor TRG is turned on to discharge the charge accumulated in the photodiode PD. This starts the shutter operation.

[0081] At time T2, the reset transistor RST and the transistor RSC are turned off, and the transistor RSD is turned on. This turns off the reset transistor RST, the conversion efficiency transistor FCG, and the conversion efficiency transistor FDG. In addition, by turning off the transfer transistor TRG, the shutter operation is completed and exposure begins.

[0082] At time T3, transistor SWD is turned off, and the conversion efficiency transistor FDG is fixed in the off state. During the exposure period, if the photodiode PD saturates, overflows the transfer transistor TRG, and charge accumulates in the floating diffusion FD1, causing the FD1 potential to drop. This low potential is then held in capacitors C1 and C2. At time T4, transistor SWC is turned off, and the potential of capacitor C1 is fixed.

[0083] At time T5, the transistor RSD is turned off and the transistors RSC and SWD are turned on, thereby turning on the conversion efficiency transistor FDG.

[0084] At time T6, the selection transistor SEL is turned on to output the reset level (P phase) of MCG to the vertical signal line VSL. Note that during the exposure period, if the photodiode PD saturates and overflows the transfer transistor TRG, causing charge to accumulate in the floating diffusion FD1, the potential of node A becomes low and is inverted to a high potential by the inverter INV1, turning on the conversion efficiency transistor FCG. As a result, the node A becomes LCG and the reset level (P phase) of MCG is not output, but this does not pose a problem because the LCG readout is used at this time and the MCG readout is not used.

[0085] At time T7, by turning off the transistor RSC and turning on the transistor RSD, if the photodiode PD is not saturated during the exposure period, the floating diffusion FD1 will be at a high potential, which is inverted to a low potential by the inverter INV2, turning off the conversion efficiency transistor FDG. As a result, the reset level (P phase) of the HCG is output to the vertical signal line VSL.

[0086] During the exposure period, if the photodiode PD saturates and overflows the transfer transistor TRG, causing charge to accumulate in the floating diffusion FD1, the potential at node A becomes low and is inverted to a high potential by the inverter INV2, turning on the conversion efficiency transistor FDG. As a result, it becomes MCG or LCG, and the reset level (P phase) of HCG is not output, but at this time, the readout of MCG or LCG is used, and the readout of HCG is not used, so this does not pose a problem.

[0087] At time T8, the transistor SWD is turned off, and the charge stored in the photodiode PD is read out by turning on the transfer transistor TRG while the gate potential of the conversion efficiency transistor FDG is fixed. The potential of the floating diffusion FD1 at this time is held in the capacitor C2.

[0088] At time T9, transistor RSD is turned off and transistor SWD is turned on. If the floating diffusion FD1 is not saturated, the potential of capacitor C2 is high and the conversion efficiency transistor FDG is turned off, resulting in an HCG readout state. On the other hand, if the floating diffusion FD1 is saturated, the potential of capacitor C2 is low and the conversion efficiency transistor FDG is turned on, resulting in an MCG readout state. Furthermore, if the photodiode PD saturates during the exposure period, causing charge to overflow the transfer transistor TRG and accumulate in the floating diffusion FD1, the potential of capacitor C1 is low and the conversion efficiency transistor FCG is turned on, resulting in an LCG readout state.

[0089] At time T10, the selection transistor SEL is turned on to output the signal level (D phase) to the vertical signal line VSL. As described above at time T9, the readout states of HCG, MCG, and LCG are appropriately selected, and the readout of the signal level (D phase) can be completed in one go.

[0090] At time T11, transistors RSC and SWC are turned on, turning on the conversion efficiency transistor FCG. If the photodiode PD is saturated during the exposure period, the conversion efficiency transistor FDG is turned on at time T9. By turning on the reset transistor RST, the floating diffusions FD1, FD2, and FD3 are reset. Note that if the photodiode PD is not saturated during the exposure period, the conversion efficiency transistor FDG is turned off at time T9, so none of the floating diffusions FD1, FD2, and FD3 are reset. However, in this case, LCG readout is not used for the image, so this does not pose a problem.

[0091] At time T12, the reset transistor RST is turned off. At time T13, the selection transistor SEL is turned on, and the reset level (P phase) of LCG is output to the vertical signal line VSL. A signal indicating the conversion efficiency at which the data was read is output to the peripheral circuitry via signal lines VFCG and VFDG.

[0092] As described above, in the solid-state imaging device 1, when a combination of the DCG method and the overflow driving method with LOFIC is adopted, by providing a conversion efficiency switching control circuit 51 in each pixel 21 arranged in the pixel array section 11 and controlling the on / off of the conversion efficiency transistor FDG and the conversion efficiency transistor FCG, reading of the signal level (D phase) can be completed in one go, thereby shortening the readout time, increasing the frame rate, and reducing power consumption.

[0093] <<Fifth Embodiment>> Fig. 11 is a cross-sectional view showing an example of the structure of a pixel in a fifth embodiment. In Fig. 11, a semiconductor substrate made of silicon (Si) or the like has a P-well layer 61 in a region near the surface, and an N-type region in the other region. This forms a photoelectric conversion region 63 as a photodiode PD. Each pixel 21 has a photoelectric conversion region 63, and is separated by an inter-pixel isolation region 62 having a trench structure such as FFTI (Front Full Trench Isolation). The P-well layer 61 contains P ＋ A region well contact 65 is formed.

[0094] Gate electrodes 71 to 74 are formed on an insulating film above the P-well layer 61. The gate electrodes 71 and 72 are gate electrodes of transistors other than the transistor of the conversion efficiency switching control circuit 51 in the pixel 21. For example, the gate electrode 71 and the left and right N ＋ The transfer transistor TRG as an NMOS transistor is formed by the source and drain made up of the region 66. The gate electrodes 73 and 74 are gate electrodes of the transistors included in the conversion efficiency switching control circuit 51. For example, the gate electrode 74 and the left and right N ＋An NMOS transistor (for example, an NMOS transistor of an inverter INV) is formed by the source and drain formed by the region 66. An N-type well region 64 is also formed, and a gate electrode 73 and left and right P ＋ The PMOS transistor of the inverter INV is formed by the source and drain of the region 68. The N-type well region 64 contains N ＋ A region well contact 67 is formed.

[0095] As described above, the pixel 21 has a structure in which the first layer including the photoelectric conversion region 63 as the photodiode PD and the second layer including the elements that constitute the conversion efficiency switching control circuit 51 are different layers. That is, the pixel 21 has a stacked structure in which the first layer and the second layer are stacked, and the elements in the pixel are also formed in the second layer that is different from the first layer including the photoelectric conversion region 63. For example, the pixel 21 having the circuit configuration shown in FIG. 2 can have the structure shown in FIG. 11.

[0096] <<Sixth Embodiment>> Fig. 12 is a cross-sectional view showing an example of the structure of a pixel in the sixth embodiment. In Fig. 12, a first layer 91 as an upper chip and a second layer 92 as an intermediate layer are bonded together at a bonding surface 93 indicated by a dashed line. At the bonding surface 93, not only are they physically bonded, but also electrically connected by exposing Cu pads at the bonding interfaces on both surfaces and bonding the two pads together (Cu-Cu bonding).

[0097] In the first layer 91, a P well layer 101 and a photoelectric conversion region 103 are formed, and the P well layer 101 is isolated from other pixels by an inter-pixel isolation region 102. ＋ A well contact 104 is formed in the P well layer 101. Gate electrodes 111 and 112 are formed on an insulating film on the upper part of the P well layer 101. The gate electrodes 111 and 112 are gate electrodes of transistors in the pixel 21 except for the transistor of the conversion efficiency switching control circuit 51. For example, the gate electrode 111 and the N ＋The source and drain regions form a transfer transistor TRG as an NMOS transistor. The first layer 91 has a plurality of wiring layers formed with wirings such as wirings 113 made of Cu, and an MIM capacitance element 114 is formed between the wiring layers.

[0098] The second layer 92 has a plurality of wiring layers in which wirings such as wirings 121 made of Cu are formed. In the second layer 92, a P-type well layer 131 and an N-type well region 132 are formed. In the P-type well layer 131, a P-type well region 132 is formed. ＋ A well contact 133 is formed in the N-type well region 132 and connected to a wiring layer. ＋ A well contact 135 is formed in the P well layer 131 and connected to the wiring layer. Gate electrodes 122 and 123 are formed on an insulating film above the P well layer 131 (below after bonding). The gate electrodes 122 and 123 are gate electrodes of transistors included in the conversion efficiency switching control circuit 51. For example, the gate electrode 123 and the N ＋ The source and drain regions 134 form an NMOS transistor (for example, an NMOS transistor of an inverter INV). ＋ The source and drain of region 136 form the PMOS transistor of inverter INV.

[0099] As described above, the pixel 21 has a structure in which the first layer 91 including the photoelectric conversion region 103 serving as the photodiode PD and the second layer 92 including the elements constituting the conversion efficiency switching control circuit 51 are formed in different layers. That is, the pixel 21 has a stacked structure in which the first layer 91 and the second layer 92 are stacked, and elements within the pixel are also formed in the second layer 92, which is different from the first layer 91 including the photoelectric conversion region 103. For example, the pixel 21 having the circuit configuration shown in FIGS. 5, 7, and 9 can have the structure shown in FIG. 12. More specifically, the conversion efficiency switching control circuit 51 in FIGS. 5, 7, and 9 is formed in the second layer 92 as an intermediate layer, and the capacitance MIM in FIGS. 5, 7, and 9 corresponds to the MIM capacitance element 114 in FIG. 12 and is formed in the first layer 91 as an upper chip.

[0100] In the pixel structure of FIG. 11 described above, many in-pixel transistors are arranged on the same plane and well isolation is also required, which may make it difficult to reduce the pixel size. However, in the pixel structure of FIG. 12, some of the in-pixel transistors and the well isolation are placed on different layers, which makes it easy to reduce the pixel size.

[0101] <<Seventh Embodiment>> Fig. 13 is a cross-sectional view showing an example of the structure of a pixel in the seventh embodiment. In Fig. 13, a first layer 151 as an upper chip and a second layer 152 as an intermediate layer are bonded together at a bonding surface 153. At the bonding surface 153, they are not only physically bonded but also electrically connected by Cu-Cu bonding.

[0102] In the first layer 151, a P well layer 161 and a photoelectric conversion region 163 are formed, and are isolated from other pixels by an inter-pixel isolation region 162. ＋ A well contact 164 is formed in the P well layer 161. Gate electrodes 171 and 172 are formed on an insulating film on the upper part of the P well layer 161. The gate electrodes 171 and 172 are gate electrodes of transistors in the pixel 21 excluding the transistor of the conversion efficiency switching control circuit 51. For example, the gate electrode 171 and the left and right N ＋ The transfer transistor TRG is formed by the source and drain regions. The first layer 151 has a plurality of wiring layers in which wirings such as wiring 173 made of Cu are formed.

[0103] The second layer 152 has a plurality of wiring layers formed with wirings such as wirings 181 made of Cu, and an MIM capacitance element 184 is formed between the wiring layers. In the second layer 152, a P-type well layer 191 and an N-type well region 192 are formed. In the P-type well layer 191, a P-type well region 192 is formed. ＋ A well contact 193 is formed in the N-type well region 192 and connected to a wiring layer. ＋A well contact 195 is formed in the P well layer 191 and connected to the wiring layer. Gate electrodes 182 and 183 are formed on an insulating film above the P well layer 191 (below after bonding). The gate electrodes 182 and 183 are gate electrodes of transistors included in the conversion efficiency switching control circuit 51. For example, the gate electrode 183 and the N ＋ An NMOS transistor (for example, an NMOS transistor of an inverter INV) is formed by the source and drain formed by the region 194. ＋ The source and drain of region 196 form the PMOS transistor of inverter INV.

[0104] As described above, the pixel 21 has a stacked structure in which the first layer 151 and the second layer 152 are stacked, and elements within the pixel are also formed in the second layer 152, which is different from the first layer 151 including the photoelectric conversion region 163. In FIG. 13 , the MIM capacitance element 184 is formed in the second layer 152, which serves as an intermediate layer. That is, in the pixel structure of FIG. 12 described above, the MIM capacitance element 114 is disposed in the first layer 91, which serves as the upper chip, but in the pixel structure of FIG. 13 , the MIM capacitance element 184 is disposed in the second layer 152, which serves as an intermediate layer. For example, the pixel 21 having the circuit configurations shown in FIGS. 5 , 7 , and 9 can have the structure shown in FIG. 13 . More specifically, the conversion efficiency switching control circuit 51 in FIGS. 5, 7, and 9 is formed on the second layer 152 serving as an intermediate layer, and the capacitance MIM in FIGS. 5, 7, and 9 corresponds to the MIM capacitance element 184 in FIG. 13 and is formed on the second layer 152 serving as an intermediate layer.

[0105] 14 is a cross-sectional view showing an example of the structure of a pixel in the eighth embodiment. In Fig. 14, a P well layer 211 and a photoelectric conversion region 213 are formed on a semiconductor substrate, and are separated from other pixels by an inter-pixel isolation region 212. The P well layer 211 has a P ＋A well contact 214 is formed in the P well layer 211. Gate electrodes 221 and 222 are formed on an insulating film on the upper part of the P well layer 211. The gate electrodes 221 and 222 are gate electrodes of transistors in the pixel 21 except for the transistor of the conversion efficiency switching control circuit 51. For example, the gate electrode 221 and the left and right N ＋ The source and drain regions form a transfer transistor TRG as an NMOS transistor.

[0106] 14 , thin film transistors 223 and 224 are formed on a second layer stacked on the first layer in which the photoelectric conversion region 213 is formed. The thin film transistor 223 is an N-type MOS TFT (Thin Film Transistor). The thin film transistor 224 is a P-type MOS TFT. That is, the second layer includes a TFT layer, and elements constituting the conversion efficiency switching control circuit 51 can be formed in the TFT layer. For example, among the transistors included in the conversion efficiency switching control circuit 51, the NMOS transistor of the inverter INV may be formed by the thin film transistor 223, and the PMOS transistor of the inverter INV may be formed by the thin film transistor 224. Furthermore, the second layer may include a plurality of wiring layers in which wirings such as wiring 225 made of Cu are formed, and an MIM capacitance element 226 may be formed between the wiring layers.

[0107] As described above, the pixel 21 has a structure in which the first layer including the photoelectric conversion region 213 as the photodiode PD and the second layer including the elements constituting the conversion efficiency switching control circuit 51 are different layers. That is, the pixel 21 has a stacked structure in which the first layer and the second layer are stacked, and elements within the pixel are also formed in the second layer different from the first layer including the photoelectric conversion region 213. For example, the pixel 21 having the circuit configurations shown in FIGS. 5, 7, and 9 can have the structure shown in FIG. 14. More specifically, the conversion efficiency switching control circuit 51 in FIGS. 5, 7, and 9 is formed in the second layer, and the capacitance MIM in FIGS. 5, 7, and 9 corresponds to the MIM capacitance element 226 in FIG. 14 and is formed in the second layer.

[0108] <Configuration of Electronic Device> A solid-state imaging device to which the present disclosure is applied can be mounted in electronic devices such as smartphones, tablet terminals, mobile phones, digital still cameras, digital video cameras, etc. Fig. 15 is a diagram showing a configuration example of an electronic device equipped with a solid-state imaging device to which the present disclosure is applied.

[0109] 15, electronic device 301 has an imaging system made up of an optical system 311 including a lens group, an imaging unit 312 having the solid-state imaging device 1 of Fig. 1, and a DSP (Digital Signal Processor) 313 that processes camera signals. In addition to the imaging system, electronic device 301 has a configuration in which a CPU (Central Processing Unit) 314, a frame memory 315, a display unit 316, an operation unit 317, an auxiliary memory 318, a communication unit 319, and a power supply unit 320 are connected to each other via a bus 321.

[0110] The CPU 314 controls the operation of each section of the electronic device 301. The optical system 311 takes in incident light (image light) from a subject and forms an image on the photodetection surface of the solid-state imaging device 1 included in the imaging section 312. In the imaging section 312, the solid-state imaging device 1 converts the amount of incident light formed on the photodetection surface by the optical system 311 into an electrical signal on a pixel-by-pixel basis and outputs the signal. The DSP 313 performs signal processing on the signal output from the imaging section 312.

[0111] The frame memory 315 temporarily stores image data of still images or videos captured by the imaging system. The display unit 316 is composed of a display such as a liquid crystal display or an organic EL display, and displays still images or videos captured by the imaging system. The operation unit 317 is composed of physical buttons, a touch panel, etc., and issues operation commands for various functions of the electronic device 301 in response to operations by the user.

[0112] The auxiliary memory 318 is composed of a storage medium including a semiconductor memory such as a flash memory, and records image data of still images or videos captured by the imaging system. The communication unit 319 has a communication module compatible with a predetermined communication method, and transmits image data of still images or videos captured by the imaging system to other devices via a network. The power supply unit 320 appropriately supplies various types of power to each unit of the electronic device 301 as operating power.

[0113] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present. In this specification, the term "connection" simply refers to "electrical connection."

[0114] The present disclosure can also be configured as follows.

[0115] (1) A solid-state imaging device comprising: a pixel array unit in which a plurality of pixels are arranged, the pixels comprising: a photoelectric conversion unit that converts incident light into electric charges, a charge-voltage conversion unit that accumulates the electric charges obtained by photoelectric conversion, a conversion efficiency switching unit provided for the charge-voltage conversion unit and that switches conversion efficiency, and a conversion efficiency switching control unit that controls switching of the conversion efficiency by the conversion efficiency switching unit based on a potential of the charge-voltage conversion unit. (2) The solid-state imaging device according to (1), wherein the conversion efficiency switching unit is composed of a first conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the electric charges from the photoelectric conversion unit and a second floating diffusion connected to a reset transistor, the first floating diffusion being connected to a gate of an amplification transistor that is connected to a vertical signal line in accordance with an operation of a selection transistor, and the conversion efficiency switching control unit controls a voltage applied to the gate of the first conversion efficiency transistor in accordance with a potential of the first floating diffusion. (3) The solid-state imaging device described in (1), wherein the conversion efficiency switching unit is composed of a second conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the charge from the photoelectric conversion unit and a third floating diffusion connected to a reset transistor, the first floating diffusion is connected to the gate of an amplifying transistor that is connected to a vertical signal line depending on the operation of a selection transistor, the third floating diffusion has a capacitance that accumulates charge that has overflowed from the photoelectric conversion unit to the first floating diffusion, and the conversion efficiency switching control unit controls the voltage applied to the gate of the second conversion efficiency transistor depending on the potential of the first floating diffusion.(4) The solid-state imaging device described in (1), wherein the conversion efficiency switching unit is composed of: a first floating diffusion connected to a transfer transistor that transfers the charge from the photoelectric conversion unit; a first conversion efficiency transistor connected between the first floating diffusion and the second floating diffusion; and a second conversion efficiency transistor connected between the second floating diffusion and a third floating diffusion that is connected to a reset transistor; the first floating diffusion is connected to the gate of an amplifying transistor that is connected to a vertical signal line depending on the operation of a selection transistor; the third floating diffusion has a capacitance that accumulates charge that has overflowed from the photoelectric conversion unit to the first floating diffusion; and the conversion efficiency switching control unit controls the voltage applied to the gate of the first conversion efficiency transistor depending on the potential of the first floating diffusion. (5) The solid-state imaging device described in (1), wherein the conversion efficiency switching unit is composed of: a first floating diffusion connected to a transfer transistor that transfers the charge from the photoelectric conversion unit; a first conversion efficiency transistor connected between the first floating diffusion and the second floating diffusion; and a second conversion efficiency transistor connected between the second floating diffusion and a third floating diffusion that is connected to a reset transistor; the first floating diffusion is connected to the gate of an amplifying transistor that is connected to a vertical signal line depending on the operation of a selection transistor; the third floating diffusion has a capacitance that accumulates charge that has overflowed from the photoelectric conversion unit to the first floating diffusion; and the conversion efficiency switching control unit controls the voltage applied to the gate of the first conversion efficiency transistor and the gate of the second conversion efficiency transistor depending on the potential of the first floating diffusion.(6) The solid-state imaging device according to any one of (1) to (5), wherein the conversion efficiency switching control unit is composed of a control circuit that controls a voltage applied to a gate of a conversion efficiency transistor that constitutes the conversion efficiency switching unit, and the control circuit has a signal line that outputs a signal indicating the selected conversion efficiency to a peripheral circuit. (7) The solid-state imaging device according to any one of (1) to (6), wherein the conversion efficiency switching control unit is composed of a control circuit that controls a voltage applied to a gate of a conversion efficiency transistor that constitutes the conversion efficiency switching unit, and the control circuit includes an inverter that inverts a potential output to the gate of the conversion efficiency transistor. (8) The solid-state imaging device according to (7), wherein the inverter is composed of CMOS. (9) The solid-state imaging device according to (1), wherein the photoelectric conversion unit is a photodiode, and wherein the pixel has a stacked structure of a first layer in which the photodiode is formed and a second layer in which elements other than the photodiode are formed. (10) The solid-state imaging device according to (9), wherein the conversion efficiency switching control unit is configured with a control circuit that controls a voltage applied to a gate of a conversion efficiency transistor that constitutes the conversion efficiency switching unit, and elements that constitute the control circuit are formed in the second layer. (11) The solid-state imaging device according to (9), wherein the conversion efficiency switching unit is configured with a second conversion efficiency transistor connected to a third floating diffusion provided with a capacitance that accumulates charge overflowing from the photoelectric conversion unit, and the capacitance is an MIM capacitance element and formed in the first layer. (12) The solid-state imaging device according to (9), wherein the conversion efficiency switching unit is configured with a second conversion efficiency transistor connected to a third floating diffusion provided with a capacitance that accumulates charge overflowing from the photoelectric conversion unit, and the capacitance is an MIM capacitance element and formed in the second layer. (13) The solid-state imaging device according to (1), wherein the conversion efficiency switching control unit is configured with a control circuit that controls a voltage applied to a gate of a conversion efficiency transistor that constitutes the conversion efficiency switching unit, and elements that constitute the control circuit are formed in the TFT layer.

[0116] 1 Solid-state imaging device, 11 Pixel array section, 12 Vertical driving section, 13 Column signal processing section, 14 Horizontal driving section, 15 Output section, 16 Control section, 21 Pixel, 31 Pixel driving line, 32 Vertical signal line, 33 Horizontal signal line, 51 Conversion efficiency switching control circuit, 63 Photoelectric conversion region, 71 to 74 Gate electrode, 103 Photoelectric conversion region, 111, 112, 122, 123 Gate electrode, 114 MIM capacitance element, 163 Photoelectric conversion region, 171, 172, 182, 183 Gate electrode, 184 MIM capacitance element, 213 Photoelectric conversion region, 223, 224 Thin film transistor, 226 MIM capacitance element, 301 Electronic device, 312 Imaging section, PD, PD1, PD2 Photodiode, TRG, TRG1, TRG2: Transfer transistors, FD1, FD2, FD3: Floating diffusion, FDG, FCG: Conversion efficiency transistor, RST: Reset transistor, AMP: Amplification transistor, SEL: Select transistor, RSC, RSD, SWD, SWC: Transistor, C1, C2: Capacitor, INV, INV1, INV2: Inverter, VFDG, VFCG: Signal line, MIM: Capacitor

Claims

1. A solid-state imaging device comprising a pixel array unit in which a plurality of pixels are arranged, wherein each pixel includes: a photoelectric conversion unit that converts incident light into charges; a charge-voltage conversion unit that accumulates the charges obtained by photoelectric conversion; a conversion efficiency switching unit that is provided for the charge-voltage conversion unit and switches conversion efficiency; and a conversion efficiency switching control unit that controls the switching of the conversion efficiency by the conversion efficiency switching unit based on the potential of the charge-voltage conversion unit.

2. The solid-state imaging device according to claim 1, wherein the conversion efficiency switching unit is composed of a first conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the charges from the photoelectric conversion unit and a second floating diffusion connected to a reset transistor, the first floating diffusion is connected to the gate of an amplification transistor connected to a vertical signal line according to the operation of a selection transistor, and the conversion efficiency switching control unit controls the voltage applied to the gate of the first conversion efficiency transistor according to the potential of the first floating diffusion.

3. The solid-state imaging device according to claim 1, wherein the conversion efficiency switching unit is composed of a second conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the charges from the photoelectric conversion unit and a third floating diffusion connected to a reset transistor, the first floating diffusion is connected to the gate of an amplification transistor connected to a vertical signal line according to the operation of a selection transistor, the third floating diffusion is provided with a capacitor that accumulates charges that overflow from the photoelectric conversion unit to the first floating diffusion, and the conversion efficiency switching control unit controls the voltage applied to the gate of the second conversion efficiency transistor according to the potential of the first floating diffusion.

4. The conversion efficiency switching unit includes a first conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the charge from the photoelectric conversion unit and a second floating diffusion, and a second conversion efficiency transistor connected between the second floating diffusion and a third floating diffusion connected to a reset transistor. The first floating diffusion is connected to the gate of an amplification transistor connected to a vertical signal line according to the operation of a selection transistor. The third floating diffusion is provided with a capacitor for accumulating the charge that has overflowed from the photoelectric conversion unit to the first floating diffusion. The conversion efficiency switching control unit controls the voltage applied to the gate of the first conversion efficiency transistor according to the potential of the first floating diffusion. The solid-state imaging device according to claim 1.

5. The conversion efficiency switching unit includes a first conversion efficiency transistor connected between a first floating diffusion connected to a transfer transistor that transfers the charge from the photoelectric conversion unit and a second floating diffusion, and a second conversion efficiency transistor connected between the second floating diffusion and a third floating diffusion connected to a reset transistor. The first floating diffusion is connected to the gate of an amplification transistor connected to a vertical signal line according to the operation of a selection transistor. The third floating diffusion is provided with a capacitor for accumulating the charge that has overflowed from the photoelectric conversion unit to the first floating diffusion. The conversion efficiency switching control unit controls the voltages applied to the gates of the first conversion efficiency transistor and the second conversion efficiency transistor according to the potential of the first floating diffusion. The solid-state imaging device according to claim 1.

6. The conversion efficiency switching control unit is composed of a control circuit that controls the voltage applied to the gate of the conversion efficiency transistor constituting the conversion efficiency switching unit. The control circuit has a signal line that outputs a signal indicating the selected conversion efficiency to a peripheral circuit. The solid-state imaging device according to claim 1.

7. The conversion efficiency switching control unit is composed of a control circuit that controls the voltage applied to the gate of the conversion efficiency transistor constituting the conversion efficiency switching unit. The control circuit includes an inverter that inverts the potential output to the gate of the conversion efficiency transistor. The solid-state imaging device according to claim 1.

8. The inverter is composed of CMOS. The solid-state imaging device according to claim 7.

9. The photoelectric conversion unit is a photodiode. The pixel has a structure in which a first layer on which the photodiode is formed and a second layer on which elements other than the photodiode are formed are stacked. The solid-state imaging device according to claim 1.

10. The conversion efficiency switching control unit is composed of a control circuit that controls the voltage applied to the gate of the conversion efficiency transistor constituting the conversion efficiency switching unit. The elements constituting the control circuit are formed in the second layer. The solid-state imaging device according to claim 9.

11. The conversion efficiency switching unit is configured to include a second conversion efficiency transistor connected to a third floating diffusion provided with a capacitor for storing charges overflowing from the photoelectric conversion unit. The capacitor is a MIM capacitor element and is formed in the first layer. The solid-state imaging device according to claim 9.

12. The conversion efficiency switching unit is configured to include a second conversion efficiency transistor connected to a third floating diffusion provided with a capacitor for storing charges overflowing from the photoelectric conversion unit. The capacitor is a MIM capacitor element and is formed in the second layer. The solid-state imaging device according to claim 9.

13. The conversion efficiency switching control unit is composed of a control circuit that controls the voltage applied to the gate of the conversion efficiency transistor constituting the conversion efficiency switching unit. The elements constituting the control circuit are formed in a TFT layer. The solid-state imaging device according to claim 1.

Images