Semiconductor device

Abstract

The present invention reduces on-resistance while ensuring short-circuit withstand time in a trench MOSFET which has a vertical channel fin structure. Provided is a trench MOSFET which has a vertical channel fin structure and which has a longitudinal direction along a first direction and a plurality of first trenches 2 arranged in a second direction, wherein: the trench MOSFET has a first JFET region 8A of a first conductivity type that is disposed below a channel region 5 and that is sandwiched between first body regions 9A of a second conductivity type and a second JFET region 8B of a first conductivity type that is disposed so as to be in contact with the lower surface of the first JFET region 8A and that is sandwiched between second body regions 9B of a second conductivity type; the length of the second JFET region 8B in the first direction is greater than the length of the first JFET region 8A in the first direction; the impurity concentration of the first JFET region 8A is higher than the impurity concentration of the second JFET region 8B; the impurity concentration of the second JFET region 8B is higher than the impurity concentration of a drift region 10; the dimension of the first body regions 9A and the dimension of the first JFET region 8A in the depth direction from the bottom of the first trenches 2 are both more than 0.5 μm.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] As one type of trench MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] 13 is a perspective view schematically showing a conventional trench MOSFET with a vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are not shown.

[0004] 13 has a longitudinal direction in a first direction and a lateral direction in a second direction when viewed from above, and has a plurality of first trenches 2 arranged in the second direction. Note that the first trenches 2 shown by dotted lines in the cross section at the front of Fig. 13 show positions that virtually correspond to the first trenches 2 in order to explain the positional relationship between other components and the first trenches 2.

[0005] The first conductivity type first source region 3 includes a region having a fin structure at least a portion of which is separated by a plurality of first trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of first trenches 2 is formed on the lower surface of the first source region 3 and in contact with the first source region 3. A first conductivity type JFET region 8 is formed below the channel region 5, and second conductivity type body regions 9 are formed on both sides of the JFET region 8. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 13 has a gate insulating film disposed inside the first trench 2 and a gate electrode including a region at least part of which is disposed inside the first trench 2, and a channel current flows vertically (in the depth direction) in the channel region 5. The gate electrodes embedded inside the first trench 2 are connected to each other outside the first trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to that of FIG. 13 described above.

[0008] Japanese Patent Application Laid-Open No. 2004-207289

[0009] According to the structure of the conventional semiconductor device 1 shown in Fig. 13, the number of channels can be increased by reducing the trench pitch and increasing the channel density, thereby reducing the on-resistance when viewed from the perspective of the entire semiconductor chip. However, the conventional semiconductor device 1 shown in Fig. 13 has a problem in that, although the on-resistance is low due to the high channel density, the short-circuit resistance is correspondingly low.

[0010] Furthermore, in the conventional semiconductor device 1 shown in FIG. 13, the thickness (dimension in the depth direction) of the JFET region 8 is thin, which causes a problem of low short-circuit resistance.

[0011] Furthermore, in the conventional semiconductor device 1 shown in FIG. 13 , when the impurity concentration of the JFET region 8 is the same as the impurity concentration of the drift region 10, the impurity concentration of the JFET region 8 is as low as the impurity concentration of the drift region 10, which increases the resistance of the JFET region 8 and makes it impossible to sufficiently reduce the on-resistance.

[0012] The problem to be solved by the present invention is to provide a semiconductor device that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.

[0013] In order to solve the above-mentioned problems, a semiconductor device of the present invention includes a first source region of a first conductivity type including a region having a fin structure at least a portion of which is separated by the first trenches when viewed from above, a gate insulating film disposed inside the first trench, a gate electrode including a region at least a portion of which is disposed inside the first trench, a first JFET region of the first conductivity type disposed below the channel region, first body regions of a second conductivity type disposed on both sides of the first JFET region, a second JFET region of the first conductivity type disposed in contact with the bottom surface of the first JFET region, and a second JFET region of the first conductivity type disposed on both sides of the second JFET region and in contact with the bottom surface of the first body region. the first JFET region has a second body region of a second conductivity type, a drift region of a first conductivity type disposed below the second JFET region, and a drain region of the first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region, wherein ends of the bottom surfaces of the plurality of first trenches in the first direction are disposed within the first body region, the channel region is connected to the first body region, and a channel current flows in the channel region in a vertical direction, the length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction, the impurity concentration of the first JFET region is higher than the impurity concentration of the second JFET region, the impurity concentration of the second JFET region is higher than the impurity concentration of the drift region, and both dimensions of the first body region and the first JFET region in the depth direction from a bottom of the first trench are greater than 0.5 μm.

[0014] According to the present invention, in a trench MOSFET with a vertical channel fin structure, it is possible to reduce the on-resistance while ensuring short-circuit resistance.

[0015] Top perspective view of the semiconductor device of Example 1. Cross-sectional view taken along the line X1-X1' of FIG. 1. Cross-sectional view taken along the line X2-X2' of FIG. 1. Cross-sectional view taken along the line Y1-Y1' of FIG. 1. Cross-sectional view taken along the line X1-X1' of the semiconductor device of Example 2. Cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 2. Cross-sectional view taken along the line Y1-Y1' of the semiconductor device of Example 2. Cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 3. Cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 4. Cross-sectional view taken along the line X2-X2' of the semiconductor device of Example 5. Impurity concentration profile with respect to the depth in the Z1-Z1' direction of FIG. 10 in the semiconductor device of Example 5. Cross-sectional view taken along the line X1-X1' of the semiconductor device of Example 6. Perspective view schematically showing a trench MOSFET having a conventional vertical channel fin structure.

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0017] FIG. 1 is a top perspective view of the semiconductor device of Example 1. FIG. 2 is a cross-sectional view taken along the line X1-X1' of FIG. 1. FIG. 3 is a cross-sectional view taken along the line X2-X2' of FIG. 1. FIG. 4 is a cross-sectional view taken along the line Y1-Y1' of FIG. 1. In FIG. 1, the gate electrode 7, the gate insulating film 6, the interlayer insulating film 14, the source electrode 12, and the barrier metal 18 are not shown. Also, in FIG. 1, the position where the source contact 17 is disposed is indicated by a dotted line.

[0018] The semiconductor device 1 of this embodiment includes a plurality of first trenches 2, a first source region 3 of the first conductivity type, a channel region 5 of the second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of the first conductivity type, a body region 9 of the second conductivity type, a drift region 10 of the first conductivity type, and a drain region 11 of the first conductivity type.

[0019] In this embodiment, the case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type. Also, regarding the impurity concentration, an example is shown in the embodiment, but the present invention is not limited to this, and it may be changed within the range where the intended operations and effects in the embodiment can be achieved.

[0020] The plurality of first trenches 2 have a longitudinal direction in a first direction (the X1-X1' direction in FIG. 1) when viewed in a plan view, and a lateral direction in a second direction (the Y1-Y1' direction in FIG. 1), and are arranged in a plurality in the second direction. Furthermore, a plurality of first trench groups constituted by the plurality of first trenches 2 arranged in the second direction are also arranged in the first direction. Note that the first trenches 2 indicated by dotted lines in the cross-sectional view of FIG. 3 are hypothetical positions corresponding to the first trenches 2 in order to explain the positional relationship between other components and the first trenches 2.

[0021] The first source region 3 of the first conductivity type includes a region having a fin structure, at least a part of which is separated by the plurality of first trenches 2. The impurity concentration of the first source region 3 is, for example, a high concentration of n+.

[0022] A second conductivity type channel region 5 having a fin structure is formed on the lower surface of the first source region 3 in contact with the first source region 3 and separated by a plurality of first trenches 2. The impurity concentration of the channel region 5 is, for example, a medium concentration of p.

[0023] A first conductivity type JFET region 8 is formed below the channel region 5, and second conductivity type body regions 9 are formed on both sides of the JFET region 8. In this embodiment, the JFET region 8 includes a first conductivity type JFET region 8A disposed below the channel region 5 and a second conductivity type JFET region 8B disposed in contact with the lower surface of the first JFET region 8A. The body region 9 includes a second conductivity type first body region 9A disposed on both sides of the first JFET region 8A and a second conductivity type second body region 9B disposed on both sides of the second JFET region 8B in contact with the lower surface of the first body region 9A. The width (length in the first direction) of the second JFET region 8B (WJ2 in FIG. 2 ) is set longer than the width (length in the first direction) of the first JFET region 8A (WJ1 in FIG. 2 ). The dimensions (tJ1 in FIG. 2) of the first body region 9A and the first JFET region 8A in the depth direction from the bottom of the first trench 2 are both set to be greater than 0.5 μm. The impurity concentration of the first JFET region 8A is set to be higher than the impurity concentration of the second JFET region 8B. The impurity concentration of the second JFET region 8B is set to be higher than the impurity concentration of the drift region 10. The impurity concentration of the first JFET region 8A is, for example, a medium concentration of n. The impurity concentration of the second JFET region 8B is, for example, a low concentration of n-. The impurity concentrations of the first body region 9A and the second body region 9B are, for example, a medium concentration of p. The operation and effects of the JFET region 8 and body region 9 of this embodiment will be described later.

[0024] 3, the channel region 5 is connected to the first body region 9A. Therefore, the width (length in the first direction) of the channel region 5 is the width (length in the first direction) of the first trench 2 minus the overlap width between the first trench 2 and the body region 9. Therefore, the width of the channel region 5 is approximately the same as the width (WJ1 in FIG. 2) of the first JFET region 8A.

[0025] A drift region 10 of the first conductivity type is arranged below the JFET region 8. The drift region 10 is also arranged below the body region 9. A drain region 11 of the first conductivity type, which has a higher impurity concentration than the drift region 10, is arranged below the drift region 10. The impurity concentration of the drift region 10 is, for example, a low concentration of n-. The impurity concentration of the drain region 11 is, for example, a high concentration of n+.

[0026] 2 and 4, a gate insulating film 6 is disposed inside the first trench 2. Furthermore, at least a portion of a gate electrode 7 is disposed inside the first trench 2. The gate electrodes 7 disposed inside the first trench 2 are connected to each other outside the first trench 2. The gate electrodes 7 can be formed of, for example, polysilicon.

[0027] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the first trench 2. In other words, the semiconductor device 1 is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch and increasing the channel density, thereby reducing the on-resistance of the entire semiconductor chip.

[0028] Furthermore, in the semiconductor device 1 of this embodiment, as shown in FIG. 2 , the width (length in the first direction) (WTG) of the gate electrode 7 disposed inside the first trench 2 is longer than the width (length in the first direction) (WJ1) of the first JFET region 8A. The width (WTG) of the gate electrode 7 is calculated by subtracting the thickness of the gate insulating film (two portions, one in the first direction) from the width (length in the first direction) (WTR) of the first trench 2. Since WTR > WTG > WJ, the ends of the bottom surfaces of the plurality of first trenches 2 in the first direction and the ends of the bottom surfaces of the gate electrodes 7 in the first trenches 2 in the first direction are located within the first body region 9A. This results in a structure in which three-dimensional corners of the first trench 2 and the gate electrode 7 exist within the first body region 9A. Therefore, even when a high voltage is applied, the concentration of the electric field is alleviated at the three-dimensional corners of the first trench 2 where the electric field is likely to concentrate and breakdown of the gate insulating film 6 is likely to occur, thereby suppressing breakdown of the gate insulating film 6. The higher the withstand voltage and the higher the applied voltage, the more likely the electric field is to concentrate at the three-dimensional corners of the first trench 2 and breakdown of the gate insulating film 6 is likely to occur, so the higher the withstand voltage of the semiconductor device 1, the more desirable this configuration is.

[0029] Next, the operation and effect of the JFET region 8 and the body region 9 of this embodiment will be described.

[0030] In the semiconductor device 1 of this embodiment, the impurity concentration of the JFET region 8 (first JFET region 8A and second JFET region 8B) is set higher than the impurity concentration of the drift region 10, and the thickness (dimension in the depth direction) (tJ1 in FIG. 2) of the first body region 9A and first JFET region 8A from the bottom of the first trench 2 is set to be greater than 0.5 μm, as shown in FIG. 3. It is desirable to set the thickness (tJ1) of the first body region 9A and the first JFET region 8A from the bottom of the first trench 2 to be approximately the same thickness.

[0031] When a high voltage is applied between the drain and source, the depletion layer spreads in the JFET region 8, ensuring a breakdown voltage. Here, when the thickness (tJ1) of the JFET region 8 is thin, as in the conventional structure shown in FIG. 13, the depletion layer spreads mainly in the depth direction. The depletion layer spreads more easily when the impurity concentration is low. Therefore, the concentration of the JFET region 8 cannot be increased, and it is set to 1×10, the same as the concentration of the general drift region 10. １６ cm －３ is set to a certain extent.

[0032] In contrast, in this embodiment, by increasing the thickness (tJ1) of the first JFET region 8A, when a high voltage is applied between the drain and source, a depletion layer begins to spread laterally from the first body region 9A on both sides of the first JFET region 8A. When a higher voltage is applied, the depletion layer closes and pinches off. This allows the depletion layer to expand only half the width (WJ1) of the first JFET region 8A, resulting in a depletion layer with the thickness (tJ1) of the first JFET region 8A. As a result, the depletion layer expansion required for complete depletion is small, allowing the impurity concentration of the first JFET region 8A to be increased while maintaining the breakdown voltage. Furthermore, since the impurity concentration of the first JFET region 8A can be set high, the resistance of the first JFET region 8A can be reduced, thereby reducing the on-resistance. The impurity concentration of the first JFET region 8A can be increased as the thickness (tJ1) of the first JFET region 8A increases and the width (WJ1) of the first JFET region 8A decreases. Furthermore, the temperature characteristic of the resistance of the first JFET region 8A is positive, but if the impurity concentration is high, the rate of increase in the resistance of the first JFET region 8A is low even in a high-temperature environment, so the on-resistance of the entire semiconductor chip at high temperatures can be maintained at a low level.

[0033] The second JFET region 8B of this embodiment operates in the same manner as the first JFET region 8A. The impurity concentration of the second JFET region 8B can also be set higher than that of the drift region 10, so the resistance of the second JFET region 8B can be reduced, and the on-resistance can be reduced. As a result, the on-resistance can be further reduced compared to when the second JFET region 8B is not present.

[0034] The thickness (tJ1) of both the first body region 9A and the first JFET region 8A from the bottom of the first trench 2 is preferably 0.8 μm or more and 1.3 μm or less. The larger the thickness (tJ1) of the first JFET region 8A, the greater the above-mentioned effects. The thickness (tJ2) of the second JFET region 8B (the dimension of the second JFET region 8B in the depth direction from the bottom of the first JFET region 8A) is preferably 0.5 μm or more and 1.0 μm or less.

[0035] The width (WTR) of the first trench 2 is preferably 0.8 μm or more and 1.8 μm or less.

[0036] The width (WJ1) of the first JFET region 8A is preferably 0.3 μm or more and 1.4 μm or less. The narrower the width (WJ1) of the first JFET region 8A, the greater the above-mentioned effects. The width (WJ2) of the second JFET region 8B is preferably 2.0 μm or more and 3.5 μm or less.

[0037] The impurity concentration of the first JFET region 8A is 8×10 １６ cm －３ That's it, 1 x 10 １８ cm －３ The impurity concentration of the second JFET region 8B is preferably 1×10 １６ cm －３ That's it, 5 x 10 １７ cm －３ The impurity concentration of the drift region 10 is preferably 1×10 or less, which is the same as the impurity concentration of a general drift region 10. １５ cm －３ That's it, 1 x 10 １６ cm －３ It is desirable that the following:

[0038] As described above, according to this embodiment, it is possible to realize a semiconductor device 1 that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure.

[0039] In addition, the semiconductor device 1 of this embodiment also has a source electrode 12, a drain electrode 13, an interlayer insulating film 14, a second source region 4 of the second conductivity type, a second trench 15, a buried film 16, a source contact 17, and a barrier metal 18.

[0040] The source electrode 12 is disposed on the front surface side and is an electrode made of a metal such as aluminum.

[0041] The drain electrode 13 is disposed on the back surface side and is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold), and is electrically connected to the drain region 11 .

[0042] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the first source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0043] The second source region 4 of the second conductivity type is provided in contact with the upper surface of at least a portion of the first body region 9A. The impurity concentration of the second source region 4 is set higher than that of the first body region 9A. The impurity concentration of the second source region 4 is, for example, a high concentration of p+. By providing the second source region 4, the first body region 9A of the second conductivity type and the source electrode 12 can be connected with lower resistance than connecting them via the first source region 3 of the first conductivity type or directly to the first body region 9A.

[0044] The second trench 15 is disposed at a position overlapping the second body region 9B. When forming the second body region 9B by ion implantation, ion implantation through the second trench 15 allows impurity ions to be implanted deep at low energy. The second trench 15 is not essential, but is preferably provided. It is desirable to set the depth of the second trench 15 to the same depth as the first trench 2, since this allows both to be formed simultaneously. However, the depth of the second trench 15 is not limited to this.

[0045] The buried film 16 is buried inside the second trench 15. For example, a single or stacked insulating film can be used as the buried film 16. For example, a silicon oxide film or a silicon nitride film can be used as the buried film 16. The buried film 16 can be formed by, for example, a CVD method. In this embodiment, the upper surface of the buried film 16 is positioned lower than the upper surface of the first source region 3, but this is not limited to this. Furthermore, the buried film 16 may at least partially include a conductive film. This allows the source potential from the source electrode 12 to be transmitted to a deep position by the conductive film, thereby more reliably fixing the potential of the body region 9 to the source potential.

[0046] The source contact 17 is a contact region that electrically connects the source electrode 12 and the first source region 3 or the source electrode 12 and the second source region 4. The source contact 17 is also formed by being filled with a metal such as aluminum, similar to the source electrode 12. It is desirable to connect the first source region 3 and the source contact 17 or the second source region 4 and the source contact 17 via a barrier metal 18. For example, TiN or Ti can be used as the barrier metal 18. By providing the source contact 17, the source electrode 12 can be connected to the first source region 3 or the second source region 4 via the source contact 17, thereby stabilizing the connection between the source electrode 12 and the first source region 3 or the second source region 4.

[0047] The first source region 3, the second source region 4, and the source contact 17 may be arranged such that the source contact 17 has its longitudinal direction in the second direction, and the first source region 3 and the second source region 4 are arranged alternately at least in the region overlapping with the source contact 17, as shown in FIG. 1 . The second source region 4 has its longitudinal direction in the first direction and its lateral direction in the second direction, and a plurality of second source regions 4 are arranged in the second direction. The arrangement of the first source region 3, the second source region 4, and the source contact 17 is not limited to this, and other arrangements may be used.

[0048] The semiconductor device 1 of this embodiment can be formed using, for example, an n+ type SiC substrate, but is not limited to this and may also be formed using a Si substrate, etc. Furthermore, for portions of this specification where no special description of the manufacturing method is given, detailed description will be omitted because the semiconductor device can be manufactured using a general semiconductor device manufacturing method, such as forming an n+ type drain region 11 on an n+ type SiC substrate and forming an n- type drift region 10 by epitaxial growth. The same applies to the method of forming the source contact 17, etc.

[0049] As a method for adjusting the impurity concentrations of the first JFET region 8A and the second JFET region 8B, for example, an n+ type SiC substrate may be used, an n+ type drain region 11 may be used as a base, an n- type drift region 10 may be formed therefrom by epitaxial growth, and then epitaxial layers with different impurity concentrations may be stacked to form the second JFET region 8B and the first JFET region 8A. Also, since stacking epitaxial layers can be costly in some cases, an epitaxial layer with a low and uniform impurity concentration equivalent to the n- type drift region 10 may be formed, and then the first JFET region 8A and the second JFET region 8B may be additionally formed in part of the formed epitaxial layer using impurity ion implantation technology or the like.

[0050] Furthermore, in a pn structure using SiC, for example, degradation of breakdown voltage and characteristics may occur as a result of energization, etc. To suppress this, a buffer region (not shown) of the same conductivity type (first conductivity type) may be provided between the drift region 10 and the drain region 11. The impurity concentration of the buffer region is preferably higher than that of the drift region 10 and lower than that of the drain region 11, for example, 1×10 １６ cm －３ That's it, 1 x 10 １９ cm －３ The following is desirable: The thickness of the buffer region may be determined arbitrarily depending on the purpose, such as the breakdown voltage of the semiconductor device 1 and the degree of deterioration suppression.

[0051] The impurity concentration and thickness of the channel region 5 are related to the threshold voltage of MOS operation and the channel resistance (and thus the on-resistance). １７ cm －３ That's it, 1 x 10 １９ cm －３ Less than 1 x 10 is desirable. １８ cm －３ The impurity concentration profile of the channel region 5 may be a uniform profile or a non-uniform profile. As an example of a non-uniform profile, a gradient profile may be used in order to shallow the channel depth. The gradient profile may be, for example, a profile in which the impurity concentration on the source side is set to a high peak value and the impurity concentration decreases in the depth direction, i.e., toward the drain side. For example, in the case of a non-uniform profile such as a gradient profile, the peak value of the impurity concentration is 1×10 １７ cm －３ That's it, 1 x 10 １９ cm －３ Less than 1 x 10 is desirable. １８ cm －３ A degree is more desirable.

[0052] For example, when a high voltage is applied between the drain and source, the first JFET region 8A is depleted and at the same time, a depletion layer extends to the body region 9 side. Therefore, from the viewpoint of promoting depletion and maintaining a high breakdown voltage, it is important to set the impurity concentration on the body region 9 side taking this into consideration.

[0053] The impurity concentration of the body region 9 is, for example, 1×10 １７ cm －３ That's it, 1 x 10 １９ cm －３ It is desirable to set the impurity concentration of the first body region 9A to be higher than the impurity concentration of the channel region 5 within the above-mentioned range of impurity concentrations.

[0054] The impurity concentration profile of the body region 9 may be either uniform or non-uniform. For example, the impurity concentration of the first body region 9A and the impurity concentration of the second body region 9B may be the same, or the impurity concentration of the first body region 9A may be made higher than the impurity concentration of the second body region 9B as the target breakdown voltage design increases.

[0055] Furthermore, in order to prevent the breakdown point in the drain-source breakdown voltage characteristics from affecting the bottom of the first trench 2, for example, in order to bring the breakdown point (avalanche point) inside the second body region 9B, the second body region 9B may have a point with a higher impurity concentration than other parts of the second body region 9B.

[0056] Fig. 5 is an X1-X1' cross-sectional view of the semiconductor device of Example 2. Fig. 6 is an X2-X2' cross-sectional view of the semiconductor device of Example 2. Fig. 7 is a Y1-Y1' cross-sectional view of the semiconductor device of Example 2.

[0057] Example 2 is a modification of Example 1. In Example 1, the JFET region 8 has a two-stage configuration, whereas in Example 2, the JFET region 8 has a three-stage or more configuration.

[0058] For example, when the JFET region 8 has a three-stage configuration, the semiconductor device 1 may have a first-conductivity-type third JFET region 8C arranged above the drift region 10 and in contact with the underside of the second JFET region 8B, and a second-conductivity-type third body region 9C arranged on both sides of the third JFET region 8C in contact with the underside of the second body region 9B. The width (length in the first direction) of the third JFET region 8C (WJ3 in FIG. 5 ) is longer than the width (length in the first direction) of the second JFET region 8B (WJ2 in FIG. 5 ). The impurity concentration of the third JFET region 8C is higher than the impurity concentration of the drift region 10. The impurity concentration of the third JFET region 8C may be the same as or lower than the impurity concentration of the second JFET region 8B. The impurity concentration of the third JFET region 8C is, for example, a low n- concentration.

[0059] Furthermore, when the JFET region 8 has a four-stage configuration, the semiconductor device 1 may have a fourth JFET region 8D of the first conductivity type arranged above the drift region 10 and in contact with the underside of the third JFET region 8C, and fourth body regions 9D of the second conductivity type arranged on both sides of the fourth JFET region 8D and in contact with the underside of the third body region 9C. The width (length in the first direction) of the fourth JFET region 8D (WJ4 in FIG. 5 ) is longer than the width (length in the first direction) of the third JFET region 8C (WJ3 in FIG. 5 ). The impurity concentration of the fourth JFET region 8D is higher than the impurity concentration of the drift region 10. The impurity concentration of the fourth JFET region 8D may be the same as or lower than the impurity concentration of the third JFET region 8C. The impurity concentration of the fourth JFET region 8D is, for example, a low n- concentration.

[0060] When the JFET region 8 has a four-stage configuration, it is desirable to have a stepped second trench 15 positioned so as to overlap the fourth body region 9D. As in the first embodiment, ion implantation through the stepped second trench 15 allows impurity ions to be implanted deep into the trench with low energy. In this case, impurity ions can be implanted not only in the vertical direction (depth direction) but also obliquely onto the sidewall of the second trench 15, thereby spreading the impurities laterally across the second trench 15. It is desirable that the bottom of the stepped second trench 15 be deeper than the bottom of the first body region 9A.

[0061] When the JFET region 8 has a three-stage configuration, a stepped second trench 15 may be provided at a position overlapping with the third body region 9C, or a normal, non-stepped second trench 15 having a bottom deeper than the bottom of the first body region 9A may be provided at a position overlapping with the third body region 9C.

[0062] When the JFET region 8 is configured to have five or more stages, the number of stages may be increased in a similar manner.

[0063] The thickness of the third JFET region 8C (dimension in the depth direction from the bottom of the second JFET region 8B) (tJ3 in FIG. 5) is preferably 0.5 μm or more and 1.0 μm or less. The thickness of the fourth JFET region 8D (dimension in the depth direction from the bottom of the third JFET region 8C) (tJ4 in FIG. 5) is preferably 0.5 μm or more and 1.0 μm or less. Regardless of the number of stages, the dimension of the JFET region 8 in the depth direction from the bottom of the first trench 2 is preferably 5.0 μm or less. Furthermore, regardless of the number of stages, the width of the JFET region 8 (length in the first direction) is preferably 3.5 μm or less.

[0064] According to the present embodiment, by adding the third JFET region 8C and the fourth JFET region 8D, which have higher impurity concentrations than the drift region 10, the on-resistance can be further reduced compared to that of the first embodiment for the same reason as the effect achieved by adding the second JFET region 8B in the first embodiment.

[0065] FIG. 8 is a cross-sectional view of the semiconductor device of the third embodiment taken along the line X2-X2'.

[0066] Example 3 is a modification of Example 1. In the semiconductor device 1 of this example, the first source region 3 has, at least in a portion separated by a plurality of first trenches 2, a thin first source region 3A whose thickness (dimension in the depth direction) is smaller than that of other portions of the first source region 3.

[0067] The thin first source region 3A has a smaller thickness than the first source region 3, and therefore has a higher resistance. Furthermore, the resistance increases at high temperatures, such as when a short circuit occurs. As a result, the thin first source region 3A has a higher potential than the first source region 3, and the voltage of the JFET region 8 increases accordingly. This strengthens the reverse bias of the PN junction between the JFET region 8 and the body region 9, thereby further depleting the JFET region 8. This reduces the saturation current compared to Example 1, and improves the short-circuit resistance.

[0068] Furthermore, since the thin first source region 3A is thinner than the first source region 3, the overlap capacitance between the gate electrode 7 extending in the depth direction of the first trench 2 and the thin first source region 3A is reduced, thereby reducing the gate capacitance, thereby enabling an increase in switching speed.

[0069] Therefore, according to the semiconductor device 1 of this embodiment, in addition to the effects of the first embodiment, it is possible to improve the short-circuit resistance and reduce the gate capacitance while maintaining a high channel density, and also to increase the switching speed.

[0070] Here, in order to fully obtain the effect of improving the short-circuit resistance, it is desirable that the sheet resistance of the thin first source region 3A be 10 times or more the sheet resistance of the other parts of the first source region 3. In order to increase the sheet resistance, it is desirable that the thin first source region 3A have a lower impurity concentration than the other parts of the first source region 3.

[0071] Furthermore, in this embodiment, since the thickness of the thin first source region 3A is reduced, the first trench 2 can be made shallower, and the dimension (tJ1) of the first JFET region 8A in the depth direction from the bottom of the first trench 2 can be increased.

[0072] FIG. 9 is a cross-sectional view of the semiconductor device of the fourth embodiment taken along the line X2-X2'.

[0073] Example 4 is a modification of Example 3. In the semiconductor device 1 of this example, only one end of the thin first source region 3A is connected to another portion of the first source region 3. While FIG. 9 shows an example in which the left end of the thin first source region 3A is connected to another portion of the first source region 3, the reverse may also be true. Furthermore, the end to be connected may be changed depending on the location, so that both a structure in which the left end of the thin first source region 3A is connected and a structure in which the right end of the thin first source region 3A is connected may exist.

[0074] In this way, by thinning out the connections, a larger resistance can be provided, further improving the short-circuit resistance.

[0075] The frequency of thinning may also be adjusted within the chip surface. For example, the frequency of thinning may be increased in areas that are prone to high temperatures in the event of a short circuit, thereby reducing the amount of heat generated.

[0076] In this case, the thin first source region 3A may have two types: a first connection structure in which both ends of the thin first source region 3A are connected to other parts of the first source region 3 as shown in FIG. 8 , and a second connection structure in which only one end of the thin first source region 3A is connected to other parts of the first source region 3 as shown in FIG. 9 .

[0077] FIG. 10 is a cross-sectional view of the semiconductor device of the fifth embodiment taken along the line X2-X2'.

[0078] Example 5 is a modification of Example 3. The semiconductor device 1 of this example has, between the channel region 5 and the first JFET region 8A, a push-back region 19 of the first conductivity type, which has a higher impurity concentration than the first JFET region 8A. The impurity concentration of the push-back region 19 is, for example, a medium concentration of n-type.

[0079] Fig. 11 shows the impurity concentration profile with respect to depth in the Z1-Z1' direction of Fig. 10 in the semiconductor device of Example 5. The vertical axis represents the impurity concentration IC, and the horizontal axis represents the depth DP.

[0080] When the channel region 5 is formed by ion implantation, for example, the profile of aluminum, which is a p-type dopant, tends to tail off, making the channel region 5 deeper than necessary. This requires the first trench 2 to be made deeper, which increases the gate capacitance and shortens the effective length of the first JFET region 8A, thereby reducing the short-circuit resistance.

[0081] Therefore, by using nitrogen, for example, as the ion species of the punch-back region 19 and arranging the first conductivity type punch-back region 19 having a higher impurity concentration than the first JFET region 8A between the channel region 5 and the first JFET region 8A, the channel region depth d1 in the case without the punch-back region can be reduced to the channel region depth d2 in the case with the punch-back region, and the low concentration region (foot region) of the channel region 5 can be reduced, so that the depth of the channel region 5 can be made shallower while maintaining the required amount of charge. This reduces the gate capacitance and allows the dimension of the first JFET region 8A in the depth direction to be increased, thereby improving short-circuit resistance.

[0082] The returning region 19 may be applied to Example 1 and the like.

[0083] FIG. 12 is a cross-sectional view of the semiconductor device of the sixth embodiment taken along the line X1-X1'.

[0084] Example 6 is a modification of Example 1. In the semiconductor device 1 of this example, the first source region 3 has a 3C—SiC region 20 provided on the outermost surface of the 4H—SiC region.

[0085] Typically, SiC used in power devices is a polytype called 4H-SiC, which has a wide band gap and is suitable for high voltage resistance, but it is difficult to achieve ohmic contact and generally requires heat treatment at 900°C or higher. In contrast, 3C-SiC has a small band gap, making it possible to achieve ohmic contact at low temperatures. Applying low-temperature ohmic contact can avoid degradation of the oxide film during high-temperature processes, improving the reliability of the oxide film and therefore short-circuit resistance.

[0086] The surface of 4H—SiC can be converted to 3C—SiC by implanting a high dose of ions with a large mass, such as phosphorus, and then recrystallizing the surface. Note that if a high-dose phosphorus implantation layer is located near the channel region 5, it will deteriorate the channel characteristics. Therefore, it is possible to avoid providing a 3C—SiC region 20 near the channel region 5.

[0087] Furthermore, when applied to Example 3, for example, since the thin first source region 3A is disposed in the vicinity of the channel region 5, the 3C-SiC region 20 may not be provided in the thin first source region 3A, and the 3C-SiC region 20 may be provided in other parts of the first source region 3.

[0088] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied.

[0089] REFERENCE SIGNS LIST 1 semiconductor device 2 first trench 3 first source region 3A thin first source region 4 second source region 5 channel region 6 gate insulating film 7 gate electrode 8 JFET region 8A first JFET region 8B second JFET region 8C third JFET region 8D fourth JFET region 9 body region 9A first body region 9B second body region 9C third body region 9D fourth body region 10 drift region 11 drain region 12 source electrode 13 drain electrode 14 interlayer insulating film 15 second trench 16 buried film 17 source contact 18 barrier metal 19 push-back region 20 3C-SiC region IC impurity concentration DP depth d1 channel region depth without push-back region d2 channel region depth with push-back region

Claims

1. A first conductive type first source region including a plurality of first trenches having a longitudinal direction in a first direction and a short side direction in a second direction when viewed in plan and arranged in a plurality in the second direction, and a region having a fin structure at least partially delimited by the plurality of first trenches; a channel region of a second conductive type of a fin structure delimited by the plurality of first trenches and in contact with the lower surface of the first source region; a gate insulating film disposed inside the first trench; a gate electrode including a region at least partially disposed inside the first trench; a first JFET region of the first conductive type disposed below the channel region; a first body region of the second conductive type disposed on both sides of the first JFET region; a second JFET region of the first conductive type disposed in contact with the lower surface of the first JFET region; a second body region of the second conductive type disposed in contact with the lower surface of the first body region on both sides of the second JFET region; a drift region of the first conductive type disposed below the second JFET region; and a drain region of the first conductive type disposed below the drift region and having a higher impurity concentration than the drift region. The end portions of the bottom surfaces of the plurality of first trenches in the first direction are disposed in the first body region. The channel region is connected to the first body region, and a channel current flows in the longitudinal direction in the channel region. The length of the second JFET region in the first direction is longer than the length of the first JFET region in the first direction. The impurity concentration of the first JFET region is higher than the impurity concentration of the second JFET region. The impurity concentration of the second JFET region is higher than the impurity concentration of the drift region. A semiconductor device characterized in that the depth dimensions of the first body region and the first JFET region from the lower part of the first trench are both larger than 0.5 μm.

2. The semiconductor device according to claim 1, wherein the depth dimension of the first JFET region from the lower part of the first trench is 0.8 μm or more and 1.3 μm or less, and the depth dimension of the second JFET region from the lower part of the first JFET region is 0.5 μm or more and 1.0 μm or less.

3. The semiconductor device according to claim 1, wherein the length of the first trench in the first direction is 0.8 μm or more and 1.8 μm or less.

4. The semiconductor device according to claim 1, wherein the length of the first JFET region in the first direction is 0.3 μm or more and 1.4 μm or less, and the length of the second JFET region in the first direction is 2.0 μm or more and 3.5 μm or less.

5. In claim 1, the impurity concentration of the first JFET region is 8×10 １６ cm －３ or more and 1×10 １８ cm －３ or less; the impurity concentration of the second JFET region is 1×10 １６ cm －３ or more and 5×10 １７ cm －３ or less; and the impurity concentration of the drift region is 1×10 １５ cm －３ or more and 1×10 １６ cm －３ or less. A semiconductor device characterized by this.

6. The semiconductor device according to claim 1, having a buffer region of a first conductivity type, between the drift region and the drain region, with an impurity concentration higher than that of the drift region and lower than that of the drain region.

7. In claim 6, the impurity concentration of the buffer region is 1×10 １６ cm －３ or more and 1×10 １９ cm －３ or less. A semiconductor device characterized by this.

8. In claim 1, the impurity concentration in the channel region is 1×10 １７ cm －３ or more and 1×10 １９ cm －３ or less. A semiconductor device characterized by this.

9. In claim 1, the impurity concentrations of the first body region and the second body region are 1×10 １７ cm －３ or more and 1×10 １９ cm －３ or less. A semiconductor device characterized by this.

10. The semiconductor device according to claim 1, having a point with a higher impurity concentration than other portions in the second body region, inside the second body region.

11. The semiconductor device according to claim 1, having a second trench disposed at a position overlapping the second body region.

12. The semiconductor device according to claim 11, having an embedded film embedded inside the second trench, wherein the embedded film is a single or stacked insulating film.

13. The semiconductor device according to claim 11, having an embedded film embedded inside the second trench, wherein the embedded film includes a conductive film at least in part.

14. The semiconductor device according to claim 1, having a second source region of a second conductivity type, in contact with the upper surface of at least a part of the first body region and having a higher impurity concentration than the first body region.

15. The semiconductor device according to claim 1, having a third JFET region of a first conductivity type, disposed in contact with the lower surface of the second JFET region above the drift region, and third body regions of a second conductivity type, disposed in contact with the lower surface of the second body region on both sides of the third JFET region, wherein the length of the third JFET region in the first direction is longer than that of the second JFET region in the first direction, and the impurity concentration of the third JFET region is higher than that of the drift region.

16. In claim 15, above the drift region, a fourth JFET region of the first conductivity type disposed in contact with the lower surface of the third JFET region, and on both sides of the fourth JFET region, a fourth body region of the second conductivity type disposed in contact with the lower surface of the third body region, wherein the length of the fourth JFET region in the first direction is longer than the length of the third JFET region in the first direction, and the impurity concentration of the fourth JFET region is higher than the impurity concentration of the drift region. A semiconductor device characterized by this.

17. In claim 16, having a stepped second trench disposed at a position overlapping the fourth body region. A semiconductor device characterized by this.

18. In claim 1, the first source region has a thin first source region in which at least in a portion separated by the plurality of first trenches, the dimension in the depth direction is smaller than that of other portions in the first source region. A semiconductor device characterized by this.

19. In claim 18, the thin first source region has an impurity concentration lower than that of other portions in the first source region. A semiconductor device characterized by this.

20. In claim 18, the sheet resistance of the thin first source region is 10 times or more the sheet resistance of other portions in the first source region. A semiconductor device characterized by this.

21. In claim 18, only one end of the thin first source region on one side is connected to other portions in the first source region. A semiconductor device characterized by this.

22. In claim 18, there are two types of connection structures: a first connection structure in which both ends of the thin first source region are connected to other portions in the first source region, and a second connection structure in which only one end of the thin first source region on one side is connected to other portions in the first source region. A semiconductor device characterized by this.

23. In claim 1, having a punch-back region of the first conductivity type with an impurity concentration higher than that of the first JFET region between the channel region and the first JFET region. A semiconductor device characterized by this.

24. In claim 1, the first source region has a 3C - SiC region provided on the outermost surface of the 4H - SiC region. A semiconductor device characterized by this.

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