Semiconductor device

Abstract

A light detecting device comprises　a main structure comprising a first section that includes a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge, and a peripheral region adjacent to the pixel region that includes a first conductive structure located at the first side of the first section. The main structure includes a second section that includes logic to process signals for the pixel region. In a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure. The main structure also includes a second conductive structure which, in the cross sectional view, is located at a second level within main structure that is between the first level and at least part of the second section.

Description

SEMICONDUCTOR DEVICECROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Japanese Priority Patent Application JP 2024-004900 filed on January 16, 2024, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device.

[0003] There has been proposed an imaging device that improves area efficiency of a substrate by stacking a sensor element and a logic chip (see PTL 1).

[0004] [PTL 1] JP 2020-80363ASummary

[0005] In the imaging device disclosed in PTL 1, a pad for joining the logic chip is provided on the back surface side of the sensor element, and a wiring layer electrically connected to a vertical signal line is disposed in the vicinity of the pad. In this case, there is a possibility that a change in a voltage level in the wiring layer of the logic chip is transmitted as noise to the sensor element via the pad, and the voltage level of the vertical signal line of the sensor element is varied. However, PTL 1 does not consider the need to suppress the noise from the logic chip, and does not disclose any countermeasure therefor.

[0006] In view of the above, the present disclosure provides a semiconductor device that improves area efficiency while improving resistance to noise.

[0007] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a first substrate including a first pad and signal wiring; a semiconductor chip joined to the first substrate by the first pad; and a conductive member disposed to cover at least a part of the signal wiring.

[0008] The conductive member may be disposed at a height different from that of the first pad.

[0009] The conductive member may be disposed on the first substrate.

[0010] The first substrate may include a second pad to which a bonding wire is connected, and the conductive member may be disposed at the same height as the second pad.

[0011] The first substrate may include a dummy wiring layer disposed at the same height as the conductive member and having an indefinite voltage level.

[0012] A thickness of the conductive member may be larger than a thickness of the signal wiring.

[0013] The conductive member may be disposed on the semiconductor chip.

[0014] The semiconductor chip may include a wiring layer disposed to at least partially overlap with the conductive member in plan view.

[0015] The semiconductor chip may include a plurality of the laminated wiring layers, and the conductive member may be disposed to cover, among the plurality of wiring layers, at least a part of the wiring layer on the side closest to the first substrate.

[0016] The conductive member may be set to a predetermined voltage level.

[0017] The first substrate may include a plurality of pixels, each of the plurality of pixels may include: a photoelectric conversion element; and a pixel circuit that generates a pixel signal photoelectrically converted by the photoelectric conversion element, and the signal wiring at least partially covered with the conductive member may transmit the pixel signal.

[0018] The semiconductor chip may be joined to the first substrate via a plurality of the first pads, and a plurality of pieces of the signal wiring may be disposed between two of the first pads adjacent to each other in a predetermined direction in plan view.

[0019] Two or more of the first pads may be arranged in a first direction and a second direction intersecting each other, the signal wiring may include: a plurality of pieces of first signal wiring disposed along the second direction between the two or more first pads arranged in the first direction in plan view; and a plurality of pieces of second signal wiring that is disposed along the first direction and connects the plurality of pieces of first signal wiring with the two or more first pads, and the conductive member may be disposed to cover at least a part of the plurality of pieces of first signal wiring and the plurality of pieces of second signal wiring.

[0020] An insulating layer disposed to cover the first pad, the signal wiring, and the plurality of pixels may be further included, and a thickness of the insulating layer may be different for each location of the first pad, the signal wiring, and the pixels.

[0021] The thickness of the insulating layer in a region that overlaps with the plurality of pixels in plan view may be larger than the thickness in a region that overlaps with the signal wiring.

[0022] The thickness of the insulating layer in a region that overlaps with the plurality of pixels in plan view may be larger than the thickness in a region that overlaps with the first pad.

[0023] The thickness of the insulating layer in a region that overlaps with the first pad in plan view may be larger than the thickness in a region that overlaps with the signal wiring.

[0024] The insulating layer may include a laminated insulating layer in which a plurality of insulating films each containing a different insulating material is laminated.

[0025] The conductive member may be disposed to face the signal wiring with the insulating layer interposed therebetween.

[0026] A second substrate stacked on a side of the first substrate opposite to a surface to which the semiconductor chip is joined, and a logic circuit disposed on at least one of the semiconductor chip or the second substrate may be further included.

[0027] Fig. 1 is a block diagram illustrating a schematic configuration of a semiconductor device according to the present disclosure.Figs. 2A and 2B are diagrams illustrating a cross-sectional configuration (Fig. 2A) and a planar configuration (Fig. 2B) of a semiconductor device according to an embodiment of the present disclosure.Fig. 3 is a planar layout diagram of a shield member.Fig. 4 is a cross-sectional view taken along line A-A in Fig. 3.Fig. 5 is a diagram illustrating a planar shape of the shield member.Figs. 6A to 6C are diagrams illustrating representative modifications of the planar shape of the shield member.Fig. 7 is a diagram illustrating a planar shape of a dummy wiring layer.Figs. 8A to 8D are diagrams illustrating representative examples of the planar shape of the dummy wiring layer.Fig. 9 is a flowchart of a process of manufacturing an imaging device according to the present embodiment.Fig. 10A is a cross-sectional view of each step of manufacturing the imaging device according to the present embodiment.Fig. 10B is a cross-sectional view of a manufacturing step subsequent to Fig. 10A.Fig. 10C is a cross-sectional view of a manufacturing step subsequent to Fig. 10B.Fig. 10D is a cross-sectional view of a manufacturing step subsequent to Fig. 10C.Fig. 10E is a cross-sectional view of a manufacturing step subsequent to Fig. 10D.Fig. 10F is a cross-sectional view of a manufacturing step subsequent to Fig. 10E.Fig. 10G is a cross-sectional view of a manufacturing step subsequent to Fig. 10F.Fig. 11 is a cross-sectional view illustrating a film thickness difference of a laminated insulating layer of SiON / SiN according to the present embodiment.Fig. 12 is a cross-sectional view illustrating a film thickness difference of a laminated insulating layer according to a comparative example.Fig. 13 is a cross-sectional view illustrating details of the film thickness of the laminated insulating layer of SiON / SiN / SiON covering a pad and the shield member.Figs. 14A to 14D are cross-sectional views illustrating a state in which the film thickness of the laminated insulating layer changes depending on an interval of structure bodies such as the shield member, the dummy wiring layer, the pad, and the like.Figs. 15A and 15B are cross-sectional views illustrating an example in which the shield member is disposed on a semiconductor chip.Fig. 16 is a diagram for explaining a thickness and a lateral width of the pad, the shield member, and the like.Fig. 17 is a cross-sectional view illustrating an exemplary layer configuration of a structure body such as the shield member, the dummy wiring layer, or the like.Fig. 18 is a cross-sectional view illustrating an exemplary layer configuration of the pad.Fig. 19 is a cross-sectional view of the semiconductor device in which a silicon substrate is joined with another silicon substrate.Fig. 20 is a block diagram illustrating an exemplary schematic configuration of a vehicle control system.Fig. 21 is an explanatory diagram illustrating exemplary installation positions of an outside-vehicle information detecting unit and an imaging section.

[0028] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. Although main components of the semiconductor device will be mainly described below, the semiconductor device may have components and functions that are not illustrated or described. The following description does not exclude components and functions that are not illustrated or described.

[0029] Fig. 1 is a block diagram illustrating a schematic configuration of a semiconductor device 1 according to the present disclosure. The semiconductor device 1 illustrated in Fig. 1 illustrates a schematic configuration of an image sensor. Note that the semiconductor device 1 according to the present disclosure is not necessarily limited to an image sensor that obtains gradation information photoelectrically converted in each pixel and generates a captured image, and is applicable to an event-based vision sensor (EVS) or the like that detects event information in each pixel and generates an event image. In at least one example, the semiconductor device 1 is a light detecting device. Although an exemplary case where the semiconductor device 1 according to the present disclosure is applied to a photodetection device such as an image sensor, an EVS, or other light detecting device will be mainly described in the present specification, the semiconductor device 1 according to the present disclosure is also applicable to various electronic devices other than the photodetection device.

[0030] As illustrated in Fig. 1, the semiconductor device 1 of Fig. 1 includes a pixel array section 2a and a peripheral circuit section 2b. The peripheral circuit section 2b includes, for example, a vertical drive unit 3, a column processing unit 4, a horizontal drive unit 5, a system control unit 6, a signal processing unit 7, a data storage unit 8, and the like, and may be roughly divided into a control circuit and a logic circuit, as will be described later. The signal processing unit 7 and the data storage unit 8 may be mounted on the same substrate as the pixel array section 2a, the vertical drive unit 3, and the like, or may be disposed on another substrate. Note that each processing of the signal processing unit 7 and the data storage unit 8 may be performed by an external signal processing unit, such as a digital signal processor (DSP) circuit or the like, provided in a semiconductor chip 50 different from the semiconductor device 1.

[0031] The pixel array section 2a has a configuration in which unit pixels px each having a photoelectric conversion unit that generates and accumulates charges corresponding to an amount of received light are two-dimensionally disposed in a matrix of a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Here, the row direction refers to a pixel row of the pixel array section 2a, that is, an array direction in the row direction, and the column direction refers to a pixel column of the pixel array section 2a, that is, an array direction in the column direction. A specific circuit configuration of the unit pixels px will be described later. Hereinafter, the unit pixels px may be abbreviated as pixels px.

[0032] In the pixel array section 2a, a pixel drive wiring L as a row signal line is wired along the row direction row each pixel row, and a vertical signal line VSL as a column signal line is wired along the column direction for each pixel column. The pixel drive wiring L transmits a drive signal for driving at a time of reading a signal from the pixel px. Although each pixel drive wiring L is illustrated as one line in Fig. 1, it is not limited to one. One end of the pixel drive wiring L is connected to an output terminal corresponding to each row of the vertical drive unit 3.

[0033] The vertical drive unit 3 includes a shift register, an address decoder, and the like, and drives the individual pixels px of the pixel array section 2a simultaneously, in units of rows, or the like. The vertical drive unit 3 constitutes a drive unit that controls the operation of each pixel px of the pixel array section 2a together with the system control unit 6. Although illustration of a specific configuration of the vertical drive unit 3 is omitted, it commonly includes two scanning systems of a reading scanning system and a sweeping scanning system.

[0034] The reading scanning system sequentially selects and scans the pixels px of the pixel array section 2a row by row to read signals from the pixels px. The signals read from the pixels px are analog signals. The sweeping scanning system performs sweep scanning on a read row to be subject to the read scanning by the reading scanning system earlier than the read scanning by an exposure time.

[0035] By the sweep scanning by the sweeping scanning system, unnecessary charges are swept out from the photoelectric conversion units of the pixels px in the read row, whereby the photoelectric conversion units of the individual pixels px are reset. Then, when the sweeping scanning system sweeps (resets) unnecessary charges, what is called an electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discharging the charges of the photoelectric conversion unit and newly starting exposure (starting accumulation of charges).

[0036] The signals read by the read operation by the reading scanning system corresponds to the amount of light received after the immediately preceding read operation or electronic shutter operation. Then, a period from the read timing by the immediately preceding read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is an exposure period in the pixel px.

[0037] The signal output from each of the pixels px in the pixel row selectively scanned by the vertical drive unit 3 is input to the column processing unit 4 through each of the vertical signal lines VSL for each pixel column. The column processing unit 4 performs predetermined signal processing on the signal output from each of the pixels px in the selected row through the vertical signal line VSL for each unit pixel column of the pixel array section 2a, and temporarily holds the pixel signal after the signal processing.

[0038] Specifically, the column processing unit 4 performs, as signal processing, at least noise removal processing, for example, correlated double sampling (CDS) processing or double data sampling (DDS) processing. For example, in the CDS processing, pixel-specific fixed pattern noise, such as reset noise, threshold variation of an amplification transistor in the unit pixel, and the like, is removed. The column processing unit 4 has, for example, a function of analog-digital (AD) conversion in addition to the noise removal processing, and converts an analog pixel signal into a digital signal to output it.

[0039] The horizontal drive unit 5 includes a shift register, an address decoder, and the like, and sequentially selects a unit circuit corresponding to the pixel column in the column processing unit 4. When the horizontal drive unit 5 performs the selective scanning, the pixel signals subjected to the signal processing for each unit circuit in the column processing unit 4 are sequentially output.

[0040] The system control unit 6 includes a timing generator that generates various timing signals and the like, and performs drive control of the vertical drive unit 3, the column processing unit 4, the horizontal drive unit 5, and the like on the basis of various timings generated by the timing generator.

[0041] The signal processing unit 7 has at least an arithmetic processing function, and performs various types of signal processing, such as arithmetic processing, on the pixel signals output from the column processing unit 4. The data storage unit 8 temporarily stores data necessary for signal processing in the signal processing unit 7. The pixel signals subjected to the signal processing in the signal processing unit 7 are converted into a predetermined format, and are output from an output unit 9 to the outside of the semiconductor device 1.

[0042] Figs. 2A and 2B are diagrams illustrating a cross-sectional configuration (Fig. 2A) and a planar configuration (Fig. 2B) of the semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 according to an embodiment is, for example, a back-illuminated (back-surface light receiving) complementary metal oxide semiconductor (CMOS) image sensor. More specifically, the semiconductor device 1 according to an embodiment is a laminated image sensor in which the semiconductor chip 50 including various signal processing circuits for performing signal processing is flip-chip mounted on a sensor element 10 (first semiconductor element) mounted on a silicon substrate (first substrate) 11. Hereinafter, the semiconductor chip 50 may be referred to as a logic chip or a second substrate. Note that Fig. 2A illustrates a cross-sectional configuration taken along line A-A illustrated in Fig. 2B.

[0043] (Sensor Element) The sensor element 10 includes a light receiving region 100A in which a plurality of photoelectric conversion units 12 is two-dimensionally arranged on the silicon substrate 11 (first substrate), and a peripheral region 100B provided around the light receiving region 100A. The pixel array section 2a in Fig. 1 is disposed in the light receiving region 100A. At least a part of the peripheral circuit section 2b in Fig. 1 is disposed in the peripheral region 100B. Each of the plurality of pixels px arrayed in the pixel array section 2a includes the photoelectric conversion unit 12.

[0044] In the sensor element 10, the back surface (surface SF1) of the silicon substrate 11 serves as a light incident surface, and a multilayer wiring layer 20 is provided on the front surface (surface SF2, another surface) of the silicon substrate 11. The semiconductor chip 50 is joined to the silicon substrate 11 by flip-chip mounting via a pad 34 (first pad or conductor) provided on the back surface (surface SF1) side of the silicon substrate 11 in the peripheral region 100B of the sensor element 10.

[0045] The semiconductor device 1 according to the present embodiment has a configuration in which a pad 36 (second pad) to be used for connection with an external substrate (not illustrated) is further provided on the back surface (surface SF1) side of the silicon substrate 11 in the peripheral region 100B of the sensor element 10. The pad 34 and the pad 36 are electrically connected by, for example, a wiring layer 33 provided on the surface SF1 of the silicon substrate 11, a through via 13 penetrating the silicon substrate 11, and the multilayer wiring layer 20 provided on the front surface (surface SF2) side of the silicon substrate 11.

[0046] (Light Receiving Region) In the light receiving region 100A, the photoelectric conversion unit 12, which selectively detects light in wavelength regions different from each other to perform photoelectric conversion, is provided for each pixel px. The photoelectric conversion unit 12, which is an n-type semiconductor region provided in the thickness direction (Z-axis direction in Fig. 2) of the silicon substrate 11, for example, includes a photodiode (PD) for pn junction with a p-type semiconductor region provided on the surface SF2 of the silicon substrate 11, and is provided in a manner of being embedded in the silicon substrate 11 for each pixel px, for example.

[0047] The silicon substrate 11 is further provided with, in the vicinity of the surface SF2, a charge accumulation unit that accumulates signal charges generated in the photoelectric conversion unit 12, and a transfer transistor (TG) that transfers signal charges to the charge accumulation unit. In the vicinity of the surface SF2 of the silicon substrate 11, for example, a reset transistor (RST), an amplification transistor (Amp), a selection transistor (SEL), and the like are provided together with the transfer transistor (TG). Such a transistor is, for example, a metal oxide semiconductor field effect transistor (MOSEFT), and constitutes a pixel circuit provided for each pixel px. Each pixel circuit may have a three-transistor configuration including, for example, a transfer transistor (TG), a reset transistor (RST), and an amplification transistor (Amp), or may have a four-transistor configuration including a selection transistor (SEL) in addition to the transistors mentioned above. Transistors other than the transfer transistor (TG) may be shared between pixels.

[0048] In the light receiving region 100A, for example, an interlayer insulating layer 31, an inner lens 37L, a planarization layer 38, a protective layer 40, a color filter 41, and an on-chip lens 42L are provided in this order on the side of the light receiving surface (surface SF1) of the silicon substrate 11. Each of the inner lens 37L, the color filter 41, and the on-chip lens 42L is disposed to face the photoelectric conversion unit 12 of each pixel px, for example.

[0049] Each of the interlayer insulating layer 31, the inner lens 37L, the planarization layer 38, the protective layer 40, the color filter 41, and the on-chip lens 42L includes, for example, a material having transparency. Specifically, for example, it includes any of silicon nitride (SiN), silicon oxynitride (SiON), and the like, or a laminated film thereof.

[0050] Furthermore, pixel separation portions 35 and 39 are stacked between the individual pixels px. The pixel separation portion 35 and the pixel separation portion 39 are provided in a part of the interlayer insulating layer 31 and in a part of the planarization layer 38, respectively. The pixel separation portions 35 and 39 include, for example, a lightproof material such as tungsten (W).

[0051] (Peripheral Region) In the peripheral region 100B, for example, the interlayer insulating layer 31, a laminated insulating layer 17, the planarization layer 38, the protective layer 40, and an on-chip lens layer 42 are laminated in this order on the side of the surface SF1 of the silicon substrate 11, for example. The laminated insulating layer 17 and the on-chip lens layer 42 extend from the inner lens 37L and the on-chip lens 42L provided in the light receiving region 100A, respectively.

[0052] In the peripheral region 100B, for example, four pads 34 (two of them are illustrated in Fig. 2A) for mounting the semiconductor chip 50 on the sensor element 10 and, for example, a plurality of pads 36 to be used for connection with an external substrate are provided. For example, the wiring layer 33 that electrically connects the pad 34 and the pad 36 is provided in the interlayer insulating layer 31. Moreover, in the interlayer insulating layer 31, for example, a light-shielding film 32 including a lightproof conductive material, such as tungsten (W), is provided between the light receiving region 100A and the peripheral region 100B, for example.

[0053] The silicon substrate 11 is provided with, for example, the through via 13 penetrating between the surface SF1 and the surface SF2. The through via 13 is provided for each of the pads 34 and 36, for example.

[0054] (Multilayer Wiring Layer) A plurality of insulating layers 21 is laminated on the surface SF2 of the silicon substrate 11, and wiring layers 22 are disposed on at least some of the insulating layers 21. The wiring layers 22 are laminated, and the individual wiring layers 22 are coupled by, for example, a via or a contact.

[0055] One end of the through via 13 penetrating the silicon substrate 11 is connected to the wiring layer 33, which is connected to the pad 34 or the pad 36 provided on the side of the surface SF1 of the silicon substrate 11, and the other end is connected to the wiring layer 22 provided on the side of the surface SF2 of the silicon substrate 11. The pad 34 and the pad 36 are electrically connected via each wiring layer 33 including the through via 13 described above. The wiring layer 33 is disposed in the interlayer insulating layer 31. The wiring layer 33 may be laminated on the interlayer insulating layer 31. The wiring layer 33 includes a plurality of vertical signal lines VSL. Those vertical signal lines VSL are electrically connected to a plurality of vertical signal lines VSL extending in a column direction in a pixel array section 2.

[0056] (Pad) The pad 34 is what is called a land electrode for flip-chip mounting the semiconductor chip 50 on the sensor element 10, and is provided in an opening H1 provided to expose a part of the wiring layer 33 provided in the interlayer insulating layer 31, for example. For example, the pad 34 has a laminated structure of a plurality of metal layers. For example, the pad 34 has a laminated structure in which metal films 34a, 34b, and 34c are laminated in this order from the side of the silicon substrate 11. For example, a conductive material such as tantalum (Ta), tantalum nitride (TaN), copper (Cu), or the like may be used as a material of the pad 34. Among those materials, tantalum (Ta) is preferably used for the metal film 34a in direct contact with the wiring layer 33, for example, tantalum nitride (TaN) is preferably used for the metal film 34b provided between the metal film 34a and the metal film 34c, for example, and copper (Cu) is preferably used for the metal film 34c coupled to the semiconductor chip 50 via the bump 52, for example. The opening H1 for exposing the pad 34 is provided in the laminated insulating layer 17, the planarization layer 38, the protective layer 40, and the on-chip lens layer 42 on the pad 34.

[0057] A bonding wire (not illustrated) is connected to the pad 36. The pad 36 is used for connection with an external substrate via the bonding wire, and is provided on the interlayer insulating layer 31, for example. The pad 36 includes, for example, a material such as a single-layer film of aluminum (Al), a laminated film with a barrier metal, or the like. An opening H2 for exposing the pad 36 is provided in the laminated insulating layer 17, the planarization layer 38, the protective layer 40, and the on-chip lens layer 42 on the pad 36.

[0058] Moreover, the pad 36 is preferably provided at a height of the same level as that of the pad 34. Here, the same level does not necessarily indicate the same height. For example, a difference in height between the lower surfaces of the pad 34 and the pad 36 is assumed to be equal to or smaller than the thickness of the insulating layer provided with one of the pad 34 and the pad 36. With this arrangement, processing of the pad 34 and the pad 36 is facilitated.

[0059] A shield member or conductor 14 and a dummy wiring layer 15 are disposed at the same height (layer) as the pad 36. Since the pad 36, the shield member 14, and the dummy wiring layer 15 include the same conductive material (e.g., aluminum (Al)), they may be formed in the same manufacturing process. The shield member 14 is set to a predetermined reference voltage (e.g., power supply voltage). On the other hand, the voltage level of the dummy wiring layer 15 is unstable (floating). Note that the shield member 14 may be disposed at a height different from that of the pad 34.

[0060] The shield member 14 is disposed to cover at least a part of the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL. More specifically, the shield member 14 is disposed to face the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL via the insulating layer 17. The shield member 14 is provided mainly for the purpose of suppressing transmission of noise generated in the semiconductor chip 50 to the vertical signal line VSL. In the present specification, the shield member 14 may be referred to as a conductive member. A shape and an arrangement position of the shield member 14 will be described later.

[0061] The dummy wiring layer 15 is provided for the purpose of, for example, adjusting a mask aperture ratio at a time of dry etching to improve processing stability. Furthermore, since there is a possibility that a step is formed when the number of structure bodies is too small in the planarization process, the dummy wiring layer 15 is provided so that the flatness may be improved at the time of film formation.

[0062] The semiconductor chip 50 flip-chip mounted on the silicon substrate (first substrate) 11 of the sensor element 10 is a logic chip on which various signal processing circuits for performing signal processing are formed. A pad 51 including aluminum (Al) or the like is disposed on a surface of the semiconductor chip 50 facing the sensor element 10. The pad 51 of the semiconductor chip 50 is joined to the pad 34 of the sensor element 10 via the solder bump 52. In this manner, the semiconductor chip 50 is flip-chip mounted on the side of the light irradiation surface (back surface) of the sensor element 10.

[0063] Fig. 3 is a planar layout diagram of the shield member 14, and Fig. 4 is a cross-sectional view taken along line A-A in Fig. 3. Fig. 3 illustrates a planar layout of a part of the silicon substrate 11. On the silicon substrate 11, a plurality of the pads 34 for joining the semiconductor chip 50 to be flip-chip mounted on the sensor element 10 is arranged in the first direction (e.g., row direction) X and in the second direction (e.g., column direction) Y. A plurality of the vertical signal lines VSL (first signal wiring) each extending in the second direction Y is disposed between two pads 34 adjacent to each other in the first direction X. The plurality of vertical signal lines VSL is coupled to the individual pads 34 via lead-out wiring (second signal wiring) 18.

[0064] Fig. 3 illustrates an exemplary case where the shield member 14 covers the entire region except for a plurality of rectangular regions surrounding each of the plurality of pads 34 on the silicon substrate (first substrate) 11. As illustrated in Figs.3 and 4, the shield member 14 is disposed to cover a region other than the regions where the plurality of pads 34 is arranged. Note that the present disclosure is not limited to such an arrangement of the shield member 14, and it is sufficient if the shield member 14 covers at least a part of the first signal wiring. Here, to “cover at least a part” indicates that the shield member 14 is superimposed on at least a part of the first signal wiring in plan view.

[0065] Fig. 5 is a diagram illustrating a planar shape of the shield member 14. As illustrated in Fig. 5, the shield member 14 is disposed in, for example, a lattice shape to surround the pads 34. Fig. 5 is merely an example of the planar shape of the shield member 14. Various modifications are conceivable for the planar shape of the shield member 14.

[0066] Figs. 6A to 6C are diagrams illustrating representative modifications of the planar shape of the shield member 14. Fig. 6A illustrates an exemplary case where the opening for the pad 34 is diamond-shaped, Fig. 6B illustrates an exemplary case where the opening H1 for the pad 34 is octagonal-shaped, and Fig. 6C illustrates an exemplary case where the opening for the pad 34 is circular-shaped. In any of Figs. 6A to 6C, portions other than the opening in the sensor element 10 are covered with the shield member 14.

[0067] As illustrated in Fig. 3, at least a part of the lead-out wiring 18 extending from the vertical signal line VSL to the pad 34 is preferably covered with the shield member 14. The planar shape of the shield member 14 is preferably octagonal-shaped as illustrated in Fig. 6B, which matches the outer shape of the pad 34, to cover the lead-out wiring 18 with the shield member 14. Note that Fig. 5 to Fig. 6C illustrate representative planar shapes of the shield member 14, and a planar shape other than the illustrated shapes may be adopted.

[0068] Fig. 7 is a diagram illustrating a planar shape of the dummy wiring layer 15. Fig. 7 illustrates an exemplary case where the planar shape of the dummy wiring layer 15 is rectangular. An interval between the two dummy wiring layers 15 adjacent to each other in the first direction (e.g., row direction) X and the second direction (e.g., column direction) Y is optional, and may not necessarily be constant.

[0069] Various modifications are conceivable for the planar shape of the dummy wiring layer 15. Figs. 8A to 8D are diagrams illustrating representative examples of the planar shape of the dummy wiring layer 15. Fig. 8A illustrates an example in which the planar shape of the dummy wiring layer 15 is circular or elliptical. Fig. 8B illustrates an example in which the planar shape of the dummy wiring layer 15 is polygonal. Fig. 8C illustrates an example in which the planar shape of the dummy wiring layer 15 has a plurality of irregularities. Fig. 8D illustrates an example in which the planar shape of the dummy wiring layer 15 is rectangular. Figs. 8A to 8D illustrate representative examples of the planar shape of the dummy wiring, and a planar shape other than the illustrated shapes may be adopted.

[0070] (Imaging Device Manufacturing Process) Fig. 9 is a flowchart of a process of manufacturing an imaging device according to the present embodiment. Figs. 10A to 10G are cross-sectional views of individual steps of manufacturing the imaging device according to the present embodiment. Hereinafter, the process of manufacturing the imaging device according to the present embodiment will be described in sequence with reference to those drawings.

[0071] First, a manufacturing step of the front end of line (FEOL) is performed (step S1). In the FEOL, the photoelectric conversion unit 12 is formed on the silicon substrate 11, and then individual gates (not illustrated) of various transistors such as the transfer transistor (TG) and the charge accumulation unit are formed on the surface (surface SF2) of the silicon substrate 11.

[0072] Subsequently, a manufacturing step of the back end of line (BEOL) is performed (step S2). In the BEOL, as illustrated in Fig. 10A, the multilayer wiring layer 20 in which the plurality of wiring layers 22 is laminated on at least a part of the plurality of laminated insulating layers 21 is formed on the surface SF2 of the silicon substrate 11. The wiring layers 22 having different layers are joined by a via or a contact. Next, a support substrate (not illustrated) is joined to the surface SF2 of the silicon substrate 11, and is vertically flipped (step S3). Fig. 10A illustrates a cross-sectional view after the vertical flip. The support substrate (not illustrated) is disposed below the multilayer wiring layer 20 in Fig. 10A.

[0073] Next, as illustrated in Fig. 10B, the interlayer insulating layer 31 and the light-shielding film 32 are formed on the silicon substrate 11 (step S4). The interlayer insulating layer 31 includes an insulating layer 31a including, for example, silicon oxide (SiO2), and the light-shielding film 32 including, for example, tungsten (W). The light-shielding film 32 forms an optical black region around the pixel array section 2. Subsequently, the insulating layer 31a and the silicon substrate 11 are processed by, for example, dry etching to form, for example, annular openings H1a and H2a at predetermined positions of the interlayer insulating layer 31. Next, for example, a film of Ta as a barrier metal is formed on the side surfaces of the openings H1a and H2a, and then the openings H1a and H2a are plated with Cu, for example, to form the through via 13 (step S5).

[0074] Next, the wiring layer 33 and the pad 34 are formed (step S6). In step S6, as illustrated in Fig. 10C, a SiO2film is formed on the through via 13 and the insulating layer 31a, for example, and then a groove is formed at a predetermined position (specifically, position at which the wiring layer 33 is to be formed), which is plated with copper (Cu). Subsequently, Cu formed outside the groove is removed by, for example, CMP to form the wiring layer 33. Next, for example, a SiO2film is formed on the insulating layer 31a and the wiring layer 33, and then an opening is formed at a predetermined position by, for example, etching to expose the wiring layer 33. The pad 34 including, for example, Ta (metal film 34a) / TaN (metal film 34b) / Cu (metal film 34c) is formed in the opening by, for example, plating, and then the surface is planarized by, for example, CMP to remove the metal films 34a, 34b, and 34c described above formed other than the pad 34.

[0075] Subsequently, as illustrated in Fig. 10C, a via 16 extending upward from the wiring layer 33 is formed (step S7). Next, as illustrated in Fig. 10D, a laminated film, which is a material of the shield member 14, the pad 36, and the dummy wiring layer 15, is formed (step S8).

[0076] In steps S7 and S8, as illustrated in Figs. 10C and 10D, a laminated film of, for example, SiCN / SiO2is formed as a part of the interlayer insulating layer 31, and then the laminated film of SiCN / SiO2is patterned by, for example, dry etching. Next, after a SiO2film is formed as a part of the interlayer insulating layer 31, an opening is formed over the wiring layer 33 by photolithography or the like, for example, and tungsten (W) or aluminum (Al) is embedded in the opening, for example, to form the via 16. Furthermore, the pixel separation portion 35 is also formed. Next, a TaN / Ta (barrier metal) film and an Al film are formed on the interlayer insulating layer 31, for example, and then patterning is performed by photolithography or the like to form the shield member 14, the pad 36, and the dummy wiring layer 15 at predetermined positions on the interlayer insulating layer 31 including the via 16.

[0077] Subsequently, the inner lens 37L is formed (step S9). In step S9, as illustrated in Fig. 10E, the laminated insulating layer 17 of SiON / SiN, for example, is formed on the interlayer insulating layer 31, the pads 34 and 36, the shield member 14, and the dummy wiring layer 15, and then a resist is formed on the laminated insulating layer 17 in the region corresponding to the light receiving region 100A using photolithography and reflow. Next, the lens shape is transferred to the laminated insulating layer 17 by etch-back, thereby forming the laminated insulating layer (also referred to as inner lens layer) 17 in which the inner lens 37L is provided in the light receiving region 100A. Subsequently, for example, a SiO2film is formed on the laminated insulating layer 17. Next, the pixel separation portion 39 is formed between the individual pixels px in the light receiving region 100A using a method similar to that of the pixel separation portion 35 described above, and then the surface of the SiO2film is planarized using, for example, a chemical mechanical polishing (CMP) method to form the planarization layer 38.

[0078] Subsequently, the color filter 41 and the on-chip lens 42L are formed (step S10). In step S10, as illustrated in Fig. 10F, resin is applied onto the planarization layer 38 by a coater or the like to form the protective layer 40, for example, and then the color filter 41 having a predetermined color is formed at a position corresponding to each pixel px in the light receiving region 100A. Next, a lens material is applied onto the protective layer 40 and the color filter 41, and then a resist is formed on the lens material in the region corresponding to the light receiving region 100A using photolithography and reflow. Next, the lens shape is transferred to the lens material by etch-back, thereby forming the on-chip lens layer 42 in which the on-chip lens 42L is provided in the light receiving region 100A.

[0079] Subsequently, the openings H1 and H2 for the pads 34 and 36 are formed (step S11). In step S11, as illustrated in Fig. 10G, the on-chip lens layer 42, the protective layer 40, the planarization layer 38, and the laminated insulating layer 17 are processed by, for example, dry etching to form, for example, the rectangular opening H2 for exposing the pad 36 at the position corresponding to the pad 36, for example.

[0080] Next, the on-chip lens layer 42, the protective layer 40, the planarization layer 38, and the laminated insulating layer 17 are processed by, for example, dry etching to form, for example, the circular opening H1 for exposing the pad 34 at the position corresponding to the pad 34, for example, whereby the sensor element 10 is complete.

[0081] Next, the semiconductor chip 50 is joined by chip on wafer (CoW) (step S12). In step S12, the semiconductor chip 50 is mounted on the pad 34 via the bump 52. As described above, the semiconductor device 1 illustrated in Fig. 2 is complete.

[0082] (Film Thickness of SiON / SiN Laminated Insulating Layer) As illustrated in Fig. 10E, the laminated insulating layer 17 of SiON / SiN is formed on the pads 34 and 36, the shield member 14, the dummy wiring layer 15, and the pixel array section 2. Fig. 11 is a cross-sectional view illustrating a film thickness difference of the laminated insulating layer 17 of SiON / SiN according to the present embodiment, and Fig. 12 is a cross-sectional view illustrating a film thickness difference of a laminated insulating layer 17 according to a comparative example. A comparative example is directed to a semiconductor device 1 having no shield member 14. Although the laminated insulating layer 17 is illustrated as one layer for the sake of simplicity in Figs. 11 and 12, it practically has a three-layer structure of SiON / SiN / SiON, for example.

[0083] As illustrated in Fig. 11, in the present embodiment, the thickness of the laminated insulating layer 17 above the pad 36, the shield member 14, and the dummy wiring layer 15, the thickness of the laminated insulating layer 17 above the pad 34, and the thickness of the laminated insulating layer 17 above the pixel array section 2 are different from each other, whereby the step of the laminated insulating layer 17 is made smaller. On the other hand, in a comparative example, the shield member 14 is not provided, and the thickness of the laminated insulating layer 17 above the pad 36 and the dummy wiring layer 15, the thickness of the laminated insulating layer 17 above the pad 34, and the thickness of the laminated insulating layer 17 above the pixel array section 2 are the same. Thus, in a comparative example, the step of the laminated insulating layer 17 is larger between the pixel array section 2 and the region other than the pixel array section 2.

[0084] In the semiconductor device 1 according to the present embodiment, the planarization step is performed after the laminated insulating layer 17 is formed as illustrated in Fig.10E, whereby the planarization step is performed easier as the step is smaller as illustrated in Fig. 11, which may improve the flatness. In the case of a comparative example, an additional step for thinning the laminated insulating layer 17 in the region other than the pixel array section 2 is necessary to proceed with the planarization step, and accordingly, the planarization step takes time and effort, and the flatness is deteriorated.

[0085] Furthermore, in the present embodiment, the laminated insulating layer 17 is thickly formed on the pixel array section 2 so that hydrogen may be supplied to the pixel array section 2 via the SiN film in the laminated insulating layer 17, which may further suppress dark current. Furthermore, with the thickened laminated insulating layer 17, moisture resistance of the pixel array section 2 may be further improved.

[0086] Fig. 13 is a cross-sectional view illustrating details of the film thickness of the laminated insulating layer 17 of SiON 17a / SiN 17b / SiON 17c covering the pad 34 and the shield member 14. As illustrated in Fig. 13, the film thickness of the laminated insulating layer 17 varies depending on the location. More specifically, the film thickness of the laminated insulating layer 17 above the pad 34 is larger than the film thickness of the laminated insulating layer 17 above the shield member 14, and is smaller than the film thickness of the laminated insulating layer 17 between the pad 34 and the shield member 14. In this manner, by making the film thickness of the laminated insulating layer 17 above the pad 34 larger than the film thickness of the laminated insulating layer 17 above the shield member 14, the flatness may be improved.

[0087] Figs. 14A to 14D are cross-sectional views illustrating a state in which the film thickness of the laminated insulating layer 17 changes depending on an interval of structure bodies 19 such as the shield member 14, the dummy wiring layer 15, the pads 34 and 36, and the like. Fig. 14A illustrates a case where no other structure body 19 exists around the structure body 19, more specifically, a case where a distance to an adjacent structure body 19 is more than 10 μm. Fig. 14B illustrates a case where an interval between two adjacent structure bodies 19 is large, more specifically, a case where a distance to an adjacent structure body 19 is equal to or more than 3 μm and less than 10 μm. Fig. 14C illustrates a case where an interval between two adjacent structure bodies 19 is slightly small, more specifically, a case where a distance to an adjacent structure body 19 is approximately 3 μm. Fig. 14D illustrates a case where an interval between two adjacent structure bodies 19 is small, more specifically, a case where a distance to an adjacent structure body 19 is less than 2 μm.

[0088] In the case of Fig. 14A, the film thickness of the laminated insulating layer 17 is substantially the same between the upper surface of the structure body 19 and the region where no structure body 19 exists. In Fig. 14A, the film thickness of the laminated insulating layer 17 in the region where no structure body 19 exists is denoted by A, and the film thickness of the laminated insulating layer 17 in the upper surface of the structure body 19 is denoted by B.

[0089] In the case of Fig. 14B, a film thickness C of the laminated insulating layer 17 between two adjacent structure bodies 19 is substantially equal to a film thickness D of the laminated insulating layer 17 in the upper surface of the structure body 19. The film thickness C and the film thickness D are the same as the film thickness A, or are slightly smaller than the film thickness A.

[0090] In the case of Fig. 14C, a film thickness E of the laminated insulating layer 17 between the two adjacent structure bodies 19 is smaller than a film thickness F of the laminated insulating layer 17 in the upper surface of the structure body 19. The film thickness F is smaller than the film thickness C and D.

[0091] In the case of Fig. 14D, a film thickness G of the laminated insulating layer 17 between the two adjacent structure bodies 19 is larger than a film thickness H of the laminated insulating layer 17 in the upper surface of the structure body 19. The film thickness H is the same level as the film thickness F. In addition, the film thickness G is larger than the film thickness A.

[0092] (Arrangement of Shield Member 14 on Semiconductor Chip 50) While Fig. 2 illustrates an exemplary case where the shield member 14 is disposed in the peripheral circuit section 2b of the silicon substrate (first substrate) 11 including the pixel array section 2, the shield member 14 may be disposed on the semiconductor chip 50.

[0093] Figs. 15A and 15B are cross-sectional views illustrating an example in which the shield member 14 is disposed on the semiconductor chip 50. There is a plurality of candidates for the place of the semiconductor chip 50 where the shield member 14 is to be disposed. Fig. 15A is a cross-sectional view illustrating a first example of the place where the shield member 14 is disposed, and Fig. 15B is a cross-sectional view illustrating a second example of the place where the shield member 14 is disposed. Although illustration is omitted in Figs. 15A and 15B, a predetermined reference voltage (e.g., power supply voltage) is applied to the shield member 14 provided on the semiconductor chip 50 by a wiring layer, a via, a contact, or the like (not illustrated). At least a part of the shield member 14 is disposed to overlap with at least one wiring layer 53 in the semiconductor chip 50 in plan view.

[0094] The shield member 14 in Fig. 15A is disposed along the lowermost surface of the semiconductor chip 50. The pad 51 is disposed on the same layer as the shield member 14, and the shield member 14 is formed using the same material (e.g., aluminum (Al)) in the same manufacturing step as the pad 51. The pad 51 is joined to the pad 34 of the silicon substrate (first substrate) 11 by the bump 52. A plurality of the wiring layers 53 is disposed above the shield member 14. With the shield member 14 provided, noise from the wiring layer 53 is not transmitted to the side of the silicon substrate (first substrate) 11.

[0095] The shield member 14 in Fig. 15B is disposed above the pad 51, that is, inside the semiconductor chip 50. The shield member 14 is disposed at the same height as the wiring layer 53, and includes the same material as the material (e.g., copper (Cu)) of the wiring layer 53. The wiring layer 53, the pad 51, or the like is disposed above the shield member 14, and the shield member 14 may suppress transmission of noise from the wiring layer 53 to the silicon substrate (first substrate) 11.

[0096] Fig. 16 is a diagram for explaining the thickness and the lateral width of the pad 34, the shield member 14, and the like. While the thicknesses of the shield member 14, the dummy wiring layer 15, and the pad 36 is approximately 500 to 750 nm, the thicknesses of the wiring layer 33, the vertical signal line VSL, and the pad 34 for bump connection is approximately 100 to 250 nm. As described above, the thickness of the shield member 14 is larger than the thickness of the vertical signal line VSL and the wiring layer 33.

[0097] The shield member 14 is disposed to cover at least some of the vertical signal lines VSL. Specifically, the lateral width of the shield member 14 is preferably equal to or larger than the lateral width of the plurality of vertical signal lines VSL.

[0098] Fig. 17 is a cross-sectional view illustrating an exemplary layer configuration of the structure body 19 such as the shield member 14, the dummy wiring layer 15, or the like. The structure body 19 in Fig. 17 has a three-layer structure, and the lowermost layer is a laminated body 19a of TaN / Ta / TaN / Ta. An AlCu layer 19b is laminated on the laminated body 19a, and a Ta layer 19c is disposed on the AlCu layer 19b. A thickness of the lowermost laminated body 19a is, for example, approximately 3,000 nm, a thickness of the AlCu layer 19b is, for example, approximately 750 nm, and a thickness of the uppermost Ta layer is, for example, approximately 25 nm.

[0099] Fig. 18 is a cross-sectional view illustrating an exemplary layer configuration of the pads 34 and 36. While the layer configuration of the pads 34 and 36 is the same as the layer configuration of the structure body 19 in Fig.17, a part of the uppermost Ta layer 19c is removed to expose the AlCu layer 19b.

[0100] As described above, the semiconductor device 1 according to the present embodiment has a CoW structure in which the semiconductor chip 50 is joined onto, via the bump, the silicon substrate (first substrate) 11 on which the pixel array section 2 is disposed, and the shield member 14 is disposed to cover at least some of the vertical signal lines VSL, whereby the noise from the semiconductor chip 50 may be blocked by the shield member 14 so that the voltage level of the vertical signal lines VSL is not varied due to the noise from the logic circuit of the semiconductor chip 50, which may improve the electrical characteristics of the semiconductor device 1.

[0101] Furthermore, since the upper surface of the shield member 14 and the pixel array section 2 is covered with the laminated insulating layer 17 containing SiN, moisture resistance may be improved. Furthermore, since the film thickness of the laminated insulating layer 17 is changed depending on the location and the SiN layer in the pixel array section 2 is made thicker, the moisture resistance may be improved while dark current is suppressed. Moreover, since the laminated insulating layer 17 in the pads 34 and 36 is made thicker than the laminated insulating layer 17 in the shield member 14 and the dummy wiring layer 15, the flatness may be improved, and the planarization process may be simplified.

[0102] While Fig. 2 illustrates an exemplary case where the semiconductor chip (logic chip) 50 is flip-chip mounted on the silicon substrate 11 on which the sensor element 10 is mounted, another silicon substrate 54 on which a logic circuit or the like is mounted may be joined to the silicon substrate 11 separately from the semiconductor chip 50.

[0103] Fig. 19 is a cross-sectional view of a semiconductor device 1a in which the silicon substrate 54 is joined to the silicon substrate 11. A logic circuit including at least a part of a peripheral circuit section of the image sensor and the like is mainly mounted on the silicon substrate 54.

[0104] The silicon substrate 54 is joined to the side of the outermost surface SF3 of the wiring layer 20 of the silicon substrate 11. The silicon substrate 54 and the silicon substrate 11 are joined by, for example, copper-to-copper connection (CCC). Alternatively, those two substrates 11 and 54 may be joined by a via, a bump, or the like. A laminated wiring layer 23 and an insulating layer 24 are laminated on the silicon substrate 54, and a Cu wiring layer 25 provided on the insulating layer 21 of the silicon substrate 11 and a Cu wiring layer 26 provided on the insulating layer 24 of the silicon substrate 54 are directly joined.

[0105] As described above, according to the present embodiment, in a case where the semiconductor chip 50 is flip-chip mounted on the silicon substrate 11 on which the sensor element 10 is mounted by CoW, the shield member 14 is provided on at least one of the silicon substrate 11 or the semiconductor chip 50 so that the noise from the wiring layer 53 of the semiconductor chip 50 is not transmitted to the wiring layer 33 (vertical signal line VSL in particular) on the silicon substrate 11. With this arrangement, the noise from the wiring layer 53 of the semiconductor chip 50 is not superimposed on the vertical signal line VSL, whereby the electrical characteristics of the semiconductor device 1, such as image quality of a captured image, may be improved.

[0106] Since the shield member 14 is disposed on the same layer as the dummy wiring layer 15 and the pad 36 for bonding wire connection, it may be formed by an existing manufacturing process.

[0107] The thickness of the shield member 14 is made larger than the thickness of the pad 34 for flip-chip mounting the semiconductor chip 50, and the thickness of the pad 34 is made larger than the upper surface of the interlayer insulating layer 31 in the pixel array section 2, whereby the step of the laminated insulating layer 17 may be made smaller and the flatness of the planarization layer 38 disposed on the laminated insulating layer 17 may be improved.

[0108] <Application Example to Mobile Body> The technology according to the present disclosure (present technology) may be applied to various products. For example, the technology according to the present disclosure may be achieved in the form of a device to be mounted on a mobile body of any kind, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a vessel, a robot, or the like.

[0109] Fig. 20 is a block diagram illustrating a schematic configuration example of a vehicle control system, which is an example of a mobile body control system to which the technology according to the present disclosure may be applied.

[0110] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In the example illustrated in Fig. 20, the vehicle control system 12000 includes a driving system control unit 12010, a body system control unit 12020, an outside-vehicle information detecting unit 12030, an in-vehicle information detecting unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and a vehicle-mounted network interface (I / F) 12053 are illustrated as a functional configuration of the integrated control unit 12050.

[0111] The driving system control unit 12010 controls the operation of devices related to the driving system of the vehicle in accordance with various kinds of programs. For example, the driving system control unit 12010 functions as a control device for a driving force generating device for generating the driving force of the vehicle, such as an internal combustion engine, a driving motor, or the like, a driving force transmitting mechanism for transmitting the driving force to wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, and the like.

[0112] The body system control unit 12020 controls the operation of various kinds of devices provided to a vehicle body in accordance with various kinds of programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various kinds of lamps such as a headlamp, a backup lamp, a brake lamp, a turn signal, a fog lamp, or the like. In this case, radio waves transmitted from a mobile device as an alternative to a key or signals of various kinds of switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, the power window device, the lamps, or the like of the vehicle.

[0113] The outside-vehicle information detecting unit 12030 detects information about the outside of the vehicle including the vehicle control system 12000. For example, the outside-vehicle information detecting unit 12030 is connected with an imaging section 12031. The outside-vehicle information detecting unit 12030 makes the imaging section 12031 image an image of the outside of the vehicle, and receives the imaged image. On the basis of the received image, the outside-vehicle information detecting unit 12030 may perform processing of detecting an object such as a human, a vehicle, an obstacle, a sign, a character on a road surface, or the like, or processing of detecting a distance thereto.

[0114] The imaging section 12031 is an optical sensor that receives light, and which outputs an electric signal corresponding to a received light amount of the light. The imaging section 12031 can output the electric signal as an image, or can output the electric signal as information about a measured distance. In addition, the light received by the imaging section 12031 may be visible light, or may be invisible light such as infrared rays or the like.

[0115] The in-vehicle information detecting unit 12040 detects information about the inside of the vehicle. The in-vehicle information detecting unit 12040 is, for example, connected with a driver state detecting section 12041 that detects the state of a driver. The driver state detecting section 12041, for example, includes a camera that images the driver. On the basis of detection information input from the driver state detecting section 12041, the in-vehicle information detecting unit 12040 may calculate a degree of fatigue of the driver or a degree of concentration of the driver, or may determine whether the driver is dozing.

[0116] The microcomputer 12051 can calculate a control target value for the driving force generating device, the steering mechanism, or the braking device on the basis of the information about the inside or outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform cooperative control intended to implement functions of an advanced driver assistance system (ADAS) which functions include collision avoidance or shock mitigation for the vehicle, following driving based on a following distance, vehicle speed maintaining driving, a warning of collision of the vehicle, a warning of deviation of the vehicle from a lane, or the like.

[0117] In addition, the microcomputer 12051 can perform cooperative control intended for automated driving, which makes the vehicle to travel automatedly without depending on the operation of the driver, or the like, by controlling the driving force generating device, the steering mechanism, the braking device, or the like on the basis of the information about the outside or inside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030 or the in-vehicle information detecting unit 12040.

[0118] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 on the basis of the information about the outside of the vehicle which information is obtained by the outside-vehicle information detecting unit 12030. For example, the microcomputer 12051 can perform cooperative control intended to prevent or mitigate a glare by controlling the headlamp so as to change from a high beam to a low beam, for example, in accordance with the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detecting unit 12030.

[0119] The sound / image output section 12052 transmits an output signal of at least one of a sound and an image to an output device capable of visually or auditorily notifying information to an occupant of the vehicle or the outside of the vehicle. In the example of Fig. 20, an audio speaker 12061, a display section 12062, and an instrument panel 12063 are exemplified as the output device. The display section 12062 may, for example, include at least one of an on-board display and a head-up display.

[0120] Fig. 21 is a view illustrating exemplary installation positions of the imaging section 12031.

[0121] In Fig. 21, the imaging section 12031 includes imaging sections 12101, 12102, 12103, 12104, and 12105.

[0122] The imaging sections 12101, 12102, 12103, 12104, and 12105 are, for example, disposed at positions on a front nose, sideview mirrors, a rear bumper, and a back door of the vehicle 12100 as well as a position on an upper portion of a windshield within the interior of the vehicle. The imaging section 12101 provided to the front nose and the imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle obtain mainly an image of the front of the vehicle 12100. The imaging sections 12102 and 12103 provided to the sideview mirrors obtain mainly an image of the sides of the vehicle 12100. The imaging section 12104 provided to the rear bumper or the back door obtains mainly an image of the rear of the vehicle 12100. The imaging section 12105 provided to the upper portion of the windshield within the interior of the vehicle is used mainly to detect a preceding vehicle, a pedestrian, an obstacle, a signal, a traffic sign, a lane, or the like.

[0123] Note that Fig. 21 illustrates exemplary imaging ranges of the imaging sections 12101 to 12104. An imaging range 12111 represents the imaging range of the imaging section 12101 provided to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging sections 12102 and 12103 provided to the sideview mirrors. An imaging range 12114 represents the imaging range of the imaging section 12104 provided to the rear bumper or the back door. A bird's-eye image of the vehicle 12100 as viewed from above is obtained by superimposing image data imaged by the imaging sections 12101 to 12104, for example.

[0124] At least one of the imaging sections 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging sections 12101 to 12104 may be a stereo camera constituted of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0125] For example, the microcomputer 12051 can determine a distance to each three-dimensional object within the imaging ranges 12111 to 12114 and a temporal change in the distance (relative speed with respect to the vehicle 12100) on the basis of the distance information obtained from the imaging sections 12101 to 12104, and thereby extract, as a preceding vehicle, a nearest three-dimensional object in particular that is present on a traveling path of the vehicle 12100 and which travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or more than 0 km / hour). Further, the microcomputer 12051 can set a following distance to be maintained in front of a preceding vehicle in advance, and perform automatic brake control (including following stop control), automatic acceleration control (including following start control), or the like. It is thus possible to perform cooperative control intended for automated driving that makes the vehicle travel automatedly without depending on the operation of the driver or the like.

[0126] For example, the microcomputer 12051 can classify three-dimensional object data on three-dimensional objects into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large-sized vehicle, a pedestrian, a utility pole, and other three-dimensional objects on the basis of the distance information obtained from the imaging sections 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic avoidance of an obstacle. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can recognize visually and obstacles that are difficult for the driver of the vehicle 12100 to recognize visually. Then, the microcomputer 12051 determines a collision risk indicating a risk of collision with each obstacle. In a situation in which the collision risk is equal to or higher than a set value and there is thus a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display section 12062, and performs forced deceleration or avoidance steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist in driving to avoid collision.

[0127] At least one of the imaging sections 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 can, for example, recognize a pedestrian by determining whether or not there is a pedestrian in imaged images of the imaging sections 12101 to 12104. Such recognition of a pedestrian is, for example, performed by a procedure of extracting characteristic points in the imaged images of the imaging sections 12101 to 12104 as infrared cameras and a procedure of determining whether or not it is the pedestrian by performing pattern matching processing on a series of characteristic points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the imaged images of the imaging sections 12101 to 12104, and thus recognizes the pedestrian, the sound / image output section 12052 controls the display section 12062 so that a square contour line for emphasis is displayed so as to be superimposed on the recognized pedestrian. The sound / image output section 12052 may also control the display section 12062 so that an icon or the like representing the pedestrian is displayed at a desired position.

[0128] An example of the vehicle control system to which the technology according to the present disclosure may be applied has been described above. The technology according to the present disclosure may be applied to the imaging section 12031 and the like, for example, among the configurations described above. Specifically, the semiconductor devices 1 and 1a according to the present disclosure may be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031 and the like, a more easily viewable captured image may be obtained, whereby fatigue of the driver may be reduced.

[0129] In view of the above, it may be said that a light detecting device comprises a main structure (not labeled but corresponding to the combination of elements 10 and 50 in Figs. 2A and 2B, for example) that includes a first section 10 comprising a pixel region 100A including a plurality of pixels to convert light incident to a first side of the first section 10 into electric charge. The first section may further comprise a peripheral region 100B adjacent to the pixel region 100A, with the peripheral region including a first conductive structure (e.g., including conductor(s) 34) located at the first side of the first section. The light detecting device may further comprise a second section 50 that includes logic to process signals for the pixel region. As shown in Fig. 2A, in a cross sectional view, the first conductive structure electrically connects to the second section 50 at a first level within the main structure. The second section 50 may further comprise a second conductive structure (e.g., including conductor(s) 14, 15). In the cross-sectional view, the second conductive structure is located at a second level within main structure that is between the first level and at least part of the second section 50. In Fig. 2A, the second level is located is in the first section 10. In some examples, the first conductive structure comprises a first conductor and a second conductor at the first level with the first conductor being spaced apart from the second conductor (e.g., two conductors 34 shown in Figs. 2A and 3B). In some cases, the second conductive structure includes a third conductor and a fourth conductor at the second level, with the third conductor being spaced apart from the second conductor (e.g., two conductors 14). In the cross sectional view, the third conductor (e.g., one conductor 14) is between the first conductor and the second conductor (e.g., two conductors 34). In the cross sectional view, the fourth conductor (e.g., conductor 15) may be between the peripheral region and the pixel region.

[0130] In some examples, such as in Figs. 15A and 15B, the second level is located in the second section 50. In this case, in the cross sectional view, the second conductive structure comprises a first conductor (e.g., conductor 14) attached to a surface of the second section 50. In addition, in the cross sectional view, the first conductor is attached to the surface of the second section 50 is between two conductive pads (e.g., pads 51) that electrically connect the second section 50 to the first conductive structure of the first section 10 (Fig. 15A). Further, in the cross sectional view, the second conductive structure comprises a first conductor (e.g., 14) disposed between two layers of the second section (Fig. 15B). The first section 10 further comprises wirings (e.g., VSLs) that overlap with at least part of the second conductive structure in a plan view. The wirings are electrically connected to the second section 50 through the first conductive structure (e.g., conductor(s) 34). The first section 10 further comprises a conductive pad (e.g., pad 36) electrically connected to the wirings, the conductive pad being configured to electrically connect to a third structure separate from the first and second sections. The wirings comprises a first set of wirings (e.g., VSLs 34) and a second set of wirings (e.g., another set of VSLs 34) spaced apart from one another in the plan view (Fig. 3). The second conductive structure comprises a first wiring that overlaps with the first set of wirings in the plan view, and a second wiring that overlaps with the second set of wirings in the plan view.

[0131] In some examples, the first section further comprises an insulating structure (e.g., layer(s) 17) including a first part that covers at least part of the first conductive structure (e.g., part of layer(s) 17 over conductor 34 in Fig. Fig. 13) and a second part that covers at least part of the second conductive structure (e.g., part of layer(s) 17 over conductor 14). A thickness of the first part may be greater than a thickness of the second part. In a plan view, the second conductive structure may have a lattice shape, such as in Fig. 5). An electronic apparatus may include the light detecting device(s) described herein and a signal processor.

[0132] In view of the above, it may be said that at least one embodiment is directed to a light detecting device comprising a first section 10 that includes a pixel region 100A including a plurality of pixels to convert light incident to a first side of the first section into electric charge, and a peripheral region 100B adjacent to the pixel region. In some examples, the peripheral region includes a first conductive structure (e.g., conductor(s) 34) located at the first side of the first section. The first conductive structure may be configured to electrically connect to a second section 50 that includes logic to process signals for the pixel region. The first section may further include wirings (e.g., VSLs), and a second conductive structure (e.g., conductor(s) 14) that overlaps with the wirings in a plan view. In a cross sectional view, the second conductive structure may be closer to the first side of the first section than the wirings, such as shown in Fig. 2A.

[0133] Note that the present technology may have the following configurations. (1) A light detecting device, comprising: 　　　　　　　a main structure comprising: 　　　　　　　　　　　a first section comprising: 　　　　　　　　　　　　　a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　　　　　　　　　　　a peripheral region adjacent to the pixel region, the peripheral region including a first conductive structure located at the first side of the first section; 　　　　　　　　　　　a second section that includes logic to process signals for the pixel region, wherein, in a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure; and 　　　　　　　　　　　a second conductive structure, wherein, in the cross sectional view, the second conductive structure is located at a second level within main structure that is between the first level and at least part of the second section. (2) The light detecting device of (1), wherein the second level is located is in the first section. (3) The light detecting device of one or more of (1) to (2), wherein the first conductive structure comprises a first conductor and a second conductor at the first level, the first conductor being spaced apart from the second conductor. (4) The light detecting device of one or more of (1) to (3), wherein the second conductive structure includes a third conductor and a fourth conductor at the second level, the third conductor being spaced apart from the second conductor. (5) The light detecting device of one or more of (1) to (4), wherein, in the cross sectional view, the third conductor is between the first conductor and the second conductor. (6) The light detecting device of one or more of (1) to (5), wherein, in the cross sectional view, the fourth conductor is between the peripheral region and the pixel region. (7) The light detecting device of one or more of (1) to (6), wherein the second level is located in the second section. (8) The light detecting device of one or more of (1) to (7), wherein, in the cross sectional view, the second conductive structure comprises a first conductor attached to a surface of the second section. (9) The light detecting device of one or more of (1) to (8), wherein, in the cross sectional view, the first conductor attached to the surface of the second section is between two conductive pads that electrically connect the second section to the first conductive structure of the first section. (10) The light detecting device of one or more of (1) to (9), wherein, in the cross sectional view, the second conductive structure comprises a first conductor disposed between two layers of the second section. (11) The light detecting device of one or more of (1) to (10), wherein the first section further comprises wirings that overlap with at least part of the second conductive structure in a plan view. (12) The light detecting device of one or more of (1) to (11), wherein the wirings are electrically connected to the second section through the first conductive structure. (13) The light detecting device of one or more of (1) to (12), wherein the first section further comprises a conductive pad electrically connected to the wirings, the conductive pad being configured to electrically connect to a third structure separate from the first and second sections. (14) The light detecting device of one or more of (1) to (13), wherein the wirings comprises a first set of wirings and a second set of wirings spaced apart from one another in the plan view. (15) The light detecting device of one or more of (1) to (14), wherein the second conductive structure comprises: 　　　　　　　a first wiring that overlaps with the first set of wirings in the plan view; and 　　　　　　　a second wiring that overlaps with the second set of wirings in the plan view. (16) The light detecting device of one or more of (1) to (15), wherein the first section further comprises: 　　　　　　　an insulating structure including a first part that covers at least part of the first conductive structure and a second part that covers at least part of the second conductive structure. (17) The light detecting device of one or more of (1) to (16), wherein a thickness of the first part is greater than a thickness of the second part. (18) The light detecting device of one or more of (1) to (17), wherein, in a plan view, the second conductive structure has a lattice shape. (19) An electronic apparatus, comprising: 　　　　　　　a light detecting device; and 　　　　　　　a signal processor to process output of the light detecting device, the light detecting device comprising: 　　　　　　　　　　　a main structure comprising: 　　　　　　　　　　　　　a first section comprising: 　　　　　　　　　　　　　a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　　　　　　　　　　　a peripheral region adjacent to the pixel region, the peripheral region including a first conductive structure located at the first side of the first section; 　　　　　　　　　　　　　a second section that includes logic to process signals for the pixel region, wherein, in a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure; and 　　　　　　　　　　　　　a second conductive structure, wherein, in the cross sectional view, the second conductive structure is located at a second level within main structure that is between the first level and at least part of the second section. (20) A light detecting device, comprising: 　　　　　　　a first section comprising: 　　　　　　　　　　　a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　　　　　　　　　a peripheral region adjacent to the pixel region, the peripheral region including: 　　　　　　　　　　　　　a first conductive structure located at the first side of the first section, the first conductive structure being configured to electrically connect to a second section that includes logic to process signals for the pixel region; and 　　　　　　　　　　　a wiring layer including: 　　　　　　　　　　　　　wirings; and　　 　　　　　　　　　　　　　a second conductive structure that overlaps with the wirings in a plan view, wherein, in a cross sectional view, the second conductive structure is closer to the first side of the first section than the wirings.

[0134] Aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the contents described above. That is, various additions, modifications, and partial deletions may be made without departing from the conceptual idea and gist of the present disclosure derived from the contents defined in the claims and equivalents thereof.

[0135] 1　　　　　　Semiconductor device 1a　　　　　　Semiconductor device 2　　　　　　Pixel array section 2a　　　　　　Pixel array section 2b　　　　　　Peripheral circuit section 3　　　　　　Vertical drive unit 4　　　　　　Column processing unit 5　　　　　　Horizontal drive unit 6　　　　　　System control unit 7　　　　　　Signal processing unit 8　　　　　　Data storage unit 9　　　　　　Output unit 10　　　　　　Sensor element 11　　　　　　Silicon substrate H1, H2, H1a, H2a　　　　　　Opening 12　　　　　　Photoelectric conversion unit 13　　　　　　Through via 14　　　　　　Shield member 15　　　　　　Dummy wiring layer 16　　　　　　Via 17　　　　　　Laminated insulating layer 18　　　　　　Wiring (Second signal wiring) 18　　　　　　Wiring 19　　　　　　Structure body 19a　　　　　　Laminated body 19b　　　　　　AlCu layer 19c　　　　　　Ta layer 20　　　　　　Multilayer wiring layer 21　　　　　　Insulating layer 22　　　　　　Wiring layer 23　　　　　　Laminated wiring layer 24　　　　　　Insulating layer 25　　　　　　Cu wiring layer 26　　　　　　Cu wiring layer 31　　　　　　Interlayer insulating layer 31a　　　　　　Insulating layer 32　　　　　　Light-shielding film 33　　　　　　Wiring layer 34　　　　　　Pad 34a　　　　　　Metal film 34b　　　　　　Metal film 34c　　　　　　Metal film 35　　　　　　Pixel separation portion 36　　　　　　Pad 37L　　　　　　Inner lens 38　　　　　　Planarization layer 39　　　　　　Pixel separation portion 40　　　　　　Protective layer 41　　　　　　Color filter 42　　　　　　On-chip lens layer 42L　　　　　　On-chip lens 50　　　　　　Semiconductor chip 51　　　　　　Pad 52　　　　　　Solder bump 53　　　　　　Wiring layer 54　　　　　　Silicon substrate 100A　　　　　Light receiving region 100B　　　　　Peripheral region

Claims

1. A light detecting device, comprising: 　　　 a main structure comprising: 　　　　　　　a first section comprising: 　　　 　　　 　　　 a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　 　　　 　　　 a peripheral region adjacent to the pixel region, the peripheral region including a first conductive structure located at the first side of the first section; 　　　 　　　 a second section that includes logic to process signals for the pixel region, wherein, in a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure; and 　　　 　　　 a second conductive structure, wherein, in the cross sectional view, the second conductive structure is located at a second level within main structure that is between the first level and at least part of the second section.

2. The light detecting device of claim 1, wherein the second level is located is in the first section.

3. The light detecting device of claim 2, wherein the first conductive structure comprises a first conductor and a second conductor at the first level, the first conductor being spaced apart from the second conductor.

4. The light detecting device of claim 3, wherein the second conductive structure includes a third conductor and a fourth conductor at the second level, the third conductor being spaced apart from the second conductor.

5. The light detecting device of claim 4, wherein, in the cross sectional view, the third conductor is between the first conductor and the second conductor.

6. The light detecting device of claim 5, wherein, in the cross sectional view, the fourth conductor is between the peripheral region and the pixel region.

7. The light detecting device of claim 1, wherein the second level is located in the second section.

8. The light detecting device of claim 7, wherein, in the cross sectional view, the second conductive structure comprises a first conductor attached to a surface of the second section.

9. The light detecting device of claim 8, wherein, in the cross sectional view, the first conductor attached to the surface of the second section is between two conductive pads that electrically connect the second section to the first conductive structure of the first section.

10. The light detecting device of claim 7, wherein, in the cross sectional view, the second conductive structure comprises a first conductor disposed between two layers of the second section.

11. The light detecting device of claim 1, wherein the first section further comprises wirings that overlap with at least part of the second conductive structure in a plan view.

12. The light detecting device of claim 11, wherein the wirings are electrically connected to the second section through the first conductive structure.

13. The light detecting device of claim 12, wherein the first section further comprises a conductive pad electrically connected to the wirings, the conductive pad being configured to electrically connect to a third structure separate from the first and second sections.

14. The light detecting device of claim 11, wherein the wirings comprises a first set of wirings and a second set of wirings spaced apart from one another in the plan view.

15. The light detecting device of claim 14, wherein the second conductive structure comprises: 　　　 a first wiring that overlaps with the first set of wirings in the plan view; and 　　　 a second wiring that overlaps with the second set of wirings in the plan view.

16. The light detecting device of claim 1, wherein the first section further comprises: 　　　 an insulating structure including a first part that covers at least part of the first conductive structure and a second part that covers at least part of the second conductive structure.

17. The light detecting device of claim 16, wherein a thickness of the first part is greater than a thickness of the second part.

18. The light detecting device of claim 1, wherein, in a plan view, the second conductive structure has a lattice shape.

19. An electronic apparatus, comprising: 　　　 a light detecting device; and 　　　 a signal processor to process output of the light detecting device, the light detecting device comprising: 　　　 　　　 a main structure comprising: 　　　 　　　 　　　 a first section comprising: 　　　 　　　 　　　 　　　 a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　 　　　 　　　 　　　 a peripheral region adjacent to the pixel region, the peripheral region including a first conductive structure located at the first side of the first section; 　　　 　　　 　　　 a second section that includes logic to process signals for the pixel region, wherein, in a cross sectional view, the first conductive structure electrically connects to the second section at a first level within the main structure; and 　　　 　　　 　　　 a second conductive structure, wherein, in the cross sectional view, the second conductive structure is located at a second level within main structure that is between the first level and at least part of the second section.

20. A light detecting device, comprising: 　　　 a first section comprising: 　　　 　　　 a pixel region including a plurality of pixels to convert light incident to a first side of the first section into electric charge; and 　　　 　　　 a peripheral region adjacent to the pixel region, the peripheral region including: 　　　 　　　 　　　 a first conductive structure located at the first side of the first section, the first conductive structure being configured to electrically connect to a second section that includes logic to process signals for the pixel region; and 　　　 　　　 a wiring layer including: 　　　 　　　 　　　 wirings; and 　　　 　　　 　　　 a second conductive structure that overlaps with the wirings in a plan view, wherein, in a cross sectional view, the second conductive structure is closer to the first side of the first section than the wirings.

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