Sic composite, method for producing same, sic laminate, and sic semiconductor device

Abstract

This SiC composite has: a SiC single crystalline substrate having a diameter of at least 150 mm; and a graphene layer formed on the top surface of the SiC single crystalline substrate by a thermal decomposition method, wherein the graphene layer has a surface roughness Ra of 1.2 nm or less. Defects in the graphene layer may be 0.2 or less in terms of intensity ratio ID / G of a Raman spectrum, the SiC single crystalline substrate may be hexagonal 4H or 6H or cubic 3C, the off-angle of the top surface may be in a range of 0.5-10°, and the graphene layer may be composed of 0-2 layers of graphene.

Description

SiC composite, method for manufacturing the same, SiC laminate, and SiC semiconductor device

[0001] The present disclosure relates to a SiC composite, a method for manufacturing the same, a SiC stack, and a SiC semiconductor device.

[0002] A conventional graphene production method known as the pyrolysis method involves heating a SiC single crystal at high temperatures to form graphene, a two-dimensional material composed of carbon atoms, on the surface. The pyrolysis method is a useful production method with a wide range of industrial applications because it allows graphene to be grown directly from the SiC single crystal and formed over a large area on a wafer scale (see Patent Document 1).

[0003] On the other hand, it is known that in the method of producing graphene by pyrolysis, surface roughness called step bunching generally occurs during heating. To date, methods to suppress the occurrence of step bunching have been used, such as controlling the temperature, heating rate, and time under constant pressure conditions, or applying a carbon-based material to the surface of the SiC single crystal in advance.

[0004] JP 2015-110485 A

[0005] [Summary] The occurrence of step bunching can cause the mobility characteristics of graphene to deteriorate due to interference from the steps, making it difficult to simultaneously control the number of layers, reduce defects, and suppress surface roughness.

[0006] The present disclosure has been proposed in view of the above-described circumstances, and aims to provide a SiC composite in which graphene is grown on the surface of a SiC single crystal by a pyrolysis method, and a method for producing the same, which suppresses the occurrence of step bunching.

[0007] The SiC composite of the present disclosure includes a SiC single crystal substrate having a diameter of 150 mm or more and a graphene layer formed by a pyrolysis method on a top surface of the SiC single crystal substrate, the graphene layer having a surface roughness Ra of 1.2 nm or less.

[0008] The method for producing a SiC composite according to the present disclosure is a method for producing a SiC composite by forming a graphene layer by pyrolysis on the surface of a SiC single crystal substrate having a diameter of 150 mm or more, and includes: a first step of forming graphene in an atmosphere having a pressure and temperature that makes it difficult for step bunching to occur; and a second step of forming graphene on the surface of the graphene formed in the first step in an atmosphere having a pressure and temperature that allows graphene with few defects to be formed with good control over the number of layers, wherein the pressure and temperature of the atmosphere in the second step are higher than those of the atmosphere in the first step.

[0009] FIG. 1 is a cross-sectional view of a SiC composite according to a first embodiment. FIG. 2 is a diagram illustrating the formation of a graphene layer by a pyrolysis method. FIG. 3 is a micrograph illustrating the surface shape of graphene according to the first embodiment. FIG. 4 is a diagram illustrating the formation of steps in the 0 layer of graphene. FIG. 5 is a diagram illustrating the occurrence of step bunching. FIG. 6 is a graph illustrating the results of Raman spectroscopy of the graphene layer according to the first embodiment. FIG. 7 is a diagram illustrating mapping of the half-width of the 2D band obtained by Raman spectroscopy of the graphene layer according to the first embodiment. FIG. 8 is a diagram illustrating the generation of graphene from a step portion. FIG. 9 is a diagram illustrating the relationship between the occurrence of step bunching and the heating rate. FIG. 10 is a table illustrating the relationship between the pressure for forming graphene and the crystallinity of graphene, the controllability of the number of layers, and step bunching. FIG. 11A is a diagram illustrating a first example of the relationship between the pressure for forming graphene and the crystallinity of graphene. FIG. 11B is a diagram illustrating a second example of the relationship between the pressure for forming graphene and the crystallinity of graphene. FIG. 12 is a table showing the relationship between the temperature for forming graphene and the crystallinity of graphene, the controllability of the number of layers, and step bunching. FIG. 13 is a flowchart showing a series of steps in a method for manufacturing a SiC composite according to the first embodiment. FIG. 14 is a cross-sectional view of a SiC composite according to the third embodiment. FIG. 15 is a flowchart showing a series of steps in a method for manufacturing a SiC composite according to the third embodiment. FIG. 16 is a cross-sectional view of a SiC composite substrate. FIG. 17A is a process diagram for manufacturing a SiC composite substrate. FIG. 17B is a process diagram for manufacturing a SiC composite substrate. FIG. 18 is a cross-sectional view of a Schottky barrier diode. FIG. 19 is a cross-sectional view of a trench structure MOSFET.

[0010] [Detailed Description] Hereinafter, embodiments of the SiC composite and its manufacturing method of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are comprehensive or specific examples, and the numerical values, shapes, materials, components, component installation positions, and connection forms are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in the independent claims that represent the highest concepts will be described as optional components. Furthermore, the dimensional proportions in the drawings are exaggerated for the sake of explanation and may differ from the actual proportions. Furthermore, the following embodiments and their variations may include similar components, and similar components will be assigned common reference numerals, and redundant description will be omitted.

[0011] First Embodiment FIG. 1 is a cross-sectional view of a SiC composite 1 according to a first embodiment. The SiC composite 1 according to the first embodiment is fabricated by a manufacturing method described below and includes a SiC single crystal substrate 10 having a diameter of 150 mm or more and a graphene layer 11 formed by pyrolysis on a top surface 10a of the SiC single crystal substrate 10. In the first embodiment, the SiC single crystal substrate 10 is assumed to have a diameter of 150 mm or 6 inches or more. The SiC single crystal substrate 10 has a hexagonal 4H crystal polytype, and the top surface 10a is assumed to be a (0001) Si-face having an off-angle in the range of 0.5° to 10°. However, the off-angle may be in the range of 0° to 10°, or in the range of 0° to 0.5°. The graphene layer 11 is assumed to have a number of layers ranging from 0 to 2. Note that the 0-layer graphene is graphene integrated with the Si layer directly below it by a covalent bond and is also referred to as a buffer layer.

[0012] 2 is a diagram illustrating the formation of a graphene layer 11 by a pyrolysis method. When the SiC single crystal substrate 10 is heated, Si sublimes from the top surface 10a, which is the Si surface, and the remaining C atoms form a zero-layer graphene 11a on the top surface 10a, covalently bonded to the Si layer directly below. As heating continues, more Si sublimes from the top surface 10a of the SiC single crystal substrate, and the zero-layer graphene 11a is released from the covalent bond to become a first-layer graphene 11b. A new zero-layer graphene 11a is formed directly below this first-layer graphene 11b. As heating continues, the zero-layer graphene 11a becomes the first-layer graphene 11b, and a new zero-layer graphene 11a is formed directly below the first-layer graphene 11b. This process is repeated. In this way, a graphene layer 11 is formed on the top surface of the SiC single crystal substrate 10, where the first or more layers of graphene 11b are stacked on the zero-layer graphene 11a.

[0013] 3 is a micrograph showing the surface shape of the graphene layer 11 according to the first embodiment. This micrograph was taken using an atomic force microscope with a 2×2 μm ２ The graphene layer 11 was observed in a range of 2 × 2 μm. It was observed that the step bunching steps were formed in a striped pattern on the surface of the graphene layer 11. The surface roughness Ra of the graphene layer 11 was measured by an atomic force microscope and was found to be 2 × 2 μm. ２ The surface roughness Ra was 0.93 nm in the range. The surface roughness Ra of the graphene layer 11 according to the first embodiment may be 1.2 nm or less, 1.0 nm or less, 0.8 nm or less, or 0.6 nm or less. The surface roughness Ra may be 0.2 μm or more, 0.3 nm or more, or 0.4 nm or more. Here, step bunching will be described.

[0014] FIG. 4 is a diagram illustrating the formation of steps in the 0th layer of graphene 11a. FIG. 4 is a cross-sectional view near the top surface 10a of a SiC single crystal substrate 10. In the figure, white circles represent Si atoms, and black circles represent C molecules. The 0th layer of graphene 11a is shown on the top surface 10a of the SiC single crystal substrate 10, among the graphene layers 11. The SiC single crystal substrate 10 has a hexagonal 4H crystal polytype, and the top surface 10a is assumed to be a (0001) Si surface. Therefore, when the 0th layer of graphene is formed by thermal decomposition, two types of terraces are formed on the top surface 10a by layers called 4H1 and 4H2 due to C atoms. The 4H1 and 4H2 layers are alternately stacked in the depth direction, occupying cubic and hexagonal crystal sites, respectively, and steps are formed between adjacent 4H1 and 4H2 terraces. 4H2 is formed at a faster rate than 4H1, and as the formation of the 0th layer of graphene 11a progresses in the depth direction of the SiC single crystal substrate 10, the steps between the 4H1 terraces and the 4H2 terraces move so as to expand the 4H2 terraces.

[0015] 5 is a diagram illustrating the occurrence of step bunching. As shown in FIG. 4, 4H1 terraces and 4H2 terraces are formed in the 0th layer of graphene 11a as Si sublimates. The steps between the 4H1 terrace and the 4H2 terrace move to expand the 4H2 terrace. As a result, adjacent terraces merge to expand the 4H2 terrace. 4H1 and 4H2 terraces are continuously formed on the top surface 10a of the SiC single crystal substrate 10 as Si sublimates. As multiple terraces merge and the step height increases, step-like surface roughness, known as step bunching, appears on the 0th layer of graphene 11a. The step bunching that appears on the 0th layer of graphene 11a appears on the surface of the graphene layer 11 through the first and subsequent layers of graphene 11b that cover the 0th layer of graphene 11a.

[0016] 6 is a graph showing the results of Raman spectroscopy measurement of the graphene layer 11 according to the first embodiment. The Raman spectrum shown in FIG. 6 is obtained by subtracting the components of SiC and the buffer layer from the spectrum of the measured graphene layer 11. This spectrum includes a peak at 1360 cm －１ Nearby D band, 1600 cm－１ Nearby G band and 2710 cm －１ A 2D band near the G band is observed. The G band is characteristic of graphene, and the D peak is due to defects in graphene. The 2D band is due to second-order two-phonon scattering and can be used to determine the number of graphene layers 11. In the spectrum of Figure 6, the intensity ratio I Ｄ／Ｇ , i.e., the G-band intensity I Ｇ The D band intensity I normalized by Ｄ is I Ｄ / I Ｇ The graphene layer 11 of the first embodiment has a thickness of 1.5 μm and a thickness of 1.5 μm. Ｄ／Ｇ may be smaller than 0.2, may be smaller than 0.15, or may be smaller than 0.1. Ｄ／Ｇ may be greater than 0.04, may be greater than 0.06, or may be greater than 0.08.

[0017] 7 is a diagram showing mapping of the half-width of the 2D band obtained by Raman spectroscopy of the graphene layer 11 according to the first embodiment. When the half-width of the 2D band was measured at 20 × 20 points at intervals of 1 μm along the surface of the graphene layer 11, the half-width was 60 cm －１ The above-mentioned portions were not observed, and it was revealed that the graphene layer 11 had two layers. Note that the graphene layer 11 of the first embodiment may be composed of only the buffer layer of 0 layer, or may be composed of one or two graphene layers.

[0018] In the first embodiment, the SiC single crystal substrate 10 constituting the SiC composite is assumed to have a hexagonal 4H crystal polytype, but this is not limitative. The SiC single crystal substrate 10 may be a hexagonal 6H crystal polytype or a cubic 3C crystal polytype.

[0019] A manufacturing method for producing the SiC composite 1 of the first embodiment described above will be described. This manufacturing method utilizes the following properties of graphene.

[0020] 8 is a diagram illustrating the generation of graphene from step portions. As shown in Fig. 8, Si sublimation occurs primarily from step portions on the top surface 10a of the SiC single crystal substrate 10 on which the zeroth layer of graphene 11a is formed. Therefore, by forming the first and subsequent layers of graphene 11b on the step portions to cover the step portions, it is possible to suppress the sublimation of Si from the step portions and reduce step bunching.

[0021] 9 is a graph showing the relationship between the temperature rise rate and the occurrence of step bunching in the process of forming the graphene layer 11. As shown in FIG. 9 , in the first profile a, in which the temperature is rapidly raised over three minutes from the starting point of 800°C to 1650°C, at which graphene grows, the temperature quickly passes through the temperature range from 1200°C to over 1600°C, at which step bunching occurs, and minimum step bunching (MSB) occurs. In contrast, in the second profile b, in which the temperature is raised over 20 minutes from the starting point of 800°C to 1650°C, at which graphene grows, the temperature range from 1200°C to over 1600°C, at which step bunching occurs, remains for a long time, and large step bunching (LSB) occurs. Comparing the first profile a and the second profile b, the first profile a has a high temperature rise rate, shortens the time spent in the temperature range at which step bunching occurs, and reduces the occurrence of step bunching.

[0022] FIG. 10 is a table showing the relationship between the pressure for forming graphene and the crystallinity of graphene, the controllability of the number of layers, and step bunching. When the pressure of the atmosphere for forming graphene is low, the crystallinity of graphene is poor, the graphene crystal has many defects, and the controllability of the number of layers of graphene to be formed is poor, leading to a tendency for multilayering. However, the progress of step bunching is slow, and when the surface roughness Ra is used as an index of step bunching, the surface roughness Ra is low. Furthermore, Si sublimation is fast. In contrast, when the pressure of the atmosphere for forming graphene is high, the crystallinity of graphene is good, the graphene crystal has few defects, and the controllability of the number of layers of graphene to be formed is good. However, the progress of step bunching is fast, and the surface roughness Ra is high.

[0023] FIG. 11A shows a first example of the relationship between the pressure at which graphene is formed and the crystallinity of the graphene. This first example shows the case where graphene is rapidly formed at high pressure. As shown in the left diagram in FIG. 11A , when defects such as threading screw dislocations and threading mixed dislocations occur near the top surface 10 a of the SiC single crystal substrate 10, Si sublimation is suppressed under high pressure, significantly reducing the graphene growth rate at defect-free areas of the SiC single crystal substrate 10. At the defect-generated areas, the energy required for thermal decomposition is low, allowing graphene to grow at a high growth rate despite the high pressure. Furthermore, since the surrounding area is not covered with graphene, the sublimation of Si at the defected areas is not inhibited by the graphene. Therefore, as shown in the right diagram in FIG. 11A , Si atoms escape from areas not covered with graphene, resulting in localized multilayering.

[0024] FIG. 11B shows a second example of the relationship between the pressure used to form graphene and the crystallinity of the graphene. This second example shows the case where graphene is formed in low-pressure and high-pressure atmospheres in that order. As shown in the left diagram in FIG. 11B , when defects such as threading screw dislocations and threading mixed dislocations occur near the top surface 10 a of the SiC single crystal substrate 10, graphene grows from areas other than the defect. As a result, a wide area of ​​the surface is covered with graphene, further inhibiting subsequent sublimation. In other words, this prevents the formation of multiple layers at the defect. Finally, the substrate is heated at high pressure and high temperature. As shown in the right diagram in FIG. 11B , since graphene has already begun to cover the surface, further increase in the number of layers does not proceed significantly. Instead, the carbon atoms in the graphene become more mobile due to heat, repairing the defects and improving the crystallinity.

[0025] FIG. 12 is a table showing the relationship between the temperature for forming graphene and the crystallinity of graphene, the controllability of the number of layers, and step bunching. When the temperature of the atmosphere for forming graphene is low, the crystallinity of graphene is poor and the graphene crystal has many defects. However, the controllability of the number of layers of graphene to be formed is good, the progress of step bunching is slow, and when the surface roughness Ra is used as an index of step bunching, the surface roughness Ra is low. In addition, Si sublimation is fast. In contrast, when the temperature of the atmosphere for forming graphene is high, the crystallinity of graphene is good and the graphene crystal has few defects. However, the controllability of the number of layers of graphene to be formed is somewhat poor, the progress of step bunching is fast, and the surface roughness Ra is high.

[0026] The manufacturing method of the first embodiment utilizes the properties of graphene described above and forms the graphene layer 11 by heating multiple times while varying not only the temperature and time but also the pressure. As shown in the table of FIG. 10 , it is generally known that a high heating pressure suppresses the desorption of Si from the SiC single crystal substrate 10, provides good control over the number of layers, and reduces defects. On the other hand, a low pressure reduces the above-mentioned benefits but is characterized by less bunching. However, since pressure significantly contributes to controlling the rate of thermal decomposition or sublimation and can be varied over a wide range of conditions, from atmospheric pressure to ultra-high vacuum, a technique of varying the pressure during graphene deposition is effective in controlling graphene growth. In the manufacturing method of the first embodiment, by appropriately controlling the pressure at multiple stages, graphene is formed that has the properties of fewer defects, low surface roughness Ra, and a thin number of layers, which cannot be achieved by temperature and time changes alone.

[0027] 13 is a flowchart showing a series of steps in the method for manufacturing the SiC composite 1 according to the first embodiment. The manufacturing of the SiC composite 1 will be described with reference to this flowchart.

[0028] In step S1, an oxide film formed on the surface of the SiC single crystal substrate 10 is removed. The SiC single crystal substrate 10 is made of 4H SiC single crystal, and the top surface 10a is a (0001) Si-face with an off-angle of 4° that has been chemically mechanically polished (CMP). The SiC single crystal substrate 10 is immersed in a 1% HF aqueous solution to remove the oxide film covering the surface of the SiC single crystal substrate 10.

[0029] In step S2, the SiC single crystal substrate 10 from which the oxide film has been removed in step S1 is placed in a heating furnace and heated at a temperature of 1400° C. and a pressure of 10 －３ The SiC single crystal substrate 10 is heated for 5 minutes in a first atmosphere of Pa. The first atmosphere may contain an inert gas such as argon (Ar), or may contain nitrogen gas (N ２ ) may also be included.

[0030] Step S2 constitutes the first process of forming graphene in an atmosphere having a pressure and temperature that are unlikely to cause step bunching. Referring to Figures 10 and 12, which respectively show the relationship between the atmospheric pressure and temperature and the properties of the graphene formed, the pressure and temperature of the first atmosphere in step S2 are "low," and the temperature is also "low." This results in poor graphene crystallinity, but the progression of step bunching is slow. Therefore, graphene layer 11 is formed on top surface 10a of SiC single crystal substrate 10 without the formation of step bunching, and top surface 10a is covered with graphene layer 11. As described with reference to Figure 8, when top surface 10a of SiC single crystal substrate 10 is covered with graphene layer 11, sublimation of Si from the steps is suppressed, reducing the occurrence of step bunching.

[0031] In step S3, the temperature is 1450° C. and the pressure is 10 ０ In step S4, the SiC single crystal substrate 10 is heated in the second atmosphere of 1700° C. and 10 Pa for 5 minutes. ２ In step S5, the SiC single crystal substrate 10 is heated in the third atmosphere of 1700° C. and 10 Pa for 5 minutes. ４The SiC single crystal substrate 10 is heated for 5 minutes in the fourth atmosphere at 1 Pa. The pressure and temperature of the second atmosphere to the fourth atmosphere are higher than the pressure and temperature of the first atmosphere in the first step. The second atmosphere to the fourth atmosphere may contain an inert gas such as argon (Ar) like the first atmosphere, and may contain nitrogen gas (N ２ ) may also be included.

[0032] Steps S3 to S5 constitute a second process for forming graphene in an atmosphere having a pressure and temperature that allows for the formation of graphene with few defects and good control over the number of graphene layers. Referring to Figures 10 and 12, which respectively show the relationship between the atmospheric pressure and temperature and the properties of the graphene formed, the pressures of the second to fourth atmospheres in steps S3 to S5 are "high" and the temperatures are "high." Although the growth of graphene layer 11 is slow due to slow Si sublimation, the crystallinity of graphene is good and the control over the number of graphene layers 11 is good or somewhat poor.

[0033] The pressure of the first atmosphere in step S2 of the first process is 10 －３ Pa, whereas the pressures of the second to fourth atmospheres in steps S3 to S5 of the second process are 10 ０ Pa to 10 ４ The pressures of the second atmosphere to the fourth atmosphere in the second step are in the range of 10 Pa higher than the pressure of the first atmosphere in the first step. ２ The pressure of the second atmosphere to the fourth atmosphere in the second step is 10 times higher than the pressure of the first atmosphere in the first step. １１ It may be higher by a factor of 10 or less.

[0034] The temperature of the first atmosphere in step S2 of the first process is 1400°C, and the temperatures of the second to fourth atmospheres in steps S3 to S5 of the second process are in the range of 1450°C to 1700°C. The temperatures of the first and second processes may be in the range of 1000°C to 2000°C. The temperatures of the first and second processes may be in the range of 1200°C to 1900°C, or in the range of 1300°C to 1800°C.

[0035] The time for step S2 of the first step is 5 minutes, and the time for steps S3 to S5 of the second step is 5 minutes each, for a total of 15 minutes. The time for the first step and the time for the second step may be different.

[0036] The first step is composed of a single step S2, while the second step is composed of multiple steps S3 to S5. At least one of the first step and the second step may be composed of multiple steps in which at least one of the atmospheric pressure and temperature is different. The first step and the second step may be composed of multiple steps in total ranging from 3 to 8. At least some of the multiple steps may have different times from each other.

[0037] The pressure of the atmosphere in the plurality of steps including at least one of the first step and the second step may be higher than or the same as the pressure of the immediately preceding step in the plurality of steps. ２ More than double 10 １１ The pressure in the multiple steps may be lowest in the first step.

[0038] The temperature of the atmosphere in the plurality of steps including at least one of the first step and the second step may be higher than or the same as the temperature of the immediately preceding step in the plurality of steps. The temperature in the plurality of steps may be the lowest in the first step.

[0039] According to the first embodiment, it is possible to suppress the occurrence of step bunching and to grow graphene with few defects with good control over the number of layers. As a result, it is possible to simultaneously control the number of layers and reduce defects while suppressing surface roughness, thereby improving the mobility of graphene and suppressing anisotropy.

[0040] Second Embodiment Next, a SiC composite according to a second embodiment will be described. The composite according to the second embodiment is produced by a manufacturing method described below and has a configuration similar to that of the SiC composite 1 according to the first embodiment, as shown in FIG. 1 . That is, as shown in FIG. 1 , the SiC composite according to the second embodiment is composed of a SiC single crystal substrate 10 having a diameter of 150 mm or more and a graphene layer 11 formed by pyrolysis on the top surface 10 a of the SiC single crystal substrate 10. In the second embodiment, the SiC single crystal substrate 10 is assumed to have a diameter of 150 mm or 6 inches or more. The SiC single crystal substrate 10 has a hexagonal 4H crystal polytype, and the top surface 10 c is assumed to be a (0001) Si-face with an off-angle in the range of 0.5° to 10°. However, the off-angle may be in the range of 0° to 10°, or in the range of 0° to 0.5°. The graphene layer 11 is assumed to have 0 to 2 layers. In the following description of the second embodiment, the description of the configuration common to the first embodiment will be omitted for simplicity.

[0041] In the SiC composite of the second embodiment, the surface roughness Ra of the graphene layer 11 was measured by an atomic force microscope and found to be 2×2 μm ２ The surface roughness Ra was 1.2 nm in the range of 1.2 nm. Ｄ／Ｇ The half width of the 2D band was measured at 20 × 20 points at intervals of 1 μm along the surface of the graphene layer 11, and the half width was 60 cm －１ The above-mentioned portions were not observed, and it was revealed that the graphene layer 11 was composed of two layers.

[0042] A manufacturing method for producing the SiC composite of the second embodiment described above will be described. The second embodiment is common to the first embodiment in that the SiC composite is manufactured by steps S1 to S5 shown in Fig. 13, and therefore will be described with reference to Fig. 13. However, the atmosphere and time in steps S2 to S4 in the second embodiment are set differently from those in the first embodiment.

[0043] In step S1, an oxide film formed on the surface of the SiC single crystal substrate 10 is removed. The SiC single crystal substrate 10 is made of 4H SiC single crystal, and the top surface 10a is a (0001) Si-face with an off-angle of 4°, which has been CMP-polished. The SiC single crystal substrate 10 is immersed in a 1% HF aqueous solution to remove the oxide film covering the surface of the SiC single crystal substrate 10.

[0044] In step S2, the SiC single crystal substrate 10 from which the oxide film has been removed in step S1 is placed in a heating furnace and heated at a temperature of 1400° C. and a pressure of 10 －５ The SiC single crystal substrate 10 is heated for 5 minutes in the first atmosphere of Pa. This step S2 constitutes a first process of forming graphene in an atmosphere having a pressure and temperature at which step bunching is unlikely to occur.

[0045] In step S3, the temperature is 1425°C and the pressure is 10 －３ In step S4, the SiC single crystal substrate 10 is heated in the second atmosphere of 1450° C. and 10 Pa for 5 minutes. ０ In step S5, the SiC single crystal substrate 10 is heated in the third atmosphere of 1800° C. and 10 Pa for 5 minutes. ４ The SiC single crystal substrate 10 is heated for 1 minute in the fourth atmosphere at 70 Pa. Steps S3 to S5 constitute a second process of forming graphene in an atmosphere having pressure and temperature that allows for the formation of graphene with few defects with good control over the number of graphene layers.

[0046] In the second embodiment, two graphene layers 11 are formed, and the surface roughness Ra of the graphene layer 11 is 1.0 nm. Ｄ／Ｇ In the first embodiment, the surface roughness was 0.93 nm, and I Ｄ／Ｇ In comparison with the fact that the value of the step bunching coefficient was 0.15, it was clear that the occurrence of step bunching was at the same level as in the second embodiment, and that the number of defects in the graphene was even smaller.

[0047] According to the second embodiment, it is possible to suppress the occurrence of step bunching and to grow graphene with few defects with good control over the number of layers. As a result, it is possible to simultaneously control the number of layers and reduce defects while suppressing surface roughness, thereby improving the mobility of graphene and suppressing anisotropy.

[0048] (Third Embodiment) FIG. 14 is a cross-sectional view of a SiC composite 2 according to a third embodiment. The SiC composite 2 according to the third embodiment is fabricated by a manufacturing method described below and includes a SiC single crystal substrate 10 having a diameter of 150 mm or more, a graphene layer 11 formed by pyrolysis on a top surface 10a of the SiC single crystal substrate 10, and a SiC epitaxy layer 12 formed to cover the graphene layer 11. In the third embodiment, the SiC single crystal substrate 10 is assumed to have a diameter of 150 mm or 6 inches or more. The SiC single crystal substrate 10 has a hexagonal 4H crystal polytype, and the top surface 10a is assumed to be a (0001) Si-face with an off-angle in the range of 0.5° to 10°. However, the off-angle may be in the range of 0° to 10°, or in the range of 0° to 0.5°. The graphene layer 11 is assumed to have 0 to 2 layers. The SiC epitaxy layer 12 is fabricated by a remote epitaxial method so as to transfer the crystal structure of the top surface 10a of the SiC single crystal substrate 10 via the graphene layer 11. In the following description of the third embodiment, for the sake of simplicity, description of the configuration common to the first embodiment will be omitted.

[0049] In the SiC composite 2 of the third embodiment, the surface roughness Ra of the graphene layer 11 was measured by an atomic force microscope and found to be 2×2 μm ２ The surface roughness Ra was 0.5 nm in the range of 1. The surface roughness Ra of the graphene layer 11 was measured before forming the SiC epitaxy layer 12 covering the graphene layer 11. When the Raman spectrum of the graphene layer 11 shown in FIG. 2 was measured, Ｄ／ＧThe half width of the 2D band was measured at 20 × 20 points at intervals of 1 μm along the surface of the graphene layer 11, and the half width was 45 cm －１ The above-mentioned portions were not observed, and it was revealed that the graphene layer 11 was a single layer.

[0050] A manufacturing method for producing the SiC composite of the third embodiment described above will now be described. FIG. 15 is a flowchart showing a series of steps in the manufacturing method for the SiC composite 1 of the third embodiment. The third embodiment is similar to the first embodiment in that the SiC composite 2 is manufactured through steps S1 to S5 shown in FIG. 13 . However, the atmosphere and time in steps S2 to S4 in the third embodiment are set differently from those in the first embodiment. Furthermore, in addition to steps S1 to S5 of the first embodiment, the third embodiment includes step S6 of forming a graphene layer 11 on a SiC single crystal substrate 10 in a fifth atmosphere, and step S7 of forming a SiC epitaxy layer 12.

[0051] In step S1, an oxide film formed on the surface of the SiC single crystal substrate 10 is removed. The SiC single crystal substrate 10 is made of 4H SiC single crystal, and the top surface 10a is a (0001) Si-face with an off-angle of 4°, which has been CMP-polished. The SiC single crystal substrate 10 is immersed in a 1% HF aqueous solution to remove the oxide film covering the surface of the SiC single crystal substrate 10.

[0052] In step S2, the SiC single crystal substrate 10 from which the oxide film has been removed in step S1 is placed in a heating furnace and heated at a temperature of 1350° C. and a pressure of 10 －３ The SiC single crystal substrate 10 is heated for 5 minutes in the first atmosphere of Pa. This step S2 constitutes a first process of forming graphene in an atmosphere having a pressure and temperature at which step bunching is unlikely to occur.

[0053] In step S3, the temperature is 1450° C. and the pressure is 10 ０ In step S4, the SiC single crystal substrate 10 is heated in the second atmosphere of 1400° C. and 10 Pa for 10 minutes. －２In step S5, the SiC single crystal substrate 10 is heated in the third atmosphere of 1450° C. and 10 Pa for 5 minutes. ０ In step S6, the SiC single crystal substrate 10 is heated in the fourth atmosphere of 1650° C. and 10 Pa for 5 minutes. ５ The SiC single crystal substrate 10 is heated for 10 minutes in a fifth atmosphere of 0.1 Pa. Steps S3 to S6 constitute a second step of forming graphene in an atmosphere having pressure and temperature that allows for the formation of graphene with few defects with good control over the number of graphene layers.

[0054] In step S7, a SiC epitaxial layer 12 is formed by remote epitaxy to cover the graphene layer 11. The source gas may be, for example, propane (C ３ H ８ ) and silane (SiH ４ ) can be used at a deposition ratio of 1:3. Hydrogen or argon gas may be used as a carrier gas for transporting the source gas. The SiC epitaxy layer 12 formed by the series of steps S1 to S7 can be evaluated by electron backscatter diffraction (EBSD) or the like.

[0055] 16 is a cross-sectional view of a SiC composite substrate 3. The SiC composite substrate 3 includes a SiC polycrystalline substrate 13 formed by SiC chemical vapor deposition (CVD) and a SiC epitaxy layer 12 bonded to a top surface 13a of the SiC polycrystalline substrate 13. The SiC epitaxy layer 12 is formed by peeling off the SiC epitaxy layer 12 from the SiC composite 2 and bonding it to the SiC polycrystalline substrate 13. Such a SiC composite 2 can be used to fabricate an electronic device using the SiC epitaxy layer 12 as an active layer.

[0056] 17A and 17B are process diagrams for manufacturing a SiC composite substrate 3. As shown in FIG. 17A , a nickel (Ni) layer 15 is deposited on the SiC epitaxy layer 12 of the SiC composite 2, and a thermal peeling tape 16 is attached to the nickel layer 15 as a handling layer. As shown in FIG. 17B , the stress exerted by the nickel layer 15 causes the SiC epitaxy layer 12 to peel off from the graphene layer 11. The peeled area of ​​the SiC epitaxy layer 12 can be evaluated by optical observation. The peeled SiC epitaxy layer 12 is supported by the thermal peeling tape 16 as a handling layer so as to face and contact the top surface 13 a of the SiC polycrystalline substrate 13, and the substrates are bonded by an appropriate method, such as room-temperature bonding.

[0057] 18 is a cross-sectional view of a Schottky barrier diode (SBD) 20. The SBD 20 is fabricated using the SiC composite substrate 3 shown in FIG. 16. In the SBD 20, a SiC epitaxy layer 12 is stacked on a SiC polycrystalline substrate 13 of the SiC composite substrate 3. The SiC polycrystalline substrate 13 is an n ＋ The SiC epitaxy layer 12 is heavily doped to form a substrate layer. － The SiC polycrystalline substrate 13 is lightly doped to form a drift layer. The bottom surface of the SiC polycrystalline substrate 13 is covered with a cathode electrode 21, which is connected to a cathode terminal K.

[0058] The top surface 12a of the SiC epitaxy layer 12 is provided with a contact hole 23 that exposes a part of the SiC epitaxy layer 12 as an active region 22. A field insulating film 25 is formed in a field region 24 surrounding the active region 22. The field insulating film 25 is made of SiO ２ The field insulating film 25 is made of silicon oxide, but may be made of other insulating materials such as silicon nitride (SiN). An anode electrode 26 is formed on the field insulating film 25 and is connected to an anode terminal A.

[0059] A p-type junction termination extension (JTE) structure 27 is formed in the vicinity of the surface 12a (surface layer portion) of the SiC epitaxy layer 12 so as to be in contact with the anode electrode 26. The JTE structure 27 is formed along the contour of the contact hole 23 in the field insulating film 25 so as to straddle the inside and outside of the contact hole 23.

[0060] 19 is a cross-sectional view of a trench-structure MOSFET (TMOSFET) 30. The TMOSFET 30 is fabricated using the SiC composite substrate 3 shown in FIG. 16. In the TMOSFET 30, a SiC epitaxy layer 12 is stacked on a SiC polycrystalline substrate 13 of the SiC composite substrate 3. The SiC polycrystalline substrate 13 is an n-type ＋ The SiC epitaxy layer 12 is heavily doped to form a substrate layer. － The bottom surface of the SiC polycrystalline substrate 13 is covered with a drain electrode 31, which is connected to a drain terminal D.

[0061] A p-type body region 32 is formed on the top surface 12a of the SiC epitaxy layer 12. In the SiC epitaxy layer 12, the portion on the SiC polycrystalline substrate 13 side with respect to the body region 32 is lightly doped n-type p ... - The SiC epitaxy layer 12 has a gate trench 34 formed therein. The gate trench 34 penetrates the body region 32 from the top surface 12a of the SiC epitaxy layer 12, and its deepest portion reaches the drain region 33(12).

[0062] A gate insulating film 35 is formed on the inner surface of the gate trench 34 and on the top surface 12a of the SiC epitaxy layer 12 so as to cover the entire inner surface of the gate trench 34. The inside of the gate insulating film 35 is filled with, for example, polysilicon, thereby embedding a gate electrode 36 in the gate trench 34. A gate terminal G is connected to the gate electrode 36.

[0063] The surface layer of the body region 32 is formed with a highly doped n-type impurity dopant (nPt) that forms part of the side surface of the gate trench 34. + The SiC epitaxy layer 12 has a highly doped p-type source region 37 formed therein. The p-type source region 37 extends from the top surface 12 a of the SiC epitaxy layer 12 through the source region 37 and is connected to the body region 32. + A mold body contact region 38 is formed.

[0064] An interlayer insulating film 41 made of SiO is formed on the SiC epitaxy layer 12. A source electrode 43 is connected to the source region 37 and the body contact region 38 via a contact hole 42 formed in the interlayer insulating film 41. A source terminal S is connected to the source electrode 43.

[0065] By applying a predetermined voltage (a voltage equal to or greater than the gate threshold voltage) to the gate electrode 36 while a predetermined potential difference is generated between the source electrode 43 and the drain electrode 31 (between the source and drain), a channel can be formed in the body region 32 near the interface with the gate insulating film 35 due to the electric field from the gate electrode 36. This allows a current to flow between the source electrode 43 and the drain electrode 31, turning the TMOSFET 30 on.

[0066] In the third embodiment, one graphene layer 11 is formed, and the surface roughness Ra of the graphene layer 11 is 0.5 nm. Ｄ／Ｇ In the first embodiment, the surface roughness was 0.93 nm, and I Ｄ／Ｇ In comparison with the fact that the value of the step bunching coefficient was 0.15, it was clear that the step bunching was suppressed more than in the first embodiment, and the number of defects in the graphene was further reduced.

[0067] According to the third embodiment, it is possible to suppress the occurrence of step bunching and to grow graphene with few defects with good controllability of the number of layers. As a result, it is possible to achieve both control of the number of layers and reduction of defects, as well as suppression of surface roughness, and it is possible to improve the mobility of graphene and suppress anisotropy. Furthermore, since it is possible to grow graphene with few defects with good controllability of the number of layers on SiC with suppressed step bunching and reduced surface roughness, it is possible to obtain improvements in the crystallinity and exfoliation yield of the SiC epitaxy layer 12 formed on the graphene layer 11.

[0068] In the third embodiment, it is possible to fabricate a SiC composite substrate 3 by forming a single graphene layer 11, forming a SiC epitaxy layer 12 on the top surface 10a of a SiC single crystal substrate 10 via the graphene layer 11, and then peeling off the SiC epitaxy layer 12 and bonding it to a SiC polycrystalline substrate 13. Furthermore, it is possible to fabricate a Schottky barrier diode 20 and a trench MOSFET 30 using the SiC composite substrate 3.

[0069] Although the present disclosure has been described in detail above, it will be apparent to those skilled in the art that the present disclosure is not limited to the embodiments described herein. One or more elements of one embodiment can be combined with one or more elements of another embodiment. The present disclosure can be implemented in modified and altered forms without departing from the spirit and scope of the present disclosure, as defined by the claims. Therefore, the description of the present disclosure is intended to be illustrative and explanatory, and is not intended to be limiting of the present disclosure.

[0070] (Supplementary Note 1) The SiC composite 1 includes a SiC single crystal substrate 10 having a diameter of 150 mm or more and a graphene layer 11 formed by pyrolysis on a top surface 10a of the SiC single crystal substrate 10, and the graphene layer 11 has a surface roughness Ra of 1.2 nm or less. The surface roughness Ra, which is an index of step bunching, is kept small.

[0071] (Supplementary Note 2) In the SiC composite 1 described in Supplementary Note 1, defects in the graphene layer 11 are detected by the Raman spectrum intensity ratio I Ｄ／ＧThe I, which is an index of defects in graphene, is 0.2 or less. Ｄ／Ｇ is kept small.

[0072] (Supplementary Note 3) In the SiC composite 1 described in Supplementary Note 1 or 2, the SiC single crystal substrate 10 is a hexagonal 4H or 6H crystal, or a cubic 3C crystal. It is not limited to 4H, and can also be applied to other crystal polytypes such as 6H and 3C.

[0073] (Supplementary Note 4) In the SiC composite 1 according to any one of Supplementary Notes 1 to 3, the off-angle of the top surface 10a is in the range of 0.5° to 10°. The off-angle can be selected from the range of 0.5° to 10°. The off-angle may be in the range of 0° to 10°, or in the range of 0° to 0.5°.

[0074] (Supplementary Note 5) In the SiC composite according to any one of Supplementary Notes 1 to 4, graphene layer 11 includes 0 to 2 graphene layers. The number of graphene layers 11 can be selected depending on the purpose, such as when exfoliating graphene layer 11 or when growing a remote epitaxy layer on graphene layer 11.

[0075] (Appendix 6) A method for producing a SiC composite 1 for forming a graphene layer 11 on the surface of a SiC single crystal substrate 10 by pyrolysis includes a first step of forming graphene in an atmosphere having a pressure and temperature that makes it difficult for step bunching to occur, and a second step of forming graphene on the surface of the graphene formed in the first step in an atmosphere having a pressure and temperature that makes it easy to form graphene with few defects and with good control over the number of layers, the pressure and temperature of the atmosphere in the second step being higher than the pressure and temperature of the atmosphere in the first step. By forming graphene under conditions that make it difficult for step bunching to occur in the first step and forming graphene under conditions that make it easy to control the number of layers and with few defects in the second step, it is possible to achieve both good control over the number of layers and a reduction in defects, and suppression of surface roughness.

[0076] (Supplementary Note 7) In the method for producing a SiC composite according to Supplementary Note 6, the pressure of the atmosphere in the second step is 10 times higher than the pressure of the atmosphere in the first step. ２ more than 10 times１１ The pressure can be varied from atmospheric pressure to ultra-high vacuum, which is effective in controlling graphene growth.

[0077] (Supplementary Note 8) In the first and second steps of the method for producing a SiC composite according to Supplementary Note 6 or 7, the atmosphere contains at least one of an inert gas and nitrogen gas. The inert gas and nitrogen gas can be used to control the pressure.

[0078] (Supplementary Note 9) In the method for producing a SiC composite according to any one of Supplementary Notes 6 to 8, the atmosphere temperature in the first step and the second step is in the range of 1000° C. to 2000° C. In this temperature range, graphene can be formed by pyrolysis.

[0079] (Supplementary Note 10) The first step and the second step in the method for producing a SiC composite according to any one of Supplementary Notes 6 to 9 have different times. The growth of graphene can be controlled by the times of the first step and the second step.

[0080] (Supplementary Note 11) At least one of the first step and the second step in the method for producing a SiC composite according to any one of Supplementary Notes 6 to 10 includes a plurality of steps in which at least one of the atmospheric pressure and the atmospheric temperature is different. The plurality of steps makes it easier to suppress the growth of graphene.

[0081] (Supplementary Note 12) In the method for producing a SiC composite according to Supplementary Note 11, the pressure of the atmosphere in each of the steps is higher than or equal to the pressure in the immediately preceding step. By gradually increasing the pressure, it becomes easier to control the growth of graphene.

[0082] (Supplementary Note 13) In the method for producing a SiC composite according to Supplementary Note 12, the pressure higher than the pressure in the immediately preceding step in the plurality of steps is 10 times higher than the pressure in the immediately preceding step. ２ More than double 10 １１ The pressure can be varied from atmospheric pressure to ultra-high vacuum, which is effective in controlling graphene growth.

[0083] (Supplementary Note 14) In the method for producing a SiC composite according to Supplementary Note 12 or 13, the pressure of the atmosphere in the plurality of steps is lowest in the first step. By making the pressure lowest in the first step, pressure control becomes easier.

[0084] (Supplementary Note 15) In the method for producing a SiC composite according to any one of Supplementary Notes 11 to 14, the temperature in each of the steps is higher than or equal to the temperature in the immediately preceding step. By gradually increasing the temperature, it becomes easier to control the growth of graphene.

[0085] (Supplementary Note 16) In the method for producing a SiC composite according to Supplementary Note 15, the temperature of the atmosphere in the plurality of steps is the lowest in the first step. By making the temperature the lowest in the first step, pressure control becomes easier.

[0086] (Supplementary Note 17) In the method for producing a SiC composite according to any one of Supplementary Notes 11 to 16, at least some of the steps have different times from one another. By making the times different from one another, it is possible to control the growth of graphene.

[0087] (Supplementary Note 18) In the method for producing a SiC composite according to any one of Supplementary Notes 11 to 17, the first step and the second step include a total of 3 to 8 steps. Such a plurality of steps makes it possible to easily control the growth of graphene.

[0088] (Supplementary Note 19) A SiC laminate includes the SiC composite according to any one of Supplementary Notes 1 to 5, and includes a SiC epitaxy layer 12 remotely epitaxially grown on the surface of a SiC single crystal substrate via graphene of the SiC composite. The graphene layer 11 of the SiC composite 1 has few defects and good layer number controllability, so that the crystallinity and exfoliation yield of the SiC epitaxy layer 12 can be improved.

[0089] (Supplementary Note 20) A SiC semiconductor device includes a SiC epitaxy layer 12 included in the SiC stack described in Supplementary Note 19, and a SiC polycrystalline substrate 13 stacked on the SiC epitaxy layer 12, and the SiC epitaxy layer 12 serves as an active layer. A SiC semiconductor device having the SiC epitaxy layer 12 as an active layer can be controlled.

[0090] (Supplementary Note 21) The SiC semiconductor device according to Supplementary Note 20 includes at least one of a Schottky barrier diode and a trench FET. The SiC semiconductor device can be provided as a Schottky barrier diode and a trench FET.

[0091] REFERENCE SIGNS LIST 1, 2 SiC composite 3 SiC composite substrate 10 SiC single crystal substrate 11 Graphene layer 12 SiC epitaxy layer 13 SiC polycrystalline substrate 20 Schottky barrier diode 30 Trench structure MOSFET

Claims

1. An SiC composite including an SiC single crystal substrate with a diameter of 150 mm or more and a graphene layer formed on the top surface of the SiC single crystal substrate by a thermal decomposition method, wherein the graphene layer has a surface roughness Ra of 1.2 nm or less.

2. The defect of the graphene layer is 0.2 or less in the intensity ratio I of the Raman spectrum. Ｄ／Ｇ The SiC composite according to claim 1.

3. The SiC composite according to claim 1 or 2, wherein the SiC single crystal substrate is hexagonal 4H or 6H or cubic 3C.

4. The SiC composite according to any one of claims 1 to 3, wherein the off-angle of the top surface is in the range of 0.5° or more and 10° or less.

5. The SiC composite according to any one of claims 1 to 4, wherein the graphene layer includes 0 or more and 2 or less layers of graphene.

6. A method for manufacturing an SiC composite in which a graphene layer is formed on the surface of an SiC single crystal substrate by thermal decomposition, the method including: a first step of forming graphene in an atmosphere having a pressure and temperature at which step bunching is unlikely to occur; and a second step of forming graphene on the surface of the graphene formed in the first step in an atmosphere having a pressure and temperature at which graphene with few defects is formed with good layer number controllability, wherein the pressure and temperature of the atmosphere in the second step are higher than the pressure and temperature of the atmosphere in the first step, respectively.

7. The pressure of the atmosphere in the second step is 10 times or more and 10 times or less higher than the pressure of the atmosphere in the first step. The method for manufacturing an SiC composite according to claim 6. ２ times or more and １１ times or less.

8. The method for manufacturing an SiC composite according to claim 6 or 7, wherein in the first step and the second step, the atmosphere includes at least one of an inert gas and a nitrogen gas.

9. The method for manufacturing an SiC composite according to any one of claims 6 to 8, wherein the temperature of the atmosphere in the first step and the second step is in the range of 1000°C or more and 2000°C or less.

10. The method for manufacturing an SiC composite according to any one of claims 6 to 9, wherein the first step and the second step have different times.

11. The method for manufacturing an SiC composite according to any one of claims 6 to 10, wherein at least one of the first step and the second step includes a plurality of steps in which at least one of the pressure and temperature of the atmosphere is different.

12. The method for manufacturing an SiC composite according to claim 11, wherein the pressure of the atmosphere in the plurality of steps is higher than or the same as the pressure of the immediately preceding step.

13. In the plurality of steps, the pressure higher than the pressure of the immediately preceding step is 10 ２ times or more and 10 １１ times or less higher than that of the immediately preceding step. The method for manufacturing an SiC composite according to claim 12.

14. The method for manufacturing an SiC composite according to claim 12 or 13, wherein the pressure of the atmosphere in the plurality of steps is the lowest in the first step.

15. The manufacturing method of the SiC composite according to any one of claims 11 to 14, wherein the temperature in the plurality of steps is higher than or the same as the temperature of the immediately preceding step.

16. The manufacturing method of the SiC composite according to claim 15, wherein the temperature of the atmosphere in the plurality of steps is the lowest in the first step.

17. The manufacturing method of the SiC composite according to any one of claims 11 to 16, wherein at least a part of the plurality of steps has different times from each other.

18. The manufacturing method of the SiC composite according to any one of claims 11 to 17, wherein the total number of steps included in the first step and the second step is in the range of 3 to 8.

19. An SiC laminate including the SiC composite according to any one of claims 1 to 5, and an epitaxial layer formed by remote epitaxial growth on the surface of the SiC single crystal substrate through graphene of the SiC composite.

20. An SiC semiconductor device including an epitaxial layer included in the SiC laminate according to claim 19, and an SiC polycrystalline substrate laminated on the epitaxial layer, wherein the epitaxial layer is an active layer.

21. The SiC semiconductor device according to claim 20, wherein the SiC semiconductor device includes at least one of a Schottky barrier diode and a trench structure FET.

Images