Electronic device and method for digital pre-distortion

Abstract

According to an embodiment, a method performed by an electronic device may comprise a step of obtaining a specified number of samples on the basis of an input signal related to a power amplifier (PA) and an output signal related to the PA. The method may comprise a step of identifying first gain information about the input signal with respect to the output signal. The method may comprise a step of performing, for each of power levels of the output signal, a first process for averaging at least some of gain values within a specified power range among the first gain information. The method may comprise a step of performing, for each of the power levels, a second process for estimating gain values outside the specified power range among the first gain information. The method may comprise a step of changing configuration information about a digital pre-distortion (DPD) circuit of the electronic device on the basis of second gain information about the input signal with respect to the output signal.

Description

Electronic device and method for digital dictionary distortion

[0001] The present disclosure relates to a wireless communication system. More specifically, the present disclosure relates to an electronic device and method for digital predistortion (DPD) in a wireless communication system.

[0002] In wireless communication systems, digitally modulated signals are amplified by a radio frequency (RF) power amplifier. To transmit the signal without distortion, the power amplifier requires high linearity. To achieve this, digital predistortion (DPD) is used to modify the input signal so that the power amplifier output approximates the ideal state.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] According to one embodiment, an electronic device may include at least one processor including a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, processing circuitry, and one or more storage media, and may include a memory storing instructions. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to acquire a specified number of samples based on an input signal relating to the PA and an output signal relating to the PA. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify first gain information of the input signal with respect to the output signal based on the specified number of samples. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform, for each of the power levels of the output signal, a first process for averaging at least some of the gain values ​​within a power range specified among the first gain information. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform, for each of the power levels, a second process for estimating gain values ​​outside the power range specified among the first gain information.The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to obtain second gain information of the input signal for the output signal based on the first process and the second process. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to change configuration information of the DPD circuit based on the second gain information.

[0005] According to one embodiment, a method performed in an electronic device may include acquiring a specified number of samples based on an input signal regarding a power amplifier (PA) of the electronic device and an output signal regarding the PA. The method may include identifying first gain information of the input signal for the output signal based on the specified number of samples. The method may include performing a first process for averaging at least some of gain values ​​within a specified power range among the first gain information for each of the power levels of the output signal. The method may include performing a second process for estimating gain values ​​outside the specified power range among the first gain information for each of the power levels. The method may include acquiring second gain information of the input signal for the output signal based on the first process and the second process. The method may include changing configuration information of a digital pre-distortion (DPD) circuit of the electronic device based on the second gain information.

[0006] According to one embodiment, an electronic device may include a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, and at least one processor. The at least one processor may be configured to acquire a specified number of samples based on an input signal for the PA and an output signal for the PA. The at least one processor may be configured to identify first gain information of the input signal for the output signal based on the specified number of samples. The at least one processor may be configured to perform a first process for averaging at least some of gain values ​​within a specified power range among the first gain information for each of the power levels of the input signal. The at least one processor may be configured to perform a second process for estimating gain values ​​outside the specified power range among the first gain information for each of the power levels. The at least one processor may be configured to obtain second gain information of the input signal for the output signal based on the first process and the second process. The at least one processor may be configured to change the setting information of the DPD circuit according to the second gain information.

[0007] According to one embodiment, a non-transitory storage medium may store one or more programs. The one or more programs may include instructions that, when executed by a processor of an electronic device, the electronic device includes a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, and an analog-to-digital converter (ADC) coupled to the PA, cause the electronic device to acquire a specified number of samples based on an input signal relating to the PA and an output signal relating to the PA. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to identify first gain information of the input signal for the output signal based on the specified number of samples. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to perform, for each of the power levels of the input signal, a first process for averaging at least some of the gain values ​​within a designated power range among the first gain information. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to perform, for each of the power levels, a second process for estimating gain values ​​outside the designated power range among the first gain information. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to obtain, based on the first process and the second process, second gain information of the input signal for the output signal.The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to change setting information of the DPD circuit according to the second gain information.

[0008] Figure 1 illustrates a wireless communication system.

[0009] Figure 2 is a diagram for explaining the principle of DPD (digital predistortion).

[0010] Figure 3 illustrates an example of a transmitter circuit including a DPD circuit.

[0011] Figure 4a shows an example of a GSM signal acquired through a capture block.

[0012] Figure 4b shows an example of the power range of a GSM signal acquired through a capture block.

[0013] FIG. 5 illustrates an example of a transmitter circuit including a DPD circuit for performing DPD modeling for a signal having a narrow bandwidth.

[0014] Figure 6 is a flowchart regarding the operation of an electronic device for changing setting information of a DPD circuit.

[0015] Figure 7 shows examples of graphs of samples obtained based on input signals and output signals.

[0016] FIG. 8 is a flowchart illustrating the operation of an electronic device for identifying a gain value corresponding to each of a plurality of power levels.

[0017] Figure 9a is a flowchart regarding the operation of an electronic device for performing the first process.

[0018] Figure 9b shows the change in gain values ​​within a specified power range according to the first process.

[0019] Figure 10a is a flowchart regarding the operation of an electronic device for performing a second process.

[0020] Figure 10b shows the change in gain values ​​outside the specified power range according to the second process.

[0021] Figure 11a illustrates the change in gain as the first gain information is changed to the second gain information.

[0022] Figure 11b illustrates the change in phase as the first gain information is changed to the second gain information.

[0023] Figure 12 shows the change in PA output when the setting information of the DPD circuit is changed according to the second gain information.

[0024] Figure 13 illustrates the functional configuration of an electronic device including a transmitter circuit.

[0025] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0026] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0027] In the following description, terms referring to signals (e.g., signal, signal flow, composite signal, digital signal, analog signal, modulated signal, distorted signal), terms referring to resources (e.g., time, symbol, slot, subframe, radio frame, subcarrier, resource element (RE), resource block (RB), bandwidth part (BWP), occasion), terms for operational states (e.g., step, operation, procedure), terms referring to data (e.g., packet, user stream, information, bit, symbol, codeword), terms referring to channels, terms referring to network entities, terms referring to components of devices, etc. are examples for convenience of description. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used.

[0028] In the following description, terms referring to parts of electronic devices (e.g., module, antenna, antenna element, circuit, processor, chip, component, device), terms referring to circuits (e.g., composite circuit, coupling circuit, separation circuit, distribution circuit, PIMC circuit, harmonic cancellation circuit), terms referring to the shape of parts (e.g., structure, construction, support, contact, protrusion), terms referring to circuits (e.g., PCB, FPCB, signal line, feeding line, data line, RF signal line, antenna line, RF path, RF module, RF circuit, splitter, divider, coupler, combiner), etc. are examples for convenience of description. Therefore, the present disclosure is not limited to the terms described below, and other terms having equivalent technical meanings may be used. In addition, terms such as '... part', '... device', '... thing', '... body' used below may mean at least one shape structure or a unit that processes a function.

[0029] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled. However, this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." Conditions described as "more than" may be replaced with "more than," conditions described as "less than," and conditions described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of the elements from A (including A) to B (including B).

[0030] Although the present disclosure describes various embodiments using terms used in some communication standards (e.g., 3rd Generation Partnership Project (3GPP), extensible radio access network (xRAN), open-radio access network (O-RAN), etc.), these are merely examples for explanation. The various embodiments of the present disclosure can be easily modified and applied to other communication systems.

[0031] Figure 1 illustrates a wireless communication system.

[0032] Referring to FIG. 1, FIG. 1 illustrates a base station (110) and a terminal (120) as some of the nodes utilizing a wireless channel in a wireless communication system. Although FIG. 1 illustrates only one base station, the wireless communication system may further include other base stations identical or similar to the base station (110).

[0033] The base station (110) is a network infrastructure that provides wireless access to the terminal (120). The base station (110) has coverage defined based on the distance at which a signal can be transmitted. In addition to the base station, the base station (110) may be referred to as an 'access point (AP)', 'eNodeB (eNB)', '5th generation node', 'next generation nodeB (gNB)', 'wireless point', 'transmission / reception point (TRP)', or other terms having equivalent technical meanings.

[0034] The terminal (120) is a device used by a user and communicates with the base station (110) via a wireless channel. The link from the base station (110) to the terminal (120) is referred to as a downlink (DL), and the link from the terminal (120) to the base station (110) is referred to as an uplink (UL). In addition, although not shown in FIG. 1, the terminal (120) and another terminal may communicate with each other via a wireless channel. In this case, the link between the terminal (120) and another terminal (device-to-device link, D2D) is referred to as a sidelink, and the sidelink may be used interchangeably with the PC5 interface. In some other embodiments, the terminal (120) may be operated without the involvement of a user. In one embodiment, the terminal (120) is a device that performs machine type communication (MTC) and may not be carried by the user. Additionally, according to one embodiment, the terminal (120) may be an NB (narrowband)-IoT (internet of things) device.

[0035] The terminal (120) may be referred to as a terminal, or other terms such as 'user equipment (UE),' 'customer premises equipment (CPE),' 'mobile station,' 'subscriber station,' 'remote terminal,' 'wireless terminal,' 'electronic device,' or 'user device,' or other terms having equivalent technical meanings.

[0036] According to one embodiment, a base station (110) may emit a signal having a high power to transmit a wireless signal. The base station (110) may include a power amplifier (PA) for amplifying the power of the signal. The PA may be used to amplify the power of an input signal. However, as the power of the input signal of the power amplifier (PA) increases, the response of the power amplifier may exhibit non-linearity. Ultimately, the response of the power amplifier may eventually reach a saturation point. This non-linearity may induce distortion in the transmitted signal and cause a degradation in link quality. Therefore, linearity of the power amplifier is required. Generally, to achieve linearity, the power amplifier is required to have an input within a limited power range. Digital pre-distortion may be used to increase the power range of the input signal for linearity.

[0037] Figure 2 is a diagram illustrating the principles of digital predistortion (DPD). Predistortion can be performed in the DPD circuit. The DPD circuit can compensate for distortion components resulting from the nonlinear characteristics of the PA based on a comparison of the PA's input and output signals. As the distorted input modulation signal passes through the DPD circuit and is input to the PA, the final modulated signal can be linearly amplified.

[0038] Referring to FIG. 2, the DPD circuit (210) can output a DPD output signal (215) based on an input signal (205). The input signal (205) can be pre-distorted into a DPD output signal (215) through the DPD circuit (210). The PA (220) can output an amplifier output signal (225) based on the DPD output signal (215). The DPD output signal (215) can be input to the PA (220). Depending on the nonlinear characteristics of the PA (220), the DPD output signal (215) is distorted. Due to the distortion caused by the PA (220), the amplifier output signal (225) is output. Although not shown in FIG. 2, analog conversion may be performed on the DPD output signal (215) through a DAC, and up-conversion may be performed on the DPD output signal (215) through a mixer.

[0039] Graph (251) represents the relationship between the magnitude of the input signal (205) and the magnitude of the DPD output signal (215). Graph (253) represents the relationship between the magnitude of the DPD output signal (215) and the magnitude of the amplifier output signal (225). Graph (255) represents the relationship between the magnitude of the input signal (205) and the magnitude of the amplifier output signal (225). Referring to graph (255), through pre-distortion of the DPD circuit (210), the input (e.g., input signal (205)) to the output (e.g., amplifier output signal (225)) can be linear.

[0040] The PA (220) may include a transistor. The transistor generates harmonic components. A memory effect occurs due to the nonlinearity of the low-frequency second-harmonic components corresponding to the bandwidth (f2-f1) (f2 is the highest frequency, f1 is the lowest frequency). The larger the low-frequency second-harmonic components, the more difficult it is to remove the impedance. Therefore, the power amplifier exhibits the memory effect as the signal bandwidth increases. When the modulation signal of a wireless communication system is used as a wide bandwidth signal, the distortion components of the power amplifier may include distortion components due to the memory effect as well as the nonlinear characteristics. The memory effect means that a signal that was generated nonlinearly in the past affects the current nonlinearity. In other words, the power amplifier is a nonlinear system that utilizes memory.

[0041] The memory effect can be attributed to the thermal constants of active devices or components of a biasing network with frequency-dependent behavior. As previously mentioned, distortion components due to the memory effect increase in proportion to the signal bandwidth. To compensate for both the nonlinear distortion components of the power amplifier and the distortion components due to the memory effect, a memory-compensated DPD (DPD) circuit is required. Below, FIG. 3 illustrates a memory-compensated DPD circuit.

[0042] Figure 3 illustrates an example of a transmitter circuit including a DPD circuit. The DPD circuit according to the embodiments can compensate for the memory effect. The memory effect refers to the effect of a signal generated in the past on current nonlinearities.

[0043] Referring to FIG. 3, the DPD circuit (300) may utilize a finite impulse response (FIR) filter structure. To implement pre-distortion, a multi-order FIR filter may be utilized. The DPD circuit (300) may include components according to the structure of the FIR filter. The DPD circuit (300) may include a plurality of DPD units, one or more delay elements, and a combiner (330). The plurality of DPD units may include a first DPD unit (320-1), a second DPD unit (320-2), a third DPD unit (320-3), ..., an i-th DPD unit (320-i). In each DPD unit, a function operation (e.g., multiplication of coefficients) for a delayed signal may be performed. i may correspond to the length of the FIR filter. One or more delay elements may include a second delay element (310-2) connected to a second DPD unit (320-2), a third delay element (310-3) connected to a third DPD unit (320-3), a fourth delay element (310-4) connected to a fourth DPD unit (320-4), ..., a delay element coupled to an Nth DPD unit. The output of each DPD unit of the plurality of DPD units may be provided to a combiner (330).

[0044] A combiner (330) can combine the outputs of multiple DPD units to generate a DPD output signal (335). The DPD output signal (335) can be transmitted from the combiner (330) to a DAC (340). In one embodiment, the DPD output signal (335) can be provided to a calculation block (380). The calculation block (380) refers to a function performed by a processor.

[0045] The DAC (340) can convert the DPD output signal (335) into an analog signal. The DAC (340) can transmit the converted analog signal to the PA (350). Although not shown in FIG. 3, up-conversion by a mixer can be performed between the DAC (340) and the PA (350).

[0046] PA (350) can amplify the input signal. The signal (395) amplified by the PA (350) may pass through the coupler (360) and be transmitted to a filter (not shown) (e.g., a bandpass filter (BPF)) and an antenna (not shown). The antenna may radiate a signal. Meanwhile, the PA (350) may include a transistor. The transistor is an active element and has inherently nonlinear characteristics. Therefore, the PA (350) may output an amplifier output signal that is nonlinear with respect to the input signal. The amplifier output signal is linearly proportional to the input signal in some areas relative to the magnitude of the input signal. However, in some other areas relative to the magnitude of the input signal, the PA (350) provides an output that is not proportional to the input signal. In particular, the wider the bandwidth of the input signal of the PA (350), the more frequently the memory effect occurs due to the second harmonic component of the input signal. The harmonic impedance of the output terminal of the PA (350) may generate a voltage component. The voltage component may be generated by a bias line. The signal may be reflected and re-input to the PA (350). Therefore, a memory effect may occur through the interaction between the current input signal and the re-input signal. To reduce performance delay due to this memory effect, a DPD circuit (300) and a calculation block (380) for controlling the DPD circuit (300) may be utilized.

[0047] The calculation block (380) may include a capture block (381) and a DPD circuit control block (382).

[0048] The capture block (381) can be used to acquire (or capture) the input signal (305), the DPD output signal (335), and the ADC output signal (375). For example, the input signal (305) can be a source signal before being input to the DPD circuit (300). The input signal (305) can be referred to as a DPD input. For example, the DPD output signal (335) can be a signal output from the DPD circuit (300). The DPD output signal (335) can be a signal in which the input signal (305) is distorted according to the DPD. The ADC output signal (375) can be a signal in which the output signal of the PA (350) is converted by the ADC (370).

[0049] For example, the capture block (381) can acquire (or collect, capture) a certain number (e.g., 8192) of data samples for DPD modeling using at least one of the input signal (305), the DPD output signal (335), and the ADC output signal (375). The number of acquired data samples can be fixed.

[0050] The DPD circuit control block (382) can control the DPD circuit (300). For example, the DPD circuit control block (382) can control the DPD circuit (300) to distort the nonlinear characteristics of the PA (350) in advance. Operations corresponding to the DPD circuit control block (382) (or the calculation block (380)) can be performed by the processor. That is, the processor of the electronic device can generate a control signal for controlling the DPD circuit (300).

[0051] According to one embodiment, a processor performing operations corresponding to the calculation block (380) may determine how much to compensate for the nonlinear characteristics of the PA (350) through the DPD circuit (300) based on the bandwidth of the input signal. As the complexity of the DPD circuit (300) increases, the degree of compensation for the nonlinear characteristics of the PA (350) increases. The complexity of the DPD circuit (300) depends on the number of activated DPD units. The number of activated DPD units may be referred to as the memory order.

[0052] According to one embodiment, a processor performing operations corresponding to the calculation block (380) may determine control parameters for pre-distorting the nonlinear characteristics of the PA (350) by comparing an input signal of the PA (350) (e.g., the DPD output signal (335)) with an output signal of the PA (350) (e.g., the ADC output signal (375)). Determining the control parameters may be referred to as DPD modeling. For example, the DPD modeling may be performed by modeling the inverse function of the PA (350) using data samples acquired through the capture block (380). The DPD modeling may be substantially equivalent to modeling a system in which the output signal of the PA (350) (e.g., the ADC output signal (375)) is set as an input and the input signal of the PA (350) (e.g., the DPD output signal (335)) is set as an output.

[0053] For example, a processor performing operations corresponding to a calculation block (380) may obtain an input signal (e.g., a DPD output signal (335)) to a DAC (340). The input signal to the DAC (340) may correspond to an input signal of a PA (350). The processor of the calculation block (380) may obtain an output signal of an ADC (370). The output signal of the ADC (370) (or the ADC output signal (375)) may correspond to an output signal of the PA (350). A signal (365) isolated through a coupler (360) coupled to the PA (350) may pass through the ADC (370) and be transmitted to the calculation block (380).

[0054] The results of DPD modeling can be stored in the form of a look-up table (LUT) with a depth of a size specified in the DPD circuit (300). The DPD modeling operation can be repeatedly performed to ensure DPD performance and respond to various environments (e.g., temperature, input signal characteristics).

[0055] According to one embodiment, the DPD circuit (300) may be configured based on the long term evolution (LTE) standard and / or the new radio (NR) standard. For example, the bandwidth of a wireless signal according to the LTE standard and / or the NR standard may be set from 5 MHz to 20 MHz or more. Accordingly, the calculation block (380) and / or the DPD circuit (300) may be configured to support signals with a bandwidth from 5 MHz to 20 MHz or more.

[0056] The calculation block (380) may not be able to identify the characteristics of the PA (350) if the bandwidth of the signal is small compared to the sample rate. For example, even if a certain number of data samples (e.g., 8192) are acquired from the capture block (382), DPD modeling may not be performed using the calculation block (380). For example, a signal in the GSM (global system for mobile communications) band (e.g., 850 MHz band, 900 MHz band, or 1800 MHz band) may have a bandwidth of 0.2 MHz. The bandwidth of a signal in the GSM band is narrower than the bandwidth of a signal in the LTE standard or NR standard. Therefore, DPD modeling may not be performed smoothly for a signal in the GSM band.

[0057] In the following Figures 4a and 4b, examples of signals (or data samples) acquired from the capture block (381) for signals in the GSM band will be described. Hereinafter, signals in the GSM band may be referred to as GSM signals.

[0058] Figure 4a shows an example of a GSM signal acquired through a capture block.

[0059] Figure 4b shows an example of the power range of a GSM signal acquired through a capture block.

[0060] Referring to FIG. 4A, signal (401) represents a GSM signal acquired (or captured) in the capture block (381) during one sampling interval. Signal (402) represents a GSM signal acquired (or captured) in the capture block (381) according to a plurality of sampling intervals.

[0061] For example, if the capture block (381) acquires a GSM signal in multiple sampling intervals, a signal (402) similar to the GSM signal can be acquired. However, if the capture block (381) acquires a GSM signal during one sampling interval, a signal (401) that is part of the GSM signal can be acquired. During one sampling interval, only the GSM signal of the time interval (410) among the time intervals (420) can be acquired through the capture block (381).

[0062] Referring to FIG. 4B, a graph (431) represents the magnitude (or power) of an output signal (e.g., signal (401) of FIG. 4A) according to the magnitude (or power) of an input signal (e.g., GSM signal). The graph (431) may be constructed based on a signal captured during one sampling interval. The graph (432) represents the magnitude (or power) of an output signal (e.g., signal (402) of FIG. 4A) according to the magnitude (or power) of an input signal (e.g., GSM signal). The graph (432) may be constructed based on signals captured during multiple sampling intervals. For example, the output signal may mean a GSM signal acquired through the capture block (381).

[0063] According to graphs (431) and (432), when the capture block (381) acquires a GSM signal in multiple sampling intervals, a signal similar to a GSM signal can be acquired. However, when the capture block (381) acquires a GSM signal during one sampling interval, only a portion of the GSM signal can be acquired.

[0064] Referring to Figures 4a and 4b, if the bandwidth of a signal is smaller than the reference bandwidth, the characteristics of the PA for the signal may not be identified based on only the data samples acquired in a single sampling interval. Furthermore, since the characteristics of the signal vary across intervals, performance may not be consistent if the sampling intervals are set differently.

[0065] In the following specification, technical features for improving DPD performance for signals (e.g., GSM signals) having a narrow bandwidth (e.g., 0.2 MHz) will be described.

[0066] Fig. 5 illustrates an example of a transmitter circuit including a DPD circuit for performing DPD modeling on a signal having a narrow bandwidth. The transmitter circuit of Fig. 5 may utilize the transmitter circuit of Fig. 3. The calculation block (580) of Fig. 5 may include at least some components (or blocks) of the calculation block (380) of Fig. 3. In addition, terms such as '... part', '... device', '... object', '... body', '... block', etc. used below may mean at least one shape structure or a unit that processes a function. The transmitter circuit illustrated in Fig. 5 may be included in an electronic device.

[0067] Referring to FIG. 5, the DPD circuit (500) may utilize a finite impulse response (FIR) filter structure. The DPD circuit (500) may include a plurality of DPD units, one or more delay elements, one or more switches, and a coupler (e.g., the coupler (330) of FIG. 3). For example, the DPD circuit (500) may correspond to the DPD circuit (300) of FIG. 3.

[0068] A DPD input signal (501) may be input to a DPD circuit (500). The DPD circuit (500) may generate a DPD output signal (505) by combining outputs of a plurality of DPD units. The DPD circuit (500) may output the DPD output signal (505). The DPD output signal (505) may be transmitted to a DAC (540). According to an embodiment, the DPD input signal (501) and the DPD output signal (505) may be provided to a calculation block (580). The calculation block (580) may refer to a function performed by a processor of an electronic device including a transmission circuit. The operation of the calculation block (580) according to the following embodiments may be understood as the operation of the processor.

[0069] The DAC (540) can convert the DPD output signal (505) into an analog signal (545). The DAC (540) can transmit the analog signal (545) to the PA (550). Although not shown in FIG. 5, up-conversion by a mixer can be performed between the DAC (540) and the PA (550). The DAC (540) can correspond to the DAC (530) of FIG. 3.

[0070] An analog signal (545) can be input to a PA (550). The PA (550) can amplify the input analog signal (545). The PA (550) can convert the analog signal (545) into an amplified signal (555). The amplified signal (555) can pass through a coupler (560) and be transmitted to a filter (not shown) (e.g., a bandpass filter (BPF)) and an antenna (not shown). The antenna can radiate a signal. Meanwhile, the PA (550) can include a transistor. The PA (550) can correspond to the PA (350) of FIG. 3. The coupler (560) can correspond to the coupler (360) of FIG. 3.

[0071] An analog signal (565) isolated through a coupler (560) can be input to an ADC (570). The ADC (570) can convert the analog signal (565) into an ADC output signal (575). The ADC output signal (575) can be a digital signal. The ADC output signal (575) can be transmitted to a calculation block (580). The ADC output signal (575) can be referenced as a PA output signal. The ADC (570) can correspond to the ADC (370) of FIG. 3.

[0072] The calculation block (580) may include a capture block (581), a sample accumulation block (582), a smoothing and extrapolation block (583), and a DPD circuit control block (584).

[0073] The capture block (581) can be used to acquire (or capture) a DPD input signal (501), a DPD output signal (505), and an ADC output signal (575). For example, the DPD input signal (501) can be a source signal before being input to the DPD circuit (500). The DPD input signal (501) can be referred to as a DPD input. For example, the DPD output signal (505) can be a signal output from the DPD circuit (500). The DPD output signal (505) can be a signal in which the DPD input signal (501) is distorted according to DPD. The ADC output signal (575) can be a signal in which the output signal of the PA (550) is converted by the ADC (570).

[0074] The capture block (581) can acquire (or collect, capture) a specified number of data samples for DPD modeling by using at least one of the DPD input signal (501), the DPD output signal (505), and the ADC output signal (575).

[0075] The sample accumulation block (582) can accumulate samples obtained through multiple sampling intervals.

[0076] The smoothing and extrapolation block (583) can perform a first process to average at least some of the gain values ​​within a specified power range and / or a second process to estimate gain values ​​outside the specified power range.

[0077] The DPD circuit control block (584) can control the DPD circuit (500). For example, the DPD circuit control block (584) can control the DPD circuit (500) to pre-distort the nonlinear characteristics of the PA (550). The DPD circuit control block (584) can be referred to as a DPD adaptation block.

[0078] According to one embodiment, the operations corresponding to the calculation block (580) may be performed by the processor. For example, the processor of the electronic device may generate a control signal for controlling the DPD circuit (500). For example, the processor of the electronic device may acquire at least one sample using the capture block (581). In the following specification, for convenience of explanation, the operations (or operations) related to the calculation block (580) will be described as being performed by the processor of the electronic device.

[0079] According to one embodiment, in order to model the inverse function characteristic of the PA (550), the processor may obtain an output signal (e.g., an ADC output signal (575)) of the PA (550) and an input signal (e.g., a DPD output signal (505)) of the PA (550). The processor may set the output signal of the PA (550) as an input signal and set the input signal of the PA (550) as a target signal. The processor may construct a complex gain table using the input signal and the target signal. The complex gain table may be used for calculating a covariance matrix of the input signal and a cross-correlation between the input signal and the target signal, which are required for modeling the inverse function characteristic of the PA (550).

[0080] The processor can perform the first process and the second process to enable stable DPD modeling using the smoothing and extrapolation block (583). The specific operations of the first process and the second process will be described later.

[0081] Figure 6 is a flowchart illustrating the operation of an electronic device for changing the configuration information of a DPD circuit. The operations described below may be performed by a processor of the electronic device. The processor may perform operations 610 to 670 using the calculation block (580) of Figure 5.

[0082] Referring to FIG. 6, at operation 610, the processor may acquire a specified number of samples based on an input signal related to the PA and an output signal related to the PA. For example, the processor may perform a sampling process to acquire at least one sample within a sampling interval. The processor may repeatedly perform the sampling process until the specified number of samples are acquired.

[0083] For example, a processor may repeatedly perform a sampling process a specified number of times (e.g., 11 times). Based on the fact that the sampling process is repeatedly performed the specified number of times, the processor may identify that a specified number of samples have been acquired. If the sampling process is performed the specified number of times, the specified number of samples may be acquired. For example, the operation for acquiring a specified number of samples may be referred to as an accumulation process.

[0084] At operation 620, the processor can identify first gain information of the input signal for the output signal. For example, the processor can identify first gain information of the input signal for the output signal based on a specified number of samples.

[0085] For example, the processor can identify a reference power range of the output signal. The processor can identify a plurality of power levels corresponding to the reference power range of the output signal. For example, the number of the plurality of power levels can be set to 256. The plurality of power levels can be configured with integer values ​​greater than or equal to 0 and less than or equal to 255. In the present disclosure, an example in which the plurality of power levels are configured with integer values ​​greater than or equal to 0 and less than or equal to 255 is described, but this is for convenience of explanation and is not limited thereto. The number and range of the plurality of power levels can be set in various ways.

[0086] The first gain information may include a gain value for each of a plurality of power levels of the output signal. For example, the processor may identify at least one sampled gain value for each of the plurality of power levels of the output signal. The processor may identify an average value of the at least one sampled gain value as the gain value for each of the plurality of power levels. By identifying the gain value for each of the plurality of power levels, the processor may identify (or obtain) the first gain information. The operation of identifying the first gain information may be referred to as a normalization process.

[0087] For example, the gain value may be composed of a complex number. The gain value may be referred to as a complex gain value. An example of at least one sampled gain value for each of a plurality of power levels of the output signal will be described later in FIG. 7. A specific example of an operation for identifying the first gain information will be described later in FIG. 8.

[0088] In operation 630, the processor can identify whether the power level of the first gain information is within a specified power range. The processor can identify whether the power level of the first gain information is within a specified power range to perform one of the first process and the second process.

[0089] In operation 640, if the power level of the first gain information is within a specified power range, the processor may perform a first process for averaging at least some of the gain values ​​within the specified power range among the first gain information. For example, the processor may perform the first process for averaging at least some of the gain values ​​within the specified power range among the first gain information for each of the power levels of the output signal.

[0090] For example, the processor may perform the first process using the smoothing and extrapolation block (583) of FIG. 5. The first process may be referred to as a smoothing process. The specific operation of the first process will be described later with reference to FIGS. 9A and 9B.

[0091] In operation 650, if the power level of the first gain information is outside the specified power range, the processor may perform a second process for estimating gain values ​​outside the specified power range among the first gain information. For example, for each of the power levels of the output signal, the second process for estimating gain values ​​outside the specified power range among the first gain information may be performed. For example, the processor may estimate gain values ​​outside the specified power range among the first gain information using extrapolation.

[0092] For example, the processor may perform a second process using the smoothing and extrapolation block (583) of FIG. 5. The second process may be referred to as an extrapolation process. The specific operations of the second process will be described later with reference to FIGS. 10A and 10B.

[0093] At operation 660, the processor may obtain second gain information of the input signal for the output signal. For example, the processor may obtain second gain information of the input signal for the output signal based on the first process and the second process. For example, the second gain information may be obtained based on the first gain information being corrected according to the operations described above.

[0094] According to one embodiment, the gain values ​​for each of the plurality of power levels included in the first gain information may be configured discontinuously. As the first gain information is corrected with the second gain information, the gain values ​​for each of the plurality of power levels may be configured continuously.

[0095] At operation 670, the processor may change the configuration information of the DPD circuit. For example, the processor may change the configuration information of the DPD circuit according to the second gain information. The processor may change the configuration information of the DPD circuit by changing a control parameter related to the DPD circuit according to the second gain information. For example, the processor may change the configuration information of the DPD circuit by storing the second gain information in the DPD circuit. As an example, the second gain information may include a table composed of gain values ​​for each of a plurality of power levels. The processor may change the configuration information of the DPD circuit by storing the table in the DPD circuit. The table may be referenced as a look-up table (LUT).

[0096] Figure 7 shows examples of graphs of samples obtained based on input signals and output signals.

[0097] Referring to FIG. 7, the processor can obtain an input signal regarding the PA (e.g., the DPD output signal (505) of FIG. 5) and an output signal regarding the PA (e.g., the ADC output signal (575) of FIG. 5). Graph (701) represents an output signal regarding the PA. Graph (702) represents an input signal regarding the PA. Graphs (701) and (702) are shown to represent the magnitude of the signal over time for convenience of explanation, but this is for convenience of explanation, and graphs (701) and (702) may also represent the intensity of the signal over frequency.

[0098] For example, the processor may set the output signal for PA as the input signal of the estimation model to model the inverse function characteristic of PA. The processor may set the input signal for PA as the target signal to model the inverse function characteristic of PA.

[0099] The processor can obtain (or identify) first gain information of an input signal to the PA for an output signal of the PA. To obtain the first gain information, the processor can obtain samples. The processor can perform a sampling process to obtain at least one sample within one sampling interval (730).

[0100] For example, the processor may obtain at least one sample (710) based on an output signal. The processor may obtain at least one sample (720) based on an input signal. The processor may identify a gain value of at least one sample (720) for at least one sample (710). For example, a sample (711) of at least one sample (710) may correspond to a sample (721) of at least one sample (720). The processor may be configured such that the signal identified based on the sample (711) and the signal identified based on the sample (721) are as follows:

[0101]

[0102] Referring to mathematical expression 1, the PA output identified through one sample (e.g., sample (711)) may mean an output signal related to the PA (e.g., ADC output signal (575) of FIG. 5). a and b are constants. i is an imaginary number.

[0103]

[0104] Referring to mathematical expression 2, the DPD output identified through one sample (e.g., sample (721)) may mean an input signal for the PA (e.g., the DPD output signal (505) of FIG. 5). c and d are constants. i is an imaginary number.

[0105] According to one embodiment, the processor may identify the magnitude of power for each of the plurality of power levels based on at least one sample (710). The processor may construct a dot plot (703) representing the magnitude of power for each of the plurality of power levels.

[0106] For example, the processor can identify a plurality of power levels corresponding to a reference power range of an output signal for the PA. The processor can set the reference power range for the output signal for the PA. For example, the processor can set the maximum value of the plurality of power levels to 255. The processor can set the minimum value of the plurality of power levels to 0. For example, the processor can perform quantization on the magnitude of the power of the output signal for the PA to identify it as one of the power levels from 0 to 255. In FIG. 7, an example in which the plurality of power levels are set to 256 is illustrated, but the present invention is not limited thereto. The number of the plurality of power levels can be set in various ways. For example, power level 255 can correspond to power value (750). According to an embodiment, power level 255 can correspond to the maximum power value of the output signal for the PA.

[0107] For example, the power magnitude of the output signal for the PA according to the power level can be configured as in the following mathematical formula.

[0108]

[0109] In mathematical expression 3, n is a power level. n is set to one of the levels greater than or equal to 0 and less than or equal to N. N is a power level corresponding to the maximum power of the output signal for the PA. pwr[n] is the magnitude of the power of the output signal for the power level n. n is a power level at which the power value of the output signal for the PA is quantized into N steps. In FIG. 7, an example in which N is set to 255 is shown, but the present invention is not limited thereto. A dot plot (703) for at least one sample (710) can be constructed according to mathematical expression 3.

[0110] According to one embodiment, the processor may construct a dot plot (704) representing the number of each of the plurality of power levels identified using at least one sample (710).

[0111] According to one embodiment, the processor can construct a dot plot (705) and a dot plot (706) representing a gain of an input signal with respect to an output signal using at least one sample (710) and at least one sample (720). The dot plot (705) can represent real part gain values ​​of the input signal with respect to the output signal. The dot plot (706) can represent imaginary part gain values ​​of the input signal with respect to the output signal.

[0112] For example, the complex gain value of the input signal for the output signal can be configured as in the following mathematical formula.

[0113]

[0114] Referring to Equation 4, complex gain[n] is the complex gain value of the input signal with respect to the output signal. pwr is configured as in Equation 3.

[0115]

[0116]

[0117] Referring to Equations 5 and 6, complex gain[n](i) represents the real part gain values ​​of the input signal with respect to the output signal. Complex gain[n](q) represents the imaginary part gain values ​​of the input signal with respect to the output signal.

[0118] The dot plot (705) and dot plot (706) for at least one sample (710) can be constructed according to Equations 5 and 6.

[0119] According to one embodiment, the processor may repeatedly perform the above-described sampling process. The processor may repeatedly perform the sampling process until a specified number of samples are acquired. Thereafter, the processor may identify (or acquire) first gain information by identifying a gain value corresponding to each of the plurality of power levels. To identify the first gain information, the operation of identifying a gain value corresponding to each of the plurality of power levels will be described later in FIG. 8.

[0120] FIG. 8 is a flowchart illustrating the operation of an electronic device for identifying a gain value corresponding to each of a plurality of power levels.

[0121] Referring to FIG. 8, at operation 810, the processor may identify a plurality of power levels corresponding to a reference power range of an output signal for the PA. For example, the processor may set the reference power range. For example, the maximum value of the reference power range may be set to the maximum value of the output signal for the PA. The minimum value of the reference power range may be set to 0. As an example, the processor may set the maximum value of the plurality of power levels to 255. The processor may set the minimum value of the plurality of power levels to 0. For example, the processor may perform quantization on the magnitude of the power of the output signal for the PA to identify it as one of power levels from 0 to 255.

[0122] At operation 820, the processor may identify an average value of at least one sampled gain value for each of the plurality of power levels as the gain value for each of the plurality of power levels. For example, the at least one sampled gain value may be identified using a specified number of samples.

[0123] In one embodiment, the processor can identify, based on a specified number of samples, an average value of at least one sampled gain value (e.g., a complex gain value) for each of the plurality of power levels. The processor can identify, as the gain value for each of the plurality of power levels, an average value of at least one sampled gain value (e.g., a complex gain value) for each of the plurality of power levels.

[0124] For example, the processor may identify an average value of at least one sampled real gain value for each of the plurality of power levels as the real gain value for each of the plurality of power levels. The processor may identify an average value of at least one sampled imaginary gain value for each of the plurality of power levels as the imaginary gain value for each of the plurality of power levels.

[0125] For example, at least one sampled gain value may be obtained for one power level. The processor may identify an average value of the at least one sampled gain value to identify one gain value for one power level. The processor may identify the identified average value as the gain value for the one power level. The processor may identify a gain value corresponding to each of the plurality of power levels by performing the same operation for each of the plurality of power levels. The operation of identifying a gain value corresponding to each of the plurality of power levels may be referred to as a normalization process.

[0126] Figure 9a is a flowchart regarding the operation of an electronic device for performing the first process.

[0127] Figure 9b shows the change in gain values ​​within a specified power range according to the first process.

[0128] Referring to FIG. 9A, in operation 910, the processor may use a first power level among power levels within a specified power range among the first gain information to identify a second power level that is less than the first power level and a third power level that is greater than the first power level.

[0129] In one embodiment, the processor can determine a designated power range. The processor can identify power levels within the designated power range. For example, the processor can set a portion of a plurality of power levels to fall within the designated power range. For example, if the plurality of power levels range from 0 to 255, the designated power range can be set to a range exceeding 25 and less than or equal to 220.

[0130] According to one embodiment, the processor can identify a first power level among power levels within a specified power range, a second power level less than the first power level, and a third power level greater than the first power level.

[0131] For example, the processor may identify a second power level that is less than the first power level. The processor may identify a third power level that is greater than the first power level. The processor may identify a second power level that is a specified level less than the first power level. The processor may identify a third power level that is a specified level greater than the first power level. The processor may determine a specified power range based on the specified levels. For example, if the first power level is 100, the processor may identify the second power level as 75 and the third power level as 125.

[0132] At operation 920, the processor can identify an average value of gain values ​​for power levels between the second power level and the third power level as a gain value for the first power level.

[0133] For example, the processor may identify power levels between a second power level and a third power level. The processor may identify a gain value for each of the identified power levels. The processor may identify an average value of the gain values ​​for the identified power levels. The processor may identify the identified average value as the gain value for the first power level.

[0134] For example, if the first power level is 100, the processor can identify the second power level as 75 and the third power level as 125. The processor can identify gain values ​​from power level 75 to power level 125. The processor can set the average value of the identified gain values ​​as the gain value of the first power level.

[0135] For example, an operation of identifying an average value of gain values ​​for power levels between a second power level and a third power level as a gain value for a first power level can be performed based on the following mathematical formula.

[0136]

[0137] Referring to Equation 7, n can be performed within a range greater than 25 and less than or equal to N-25. In other words, the specified power range can be greater than 25 and less than or equal to N-25. n is the first power level. (n-25) is the second power level. (n+25) is the third power level.

[0138] According to one embodiment, the processor may perform the above-described operation for each power level within a specified power range. Based on performing the above-described operation for each power level within the specified power range, the processor may perform a first process. An example of changes in gain values ​​for power levels within the specified power range according to the first process will be described in FIG. 9B.

[0139] Referring to FIG. 9B, the designated power range may be set to a range exceeding 25 and less than or equal to 220. The processor may perform the first process by performing the above-described operation for each power level within the designated power range. Before the first process is performed, the gain values ​​according to the power levels within the designated power range may be configured as in graph (931). After the first process is performed, the gain values ​​according to the power levels within the designated power range may be configured as in graph (932).

[0140] According to one embodiment, the processor can smoothly change the change in the gain value according to power levels within a specified power range by performing the first process (or smoothing process) using the smoothing and extrapolation block (583) of FIG. 5.

[0141] Figure 10a is a flowchart regarding the operation of an electronic device for performing a second process.

[0142] Figure 10b shows the change in gain values ​​outside the specified power range according to the second process.

[0143] Referring to FIG. 10A, at operation 1010, the processor may identify power levels outside a specified power range.

[0144] In one embodiment, the processor can determine a designated power range. The processor can identify power levels outside the designated power range. For example, the processor can set a portion of a plurality of power levels to the designated power range. For example, if the plurality of power levels are comprised of values ​​from 0 to 255, the designated power range can be set to a range greater than 25 and less than or equal to 220. The power levels outside the designated power range can include power levels from 0 to 25 and power levels from 221 to 225.

[0145] At operation 1020, the processor may estimate gain values ​​for power levels outside the specified power range. For example, the processor may estimate gain values ​​for power levels outside the specified power range by performing extrapolation using the first gain information.

[0146] For example, if a plurality of power levels are configured from 0 to 255, the power levels outside the designated power range may include the power levels from 0 to 25 and the power levels from 221 to 225. Extrapolation may be performed according to Equation 8 below for the gain values ​​(e.g., complex gain values) of the power levels from 0 to 25. Extrapolation may be performed according to Equation 9 below for the gain values ​​(e.g., complex gain values) of the power levels from 221 to 225. By performing the extrapolation, the processor may estimate the gain value for each of the power levels outside the designated power range.

[0147]

[0148]

[0149] Referring to Equations 8 and 9, Extrapolation_size is a value used to determine the slope for extrapolation. For example, Extrapolation_size can be set to 12.

[0150] According to one embodiment, the processor may perform the above-described operation for each power level outside the designated power range. Based on performing the above-described operation for each power level outside the designated power range, the processor may perform a second process. An example of estimating gain values ​​for power levels outside the designated power range according to the second process will be described in FIG. 10b.

[0151] Referring to FIG. 10b, the specified power range can be set to a range exceeding 25 and less than or equal to 220. Power levels outside the specified power range can include power levels from 0 to 25 and power levels from 221 to 225.

[0152] The processor can perform the second process by performing the above-described operation for each power level outside the designated power range. Before the second process is performed, the gain values ​​according to the power levels within the designated power range can be configured as in graph (1031). After the second process is performed, the estimated gain values ​​according to the power levels outside the designated power range can be configured as in graph (1032) and graph (1033).

[0153] According to one embodiment, the processor can estimate a gain value according to power levels outside a specified power range by performing a second process (or extrapolation process) using the smoothing and extrapolation block (583) of FIG. 5.

[0154] Figure 11a illustrates the change in gain as the first gain information is changed to the second gain information.

[0155] Figure 11b illustrates the change in phase as the first gain information is changed to the second gain information.

[0156] Figure 12 shows the change in PA output when the setting information of the DPD circuit is changed according to the second gain information.

[0157] Referring to FIGS. 11A and 11B , graphs (1101) and (1102) represent changes in gain according to power levels. Graphs (1111) and (1112) represent changes in phase according to power levels. Graphs (1101) and (1111) may be constructed based on first gain information. Graphs (1102) and (1112) may be constructed based on second gain information. Graphs (1101) and (1111) may be discontinuous or not smoothly constructed in signals with narrow bandwidths. Graphs (1101) and (1111) may not be suitable for modeling the inverse function characteristics of the PA. The processor may identify second gain information using the first gain information. Graphs (1102) and (1112) constructed based on the second gain information can be constructed continuously and smoothly even for signals with narrow bandwidths. Graphs (1102) and (1112) can be suitable for modeling the inverse function characteristics of the PA.

[0158] Referring to Fig. 12, graphs (1201) and (1202) represent the output of a PA according to frequency. Graph (1201) represents the output of a PA according to frequency when the transmission circuit illustrated in Fig. 3 is applied. Graph (1202) represents the output of a PA according to frequency when the transmission circuit illustrated in Fig. 5 is applied. By applying the transmission circuit illustrated in Fig. 5, the performance of the PA output is further improved.

[0159] According to the above-described embodiment, even for narrow-bandwidth signals, DPD modeling can be performed simultaneously by accumulating numerous samples. Furthermore, discretely structured signals can be seamlessly structured and constructed continuously through the first process (or smoothing process) and the second process (or extrapolation process).

[0160] According to the above-described embodiment, signals can be captured across various time intervals, not just for specific power levels, but for all power levels of the signal. DPD modeling can be performed smoothly even for signals with narrow bandwidths. Consequently, DPD performance can be improved.

[0161] Figure 13 illustrates the functional configuration of an electronic device including a transmitter circuit.

[0162] The electronic device (1310) may be the base station (110) of FIG. 1 or the MMU of the base station (110). Meanwhile, unlike the illustration, the present disclosure does not exclude that the electronic device (1310) may be implemented in the terminal (120) of FIG. 1. Not only the communication module for the transmission circuit as shown in FIGS. 1 to 12, but also the electronic device including the same are included in the embodiments of the present disclosure.

[0163] Referring to FIG. 13, an exemplary functional configuration of an electronic device (1310) is illustrated. The electronic device (1310) may include an antenna unit (1311), a filter unit (1312), an RF (radio frequency) processing unit (1313), and a processor (1314).

[0164] The antenna unit (1311) may include one or more antennas. The antenna performs functions for transmitting and receiving signals via a wireless channel. The antenna may include a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). The antenna may radiate an upconverted signal on a wireless channel or acquire a signal radiated by another device. Each antenna may be referred to as an antenna element or antenna element. In some embodiments, the antenna unit (1311) may include an antenna array in which a plurality of antenna elements form an array. The antenna unit (1311) may be electrically connected to the filter unit (1312) via RF signal lines. The antenna unit (1311) may be mounted on a PCB including a plurality of antenna elements. The PCB may include a plurality of RF signal lines connecting each antenna element to a filter of the filter unit (1312). These RF signal lines may be referred to as a feeding network.

[0165] The antenna unit (1311) can provide a received signal to the filter unit (1312) or radiate a signal provided from the filter unit (1312) into the air. The filter unit (1312) can perform filtering to transmit a signal of a desired frequency. The filter unit (1312) can perform a function to selectively identify a frequency by forming a resonance. The filter unit (1312) can include at least one of a band pass filter, a low pass filter, a high pass filter, or a band reject filter. That is, the filter unit (1312) can include RF circuits for obtaining a signal of a frequency band for transmission or a frequency band for reception. The filter unit (1312) according to embodiments can electrically connect the antenna unit (1311) and the RF processing unit (1313).

[0166] The RF processing unit (1313) may include multiple RF paths. An RF path may be a unit of a path through which a signal received through an antenna or a signal radiated through an antenna passes. At least one RF path may be referred to as an RF chain. The RF chain may include multiple RF components. The RF components may include amplifiers, mixers, oscillators, DACs, ADCs, etc. For example, the RF processing unit (1313) may include a mixer for up-converting a transmission signal to a transmission frequency. The transmission path of the RF processing unit (1313) may include a DAC, a mixer, an oscillator, and an amplifier. The reception path of the RF processing unit (1313) may include an ADC, a mixer, an oscillator, and an LNA. The transmission path may further include a coupler (or combiner). In addition, for example, the RF processing unit (1313) may include a mixer for down-converting an analog RF reception signal to a digital frequency. The receiving path of the RF processing unit (1313) may include a low-noise amplifier (LNA), a mixer, an oscillator, and an ADC. The receiving path may further include a coupler or attenuator.

[0167] The RF components of the RF processing unit may be implemented on a PCB. The electronic device (1310) may include a structure in which an antenna unit (1311) - a filter unit (1312) - an RF processing unit (1313) are stacked in that order. The antennas and the RF components of the RF processing unit may be implemented on the PCB, and filters may be repeatedly connected between the PCBs to form a plurality of layers.

[0168] The processor (1314) can control the overall operations of the electronic device (1310). The processor (1314) can include various modules for performing communication. Although one processor is illustrated in FIG. 13, the processor (1314) may include multiple processors. The processor (1314) can include modules for digital signal processing. For example, the processor (1314) can include a component (e.g., a baseband modem) for controlling a DPD circuit. As another example, the processor (1314) can include a component (e.g., a chip) for operating the DPD circuit. When transmitting data, the processor (1314) generates complex symbols by encoding and modulating a transmission bit stream. In addition, for example, when receiving data, the processor (1314) restores a reception bit stream by demodulating and decoding a baseband signal. The processor (1314) can perform the functions of the protocol stack required by the communication standard.

[0169] FIG. 13 illustrates the functional configuration of an electronic device (1310) as equipment that can utilize the antenna structure of the present disclosure. However, the example illustrated in FIG. 13 is merely an exemplary configuration for utilizing the antenna structure according to the embodiments of the present disclosure described through FIGS. 1 to 12 , and the embodiments of the present disclosure are not limited to the components of the equipment illustrated in FIG. 13 . Accordingly, an antenna module including an antenna structure, communication equipment of other configurations, and the antenna structure itself can also be understood as embodiments of the present disclosure.

[0170] According to one embodiment, an electronic device may include at least one processor including a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, processing circuitry, and one or more storage media, and may include a memory storing instructions. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to acquire a specified number of samples based on an input signal relating to the PA and an output signal relating to the PA. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify first gain information of the input signal with respect to the output signal based on the specified number of samples. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform, for each of the power levels of the output signal, a first process for averaging at least some of the gain values ​​within a power range specified among the first gain information. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform, for each of the power levels, a second process for estimating gain values ​​outside the power range specified among the first gain information.The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to obtain second gain information of the input signal for the output signal based on the first process and the second process. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to change configuration information of the DPD circuit based on the second gain information.

[0171] In one embodiment, the instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform a sampling process for obtaining at least one sample within a sampling interval. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to repeatedly perform the sampling process until the specified number of samples is obtained.

[0172] In one embodiment, the instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify a plurality of power levels corresponding to a reference power range of the output signal. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify an average value of at least one sampled gain value for each of the plurality of power levels as a gain value for each of the plurality of power levels. The at least one sampled gain value may be identified using the specified number of samples.

[0173] In one embodiment, the instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify, using a first power level among power levels within the designated power range, a second power level less than the first power level and a third power level greater than the first power level. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify gain values ​​for power levels within the designated power range by identifying an average value of gain values ​​for power levels between the second power level and the third power level as a gain value for the first power level. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform the first process based on identifying the gain values ​​for the power levels within the designated power range.

[0174] In one embodiment, the instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to identify power levels outside the designated power range. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to estimate gain values ​​for the power levels outside the designated power range by performing extrapolation using the first gain information. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to perform the second process based on estimating the gain values ​​for the power levels outside the designated power range.

[0175] According to one embodiment, the output signal may be configured for a wireless signal transmitted over a GSM (global system for mobile communications) band.

[0176] In one embodiment, the wireless signal may have a bandwidth of 0.2 MHz.

[0177] According to one embodiment, the input signal for the PA may include a signal input to the PA via the DAC. The output signal for the PA may include a signal output from the PA via the ADC.

[0178] In one embodiment, the instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to store the second gain information in the DPD circuit.

[0179] According to one embodiment, the second gain information may include a table consisting of gain values ​​for each of the plurality of power levels.

[0180] According to one embodiment, a method performed by an electronic device may include acquiring a specified number of samples based on an input signal regarding a power amplifier (PA) of the electronic device and an output signal regarding the PA. The method may include identifying first gain information of the input signal for the output signal based on the specified number of samples. The method may include performing a first process for averaging at least some of gain values ​​within a specified power range among the first gain information for each of the power levels of the output signal. The method may include performing a second process for estimating gain values ​​outside the specified power range among the first gain information for each of the power levels. The method may include acquiring second gain information of the input signal for the output signal based on the first process and the second process. The method may include changing configuration information of a digital pre-distortion (DPD) circuit of the electronic device based on the second gain information.

[0181] In one embodiment, the method may include performing a sampling process to obtain at least one sample within a sampling interval. The method may include repeatedly performing the sampling process until the specified number of samples are obtained.

[0182] According to one embodiment, the method may include an operation of identifying a plurality of power levels corresponding to a reference power range of the output signal. The method may include an operation of identifying an average value of at least one sampled gain value for each of the plurality of power levels as the gain value for each of the plurality of power levels. The at least one sampled gain value may be identified using the specified number of samples.

[0183] According to one embodiment, the method may include an operation of identifying a second power level that is less than the first power level and a third power level that is greater than the first power level, using a first power level among power levels within the specified power range. The method may include an operation of identifying gain values ​​for the power levels within the specified power range by identifying an average value of gain values ​​for power levels between the second power level and the third power level as a gain value for the first power level. The method may include an operation of performing the first process based on identifying the gain values ​​for the power levels within the specified power range.

[0184] In one embodiment, the method may include an operation of identifying power levels outside the specified power range. The method may include an operation of estimating the gain values ​​for the power levels outside the specified power range by performing extrapolation using the first gain information. The method may include an operation of performing the second process based on the estimation of the gain values ​​for the power levels outside the specified power range.

[0185] According to one embodiment, the output signal may be configured for a wireless signal transmitted over a GSM (global system for mobile communications) band.

[0186] In one embodiment, the wireless signal may have a bandwidth of 0.2 MHz.

[0187] According to one embodiment, the input signal for the PA may include a signal input to the PA through a digital-to-analog converter (DAC) of the electronic device. The output signal for the PA may include a signal output from the PA through an analog-to-digital converter (ADC) of the electronic device.

[0188] According to one embodiment, the method may include storing the second gain information in the DPD circuit.

[0189] According to one embodiment, an electronic device may include a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, an analog-to-digital converter (ADC) coupled to the PA, and at least one processor. The at least one processor may be configured to acquire a specified number of samples based on an input signal for the PA and an output signal for the PA. The at least one processor may be configured to identify first gain information of the input signal for the output signal based on the specified number of samples. The at least one processor may be configured to perform a first process for averaging at least some of gain values ​​within a specified power range among the first gain information for each of the power levels of the input signal. The at least one processor may be configured to perform a second process for estimating gain values ​​outside the specified power range among the first gain information for each of the power levels. The at least one processor may be configured to obtain second gain information of the input signal for the output signal based on the first process and the second process. The at least one processor may be configured to change the setting information of the DPD circuit according to the second gain information.

[0190] According to one embodiment, a non-transitory storage medium may store one or more programs. The one or more programs may include instructions that, when executed by a processor of an electronic device, the electronic device includes a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC, and an analog-to-digital converter (ADC) coupled to the PA, cause the electronic device to acquire a specified number of samples based on an input signal relating to the PA and an output signal relating to the PA. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to identify first gain information of the input signal for the output signal based on the specified number of samples. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to perform, for each of the power levels of the input signal, a first process for averaging at least some of the gain values ​​within a designated power range among the first gain information. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to perform, for each of the power levels, a second process for estimating gain values ​​outside the designated power range among the first gain information. The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to obtain, based on the first process and the second process, second gain information of the input signal for the output signal.The one or more programs may include instructions that, when executed by the processor of the electronic device, cause the electronic device to change setting information of the DPD circuit according to the second gain information.

[0191] According to the above-described embodiments, in a wireless communication system, DPD performance can be improved to stably compensate for PA nonlinearity. When conventional data capture methods are used, DPD performance degradation occurs for signals with narrow bandwidths. According to the above-described embodiments, DPD modeling can be performed stably even in narrow communication bands such as the GSM band. According to the above-described embodiments, DPD modeling and / or AMP (amplifier) ​​performance can be improved for all signals, regardless of bandwidth size.

[0192] The methods according to the embodiments described in the claims or specification of the present disclosure may be implemented in the form of hardware, software, or a combination of hardware and software.

[0193] When implemented in software, a computer-readable storage medium storing one or more programs (software modules) may be provided. The one or more programs stored in the computer-readable storage medium are configured for execution by one or more processors within an electronic device. The one or more programs include instructions that cause the electronic device to execute methods according to embodiments described in the claims or specification of the present disclosure.

[0194] These programs (software modules, software) may be stored in random access memory, non-volatile memory including flash memory, read only memory (ROM), electrically erasable programmable read only memory (EEPROM), magnetic disc storage devices, compact disc-ROM (CD-ROM), digital versatile discs (DVDs) or other forms of optical storage devices, magnetic cassettes, or may be stored in memories formed by a combination of some or all of these. In addition, each configuration memory may include multiple copies.

[0195] Additionally, the program may be stored on an attachable storage device that is accessible via a communication network, such as the Internet, an intranet, a local area network (LAN), a wide area network (WAN), a storage area network (SAN), or a combination thereof. Such a storage device may be connected to a device implementing an embodiment of the present disclosure via an external port. Additionally, a separate storage device on the communication network may be connected to a device implementing an embodiment of the present disclosure.

[0196] In the specific embodiments of the present disclosure described above, components included in the disclosure are expressed singularly or plurally, depending on the specific embodiment presented. However, the singular or plural expressions are selected to suit the presented situation for convenience of explanation, and the present disclosure is not limited to singular or plural components. Components expressed in plural may be composed of singular elements, or components expressed in singular may be composed of plural elements.

[0197] Meanwhile, although the detailed description of the present disclosure has described specific embodiments, it is obvious that various modifications are possible within the scope of the present disclosure.

Claims

1. In electronic devices, DPD(digital pre-distortion) circuit; A digital-to-analog converter (DAC) coupled to the above DPD circuit; A PA (power amplifier) coupled to the above DAC; An analog-to-digital converter (ADC) coupled to the above PA; At least one processor comprising processing circuitry; and comprising one or more storage media, and including a memory storing instructions; The above instructions, when individually or collectively executed by the at least one processor, Based on the input signal for the PA and the output signal for the PA, a specified number of samples are acquired, Based on the above-mentioned specified number of samples, identifying the first gain information of the input signal for the output signal, For each of the power levels of the above output signal, a first process is performed to average at least some of the gain values within a specified power range among the first gain information, For each of the above power levels, a second process is performed to estimate gain values outside the specified power range among the first gain information, Based on the first process and the second process, second gain information of the input signal for the output signal is obtained, Causing the electronic device to change the setting information of the DPD circuit according to the second gain information. Electronic devices.

2. In the first paragraph, when the instructions are individually or collectively executed by the at least one processor, Performing a sampling process to obtain at least one sample within a sampling interval, Further causing the electronic device to repeatedly perform the sampling process until the specified number of samples are obtained. Electronic devices.

3. In the first paragraph, when the instructions are individually or collectively executed by the at least one processor, Identifying a plurality of power levels corresponding to the reference power range of the above output signal, Further causing the electronic device to identify an average value of at least one sampled gain value for each of the plurality of power levels as the gain value for each of the plurality of power levels, wherein at least one of the sampled gain values is, Identified using the above specified number of samples, Electronic devices.

4. In the first paragraph, when the instructions are individually or collectively executed by the at least one processor, Using a first power level among the power levels within the above-mentioned specified power range, a second power level smaller than the first power level and a third power level larger than the first power level are identified, By identifying the average value of the gain values for the power levels between the second power level and the third power level as the gain value for the first power level, the gain values for the power levels within the specified power range are identified, Further causing the electronic device to perform the first process based on identifying the gain values for the power levels within the specified power range; Electronic devices.

5. In the first paragraph, when the instructions are individually or collectively executed by the at least one processor, Identify power levels outside the specified power range, By performing extrapolation using the above first gain information, the gain values for the power levels outside the above specified power range are estimated, Further causing the electronic device to perform the second process based on estimating the gain values for the power levels outside the specified power range. Electronic devices.

6. In the first paragraph, the output signal is, Configured for wireless signals transmitted via the GSM (global system for mobile communications) band, Electronic devices.

7. In the 6th paragraph, the wireless signal, With a bandwidth of 0.2 MHz, Electronic devices.

8. In the first paragraph, the input signal for the PA is, Contains a signal input to the PA through the DAC, The above output signal regarding the above PA is, Containing a signal output from the above PA through the above ADC, Electronic devices.

9. In the first paragraph, when the instructions are individually or collectively executed by the at least one processor, Further causing the electronic device to store the second gain information in the DPD circuit, Electronic devices.

10. In the 9th paragraph, the second gain information is, A table comprising gain values for each of the plurality of power levels, Electronic devices.

11. In a method performed by an electronic device, An operation of acquiring a specified number of samples based on an input signal regarding a power amplifier (PA) of the electronic device and an output signal regarding the PA; An operation of identifying first gain information of the input signal for the output signal based on the specified number of samples; For each of the power levels of the output signal, an operation of performing a first process for averaging at least some of the gain values within a specified power range among the first gain information; For each of the above power levels, an operation of performing a second process for estimating gain values outside the specified power range among the first gain information; An operation of obtaining second gain information of the input signal for the output signal based on the first process and the second process; and An operation for changing setting information of a DPD (digital pre-distortion) circuit of the electronic device according to the second gain information, method.

12. In the 11th paragraph, the method, An operation of performing a sampling process to obtain at least one sample within a sampling interval; and Further comprising an action of repeatedly performing the sampling process until the specified number of samples are obtained. method.

13. In the 11th paragraph, the method, An operation for identifying a plurality of power levels corresponding to a reference power range of the output signal; and Further comprising an operation of identifying an average value of at least one sampled gain value for each of the plurality of power levels as a gain value for each of the plurality of power levels; wherein at least one of the sampled gain values is, Identified using the above specified number of samples, method.

14. In the 11th paragraph, the method, An operation of identifying a second power level that is less than the first power level and a third power level that is greater than the first power level by using a first power level among power levels within the specified power range; An operation of identifying gain values for the power levels within the specified power range by identifying an average value of gain values for power levels between the second power level and the third power level as a gain value for the first power level; and Further comprising an operation of performing said first process based on identifying said gain values for said power levels within said specified power range. method.

15. In a non-transitory storage medium storing one or more programs, the one or more programs, when executed by a processor of an electronic device including a digital pre-distortion (DPD) circuit, a digital-to-analog converter (DAC) coupled to the DPD circuit, a power amplifier (PA) coupled to the DAC; and an analog-to-digital converter (ADC) coupled to the PA, Based on the input signal for the PA and the output signal for the PA, a specified number of samples are acquired, Based on the above-mentioned specified number of samples, identifying the first gain information of the input signal for the output signal, For each of the power levels of the input signal, a first process is performed to average at least some of the gain values within a specified power range among the first gain information, For each of the above power levels, a second process is performed to estimate gain values outside the specified power range among the first gain information, Based on the first process and the second process, second gain information of the input signal for the output signal is obtained, Including instructions for causing the electronic device to change the setting information of the DPD circuit according to the second gain information. Computer readable storage medium.

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