Error correction code circuit, repair system and memory

Abstract

Provided in the present invention are an error correction code circuit, a repair system and a memory. The error correction code circuit comprises: a first decoding module, which is used for receiving first data, decoding the first data on the basis of an error correction code with an m-bit error correction capability, and outputting a first decoding result and a first number of error bits, wherein the first data is original data of data bits and check bits; a second decoding module, which is used for receiving second data, decoding the second data on the basis of the error correction code with the m-bit error correction capability, and outputting a second decoding result and a second number of error bits, wherein the second data is data obtained after data, which corresponds to short-circuit data bits and check bits, among the first data is all negated; and an output logic module, which is used for outputting one of the first decoding result and the second decoding result or outputting an error prompt of an error correction failure on the basis of the first number of error bits and the second number of error bits. The present invention can shorten the delay of the error correction code circuit.

Description

Error correction code circuit, repair system and memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent application No. 202410115685.8 filed on January 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of memory technology, and in particular to an error correction code circuit, a repair system and a memory. Background Art

[0004] MRAM is a new memory and storage technology that offers the same fast random read and write capabilities as SRAM / DRAM, but with the ability of flash to permanently retain data after a power outage. The core structure of an MRAM storage bit is a magnetic tunnel junction, consisting of two layers of ferromagnetic material sandwiched by a very thin layer of non-ferromagnetic insulating material. The lower ferromagnetic layer is a reference layer with a fixed magnetization direction, while the upper ferromagnetic layer is a free layer with a variable magnetization direction. The magnetization direction of the free layer can be parallel or antiparallel to that of the reference layer.

[0005] When reading data from an MRAM, the readout circuit needs to detect the resistance of the MRAM storage bit. Because the resistance of the magnetic tunnel junction may drift due to factors such as the production process, the number of reads and writes, and temperature, data errors may occur, and the read data bits may be the opposite of the previously written data bits. To address this issue, an ECC (Error Correction Code) circuit can be added to encode the original data and add some check bits to detect and correct data errors. The delay of the ECC circuit directly affects the decoding speed, so how to reduce the delay of the ECC circuit is a key consideration. Summary of the Invention

[0006] In view of this, the present invention provides an error correction code circuit, a repair system and a memory, which can basically achieve the error correction capability of m+1 bits based on an error correction code with an error correction capability of m bits, and reduce the delay of the error correction code circuit under the same error correction capability.

[0007] In a first aspect, the present invention provides an error correction code circuit, comprising:

[0008] a first decoding module, configured to receive first data, in a case where there are shorted data bits and check bits, and the shorted data bits and check bits are less than or equal to m+1 bits, decode the first data based on an error correction code with an error correction capability of m bits, and output a first decoding result and a first number of error bits, where the first data is original data of the data bits and the check bits;

[0009] a second decoding module, operating in parallel with the first decoding module when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, to receive second data, decode the second data based on an error correction code with an error correction capability of m bits, and output a second decoding result and a second number of error bits, where the second data is obtained by inverting all data corresponding to the short-circuited data bits and check bits in the first data;

[0010] An output logic module is used to output one of the first decoding result and the second decoding result or output an error prompt that cannot be corrected according to the first number of error bits and the second number of error bits.

[0011] Optionally, the output logic module is used to:

[0012] If the first error bit number is 0, output the first decoding result; if the first error bit number is m+1 bits and the second error bit number is 0, output the second decoding result; if the first error bit number is m+1 bits and the second error bit number is also m+1 bits, output an error prompt that cannot be corrected.

[0013] Optionally, the error correction code circuit further includes:

[0014] A control module is configured to receive first data and short-circuit information of data bits and check bits, wherein the short-circuit information is used to indicate whether the data bits and check bits are short-circuited; based on the short-circuit information of the data bits and check bits, check whether there are short-circuited data bits and check bits; if there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, invert all data corresponding to the short-circuited data bits and check bits in the first data to obtain second data; and enable the first decoding module and the second decoding module.

[0015] Optionally, the control module is further configured to enable only the first decoding module if there are no short-circuited data bits and check bits, or if the number of short-circuited data bits and check bits is greater than m+1 bits;

[0016] The first decoding module is further configured to, when there are no short-circuited data bits and check bits, or when the number of short-circuited data bits and check bits is greater than m+1 bits, receive the first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a third decoding result and a third number of error bits;

[0017] The output logic module is further configured to output a third decoding result or an error prompt that cannot be corrected based on the third number of error bits.

[0018] Optionally, if the short-circuit information of the data bit and the check bit is 1, it indicates that the data bit and the check bit are short-circuited; if the short-circuit information of the data bit and the check bit is 0, it indicates that the data bit and the check bit are normal.

[0019] Optionally, the error correction code with an error correction capability of m bits is any type of error correction code that corrects m and detects m+1 bits.

[0020] In a second aspect, the present invention provides a memory repair system, comprising the error correction code circuit provided in the first aspect, and further comprising:

[0021] a storage bit array, the storage bit array being used to store data of data bits;

[0022] A check bit array, the check bit array being used to store check bit data, the check bit data being obtained by encoding according to the data bit data;

[0023] A data reading circuit is connected to the error correction code circuit, the storage bit array, and the check bit array, and is used to read the storage bit array and the check bit array, obtain original data of the data bits and the check bits as first data, and obtain short-circuit information of the data bits and the check bits, and input the read first data and the short-circuit information of the data bits and the check bits into the error correction code circuit.

[0024] Optionally, the data reading circuit includes:

[0025] a first reference circuit, configured to read data from the storage bit array and the check bit array to obtain original data of data bits and check bits as first data;

[0026] The second reference circuit is used to read the bit states of the storage bit array and the check bit array to obtain short circuit information of the data bits and the check bits.

[0027] In a third aspect, the present invention provides a memory, comprising the memory repair system provided in the second aspect.

[0028] The error correction code circuit, repair system, and memory provided by the present invention, when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, the first decoding module and the second decoding module decode in parallel, the first decoding module decodes the first data, the first data is the original data of the data bits and check bits, the second decoding module decodes the second data, the second data is the data obtained by inverting all the data corresponding to the short-circuited data bits and check bits in the first data, and the output logic module outputs the decoding result. When the error correction capability of the error correction code is m bits, the error correction capability of m+1 bits can be basically achieved, which improves the error correction capability of the error correction code. Moreover, compared with conventional error correction codes with the same error correction capability, the error correction code circuit of this embodiment has a significant low latency advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of an error correction code circuit in one embodiment;

[0030] FIG2 is a schematic diagram of a flow chart of error correction steps of an error correction code circuit according to one embodiment;

[0031] FIG3 is a schematic diagram showing a low-latency comparison of an error correction code circuit according to an embodiment;

[0032] FIG4 is a schematic diagram of the structure of a memory repair system according to an embodiment;

[0033] FIG5 is a schematic diagram of the array structure of a storage bit array and a check bit array in one embodiment;

[0034] FIG6 is a schematic structural diagram of a data reading circuit in one embodiment. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0038] An embodiment of the present invention provides an error correction code circuit, as shown in FIG1 , which includes:

[0039] A first decoding module 101 is configured to receive first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a first decoding result and a first number of error bits, where the first data is original data of the data bits and the check bits, when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits;

[0040] a second decoding module 102, configured to operate in parallel with the first decoding module 101 when there are short-circuited data bits and check bits, and the number of short-circuited data bits and check bits is less than or equal to m+1 bits, to receive second data, decode the second data based on an error correction code with an error correction capability of m bits, and output a second decoding result and a second number of error bits, where the second data is obtained by inverting all data corresponding to the short-circuited data bits and check bits in the first data;

[0041] The output logic module 103 is configured to output one of the first decoding result and the second decoding result or output an error prompt indicating that the error cannot be corrected according to the first number of error bits and the second number of error bits.

[0042] Furthermore, in one embodiment, the output logic module 103 is specifically used to: output a first decoding result if the first error bit number is 0; output a second decoding result if the first error bit number is m+1 bits and the second error bit number is 0; output an error prompt that cannot be corrected if the first error bit number is m+1 bits and the second error bit number is also m+1 bits.

[0043] There are four situations:

[0044] 1) The first error bit is 0, and the second error bit is m+1;

[0045] 2) The first error bit is 0, and the second error bit is also 0;

[0046] 3) The first error bit is m+1, and the second error bit is 0;

[0047] 4) The first error bit number is m+1, and the second error bit number is also m+1;

[0048] For cases 1) and 2), the first decoding result is output; for case 3), the second decoding result is output; for case 4), an error prompt indicating that the error cannot be corrected is output.

[0049] Based on the above error correction logic, the error correction code circuit of this embodiment can obtain information that should be stored in the memory byte or output error information that cannot be corrected.

[0050] Furthermore, in one embodiment, referring to FIG1 , the error correction code circuit further includes:

[0051] The control module 100 is used to receive first data and short-circuit information of data bits and check bits, where the short-circuit information is used to indicate whether the data bits and check bits are short-circuited; based on the short-circuit information of the data bits and check bits, check whether there are short-circuited data bits and check bits; if there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, invert all data corresponding to the short-circuited data bits and check bits in the first data to obtain second data; and enable the first decoding module 101 and the second decoding module 102.

[0052] In one embodiment, if the short circuit information of the data bit and the check bit is 1, it indicates that the data bit and the check bit are short-circuited; if the short circuit information of the data bit and the check bit is 0, it indicates that the data bit and the check bit are normal.

[0053] The above analysis covers the case where there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits. In addition, the following cases may occur: there are no short-circuited data bits and check bits, or the short-circuited data bits and check bits are greater than m+1 bits.

[0054] Furthermore, the control module 100 is further configured to enable only the first decoding module 101 if there are no short-circuited data bits and check bits, or if the short-circuited data bits and check bits are greater than m+1 bits;

[0055] Correspondingly, the first decoding module 101 is further configured to, when there are no short-circuited data bits and check bits, or when the number of short-circuited data bits and check bits is greater than m+1 bits, receive the first data, decode the first data based on an error correction code with an error correction capability of m bits, and output a third decoding result and a third number of error bits;

[0056] The output logic module 103 is further configured to output a third decoding result or an error prompt that cannot be corrected according to the third number of error bits.

[0057] The following is a brief description of the error correction steps of the error correction code circuit shown in FIG1 .

[0058] Referring to Figure 2, the control module 100 first receives the first data and the short-circuit information of the data bits and the check bits, and checks whether there are short-circuited data bits and check bits based on the short-circuit information of the data bits and the check bits; if there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, all the data corresponding to the short-circuited data bits and check bits in the first data are inverted to obtain the second data; the first decoding module 101 and the second decoding module 102 are enabled, where m represents the error correction capability of the error correction code used by the first decoding module 101 and the second decoding module 102.

[0059] Then, when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, the first decoding module 101 and the second decoding module 102 decode in parallel, the first decoding module 101 decodes the first data based on the error correction code with an error correction capability of m bits, and outputs a first decoding result and a first number of error bits, and the second decoding module 102 decodes the second data based on the error correction code with an error correction capability of m bits, and outputs a second decoding result and a second number of error bits.

[0060] Finally, the output logic module 103 obtains the information that should have been stored in the memory byte or outputs uncorrectable error information based on the following error correction logic: if the first error bit is 0, the first decoding result is output; if the first error bit is m+1 bits and the second error bit is 0, the second decoding result is output; if the first error bit is m+1 bits and the second error bit is also m+1 bits, an uncorrectable error prompt is output.

[0061] It is also noted that in the above-mentioned error correction step, if there are no short-circuited data bits and check bits, or the short-circuited data bits and check bits are greater than m+1 bits, the control module 100 only enables the first decoding module 101, and the first decoding module 101 decodes the first data based on an error correction code with an error correction capability of m bits, and outputs a third decoding result and a third number of error bits; the output logic module 103 outputs the third decoding result or outputs an error prompt that cannot be corrected according to the third number of error bits.

[0062] The following examples illustrate how the error correction code circuit according to an embodiment of the present invention can improve the error correction capability of an error correction code. In this embodiment, the error correction code with an error correction capability of m bits used by the first decoding module 101 and the second decoding module 102 can be any type of error correction code that corrects m and detects m+1 errors, such as a Hamming code that corrects 1 and detects 2, or a BCH code that corrects 2 and detects 3.

[0063] 1. For a 1-bit check-2 Hamming code with an error correction capability of 1 bit, analyze the error correction capability in different situations.

[0064] a) When three or more data bits and check bits are short-circuited, or when there is no short-circuit between the data bits and the check bits, only the first decoding module decodes, and in this case, only one soft error can be corrected.

[0065] When one or two data bits and check bits are short-circuited, the first decoding module and the second decoding module decode in parallel, which can basically achieve the error correction capability of 2 bits.

[0066] The specific analysis is as follows:

[0067] b) If one of the data bits and the check bit is short-circuited, and if there is still one soft error, then one of the first data and the second data can always be decoded correctly, and the other reports a two-bit error. That is, one of the first error bit and the second error bit is always 0 and the other is 2, so it can be decoded correctly.

[0068] c) If two data bits and two check bits are shorted, and there are no soft error bits, the data at the shorted position is as follows:

[0069] It can be seen that this situation can be decoded correctly.

[0070] In summary, except for the case of 2-bit soft errors, the error correction code circuit of the embodiment of the present invention is based on the Hamming code with 1 correction and 2 check, combined with the short-circuit information of the data bit and the check bit, to achieve the error correction capability of 2-bit errors. The probability of a 2-bit soft error in an error correction unit data is very low. Taking a 32-bit array + 7-bit error correction code with a soft error rate of 1ppm as an example, the probability of a 2-bit soft error is only 7.4e-10. In comparison, the probability of a 1-bit soft error is 3.9e-5, which is about 5 orders of magnitude higher. Therefore, it can be considered that the error correction code circuit of this embodiment can basically achieve the error correction capability of 2-bit errors based on the Hamming code with 1 correction and 2 check, and compared with the conventional 2-bit error correction code, it has advantages in decoding delay and area.

[0071] 2. For the BCH code with a 2-bit error correction capability, analyze the error correction capability in different situations.

[0072] a) When 4 or more data bits and check bits are short-circuited, or when there is no short-circuit between the data bits and check bits, only the first decoding module decodes, and in this case, only 2 soft errors can be corrected.

[0073] When one, two or three data bits and check bits are short-circuited, the first decoding module and the second decoding module decode in parallel, which can basically achieve a 3-bit error correction capability.

[0074] The specific analysis is as follows:

[0075] b) If one of the data bits and the check bit is short-circuited, and if there are still two soft errors, then one of the first data and the second data can always be decoded correctly, and the other reports a three-bit error. That is, one of the first error bit and the second error bit is always 0 and the other is 3, so it can be decoded correctly.

[0076] c) If two data bits and two check bits are shorted, and there is one soft error, the data at the shorted position is as follows:

[0077] It can be seen that this situation can be decoded correctly.

[0078] d) If three data bits and check bits are short-circuited and there are no soft error bits, the data at the short-circuit position is as follows:

[0079] It can be seen that this situation can be decoded correctly.

[0080] In summary, except for the case of 3-bit soft errors, the error correction code circuit of the embodiment of the present invention is based on the BCH code with 2 corrections and 3 checks, combined with the short-circuit information of the data bits and the check bits, to achieve 3-bit error correction capability. The probability of a 3-bit soft error in an error correction unit data is very low. Taking a 32-bit array + 13-bit error correction code with a soft error rate of 1ppm as an example, the probability of a 3-bit soft error is only 1.4e-14. Therefore, it can be considered that the error correction code circuit of this embodiment can basically achieve 3-bit error correction capability based on the BCH code with 2 corrections and 3 checks, and compared with conventional 3-bit error correction codes, it has advantages in decoding delay and area.

[0081] The following table shows the failure rates of erroneous data repair using this embodiment's BCH code with a 2-check-3 error correction method, conventional 2-check-3 error correction codes, and conventional 3-check-3 error correction codes. The calculations are based on a 4Mb chip with an 8-bit bit width. This shows that compared to conventional 2-check-3 error correction codes, this embodiment can repair short-circuit errors at a rate over an order of magnitude higher, thereby improving the endurance of MRAM products by over 10 times.

[0082] In addition, FIG3 shows the error correction delays of different error correction codes. It can be seen that compared with conventional error correction codes with the same error correction capability, the error correction code circuit of this embodiment has a significant low delay advantage.

[0083] The error correction code circuit provided by an embodiment of the present invention, when there are short-circuited data bits and check bits, and the short-circuited data bits and check bits are less than or equal to m+1 bits, the first decoding module and the second decoding module decode in parallel, the first decoding module decodes the first data, the first data is the original data of the data bits and check bits, the second decoding module decodes the second data, the second data is the data obtained by inverting all the data corresponding to the short-circuited data bits and check bits in the first data, and the output logic module outputs the decoding result. When the error correction capability of the error correction code is m bits, the error correction capability of m+1 bits can be basically achieved, thereby improving the error correction capability of the error correction code. Moreover, compared with conventional error correction codes with the same error correction capability, the error correction code circuit of this embodiment has a significant low latency advantage.

[0084] On the other hand, an embodiment of the present invention provides a memory repair system. As shown in FIG4 , the memory repair system includes the error correction code circuit 401 provided in the above embodiments, and further includes:

[0085] A storage bit array 402, the storage bit array 402 is used to store data bits;

[0086] A check bit array 403, which is used to store check bit data, wherein the check bit data is obtained by encoding according to the data bits;

[0087] The data reading circuit 404 is connected to the error correction code circuit 401, the storage bit array 402, and the check bit array 403. The data reading circuit 404 is configured to read the storage bit array 402 and the check bit array 403, obtain the original data of the data bits and the check bits as the first data, obtain short-circuit information of the data bits and the check bits, and input the read first data and the short-circuit information of the data bits and the check bits into the error correction code circuit 401.

[0088] FIG5 is a schematic diagram of the array structure of the storage bit array and the check bit array. The storage bit array includes M columns of storage bits, and the check bit array includes N columns of check bits, where M and N are both positive integers and M>N.

[0089] Taking MRAM as an example, the structure of the data reading circuit 404 may adopt the circuit structure shown in FIG6 , including:

[0090] A first reference circuit is used to read data from the storage bit array and the check bit array to obtain original data of the data bits and the check bits as first data;

[0091] The second reference circuit is used to read the bit states of the storage bit array and the check bit array to obtain short circuit information of the data bits and the check bits.

[0092] As shown in Figure 6, the first reference circuit compares the current flowing through the memory bit / check bit with the current flowing through the reference resistor Rref, and current comparator 1 outputs first data bit by bit. The second reference circuit compares the current flowing through the memory bit / check bit with the current flowing through the reference resistor Rref_short, and current comparator 2 outputs short-circuit information bit by bit.

[0093] On the other hand, an embodiment of the present invention further provides a memory, which includes the above-mentioned memory repair system.

[0094] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0095] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. An error correction code circuit, characterized in that, The error correction code circuit includes: A first decoding module, configured to receive first data and decode the first data based on an error correction code with an error correction capability of m bits when there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits, and output a first decoding result and a first number of error bits. The first data is the original data of the data bits and parity bits. A second decoding module, which works in parallel with the first decoding module when there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits. The second decoding module is configured to receive second data and decode the second data based on an error correction code with an error correction capability of m bits, and output a second decoding result and a second number of error bits. The second data is the data obtained by inverting all the data corresponding to the shorted data bits and parity bits in the first data. An output logic module, configured to output one of the first decoding result and the second decoding result or an error prompt indicating that error correction cannot be performed according to the first number of error bits and the second number of error bits.

2. The error correction code circuit according to claim 1, wherein The output logic module is configured to: If the first number of error bits is 0, output the first decoding result; if the first number of error bits is m + 1 bits and the second number of error bits is 0, output the second decoding result. If the first number of error bits is m + 1 bits and the second number of error bits is also m + 1 bits, output an error prompt indicating that error correction cannot be performed.

3. The error correction code circuit according to claim 1, wherein The error correction code circuit further includes: A control module, configured to receive the first data and the short circuit information of the data bits and parity bits, where the short circuit information is used to indicate whether the data bits and parity bits are shorted; check whether there are shorted data bits and parity bits according to the short circuit information of the data bits and parity bits; if there are shorted data bits and parity bits, and the number of shorted data bits and parity bits is less than or equal to m + 1 bits, invert all the data corresponding to the shorted data bits and parity bits in the first data to obtain second data; enable the first decoding module and the second decoding module.

4. The error correction code circuit according to claim 3, wherein The control module is further configured to, if there are no shorted data bits and parity bits, or the number of shorted data bits and parity bits is greater than m + 1 bits, only enable the first decoding module. The first decoding module is further configured to, when there are no shorted data bits and parity bits, or when the number of shorted data bits and parity bits is greater than m + 1 bits, receive the first data and decode the first data based on an error correction code with an error correction capability of m bits, and output a third decoding result and a third number of error bits. The output logic module is further configured to output the third decoding result or an error prompt indicating that error correction cannot be performed according to the third number of error bits.

5. The error correction code circuit according to claim 3, characterized in that If the short circuit information of the data bits and parity bits is 1, it indicates that the data bits and parity bits are shorted; if the short circuit information of the data bits and parity bits is 0, it indicates that the data bits and parity bits are normal.

6. The error correction code circuit according to claim 1, wherein The error correction code with an error correction capability of m bits is any type of error correction code that corrects m errors and detects m + 1 errors.

7. A memory repair system, characterized in that, including: The error correction code circuit according to any one of claims 1 to 6 further includes: A storage bit array for storing data bits of data; A parity bit array for storing parity bit data, the parity bit data being obtained by encoding based on the data bit data; A data reading circuit connected to the error correction code circuit, the storage bit array, and the parity bit array, for reading the storage bit array and the parity bit array to obtain the original data of the data bits and the parity bits as first data, and for obtaining the short circuit information of the data bits and the parity bits, and inputting the read first data and the short circuit information of the data bits and the parity bits into the error correction code circuit.

8. The memory repair system according to claim 7, wherein The data reading circuit includes: A first reference circuit for reading the data of the storage bit array and the parity bit array to obtain the original data of the data bits and the parity bits as first data; A second reference circuit for reading the bit states of the storage bit array and the parity bit array to obtain the short circuit information of the data bits and the parity bits.

9. A memory, characterized in that, The memory includes the memory repair system according to claim 7 or 8.

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