Brain-computer interface device, operation method therefor, and brain-computer interface system

Abstract

Embodiments of the present disclosure provide a brain-computer interface device, an operation method therefor, and a brain-computer interface system. The brain-computer interface device comprises: a signal acquisition module, configured to acquire a first electroencephalogram signal and a second electroencephalogram signal generated by a target object; a signal processing module, comprising a memristor array and configured to process and decode the first electroencephalogram signal and output a corresponding decoding signal to be fed back to the target object to generate the second electroencephalogram signal, wherein the memristor array is configured to realize a decoding model; a detection module, configured to detect whether an error-related potential signal is present in the second electroencephalogram signal; and a determination module, configured to determine, on the basis of the detection result, whether to use the first electroencephalogram signal and the decoding signal to update the decoding model. According to the device, new electroencephalogram sample data can be accumulated during interaction, and the impact of conductance drift in memristors and temporal variability of electroencephalogram signals on decoding accuracy is effectively mitigated by updating parameters of the decoding model.

Description

Brain-computer interface device and operation method thereof, and brain-computer interface system

[0001] This application claims priority to Chinese patent application No. 202410109224.X filed on January 25, 2024. The contents of the above-mentioned Chinese patent application disclosure are hereby incorporated by reference in their entirety as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to a brain-computer interface device and an operating method thereof, and a brain-computer interface system. Background Art

[0003] With the advancement of science and technology, people have gradually realized the analysis of neural signals and the utilization of the results. For example, brain-computer interfaces are used to analyze neural signals emitted by the brain to help people with neurological diseases monitor and control their diseases.

[0004] Memristors are a new type of micro-nanoelectronic device whose resistance state can be dynamically controlled in response to changes in applied voltage. Memristor-based neuromorphic computing overcomes the limitations of traditional von Neumann architectures, enabling computation and storage to be performed in the same location, significantly reducing data transmission time. This allows for high energy efficiency, low power consumption, and a smaller size. These unique advantages make memristor-based EEG signal processing methods promising for the development of low-power, high-performance brain-computer interface devices. Summary of the Invention

[0005] At least one embodiment of the present disclosure provides a brain-computer interface device, which includes: a signal acquisition module, configured to acquire a first EEG signal generated by a target object and a second EEG signal generated after the target object receives feedback corresponding to the first EEG signal; a signal processing module, including a memristor array and coupled to the signal acquisition module, configured to process and decode the first EEG signal, and output a corresponding decoded signal for feedback to the target object to generate the second EEG signal, wherein the memristor array is configured to implement a decoding model; a detection module, coupled to the signal acquisition module, configured to detect whether there is an error-related potential signal in the second EEG signal; and a determination module, configured to determine whether to use the first EEG signal and the decoded signal to update the decoding model of the signal processing module based on the detection result.

[0006] For example, in the brain-computer interface device provided in at least one embodiment of the present disclosure, the signal processing module further includes a deployment module configured to deploy the decoding model onto the memristor array.

[0007] For example, in the brain-computer interface device provided in at least one embodiment of the present disclosure, the decoding model includes a neural network model or a machine learning model, and the memristor array is used to map the weight matrix of the decoding model.

[0008] For example, in the brain-computer interface device provided in at least one embodiment of the present disclosure, the first EEG signal includes steady-state visual evoked potential, motor imagery data, local field potential or cortical electroencephalogram.

[0009] For example, in the brain-computer interface device provided in at least one embodiment of the present disclosure, the determination module and the signal processing module are provided integrally.

[0010] At least one embodiment of the present disclosure provides a brain-computer interface system, including a brain-computer interface device as provided in at least one embodiment of the present disclosure.

[0011] For example, the brain-computer interface system provided by at least one embodiment of the present disclosure further includes: an effector, electrically connected to the signal processing module, and configured to be controlled by the decoded signal to perform corresponding operations.

[0012] For example, the brain-computer interface system provided by at least one embodiment of the present disclosure further includes: a feedback device, electrically connected to the signal processing module, configured to generate a feedback signal based on the decoded signal and feed it back to the target object.

[0013] For example, in the brain-computer interface system provided in at least one embodiment of the present disclosure, the feedback signal includes visual stimulation, electrical stimulation, tactile stimulation or olfactory stimulation.

[0014] For example, in the brain-computer interface system provided in at least one embodiment of the present disclosure, the feedback module includes a display, an electrical stimulator, a tactile device, or a gas release device.

[0015] At least one embodiment of the present disclosure provides an operating method for a brain-computer interface device as provided in at least one embodiment of the present disclosure, comprising: acquiring the first EEG signal generated by the target object; decoding the first EEG signal using the signal processing module to obtain the decoded signal; acquiring the second EEG signal generated by the target object receiving feedback on the decoded signal; determining whether the error-related potential signal exists in the second EEG signal, and in response to the absence of the error-related potential signal, updating the decoding model of the signal processing module using the first EEG signal and the decoded signal.

[0016] For example, in the operating method provided in at least one embodiment of the present disclosure, the decoding model includes a trained decoding model, and the trained decoding model is trained through the following steps: obtaining a set of training sample EEG signals and sample labels corresponding to the training sample EEG signals; inputting at least one training sample EEG signal in the training sample EEG signal set into the decoding model to be trained to obtain a predicted sample label; and adjusting the parameters of the decoding model to be trained based on the sample label corresponding to the at least one training sample EEG signal and the predicted sample label.

[0017] For example, in the operating method provided in at least one embodiment of the present disclosure, the use of the first EEG signal and the decoding signal to update the decoding model of the signal processing module includes: adjusting the parameters of the decoding model according to the first EEG signal and the decoding signal; updating the decoding model using the adjusted parameters of the decoding model; and updating the signal processing module according to the updated decoding model.

[0018] For example, in the operating method provided in at least one embodiment of the present disclosure, updating the signal processing module according to the updated decoding model includes: updating the conductance values ​​of multiple memristors in the memristor array of the signal processing module according to the weight matrix of the decoding model. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0020] FIG1 is a schematic block diagram of a brain-computer interface device according to at least one embodiment of the present disclosure;

[0021] FIG2 is a schematic block diagram of a brain-computer interface system provided by at least one embodiment of the present disclosure;

[0022] FIG3 is a schematic diagram of a brain-computer interface system provided by at least one embodiment of the present disclosure; and

[0023] FIG4 is a schematic flowchart of an operating method of a brain-computer interface device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0026] Error-related potentials (ErrPs) are a specific type of EEG signal that originates from the brain's inherent error response mechanism. They are typically triggered when an individual perceives and recognizes an operational error or an unexpected result. For example, when an unexpected result is displayed on a screen, the brain will naturally generate an ErrP signal as feedback. Therefore, ErrP signals play a crucial role in brain-computer interfaces and related fields.

[0027] A memristor element is a non-volatile device whose conductance state can be adjusted by applying an external stimulus. As a two-terminal device, a memristor element has adjustable resistance and is non-volatile. A memristor array includes multiple rows and columns of memristor cells. The memristor cells can have either a 1T1R or 2T2R structure. A 1T1R memristor cell includes a switch element and a memristor element, with the first terminal of the memristor element electrically connected to the first terminal of the switch element (e.g., the drain of a transistor). A 2T2R memristor cell includes two switch elements and two memristor elements.

[0028] Memristor elements can perform operations directly in the analog domain. For example, memristor elements can perform multiplication operations based on Ohm's law and addition operations based on Kirchhoff's current law. For example, according to Kirchhoff's law, by setting the state of the memristor element (for example, resistance) and applying corresponding word line signals and bit line signals to the word line and bit line, the above-mentioned memristor array can perform multiplication and accumulation calculations in parallel, and storage and calculation occur in each element of the array. Based on this computing architecture, storage and calculation can be achieved without the need for large-scale data movement. Therefore, memristors can be used to construct a signal processing module for a brain-computer interface device. For example, this signal processing module can process and decode EEG signals.

[0029] The present disclosure does not limit the type, structure, etc. of the memristor element. The memristor element used in the embodiments of the present disclosure may be, for example, a resistive random access memory, a phase change memory, a conductive bridge memory, or other memristor elements with the same characteristics. The switching element used in the embodiments of the present disclosure may be, for example, a thin film transistor, a field effect transistor, or other switching element with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be structurally identical.

[0030] Memristors demonstrate excellent energy efficiency and low power consumption in EEG signal processing. However, due to the inherent non-ideality of memristor devices, the accuracy achieved in EEG signal processing is still far from fully comparable to the corresponding software calculation results. In addition, the inherent relaxation effect of memristors can cause unpredictable drift in their conductance. At the same time, the EEG signals generated by the brain are inherently variable, meaning that for the same thought activity or behavioral intention (such as observing the same stimulus or performing the same action intention), different EEG signals will be generated at different times. These problems together make it impossible for the performance of the brain-computer interface system to always maintain optimal performance, thereby limiting the effectiveness of brain-computer interface technology in actual application environments.

[0031] At least one embodiment of the present disclosure provides a brain-computer interface device, which includes a signal acquisition module, a signal processing module, a detection module, and a determination module. The signal acquisition module is configured to acquire a first EEG signal generated by a target object and a second EEG signal generated after the target object receives feedback corresponding to the first EEG signal; the signal processing module includes a memristor array and is coupled to the signal acquisition module, and is configured to process and decode the first EEG signal, and output a corresponding decoded signal for feedback to the target object to generate a second EEG signal, wherein the memristor array is configured to implement a decoding model; the detection module is coupled to the signal acquisition module and is configured to detect whether there is an error-related potential signal in the second EEG signal; and the determination module is configured to determine whether to use the first EEG signal and the decoded signal to update the decoding model of the signal processing module based on the detection result.

[0032] The brain-computer interface device provided by at least one embodiment of the present disclosure can accumulate new EEG sample data during the interaction process by detecting the error-related potential signal as the response of the target object to the decoding signal. By updating the decoding model parameters in the signal processing module on the original basis, it effectively overcomes the natural variability of EEG activity and the potential impact of the memristor conductivity drift phenomenon on decoding accuracy. Furthermore, it realizes a brain-computer interface system with continuous improvement and even continuous improvement in performance, providing a foundation for the research and development of high-efficiency, high-performance brain-computer interface technology and people-oriented human-computer fusion applications.

[0033] The brain-computer interface device provided by the present disclosure is described below in a non-restrictive manner through multiple embodiments and examples. As described below, different features in these specific examples or embodiments can be combined with each other without conflicting with each other to obtain new examples or embodiments, and these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0034] FIG1 is a schematic block diagram of a brain-computer interface device provided by at least one embodiment of the present disclosure.

[0035] For example, as shown in FIG1 , the brain-computer interface device 10 provided in an embodiment of the present disclosure includes a signal acquisition module 11 , a signal processing module 12 , a detection module 13 , and a determination module 14 .

[0036] For example, as shown in FIG1 , the signal acquisition module 11 is configured to acquire a first EEG signal generated by the target object and a second EEG signal generated after the target object receives feedback corresponding to the first EEG signal.

[0037] For example, the signal acquisition module 11 may include EEG signal acquisition electrodes, a low-noise amplifier, a filter, an analog-to-digital converter, etc., and may directly or indirectly acquire EEG signals from a target object. For example, the target object may be a brain, such as a human brain or an animal brain.

[0038] For example, the first EEG signal can be a steady-state visual evoked potential (SSVEP), motor imagery data (MI), local field potential (LFP) or electrocorticography (ECoG), or any other type of EEG signal, or any combination of the above signals, and the present disclosure does not limit this.

[0039] For example, the first EEG signal can be generated spontaneously by the target subject's brain or induced, and this disclosure does not limit this. For example, spontaneous generation can be caused by the target subject's desire to control the movement of a robot or a mouse. For example, induced generation can be caused by visual stimulation or electrical stimulation of the target subject.

[0040] For example, as shown in Figure 1, the signal processing module 12 includes a memristor array and is coupled to the signal acquisition module 11, and is configured to process and decode the first EEG signal, and output a corresponding decoded signal for feedback to the target object to generate a second EEG signal, wherein the memristor array is configured to implement a decoding model.

[0041] For example, the decoding model includes a neural network model or a machine learning model, or may be any other type of decoding model, and the present disclosure does not limit this. For example, the neural network model may be a multilayer perceptron (MLP), a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network (DBN), etc., and the present disclosure does not limit this; the machine learning model may be a linear discriminant analysis (LDA), a support vector machine (SVM), a decision tree and random forest (Decision Tree and Random Forest), a hidden Markov model (HMM), etc., and the present disclosure does not limit this.

[0042] For example, the parameters of the decoding model may be pre-trained or randomly generated, and this disclosure does not impose any restrictions on this.

[0043] For example, a memristor array is used to map a weight matrix of a decoding model. For example, the conductance values ​​of multiple memristor units in the memristor array correspond to the weight matrix of a neural network. The memristor array calculates multiple input data to obtain multiple output values, and determines a decoding signal corresponding to the first EEG signal based on the multiple output values.

[0044] For example, the signal processing module 12 also includes a deployment module configured to deploy the decoding model on the memristor array. For example, the deployment module may include a programming verification circuit configured to perform programming verification on the memristor unit in the memristor array so that the conductance value of the memristor unit corresponds to the weight matrix of the decoding model. For example, the deployment module determines the mapped conductance value of the corresponding memristor unit in the memristor array based on the weight matrix of the decoding model, and writes the mapped conductance value to the memristor array; reads the conductance value of the memristor unit, compares the difference between the read conductance value of the memristor unit and the mapped conductance value to see if it is within a preset range, and if the difference between the read conductance value of the memristor unit and the mapped conductance value is not within the preset range, then continues to perform the above operations again until the difference between the read conductance value of the memristor unit and the mapped conductance value is within the preset range.

[0045] For example, the signal processing module 12 may also include peripheral circuits for performing some pre-processing calculations, such as converting vector multiplications that cannot be directly performed using the memristor array. For example, multiple memristors may be used to filter and Fourier transform the first EEG signal, and then perform neural network-based calculations on the filtered and / or Fourier transformed signal.

[0046] For example, as shown in FIG1 , the detection module 13 is coupled to the signal acquisition module 11 and is configured to detect whether an error-related potential signal exists in the second EEG signal.

[0047] For example, the detection module 13 may be in the form of a processor, microcontroller, single chip microcomputer, digital signal processor or field programmable gate array configured with an ERRP detection algorithm, or may be a dedicated detection hardware, which is not limited in the present disclosure.

[0048] For example, as shown in FIG1 , the determination module 14 is configured to determine whether to update the decoding model of the signal processing module using the first EEG signal and the decoding signal according to the detection result.

[0049] For example, according to the detection result generated by the detection module 13, if there is an error-related potential signal in the second EEG signal, it means that the decoding result is wrong; if there is no error-related potential signal in the second EEG signal, the decoding model of the signal processing module is updated using the first EEG signal and the decoding signal. For example, the decoding model can be updated after accumulating multiple groups of first EEG signals and decoding signals; or the decoding model can be updated using only one group of first EEG signals and decoding signals, and the present disclosure does not limit this. For example, the decoding model can be updated using transfer learning, incremental learning, etc., or the decoding model can be retrained using only newly obtained first EEG signals and decoding signal samples, and the present disclosure does not limit this. For example, when the parameters of the updated decoding model change relatively little compared to before the update, the decoding model may not be updated.

[0050] For example, the determination module 14 may be provided integrally with the detection module 13. For example, the determination module 14 may also be provided integrally with the signal processing module 12. For example, the functions of the determination module 14 may be implemented by a peripheral circuit in the signal processing module 12.

[0051] For example, the determination module 14 may be in the form of a processor, a microcontroller, a single chip microcomputer, a digital signal processor, or a field programmable gate array, etc., and the present disclosure does not limit this.

[0052] FIG2 is a schematic block diagram of a brain-computer interface system provided by at least one embodiment of the present disclosure.

[0053] For example, as shown in FIG2 , the brain-computer interface system 20 provided in an embodiment of the present disclosure includes the brain-computer interface device 10 provided in at least one embodiment of the present disclosure, and may also include an effector 21 and a feedback device 22 depending on the configuration.

[0054] For example, as shown in Figure 2, the effector 21 is electrically connected to the signal processing module and is configured to be controlled by the decoded signal to perform a corresponding operation. For example, the effector 21 can be a robotic arm, a brain-controlled robot, etc., which is not limited in this disclosure.

[0055] For example, as shown in Figure 2, the feedback device 22 is electrically connected to the signal processing module of the brain-computer interface device 10, and is configured to generate a feedback signal based on the decoded signal and feed it back to the target object. For example, the feedback signal can be visual stimulation, electrical stimulation, tactile stimulation or olfactory stimulation, or any other type of feedback signal that can induce an error-related potential signal, and the present disclosure does not limit this. For example, the feedback module can be a display, an electrical stimulator, a tactile device or a gas release device, or any other type of feedback module that can induce an error-related potential signal, and the present disclosure does not limit this.

[0056] FIG3 is a schematic diagram of a brain-computer interface system provided by at least one embodiment of the present disclosure.

[0057] For example, taking the steady-state visual evoked potential (SSVEP) as the first EEG signal, Figure 3 shows a brain-computer interface system using the SSVEP signal. SSVEP is a common EEG signal, usually induced by a visual stimulus block with a certain frequency. EEG signals with the same frequency as the input stimulus and multiple frequencies can be detected in specific areas such as the occipital lobe of the brain. Since the SSVEP signal has distinct characteristics and high information transmission efficiency, it has been widely used as an effective control signal in brain-computer interface technology.

[0058] For example, as shown in Figure 3, a display presenting a stimulus signal induces a first EEG signal comprising a steady-state visual evoked potential. For example, the display may contain multiple flickering blocks, with the first flickering block being in a flickering state. The signal acquisition module acquires the first EEG signal comprising a steady-state visual evoked potential generated by the target subject and feeds it into the signal processing module for processing and decoding. The module then outputs a corresponding decoded signal for controlling the effector device to perform a corresponding operation.

[0059] The decoded signal output by the signal processing module is also transmitted to the display, which serves as a feedback device. The display generates a visual feedback signal based on the decoded signal, providing visual stimulation to the target object. If the second blinking block on the display flickers under the control of the decoded signal, it indicates an error in the decoded signal, and the target object will generate an error-related potential signal. If the first blinking block on the display flickers under the control of the decoded signal, it indicates a correct decoded signal, and the target object will not generate an error-related potential signal.

[0060] The signal acquisition module acquires a second EEG signal containing a steady-state visual evoked potential signal generated by the target subject after receiving feedback corresponding to the first EEG signal. The detection module detects whether an error-related potential signal is present in the second EEG signal. The determination module determines, based on the detection result, whether to update the decoding model of the signal processing module using the first EEG signal and the decoded signal. For example, if the error-related potential signal is present in the second EEG signal, the decoding model of the signal processing module is not updated; if the error-related potential signal is not present in the second EEG signal, the decoding model of the signal processing module is updated.

[0061] FIG4 is a schematic flowchart of an operating method of a brain-computer interface device provided in at least one embodiment of the present disclosure.

[0062] For example, as shown in FIG4 , the operating method provided by the embodiment of the present disclosure includes the following steps S101 to S104 .

[0063] S101: Acquire a first EEG signal generated by a target object.

[0064] For example, the signal acquisition module provided in the above embodiment may be used to acquire the first EEG signal generated by the target object.

[0065] S102: Decoding the first EEG signal using a signal processing module to obtain a decoded signal.

[0066] For example, the first EEG signal may be decoded using a decoding module in the signal processing module. For example, the decoding model includes a trained decoding model, which is trained by the following steps S1021-S1023:

[0067] S1021: Obtain a set of training sample EEG signals and sample labels corresponding to the training sample EEG signals;

[0068] S1022: Inputting at least one training sample EEG signal in the training sample EEG signal set into the decoding model to be trained to obtain a predicted sample label;

[0069] S1023: Adjust the parameters of the decoding model to be trained according to the sample label and the predicted sample label corresponding to at least one training sample EEG signal.

[0070] S103: Acquire a second EEG signal generated by the target object receiving feedback on the decoded signal.

[0071] For example, the second EEG signal may be acquired using the signal acquisition module provided in the above embodiment.

[0072] S104: Determine whether there is an error-related potential signal in the second EEG signal, and in response to the absence of the error-related potential signal, update the decoding model of the signal processing module using the first EEG signal and the decoding signal.

[0073] For example, the detection module provided in the above embodiment can be used to determine whether an error-related potential signal is present in the second EEG signal. For example, the decoding model can be trained on a memristor array or other hardware circuit modules for training, and this disclosure does not limit this.

[0074] For example, in step S104, the following steps S1041 to S1043 are included:

[0075] S1041: Adjusting parameters of a decoding model according to the first EEG signal and the decoding signal;

[0076] S1042: Update the decoding model using the adjusted parameters of the decoding model;

[0077] S1043: Update the signal processing module according to the updated decoding model.

[0078] For example, the conductance values ​​of multiple memristors in the memristor array of the signal processing module are updated according to the weight matrix of the decoding model.

[0079] One or more embodiments of the present disclosure provide a brain-computer interface device and an operating method thereof, and a brain-computer interface system, which have one or more of the following beneficial effects:

[0080] (1) The brain-computer interface device provided by at least one embodiment of the present disclosure can accumulate new EEG sample data during the interaction process by detecting the error-related potential signal as the target object's response to the decoding signal. By updating the decoding model parameters in the signal processing module on the original basis, the potential impact of the natural variability of EEG activity and the conductance drift phenomenon of the memristor on the decoding accuracy is effectively overcome;

[0081] (2) The brain-computer interface device provided by at least one embodiment of the present disclosure implements a decoding model based on a memristor array, achieves computation and storage at the same location, significantly reduces the time required for data transmission, and thus exhibits the advantages of high energy efficiency, low power consumption, and smaller size;

[0082] (3) The performance of the brain-computer interface system provided by at least one embodiment of the present disclosure is continuously improved or even continuously enhanced, providing a foundation for the research and development of high-efficiency, high-performance brain-computer interface technology and human-centered human-computer fusion applications.

[0083] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, it will be apparent to those skilled in the art that modifications or improvements may be made based on the embodiments of the present disclosure. Therefore, such modifications or improvements, as long as they do not depart from the spirit of the present disclosure, are within the scope of protection claimed by the present disclosure.

[0084] Regarding this disclosure, the following points need to be explained:

[0085] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0086] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale.

[0087] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0088] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A brain-computer interface device, comprising: A signal acquisition module configured to acquire a first electroencephalogram signal generated by a target object and a second electroencephalogram signal generated by the target object after receiving feedback corresponding to the first electroencephalogram signal; A signal processing module including a memristor array and coupled to the signal acquisition module, configured to process and decode the first electroencephalogram signal and output a corresponding decoded signal for feedback to the target object to generate the second electroencephalogram signal, wherein the memristor array is configured to implement a decoding model; A detection module coupled to the signal acquisition module, configured to detect whether there is an error-related potential signal in the second electroencephalogram signal; A determination module configured to determine whether to update the decoding model of the signal processing module using the first electroencephalogram signal and the decoded signal according to the detection result.

2. The brain-computer interface device according to claim 1, wherein The signal processing module further includes a deployment module configured to deploy the decoding model onto the memristor array.

3. The brain-computer interface device according to claim 1 or 2, wherein, The decoding model includes a neural network model or a machine learning model, and the memristor array is used to map the weight matrix of the decoding model.

4. The brain-computer interface device according to any one of claims 1-3, wherein, The first electroencephalogram signal includes a steady-state visual evoked potential, motor imagery data, a local field potential, or an electrocorticogram.

5. The brain-computer interface device according to any one of claims 1-4, wherein, The determination module is provided integrally with the signal processing module.

6. A brain-computer interface system, comprising the brain-computer interface device according to any one of claims 1-5.

7. According to the brain-computer interface system of claim 6, further comprising: An effector electrically connected to the signal processing module, configured to be controlled by the decoded signal to perform corresponding operations.

8. According to the brain-computer interface system of claim 6 or 7, further comprising: A feedback device electrically connected to the signal processing module, configured to generate a feedback signal according to the decoded signal and feedback it to the target object.

9. The brain-computer interface system according to claim 8, wherein, The feedback signal includes a visual stimulus, an electrical stimulus, a tactile stimulus, or an olfactory stimulus.

10. The brain-computer interface system according to claim 8 or 9, wherein The feedback module includes a display, an electrical stimulator, a tactile device, or a gas release device.

11. An operation method for the brain-computer interface device according to any one of claims 1-5, comprising: Acquiring the first electroencephalogram signal generated by the target object; Decoding the first electroencephalogram signal using the signal processing module to obtain the decoded signal; Acquiring the second electroencephalogram signal generated by the target object after receiving feedback for the decoded signal; Judging whether there is the error-related potential signal in the second electroencephalogram signal, and in response to the absence of the error-related potential signal, updating the decoding model of the signal processing module using the first electroencephalogram signal and the decoded signal.

12. The operating method according to claim 11, wherein, The decoding model includes a trained decoding model, and the trained decoding model is obtained by training through the following steps: Acquiring a set of training sample electroencephalogram signals and sample labels corresponding to the training sample electroencephalogram signals; Inputting at least one training sample electroencephalogram signal in the set of training sample electroencephalogram signals into a decoding model to be trained to obtain a predicted sample label; Adjusting the parameters of the decoding model to be trained according to the sample labels corresponding to the at least one training sample electroencephalogram signal and the predicted sample label.

13. The operating method according to claim 11 or 12, wherein, Updating the decoding model of the signal processing module by using the first EEG signal and the decoding signal includes: Adjusting the parameters of the decoding model according to the first EEG signal and the decoding signal; Updating the decoding model by using the adjusted parameters of the decoding model; Updating the signal processing module according to the updated decoding model.

14. The operating method according to any one of claims 11-13, wherein, The updating the signal processing module according to the updated decoding model includes: Updating the conductance values of multiple memristors in the memristor array of the signal processing module according to the weight matrix of the decoding model.

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