Balancing of the intermediate circuit voltage components of a 3-level npc network converter

Abstract

The invention relates to a balancing method (1) for balancing voltage components (UDC1, UDC1) of electrical capacitors (6, 7) on the DC voltage circuit (2) of a multi-level converter (3) comprising a rectifier (33), wherein the rectifier (33) is operated between an AC voltage network (5) and the DC voltage circuit (2), wherein a first capacitor (6) and a second capacitor (7), which is electrically connected in series with the first capacitor (6), said capacitors forming a symmetry point (22), are operated at a DC voltage (UDC) between a first and second DC voltage phase (DC+, DC-) of the DC voltage circuit (2), wherein a harmonics-impacted additional current value (IZ) is applied to an active current reference value (IWsoll) for an active current (IW) of the AC voltage network (5) and a first voltage component (UDC1) of the DC voltage (UDC) at the first capacitor (6) and / or a second voltage component (UDC2) of the DC voltage (UDC) at the second capacitor (7) are / is varied on the basis of the harmonics-impacted additional current value (IZ) at the symmetry point (22) so as to generate symmetry between the first voltage component (UDC1) and the second voltage component (UDC2). The invention furthermore relates to a balancing device (11) for performing the balancing method (1) and to a multi-level converter (3) comprising the balancing device (11).

Description

[0001] SYMMETRATION OF THE PARTIAL DC LINK VOLTAGES OF A 3-POINT NPC MAINS CONVERTER

[0002] Description

[0003] The invention relates to a balancing method for balancing partial voltages of electrical capacitors on the DC voltage circuit of a multilevel converter with a rectifier, wherein the rectifier is operated between an AC voltage network and the DC voltage circuit, wherein a first capacitor and a second capacitor electrically connected in series with the first capacitor, which form a symmetry point, are operated at a DC voltage between a first and second DC voltage phase of the DC voltage circuit, and wherein a first partial voltage of the DC voltage is generated across the first capacitor and a second partial voltage of the DC voltage is generated across the second capacitor. Furthermore, the invention relates to a balancing device for carrying out the balancing method and to a multilevel converter with the balancing device.

[0004] Frequency converters which provide more than two voltage levels - also called voltage stages - on their DC voltage circuit - also known as DC intermediate circuit - and in this context are also referred to as multilevel converters, have at least two DC circuit capacitors connected in series between the DC voltage phases of the DC circuit and forming a total capacitance.

[0005] A partial voltage drops across each of these capacitors, the sum of which forms the DC voltage in the DC circuit. Due to manufacturing tolerances of the capacitors, for example, as well as wear and tear due to aging, a divergence of the partial voltages across the capacitors is often to be expected. As a result, undesirably high partial voltages occur on at least some of the capacitors, which can damage or even destroy the affected capacitors.

[0006] The divergence of the partial voltages also means that the voltage setpoint for the desired voltage levels on the DC voltage circuit can only be output in a distorted manner and cannot be output precisely.

[0007] Accordingly, equal voltage values ​​in the upper and lower halves of the DC circuit should be aimed for, both in order to avoid overvoltage on the capacitors of the DC circuit - as well as for the correct setting of, for example, the AC-side mains voltage of the input voltage of the rectifier.

[0008] It is therefore necessary to provide means which, when the converter is in operation, symmetrically balance the partial voltages across the capacitors, i.e. continuously adjust them to one another, in order to prevent an undesirable increase in these partial voltages or their drifting apart.

[0009] The balancing of the partial voltages can be achieved with the help of a balancing regulator, which ensures that the individual voltage levels on the DC circuit have the same voltage value.

[0010] However, a corresponding control intervention of previously known balancing controllers influences the so-called zero system of the affected voltage system in an undesirable manner, such as that of the AC-side mains voltage system.

[0011] Using a conventional space vector modulation to generate the switching signals for the power semiconductor switches of the rectifier, the zero system is formed on the AC-side mains voltage system, for example, in such a way that, for a given intermediate circuit voltage on the DC voltage circuit, the maximum possible interlinked voltage of the AC-side mains voltage can be output.

[0012] By means of an offset generated in the zero-system, the common-mode voltage of the line voltages of this AC-side mains voltage system can be shifted.

[0013] With a 3-level converter, for example, it is possible to charge the capacitor in the upper half of the DC circuit more strongly and thus increase its partial voltage compared to the capacitor in the lower half of the DC circuit if the offset in the zero-system - with positive active power - assumes a positive value.

[0014] In discontinuous modulation methods or flat modulation methods, the offset of the zero-sequence system can be selected so that individual phases of a bridge circuit of the rectifier are not switched at specific times. In these cases, a reduction in switching losses in the power semiconductor switches can be achieved, for example, in the area of ​​a maximum current of a mains phase of the AC-side mains voltage system. A disadvantage in this context, however, is that the zero-sequence system can no longer be provided as a manipulated variable for balancing the partial voltages in the DC circuit, or only to a limited extent.

[0015] The choice of, for example, flat modulation to minimize the power loss of the rectifier or to optimize a common mode disturbance therefore contradicts an optimal choice of the modulation type, which would be given for balancing or symmetrizing the partial voltages across the capacitors in the DC voltage circuit, whereby the manipulated variable of the zero-system system does not meet the various control objectives.

[0016] Currently, for example, hysteresis controllers are used which switch between top and bot modulation and in doing so generate large disturbance excitations, for example in the common mode system.

[0017] Another possibility, which is also based on the zero system as a manipulated variable, results from influencing switching times between a top modulation and a bottom modulation of the flat modulation, whereby one of the mentioned variants is then active for a longer time.

[0018] The invention is based on the object of proposing a symmetrization method for the symmetrization of partial voltages of electrical capacitors on the DC voltage circuit of a multilevel converter with a rectifier, which is improved compared to the prior art, and in connection therewith a symmetrization device for carrying out the symmetrization method and a multilevel converter with the symmetrization device.

[0019] The object is achieved by a balancing method having the features specified in claim 1, a balancing device for carrying out the balancing method according to the features specified in claim 13 and a multilevel converter having the balancing device according to the features specified in claim 15.

[0020] To solve the problem, a symmetrization method for symmetrizing partial voltages of electrical capacitors on the DC voltage circuit of a multilevel converter with a rectifier is proposed, wherein the rectifier is operated between an AC voltage network and the DC voltage circuit, wherein a first capacitor and a second capacitor electrically connected in series with the first capacitor, which form a symmetry point, are operated between a first and second DC voltage phase of the DC voltage circuit at a DC voltage,wherein an active current setpoint for an active current of the AC voltage network is subjected to a harmonic additional current value and a first partial voltage of the DC voltage at the first capacitor and / or a second partial voltage of the DC voltage at the second capacitor is / are changed depending on the harmonic additional current value at the symmetry point to generate a symmetry between the first partial voltage and the second partial voltage.

[0021] The at least two capacitors - the first and the second capacitor - form a total capacitance in the DC voltage circuit, whereby the division into further capacitors to form the total capacitance is possible and the symmetrization of the respective partial voltages of the capacitors used takes place according to the symmetrization method at the symmetry point.

[0022] Multilevel converters often have, as designs of their rectifiers, in addition to a first bridge circuit - for example a six-pulse bridge circuit - a further switching device - for example in the form of a first bidirectional switching device - which supports the setting of the voltage level of the multilevel converter on the DC voltage circuit.

[0023] The balancing method according to the invention is used for various types of multilevel converters, for example for multilevel converters which can feed energy back from the DC voltage circuit into the AC voltage network by means of the rectifier or not when using a known Vienna rectifier, for example, for T-type multilevel converters and for NPC (Neutral Point Clamped) multilevel converters.

[0024] By means of the rectifier of the multilevel converter - provided the first bridge circuit of the rectifier has power semiconductor switches - electrical energy can be fed back from the DC circuit into the AC network. The rectifier also provides the option of intervening in the AC voltage on the AC network on the input side of the multilevel converter in order to obtain the desired DC voltage in the DC circuit. The symmetry of the partial voltages at the electrical capacitors in the DC circuit influences the quality of the DC voltage to be regulated in the DC circuit and, when the electrical energy is fed back into the AC network, also influences its AC voltage, since an asymmetry of these partial voltages generally causes distortion in the output of setpoints for the DC voltage applied to the DC circuit.

[0025] Furthermore, the symmetry of the partial voltages achieved by the symmetry process prevents overvoltages on the capacitors of the DC circuit, since an inadmissible increase in one of the partial voltages is compensated and thus prevented by the adjustment of the other partial voltages.

[0026] The proposed symmetrization method advantageously uses the active current setpoint of the AC voltage network for the symmetrization of the partial voltages in a control which determines the energy provision at the multilevel converter depending on the operating mode feed-in vs. feed-in, in order to increase or reduce the respective partial voltages at the capacitors in the DC voltage circuit by applying the additional current value with harmonics until the symmetry of the partial voltages is established or restored.

[0027] The zero system of the AC voltage system, which can be specified for the control of the rectifier to provide the electrical energy of the multilevel converter, e.g. by means of particularly suitable flat-top modulation or flat-middle modulation for power semiconductor switches of the first bridge circuit of the rectifier, is not influenced by the symmetrization method in the sense of its intended function, since a voltage modulation via the active current setpoint and the application of the harmonic additional current value takes place in phase with the zero system of the AC voltage.

[0028] Advantageous embodiments of the synchronization method are specified in the dependent claims.

[0029] In a first advantageous embodiment of the balancing method, the harmonic-affected additional current value is set as a function of a voltage difference between the partial voltages determined using a difference-forming element. The difference-forming element therefore advantageously determines the voltage difference between the partial voltages—if present—which is then compensated for by applying the harmonic-affected additional current value to the active current setpoint.

[0030] In a further advantageous embodiment of the symmetrization method, the harmonic-affected additional current value is formed as a function of at least three times a grid frequency or a grid angle of the AC voltage grid.

[0031] With three times the mains frequency of the alternating voltage, which can be converted into the mains angle of the alternating voltage, an improved effect of the symmetrization method is advantageously achieved, since undesirable side effects with regard to generated harmonic components in the current of the alternating voltage network are reduced or a harmonic ripple of the direct voltage on the direct voltage circuit is at least reduced.

[0032] The conversion of the grid angle from the grid frequency can be calculated from the following relationship (p = f N *t, where (p is the net angle, f N is the grid frequency and t is time. The grid angle can be determined, for example, over a period of the alternating voltage of the AC grid in an alpha / beta coordinate system—also called a Clarke transformation or stator-fixed transformation system.

[0033] In a further advantageous embodiment of the symmetrization method, the harmonic additional current value is designed as a rectangular function or sine function or cosine function or as a combination of sine function and cosine function with at least 3 times the mains frequency or the mains angle of the AC voltage network.

[0034] In addition to the characteristic of the additional current value with harmonics at three times the mains frequency of the alternating voltage, this design also advantageously results in an improved effect of the symmetrization method, since the undesirable side effects with regard to generated harmonic components in the current of the alternating voltage network are also reduced and a harmonic ripple of the direct voltage on the direct voltage circuit is also reduced.

[0035] In a further advantageous embodiment of the symmetrization method, the harmonic-affected additional current value formed with at least 3 times the mains frequency or the mains angle of the AC voltage network as a sine function or as a cosine function or as a combination of sine function and cosine functions has an odd power, in particular a third power, of the sine function or the cosine function or the combination of sine function and cosine functions.

[0036] In addition to the expression of the harmonic additional current value with three times the mains frequency of the AC voltage and the odd power of the sine function or the cosine function or the combination of sine function and cosine functions, this advantageous embodiment of the symmetrization method further advantageously results in an improved effect of the symmetrization method, since the undesirable side effects with regard to generated harmonic components in the current of the AC voltage network are also reduced and a harmonic ripple of the DC voltage on the DC voltage circuit is also reduced.

[0037] In a further advantageous embodiment of the symmetrization method, the harmonic-affected additional current value depends on a zero-sequence system voltage of the AC voltage network.

[0038] The zero-sequence system voltage of the AC network is generally generated by the first bridge circuit of the rectifier using its power semiconductor switch. The harmonic-affected additional current value should preferably be applied to the active current setpoint in proportion to the zero-sequence system voltage of the AC network.

[0039] The symmetrization method can be used particularly effectively with modulation methods such as pulse width modulation (PWM), which specify the zero-sequence system using, for example, flat-top modulation or flat-middle modulation. These modulation types can significantly reduce the switching losses of switchable power semiconductors by selecting a suitable offset in the zero-sequence system.

[0040] Accordingly, the additional current value affected by harmonics depends on the zero-sequence system voltage, but should not influence the zero-sequence system itself or its advantages, or should not influence them significantly.

[0041] In a further advantageous embodiment of the balancing method, the harmonic-affected additional current value is signed depending on the active power fed into the rectifier via the active current or, if possible, fed back into the grid. The sign of the harmonic-affected additional current value means that the balancing of the partial voltages at the capacitors of the DC circuit is advantageously used both for the operation of the multilevel converter's rectifier when feeding active power into the DC circuit (rectifier operation) and, if possible, when feeding active power back into the AC grid (inverter operation).

[0042] In a further advantageous embodiment of the symmetrization method, the additional current value subject to harmonics is formed at least by means of a proportional gain of a proportional controller.

[0043] In a further advantageous embodiment of the symmetrization method, the harmonic additional current value is added to the active current setpoint as the harmonic additional current value to be added.

[0044] If a sign of the harmonic additional current value is provided, this is taken into account when adding the harmonic additional current value to the active power setpoint in order to represent the operation of feeding in the active power vs. - if possible - feeding back the active power.

[0045] In a further advantageous embodiment of the symmetrization method, the harmonic additional current value is multiplied by means of a normalization element as the harmonic additional current value to be multiplied by the active current setpoint.

[0046] If a sign of the harmonic additional current value is provided, this is taken into account when multiplying the harmonic additional current value with the active power setpoint in order to represent the operation of feeding in the active power vs. - if possible - feeding back the active power.

[0047] In a further advantageous embodiment of the balancing method, the active current setpoint for the active current in the AC network, which is subject to the harmonics-affected additional current value, is determined using a d / q transformation. The d / q transformation, also called Park transformation or rotor-fixed transformation, is often used, for example, for a space vector model in PWM modulation types to convert three-phase electrical quantities of a three-phase system into a two-axis coordinate system with the axes d (d component, e.g., the excitation current of an electrical machine) and q (q component, e.g., the torque-generating current of the electrical machine).

[0048] It should be noted that, for example, a 3-fold harmonic in an electrical network causes a "back-turn" around a fundamental frequency by means of the d / q transformation, whereby the 3-fold harmonic is converted into at least a 2-fold harmonic in the d / q system.

[0049] At this point, it is advantageous for the balancing procedure to apply the harmonic-affected additional current value to the active current setpoint (here the d-component of the current).

[0050] In a further advantageous embodiment of the symmetrization method, the active current setpoint value to which the additional current value subject to harmonics is applied is determined by means of an alpha / beta transformation or by means of a complex calculation of the AC voltage network, which is in particular three-phase.

[0051] In addition to the use of the d / q transformation to apply the harmonic-affected additional current value to the active current setpoint, other transformation types such as the alpha / beta transformation, also called Clarke transformation or stator-fixed transformation, or a complex calculation of the AC voltage network as a three-phase system with the respective predeterminable active current setpoint can be used advantageously.

[0052] To achieve this objective, a balancing device—configured to implement the balancing method according to the invention—is further proposed, comprising the rectifier of the multilevel converter and the first and second capacitors on the DC voltage circuit. The rectifier is electrically interconnectable between the AC voltage network and the DC voltage circuit for operation, and the first capacitor, electrically interconnected in series with the second capacitor, is electrically connected between the first and second DC voltage phases of the DC voltage circuit. In a first advantageous embodiment of the balancing device, the balancing device comprises a computing unit with a balancing controller configured to implement the balancing method.

[0053] To achieve the object, a multilevel converter with the balancing device according to the invention is further proposed, which is designed for operation of an electrical consumer or an electrical generator or an electrical network on an AC voltage network.

[0054] The symmetrizing device for carrying out the symmetrizing method according to the invention can be used advantageously independently for multilevel converters, regardless of whether, for example, an electrical machine driven as a motor for a mechanical load is used as a consumer or an electrical machine driven as a generator by a mechanical load or an electrical network without concrete proof of the origin of an electrical load is used as a generator.

[0055] In all these cases, the partial voltages of the capacitors on the DC circuit are symmetrical according to the symmetry method and the set zero voltage system of the AC network is not influenced or only influenced to a non-significant extent.

[0056] The above-described properties, features, and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more readily understood in connection with the following description of the embodiments, which are explained in more detail in conjunction with the figures. It shows:

[0057] FIG 1 is a schematic representation of the balancing method according to the invention, carried out with a balancing device of a multilevel converter,

[0058] FIG. 2 shows a first schematic representation of a balancing controller of the balancing device for carrying out the balancing method according to the invention as shown in FIG. 1, FIG. 3 shows a further schematic representation of the balancing controller of the balancing device for carrying out the balancing method according to the invention as shown in FIG. 1 and

[0059] FIG. 4 shows a schematic diagram of signal waveforms for the balancing method according to the invention shown in FIG. 1. FIG. 1 shows the schematic representation of the balancing method 1 according to the invention, carried out with a balancing device 11 of a multilevel converter 3.

[0060] The multilevel converter 3 has a rectifier 33, a DC voltage circuit 2, often also referred to as a DC voltage intermediate circuit, and, for the exemplary embodiment, an inverter 34.

[0061] Furthermore, the rectifier 33 has a first bridge circuit 4 - here a B6 bridge - and a first bidirectional switching device 8 and the inverter 34 has a second bridge circuit 19 - here another B6 bridge - and a second bidirectional switching device 27.

[0062] The multilevel converter 3 is operated on the input side from an AC voltage network 5, which in the exemplary embodiment is designed as a three-phase system with AC voltage phases L1, L2, L3. The AC voltage U1 is applied to the AC voltage phase L1, the AC voltage UL2 is applied to the AC voltage phase L2, and the AC voltage UL3 is applied to the AC voltage phase L3. The AC voltage phases L1, L2, L3 are connected on the input side of the rectifier 33 to its first bridge circuit 4 and its first bidirectional switching device 8.

[0063] The DC voltage UDC is applied to the first DC voltage phase DC+ and the second DC voltage phase DC- of the DC voltage circuit 2, with a direct current I DC flowing through the DC voltage phases DC+ and DC-. The DC voltage circuit 2 is electrically connected on the input side to the first bridge circuit 4 of the rectifier 33 and on the output side to the second bridge circuit 19 of the inverter 34.

[0064] On the output side, the inverter 34 has a three-phase system with alternating voltage phases U, V, W, which are connected to an electrical consumer 13, e.g. a motor-driven electrical machine 24, an electrical generator 23, e.g. the generator-driven electrical machine 24 or an electrical network 14.

[0065] On the output side of the inverter 34 and the multilevel converter 3, the alternating voltage Uu is present on the alternating voltage phase U, the alternating voltage Uv is present on the alternating voltage phase V, and the alternating voltage Uw is present on the alternating voltage phase W. The alternating voltage phases U, V, W are connected on the output side of the inverter 34 to its second bridge circuit 19 and its second bidirectional switching device 27.

[0066] The specific electrical load of the electrical network 14 (fed-in electrical network 14 or regenerating electrical network 14) is shown here in an indeterminate manner.

[0067] Both the first bridge circuit 4 and the first bidirectional switching device 8 of the rectifier 33, as well as the second bridge circuit 19 and the second bidirectional switching device 27 of the inverter 34, each have power semiconductor switches 10 in FIG. 1. In the embodiment of FIG. 1, these are arranged and designed as a six-pulse bridge circuit (B6 bridge).

[0068] The respective arrangement and design of the power semiconductor switches 10 for the first bridge circuit 4 of the rectifier 33, as well as for the second bridge circuit of the inverter 34, accordingly each comprise top power semiconductor switches 20 (upper power semiconductor switches) and bottom power semiconductor switches 21 (lower power semiconductor switches) of the respective six-pulse bridge circuit.

[0069] In particular, if the first bridge circuit 4 of the rectifier 33 - as shown in FIG 1 - is designed with power semiconductor switches 10, it is possible to feed energy back from the DC voltage circuit 2 into the AC voltage network 5.

[0070] However, the first bridge circuit 4 of the rectifier 33 can have power diodes instead of the power semiconductor switches 10, thus being operated as a diode bridge circuit (not shown in FIG. 1), so that the multilevel converter is used by means of a Vienna rectifier - using the balancing method according to the invention.

[0071] The DC voltage circuit 2 has two capacitors 6, 7 connected in series between the DC voltage phases DC+, DC- - a first capacitor 6 and a second capacitor 7 - which together form a symmetry point 22.

[0072] The first partial voltage UDCI of the direct voltage UDC drops across the first capacitor 6, and the second partial voltage UDC2 of the direct voltage UDC of the direct voltage circuit 2 drops across the second capacitor 7. The alternating voltage phases L1, L2, L3 of the alternating voltage network 5 are electrically connected on the input side of the multilevel converter 3 to the first bidirectional switching device 8 of the rectifier 33 (on the input side of the first bidirectional switching device 8), with the first bidirectional switching device 8 being connected on the output side to the symmetry point 22 by means of an electrical star point connection.

[0073] The alternating voltage phases U, V, W of the electrical consumer 13 or the electrical generator 23 or the electrical network 14 are electrically connected on the output side of the multilevel converter 3 to a second bidirectional switching device 27 of the inverter 34 (output side of the second bidirectional switching device 27), wherein the second bidirectional switching device 27 is connected on the input side to the symmetry point 22 by means of an electrical star point connection.

[0074] Both the first and the second bidirectional switching device 8, 27 comprise power semiconductor switches, wherein the bidirectional switching devices 8, 27 are designed to set a voltage level for the multilevel converter 3 at the symmetry point 22 and to generate a harmonic current value l formed by one of the harmonic additional current values ​​Izmod zadd z to symmetry point 22.

[0075] The multilevel converter 3 can be operated from the AC voltage network 5 as a feed-in for the electrical consumer 13 or the electrical network 14. In contrast, the multilevel converter 3 can be operated from the electrical generator 23 or the electrical network 14 in FIG. 1 as a feed-in to the AC voltage network 5.

[0076] Starting from the operation of feed-in vs. - as far as possible - feed-back of the multilevel converter 3, and thus of the rectifier 33, the balancing method 1 and the balancing device 11 carrying out the balancing method 1 are considered as an example using the feed-in of electrical energy.

[0077] The harmonic additional current value lz acts on the active current setpoint Iwsoii for an active current Iw to be achieved, whereby the active current setpoint Iwsoii is multiplied by the harmonic additional current value Izmod - as harmonic additional current value lz - or the harmonic additional current value Izadd - as harmonic additional current value l z - depending on a determined voltage difference AUDCI2 of the partial voltages UDCI, UDC2 was applied to the respective capacitors 6, 7 of the DC voltage circuit 2. Depending on the determined voltage difference AUDCI2, the first capacitor 6 or the second capacitor 7 is charged by means of the harmonic additional current value lz in such a way that a symmetry of the two partial voltages UDCI, UDC2 of the DC voltage UDC is established on the DC voltage circuit 2.

[0078] The multilevel converter according to FIG. 1 has a computing unit 12, which determines control signals for the power semiconductor switches 10 of both the first bridge circuit 4 of the rectifier 33 and the second bridge circuit 19 of the inverter 34 and transmits them to the power semiconductor switches 10. Furthermore, control signals for the power semiconductor switches of the bidirectional switching devices 8, 27 of the rectifier 33 and the inverter 34 are also determined by the computing unit 12 and transmitted to their respective power semiconductor switches.

[0079] The computing unit 12 has a symmetrization controller 15, which adjusts the active current setpoint Iwsoii of the active current l w the harmonic additional current value Izmod to be multiplied or the harmonic additional current value l to be added Zadd depending on a determined voltage difference AUDCI2 of the partial voltages UDCI , UDC2 at the respective capacitors 6,7 as harmonic additional current value l z determined and used to adjust the symmetry of the partial voltages UDCI, UDC2.

[0080] FIG. 2 shows a first schematic representation of a balancing controller 15 of the balancing device 11 for carrying out the balancing method according to the invention as shown in FIG. 1.

[0081] In the embodiment of FIG 2, the symmetrization controller 15 forms the harmonic additional current value Izmod which is subsequently to be multiplied by the active current setpoint (not shown here), whereby the current value dependent on the harmonic additional current value is generated as a result (not shown here).

[0082] For this purpose, the symmetrization controller 15 has a multiplication element 29 which multiplies several input variables with one another.

[0083] A first input variable determines a 3-fold of the mains frequency f N or the net angle (p N of the AC voltage network 5 as an argument of a rectangular function 16, a cosine function 17 or a sine function 25 or the argument of an odd power 18 of the cosine function 17, the sine function 25 or the combination 26 of sine function and cosine function.

[0084] A second input variable determines a difference forming element 32 for determining the voltage difference AUDCI2 of the partial voltages UDCI, UDC2 at the capacitors of the DC voltage circuit.

[0085] A third input variable determines a proportional component KP for a proportional controller P.

[0086] A fourth input variable determines a sign element 30, which indicates whether the feed-in or - as far as possible - the feedback is operated for the symmetrization of the partial voltages UDCI, UDC2 at the respective capacitors of the DC voltage circuit of the multilevel converter or, for example, the rectifier.

[0087] The result of the multiplication of the four input variables from the multiplication element 29 is added to a normalization element N by means of an adder 28, whereby the additional current value l which is subject to harmonics and is to be multiplied by the active current setpoint Zm od is generated.

[0088] FIG. 3 shows a further schematic representation of a symmetrization controller 15 of the symmetrization device 11 for carrying out the symmetrization method according to the invention according to FIG. 1, which is to be considered essentially analogous to FIG. 2.

[0089] In the embodiment of FIG 3, the symmetrization controller 15 forms the harmonic additional current value Izadd to be added to the active current setpoint (not shown here), whereby the current value dependent on the harmonic additional current value is generated as a result (not shown here).

[0090] For this purpose, the symmetrization controller 15 has a multiplication element 29 which multiplies several input variables with one another.

[0091] A first input variable determines a 3-fold of the mains frequency f N or the grid angle q>N of the AC voltage network 5 as an argument of a rectangular function 16, a cosine function 17 or a sine function 25 or the argument of an odd power 18 of the cosine function 17, the sine function 25 or the combination 26 of sine function and cosine function.

[0092] A second input variable determines a difference forming element 32 for determining the voltage difference AUDCI2 of the partial voltages UDCI, UDC2 at the capacitors of the DC voltage circuit.

[0093] A third input variable determines a proportional component KP for a proportional controller P.

[0094] A fourth input variable determines a sign element 30, which indicates whether the feed-in or - as far as possible - the feedback is operated for the symmetrization of the partial voltages UDCI, UDC2 at the respective capacitors of the DC voltage circuit of the multilevel converter or, for example, the rectifier.

[0095] The result of the multiplication of the four input variables of the multiplication element 29 generates the harmonic additional current value Izadd- to be added to the active current setpoint.

[0096] FIG 4 visualizes a schematic diagram representation of signal curves for the symmetrization method according to the invention according to FIG 1.

[0097] The first sub-diagram shows, over a time t, current waveforms I of determined signal waveforms 9 of the additional current value Izmod with harmonics to be multiplied or the additional current value Izadd with harmonics to be added, as well as the current value lz dependent on the additional current value with harmonics, based on the rectangular function 16, the cosine function 17 and the odd power of the cosine function (here the 3rd power) in conjunction with their respective arguments as 3 times 31 of the mains frequency or the mains angle >N of the AC voltage network.

[0098] The second sub-diagram shows the voltage curves U of the alternating voltages ULI, UL2, UL3 over time t as well as a set zero-sequence system voltage UN on the alternating voltage network on the input side of the multilevel converter or the regulated rectifier.

[0099] The third part of the diagram shows an angle progression (p of the network angle (p N for one period of alternating voltages ULI, UL2, UL3-

Claims

Patent claims 1. Symmetrization method (1) for symmetrizing partial voltages (UDCI ,UDCI) of electrical capacitors (6,7) on the DC voltage circuit (2) of a multilevel converter (3) with a rectifier (33), wherein - the rectifier (33) is operated between an alternating voltage network (5) and the direct voltage circuit (2), - a first capacitor (6) and a second capacitor (7) electrically connected in series with the first capacitor (6), which form a symmetry point (22), are operated at a direct voltage (UDC) between a first and second direct voltage phase (DC+, DC-) of the direct voltage circuit (2), - an active current setpoint (Iwsoii) for an active current (Iw) of the AC voltage network (5) is subjected to a harmonic additional current value (lz) and - a first partial voltage (UDCI) of the direct voltage (UDC) at the first capacitor (6) and / or a second partial voltage (UDCZ) of the direct voltage (UDC) at the second capacitor (7) as a function of the additional current value (l) with harmonics z ) at the symmetry point (22) to generate a symmetry between the first partial voltage (UDCI) and the second partial voltage (UDCZ).

2. Symmetrization method (1) according to claim 1, wherein the harmonic additional current value (lz) is set as a function of a voltage difference (AUDCI2) of the partial voltages (UDCI, UDC2) determined by a difference forming element (32).

3. Symmetry method (1) according to one of claims 1 or 2, wherein the harmonic additional current value (lz) is formed as a function of at least 3 times (31) a mains frequency (frsi) or a mains angle (cp) of the AC voltage network (5).

4. Symmetrization method (1) according to claim 3, wherein the harmonic additional current value (lz) is formed with at least 3 times (31) the mains frequency (frsi) or the mains angle (cp) of the AC voltage network (5) as a rectangular function (16) or sine function (25) or cosine function (17) or as a combination (26) of sine function and cosine function.

5. Symmetry method (1) according to claim 4, wherein the frequency (31) at least three times the mains frequency (f N ) or the network angle (cp) of the AC voltage network (5) as a sine function (25) or as a cosine function (17) or as a combination (26) of sine function and cosine functions, the additional current value (lz) subject to harmonics has an odd power (18), in particular a third power, of the sine function (25) or the cosine function (17) or the combination (26) of sine function and cosine functions.

6. Symmetry method (1) according to one of claims 3 to 5, wherein the harmonic additional current value (lz) is dependent on a zero-sequence system voltage (UN) of the AC voltage network (5).

7. Symmetry method (1) according to one of the preceding claims, wherein the harmonic additional current value (lz) is signed as a function of an active power fed in or - if possible - fed back to the rectifier (33) by means of the active current (Iw).

8. Symmetrization method (1) according to one of the preceding claims, wherein the harmonic additional current value (l z ) is formed at least by means of a proportional gain (KP) of a proportional controller (P).

9. Symmetrization method (1) according to one of the preceding claims, wherein the harmonic additional current value (lz) is added to the active current setpoint value (Iwsoii) as the harmonic additional current value (Izadd) to be added.

10. Symmetrization method (1) according to one of claims 1 to 8, wherein the harmonic additional current value (lz) is multiplied by means of a normalization element (N) as the harmonic additional current value (Izmod) to be multiplied by the active current setpoint value (Iwsoii).

11. Symmetry method (1) according to one of the preceding claims, wherein the active current setpoint value (Iwsoii) to which the harmonic additional current value (lz) is applied is determined by means of a d / q transformation.

12. Symmetry method (1) according to one of claims 1 to 10, wherein the additional current value (l z) is determined by means of an alpha / beta transformation or by means of a complex calculation of the alternating voltage network (5), which is in particular three-phase.

13. Balancing device (11) designed to carry out a balancing method (1) according to one of the preceding claims 1 to 12, comprising the rectifier (33) of the multilevel converter (3) and the first and second capacitors (6, 7) on the DC voltage circuit (2), wherein the rectifier (33) is electrically connectable for operation between the AC voltage network (5) and the DC voltage circuit (2) and the first capacitor (6), electrically connected in series with the second capacitor (7), is electrically connected between the first and second DC voltage phases (DC+, DC-) of the DC voltage circuit (2).

14. Symmetrization device (11) according to claim 13, comprising a computing unit (12) with a symmetrization controller (15), designed to carry out the symmetrization method (1).

15. Multilevel converter (3) with a balancing device (11) according to one of claims 13 or 14, wherein the multilevel converter (3) is designed for operation of an electrical consumer (13) or an electrical generator (23) or an electrical network (14) on an AC voltage network (5).

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