Imaging device

Abstract

The present invention makes it possible to transfer charge from a photoelectric conversion unit while eliminating a trade-off relationship with pinning of an insulating layer.　This imaging device is provided with pixels separated by a pixel separation region. Each pixel comprises a photoelectric conversion unit, a transfer transistor that transfers charge accumulated in the photoelectric conversion unit to a floating diffusion, an amplification transistor that outputs a signal corresponding to the potential of the floating diffusion, a selection transistor that selects an output of the amplification transistor, a reset transistor that resets the floating diffusion, an overflow control transistor that can set a path for charge overflowing from the photoelectric conversion unit, an element separation region that separates the transfer transistor from the amplification transistor, the selection transistor, and the reset transistor, and a P-type impurity diffusion layer that separates the transfer transistor from the overflow control transistor.

Description

Imaging device

[0001] The present technology relates to an imaging device, and more particularly, to an imaging device that can set a path for electric charges that overflow from a photoelectric conversion unit.

[0002] An imaging device may be provided with an overflow control transistor that can set a path for electric charges that overflow from a photoelectric conversion unit. For example, an imaging device has been disclosed in which an overflow control transistor that transfers electric charges that overflow from a photoelectric conversion unit is provided as a planar transistor on the surface of a semiconductor substrate (see, for example, Patent Document 1).

[0003] International Publication No. 2021 / 235101

[0004] However, in the above-mentioned conventional technology, the transfer path for the charges overflowing from the photoelectric conversion section is arranged under the insulating layer, which creates a trade-off with the pinning of the insulating layer and may result in a reduction in the dark current margin.

[0005] This technology was developed in light of these circumstances, and aims to enable charge transfer from the photoelectric conversion section while eliminating the trade-off with the pinning of the insulating layer.

[0006] The present technology has been made to solve the above-described problems, and a first aspect thereof is an imaging device including pixels separated by a pixel isolation region, each pixel including a photoelectric conversion unit, a transfer transistor that transfers charge accumulated in the photoelectric conversion unit to a floating diffusion, an amplification transistor that outputs a signal corresponding to the potential of the floating diffusion, a selection transistor that selects the output of the amplification transistor, a reset transistor that resets the floating diffusion, an overflow control transistor that can set a path for charge overflowing from the photoelectric conversion unit, an element isolation region that isolates the transfer transistor from the amplification transistor, the selection transistor, and the reset transistor, and a P-type impurity diffusion layer that isolates the transfer transistor from the overflow control transistor. This provides the effect of isolating the transfer transistor and the overflow control transistor while avoiding interference between the element isolation region and the charge transfer path from the overflow control transistor.

[0007] In the first aspect, the element isolation region may isolate the amplifier transistor, the select transistor, the reset transistor, and the overflow control transistor from one another, thereby ensuring the withstand voltage of the amplifier transistor, the select transistor, the reset transistor, and the overflow control transistor.

[0008] In the first aspect, the transfer transistor may be disposed in a central portion of the pixel, and the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor may be disposed at edges of the pixel, thereby providing an effect of setting a transfer path for charges from the transfer transistor to the floating diffusion while avoiding interference with an element isolation region.

[0009] In addition, in the first aspect, the pixel may further include a capacitor that accumulates charge overflowing from the photoelectric conversion unit, and a pass transistor that sets a path for transferring the charge accumulated in the capacitor to the floating diffusion, the pass transistor being disposed at an end of the pixel, thereby providing an effect of setting a transfer path for charge from the capacitor to the floating diffusion while disposing a transfer transistor at the center of the pixel.

[0010] In the first aspect, the drain of the overflow control transistor may be connected to the capacitor, thereby providing an effect that charges overflowing from the photoelectric conversion unit are transferred to the capacitor via the overflow control transistor.

[0011] In addition, in the first aspect, the pixel may further include a switching transistor that switches the conversion efficiency of the amplification transistor, and the switching transistor may be disposed at an end of the pixel, thereby achieving the effect of switching the conversion efficiency of the amplification transistor while disposing a transfer transistor at the center of the pixel.

[0012] In the first aspect, the drain of the overflow control transistor may be connected to a power supply potential, thereby providing an effect that charges overflowing from the photoelectric conversion unit are discharged via the overflow control transistor.

[0013] In the first aspect, the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor may be in contact with the pixel isolation region, thereby providing an effect of isolating the pixel transistors while eliminating the need for an isolation region between the pixel transistors arranged at the edge of the pixel and the pixel isolation region.

[0014] In the first aspect, the amplification transistor, the selection transistor, and the reset transistor may be in contact with the pixel isolation region, and the overflow control transistor may be spaced apart from the pixel isolation region, thereby achieving pinning of the overflow control transistor on the pixel isolation region side.

[0015] In the first aspect, the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor may be spaced apart from the pixel isolation region, thereby achieving pinning of pixel transistors arranged at edges of pixels on the pixel isolation region side.

[0016] In the first aspect, the pixel isolation region may be a rear deep trench isolation (RDTI), which provides the effect of isolating pixels while arranging a channel region of a transistor on the pixel isolation region.

[0017] In the first aspect, the pixel isolation region may be a full-thickness front deep trench isolation (FFTI), which provides the effect of completely isolating pixels in the depth direction.

[0018] 10 is a block diagram showing a configuration example of an imaging device according to a first embodiment. FIG. 11 is a block diagram showing a configuration example of a solid-state imaging device according to the first embodiment. FIG. 12 is a diagram showing a circuit configuration example of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 13 is a plan view showing a layout example of a pixel according to the first embodiment. FIG. 14 is a cross-sectional view showing a configuration example of a pixel according to the second embodiment. FIG. 15 is a cross-sectional view showing a configuration example of a pixel according to the second embodiment. FIG. 16 is a plan view showing a layout example of a pixel according to the third embodiment. FIG. 17 is a cross-sectional view showing a configuration example of a pixel according to the third embodiment. FIG. 18 is a diagram showing a circuit configuration example of a pixel provided in a solid-state imaging device according to a fourth embodiment. FIG. 19 is a plan view showing a layout example of a pixel according to the fourth embodiment. FIG. 19 is a plan view showing a layout example of a pixel according to the fifth embodiment. FIG. 19 is a plan view showing a layout example of a pixel according to the sixth embodiment. FIG. 19 is a cross-sectional view showing a configuration example of a pixel according to the seventh embodiment. FIG. 19 is a perspective view showing a stacking example of a solid-state imaging device according to the eighth embodiment. FIG. 19 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0019] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be made in the following order: 1. First embodiment (an example in which, in a pixel provided with a lateral overflow integration capacitor (LOFIC), a transfer transistor is arranged in the center of the pixel, and the transfer transistor and the overflow control transistor are isolated from each other via an impurity diffusion layer) 2. Second embodiment (an example in which, in a pixel provided with a LOFIC, a transfer transistor is arranged in the center of the pixel, and the transfer transistor and the overflow control transistor are isolated from each other via an impurity diffusion layer, and the overflow control transistor is arranged away from the pixel isolation region) 3. Third embodiment (an example in which, in a pixel provided with a LOFIC, a transfer transistor is arranged in the center of the pixel, and the transfer transistor and the overflow control transistor are isolated from each other via an impurity diffusion layer, and pixel transistors other than the transfer transistor are arranged away from the pixel isolation region) 4. 4. Fourth Embodiment (an example in which, in a floating diffusion holding type global shutter, a transfer transistor is arranged in the center of a pixel, and the transfer transistor and overflow control transistor are isolated from each other via an impurity diffusion layer) 5. Fifth Embodiment (an example in which, in a floating diffusion holding type global shutter, a transfer transistor is arranged in the center of a pixel, and the transfer transistor and overflow control transistor are isolated from each other via an impurity diffusion layer, and the overflow control transistor is arranged away from the pixel isolation region) 6. Sixth Embodiment (an example in which, in a floating diffusion holding type global shutter, a transfer transistor is arranged in the center of a pixel, and the transfer transistor and overflow control transistor are isolated from each other via an impurity diffusion layer, and pixel transistors other than the transfer transistor are arranged away from the pixel isolation region) 7. Seventh Embodiment (an example in which RDTI (Rear Deep Trench Isolation) is provided in the pixel isolation region) 8. Eighth Embodiment (an example in which pixel array sections are stacked) 9. Application to a Mobile Object

[0020] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0021] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0022] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0023] The solid-state imaging device 102 converts an optical image formed on a light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs the digitized signal. The solid-state imaging device 102 is, for example, a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0024] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0025] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0026] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0027] The display unit 106 displays captured images and various information that supports the image capturing operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0028] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0029] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0030] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0031] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0032] The pixel array unit 111 includes a plurality of pixels 120. The pixels 120 are arranged in a matrix along a row direction (also referred to as the horizontal direction) and a column direction (also referred to as the vertical direction). Each pixel 120 may be compatible with a lateral overflow integration capacitor (LOFIC) system or a floating diffusion hold global shutter operation. In the LOFIC system, each pixel 120 may include a capacitor that accumulates charge overflowing from a photodiode. Each pixel 120 may include multiple photodiodes with different sensitivities. Furthermore, each pixel 120 may form a source follower with the column readout circuit 113 when reading out a signal. Each pixel 120 is connected to a horizontal drive line 131 for each row and to a vertical signal line 132 for each column. The horizontal drive line 131 drives each pixel 120 row by row when reading out a signal from each pixel 120. The vertical signal line 132 transmits a potential based on a current that flows when a signal is read out from the pixel 120 to the column signal processing unit 114 for each column.

[0033] The pixels 120 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 120 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0034] The vertical scanning circuit 112 scans the pixels 120 to be read in the column direction. The vertical scanning circuit 112 may be configured using vertical registers. The vertical scanning circuit 112 may include an address decoder or a driver that drives the horizontal drive lines 131 selected via the address decoder for each row.

[0035] The column readout circuit 113 can form a source follower between itself and each pixel 120 when reading out a signal from the pixel 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the pixel 120.

[0036] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 120, and output an imaging signal Gout.

[0037] The column signal processing unit 114 includes a column ADC unit 114A. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 120 and the reference signal.

[0038] The horizontal scanning circuit 115 scans the pixels 120 to be read in the row direction. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0039] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0040] 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. Note that this diagram shows an example of the configuration of a pixel 120 that is compatible with the LOFIC method.

[0041] In the figure, the pixel 120 includes a photodiode PD, a transfer transistor 122, a reset transistor 123, an amplifier transistor 124, a selection transistor 125, and floating diffusions FD1 to FD3. The pixel 120 further includes a capacitor 126, a pass transistor 127, a switching transistor 128, and an overflow control transistor 130. The transfer transistor 122, the reset transistor 123, the amplifier transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 may be MOS (Metal Oxide Semiconductor) transistors. The capacitor 126 may be a metal-insulation-metal (MIM) capacitor. The capacitor 126 may also be a three-dimensional MIM capacitor. The capacitor 126 may also be a high-dielectric capacitor. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are examples of pixel transistors defined in the claims.

[0042] The photodiode PD performs photoelectric conversion and accumulates the photoelectrically converted charge. The capacitor 126 accumulates charge that overflows from the photodiode PD. The capacitor 126 may be shielded from light. One end of the capacitor 126 is connected to a control potential MVDD, and the other end of the capacitor 126 is connected to the cathode of the photodiode PD via an overflow control transistor 130. The control potential MVDD can control the voltage applied to the capacitor 126 during the shutter period, accumulation period, etc. At this time, the capacitor 126 can be pulse-driven based on the control potential MVDD to reduce dark current.

[0043] The transfer transistor 122 transfers the charge accumulated in the photodiode PD to the floating diffusion FD1. The reset transistor 123 resets the floating diffusion FD1. The amplification transistor 124 outputs a signal according to the potential of the floating diffusion FD1. The selection transistor 125 selects the output of the amplification transistor 124. The pass transistor 127 sets a path for transferring the charge accumulated in the capacitor 126 to the floating diffusion FD1. The switching transistor 128 switches the conversion efficiency of the amplification transistor 124. The overflow control transistor 130 controls the overflow of charge from the photodiode PD to the capacitor 126.

[0044] The transfer transistor 122 is connected between the cathode of the photodiode PD and the floating diffusion FD1. The amplification transistor 124 and the selection transistor 125 are connected in series. The drain of the amplification transistor 124 is connected to the power supply voltage VDD. The gate of the amplification transistor 124 is connected to the floating diffusion FD1. The source of the selection transistor 125 is connected to the vertical signal line 132.

[0045] The pass transistor 127 is connected between the connection point of the overflow control transistor 130 and the capacitor 126 and the switching transistor 128. A floating diffusion FD3 is formed at the connection point of the overflow control transistor 130 and the capacitor 126. A floating diffusion FD2 is formed at the connection point of the pass transistor 127 and the switching transistor 128. The switching transistor 128 is connected between the floating diffusions FD1 and FD2. The reset transistor 123 is connected between the floating diffusion FD2 and the power supply voltage VDD. The overflow control transistor 130 is connected between the photodiode PD and the capacitor 126.

[0046] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A select signal SEL is applied to the gate of the select transistor 125. A pass setting signal FCG is applied to the gate of the pass transistor 127. A switching signal FDG is applied to the gate of the switching transistor 128. An overflow control voltage OFG is applied to the gate of the overflow control transistor 130. A control potential MVDD is applied to the capacitor 126. The transfer signal TGL, reset signal RST, select signal SEL, pass setting signal FCG, switching signal FDG, overflow control voltage OFG, and control potential MVDD can be transmitted to the pixel 120 via the horizontal drive line 131 in FIG. 2. The overflow control voltage OFG may be a fixed voltage.

[0047] FIG. 4 is a plan view showing an example of a layout configuration of a pixel according to the first embodiment.

[0048] In the figure, a semiconductor substrate SUB is separated into pixels 120 by pixel isolation regions ISG. An N-type semiconductor substrate can be used for the semiconductor substrate SUB. A photodiode PD is formed for each pixel 120 on the back surface side of the semiconductor substrate SUB. An active region AK1 is provided on the front surface side of the semiconductor substrate SUB, and the active region AK1 is isolated by an element isolation region ISA1. The element isolation region ISA1 may be STI (Shallow Trench Isolation). A channel region and an impurity diffusion layer are formed in the active region AK1. A floating diffusion FD, a source layer, and a drain layer are formed in the impurity diffusion layer.

[0049] In the pixel 120, gate electrodes G1 to G7 are formed on the channel region of the active region AK1 via a gate insulating film. The gate electrode G1 can be used for the overflow control transistor 130. The gate electrode G2 can be used for the transfer transistor 122. The gate electrode G3 can be used for the reset transistor 123. The gate electrode G4 can be used for the amplification transistor 124. The gate electrode G5 can be used for the selection transistor 125. The gate electrode G6 can be used for the pass transistor 127. The gate electrode G7 can be used for the switching transistor 128. A floating diffusion FD is formed between the channel regions below the gate electrodes G2 and G7. A capacitor 126 is formed between the gate electrodes G1 and G6.

[0050] The transfer transistor 122 can be arranged in the center of the pixel 120. The reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 can be arranged at the edge of the pixel 120. Note that the center of the pixel 120 here refers to the inside of the arrangement positions of the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130.

[0051] In this case, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 may be in contact with the pixel isolation region ISG. For example, on the pixel isolation region ISG side, the boundaries of the active regions AK1 of the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 can be defined by the pixel isolation region ISG. In this case, part of the ends of the gate electrodes G1, G3 to G7 may be disposed on the pixel isolation region ISG.

[0052] The reset transistor 123, the amplifying transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 can be isolated from one another via an isolation region ISA1.

[0053] An impurity diffusion layer D2 is formed between the channel regions below the gate electrodes G1 and G2. The impurity diffusion layer D2 may be an N-type impurity diffusion layer. In this case, the impurity concentration of the impurity diffusion layer D2 may be higher than the impurity concentration of the semiconductor substrate SUB. This allows the potential gradient of the transfer path via the overflow control transistor 130 for the charge stored in the photodiode PD to be optimized. Therefore, even when the overflow control transistor 130 is disposed at the end of the pixel 120, the transfer efficiency of the charge stored in the photodiode PD via the overflow control transistor 130 can be improved. The impurity diffusion layer D2 may extend into the active region AK1 below the gate electrodes G1 and G2.

[0054] Furthermore, an impurity diffusion layer D1 is formed between the channel regions below the gate electrodes G1 and G2. The impurity diffusion layer D1 can be disposed between the transfer transistor 122 and the overflow control transistor 130. The impurity diffusion layer D1 can be formed at a position shallower than the impurity diffusion layer D2. The impurity diffusion layer D1 can isolate the transfer transistor 122 and the overflow control transistor 130. The impurity diffusion layer D1 can be a P-type impurity diffusion layer. The impurity concentration of the impurity diffusion layer D1 can be higher than the impurity concentration of the well D10. This allows the formation of a potential barrier for isolating the transfer transistor 122 and the overflow control transistor 130.

[0055] The material of the semiconductor substrate SUB may be Si, InGaAs, InP, InSb, HgCdTe, etc. The material of the gate electrodes G1 to G7 may be, for example, polycrystalline silicon. The material of the pixel isolation region ISG and the element isolation region ISA1 may be SiO. ２In order to prevent color mixing, a light blocking material such as carbon black may be embedded in the pixel isolation region ISG.

[0056] 5 is a cross-sectional view showing an example of the configuration of a pixel according to the first embodiment. The figure shows an example of the configuration of a portion of one pixel of a back-illuminated image sensor. The figure also shows a cross-sectional view taken along line A1-A2 in FIG. 4.

[0057] In the figure, the solid-state imaging device 102 includes a semiconductor substrate SUB. A light-receiving surface is provided on the back side of the semiconductor substrate SUB. At this time, incident light can be incident on each pixel 120 from the back side of the semiconductor substrate SUB. A color filter 513 may be formed for each pixel 120 on the back side of the semiconductor substrate SUB, or an on-chip lens 512 may be formed for each pixel 120 on the color filter 513. The material of the color filter 513 and the on-chip lens 512 may be, for example, SiO ２ The color filter 513 may be an insulating film made of silicon nitride (SiN), silicon nitride (SiCN), or a transparent resin such as acrylic or polycarbonate. The color filter 513 may contain a pigment. The color filter 513 may include an RGB filter, a complementary color filter, or a white filter.

[0058] The semiconductor substrate SUB is provided with pixel isolation regions ISG that separate the pixel array section 111 into individual pixels 120. The pixel isolation regions ISG may be FFTI. In this case, the pixel isolation regions ISG can penetrate the semiconductor substrate SUB in the depth direction. The pixel isolation regions ISG can be arranged at the boundaries of the pixels 120.

[0059] Furthermore, an element isolation region ISA1 that isolates the active region AK1 is provided in the semiconductor substrate SUB. The element isolation region ISA1 can be formed using an STI buried in the semiconductor substrate SUB. A well D10 that is PN junctioned with the semiconductor substrate SUB can be formed in the active region AK1. A P well can be formed in the well D10. Gate electrodes G1, G2, and G5 are formed on the active region AK1 with a gate insulating film 511 interposed therebetween.

[0060] An impurity diffusion layer D11 may be formed under the gate electrode G1, an impurity diffusion layer D12 may be formed under the gate electrode G2, and an impurity diffusion layer D15 may be formed under the gate electrode G5. Each of the impurity diffusion layers D11, D12, and D15 may be an N-type impurity diffusion layer. In this case, charges accumulated in the photodiode PD can be transferred from the transfer transistor 122 to the floating diffusion FD1 via a transfer path formed by the impurity diffusion layer D11. Charges accumulated in the photodiode PD can also be transferred from the overflow control transistor 130 to the capacitor 126 via a transfer path formed by the impurity diffusion layers D2 and D11. The depth of the impurity diffusion layers D11 and D12 may be set to be equal to or greater than the depth of the well D10. The depth of the impurity diffusion layer D15 may be smaller than the depth of the well D10. The impurity diffusion layers D11 and D12 may penetrate into the well D10. The impurity diffusion layer D15 may be spaced apart from the well D10. This allows the transfer transistor 122 and the overflow control transistor 130 to form a transfer path for the charge accumulated in the photodiode PD. The selection transistor 125 can be separated from the transfer path for the charge accumulated in the photodiode PD.

[0061] An impurity diffusion layer D2 is formed below the channel regions below each of the gate electrodes G1 and G2. The impurity diffusion layer D2 may extend across the junction between the semiconductor substrate SUB and the well D10. Furthermore, an impurity diffusion layer D1 is formed between the channel regions below each of the gate electrodes G1 and G2. The impurity diffusion layer D1 can be formed on the impurity diffusion layer D2. In this case, the impurity diffusion layer D1 can isolate the transfer transistor 122 and the overflow control transistor 130 from each other.

[0062] Furthermore, an impurity diffusion layer D3 is formed in the semiconductor substrate SUB along the pixel isolation region ISG. The impurity diffusion layer D3 can be formed under the well D10. The impurity diffusion layer D3 can form a PN junction of the photodiode PD between the semiconductor substrate SUB and the impurity diffusion layer D3. The impurity diffusion layer D3 can also be used as a pinning layer at the interface of the pixel isolation region ISG. The impurity diffusion layer D3 can be a P-type impurity diffusion layer. The impurity concentration of the impurity diffusion layer D3 can be higher than the impurity concentration of the impurity diffusion layer D1.

[0063] As described above, in the first embodiment, in the pixel 120 provided with the LOFIC, the transfer transistor 122 is disposed in the center of the pixel 120, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are disposed at the edge of the pixel 120. This makes it possible to set a charge transfer path from the transfer transistor 122 to the floating diffusion FD1 while avoiding an area below the element isolation region ISA1. This eliminates the trade-off between setting the charge transfer path from the transfer transistor 122 to the floating diffusion FD1 and the pinning of the element isolation region ISA1, and makes it possible to suppress a decrease in the dark current margin.

[0064] Furthermore, the transfer transistor 122 and the overflow control transistor 130 are isolated from each other via the impurity diffusion layer D1. This allows the transfer transistor 122 and the overflow control transistor 130 to be isolated from each other while avoiding interference between the charge transfer path from the photodiode PD to the capacitor 126 via the overflow control transistor 130 and the isolation region ISA1, thereby preventing a decrease in the dark current margin.

[0065] Furthermore, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged in positions that contact the pixel isolation region ISG. This eliminates the need to form an element isolation region ISA1 between the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 and the pixel isolation region ISG. This allows the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 to be arranged at the end of the pixel 120 while suppressing an increase in pixel size.

[0066] 2. Second Embodiment In the first embodiment described above, in a pixel 120 provided with a LOFIC, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged in positions in contact with the pixel isolation region ISG. In this second embodiment, in a pixel 120 provided with a LOFIC, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, and the switching transistor 128 are arranged in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130 is arranged in a position away from the pixel isolation region ISG.

[0067] FIG. 6 is a plan view showing an example of a pixel layout according to the second embodiment.

[0068] In the figure, this pixel has an active region AK2, an element isolation region ISA2, and a gate electrode G1' instead of the active region AK1, element isolation region ISA1, and gate electrode G1 of the first embodiment. Other configurations of the pixel of the second embodiment are the same as those of the pixel of the first embodiment.

[0069] The active region AK2 is provided on the surface side of the semiconductor substrate SUB and is isolated by an element isolation region ISA2. The gate electrode G1' can be used for the overflow control transistor 130. In this case, the active region AK2 and gate electrode G1' of the overflow control transistor 130 are arranged spaced apart from the pixel isolation region ISG. Other configurations of the active region AK2, element isolation region ISA2, and gate electrode G1' are similar to the configurations of the active region AK1, element isolation region ISA1, and gate electrode G1 of the first embodiment described above.

[0070] 7 is a cross-sectional view showing an example of the configuration of a pixel according to the second embodiment. The figure shows an example of the configuration of a portion of one pixel of a back-illuminated image sensor. The figure also shows a cross-sectional view taken along line A1-A2 in FIG. 6.

[0071] In the figure, the gate electrode G1' of the overflow control transistor 130 is arranged apart from the pixel isolation region ISG. In this case, on the pixel isolation region ISG side, the end of the gate electrode G1' can be arranged on the element isolation region ISA2.

[0072] As described above, in the second embodiment, in the pixel 120 provided with the LOFIC, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, and the switching transistor 128 are arranged in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130 is arranged in a position away from the pixel isolation region ISG. This makes it possible to realize pinning of the overflow control transistor 130 on the pixel isolation region ISG side, and to arrange the overflow control transistor 130 at the end of the pixel 120 while suppressing a decrease in the dark current margin.

[0073] 3. Third Embodiment In the second embodiment described above, in a pixel 120 provided with a LOFIC, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, and the switching transistor 128 are arranged in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130 is arranged in a position away from the pixel isolation region ISG. In this third embodiment, in a pixel 120 provided with a LOFIC, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged in positions away from the pixel isolation region ISG.

[0074] FIG. 8 is a plan view showing an example of a pixel layout according to the third embodiment.

[0075] In the figure, this pixel has an active region AK3, an element isolation region ISA3, and gate electrodes G3' to G7' instead of the active region AK2, element isolation region ISA2, and gate electrodes G3 to G7 of the second embodiment. Other configurations of the pixel of the third embodiment are the same as those of the pixel of the second embodiment.

[0076] The active region AK3 is provided on the surface side of the semiconductor substrate SUB and is isolated by an element isolation region ISA3. The gate electrode G3' can be used for the reset transistor 123. The gate electrode G4' can be used for the amplifier transistor 124. The gate electrode G5' can be used for the select transistor 125. The gate electrode G6' can be used for the pass transistor 127. The gate electrode G7' can be used for the switching transistor 128. In this case, the active region AK3 and gate electrodes G3' to G7' of the reset transistor 123, amplifier transistor 124, select transistor 125, pass transistor 127, and switching transistor 128 are arranged apart from the pixel isolation region ISG. Other configurations of the active region AK3, element isolation region ISA3, and gate electrodes G3' to G7' are the same as the configurations of the active region AK2, element isolation region ISA2, and gate electrodes G3 to G7 in the second embodiment described above.

[0077] 9 is a cross-sectional view showing an example of the configuration of a pixel according to the third embodiment. The figure shows an example of the configuration of a portion of one pixel of a back-illuminated image sensor. The figure also shows a cross-sectional view taken along line A1-A2 in FIG. 8.

[0078] In the figure, the gate electrode G1' of the overflow control transistor 130 and the gate electrode G5' of the selection transistor 125 are arranged apart from the pixel isolation region ISG. At this time, on the pixel isolation region ISG side, the ends of the gate electrodes G1' and G5' can be arranged on the element isolation region ISA3.

[0079] As described above, in the third embodiment, in the pixel 120 provided with the LOFIC, the reset transistor 123, the amplifier transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged at positions away from the pixel isolation region ISG. This makes it possible to realize pinning of the reset transistor 123, the amplifier transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 on the pixel isolation region ISG side. This makes it possible to arrange the reset transistor 123, the amplifier transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 at the end of the pixel 120 while suppressing a decrease in the dark current margin.

[0080] 4. Fourth Embodiment In the first embodiment described above, in the pixel 120 provided with the LOFIC, the transfer transistor 122 is arranged in the center of the pixel 120, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged at the edges of the pixel 120. In this fourth embodiment, in a floating diffusion holding type global shutter, the transfer transistor 122 is arranged in the center of the pixel, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the switching transistor 128, and the overflow control transistor 130 are arranged at the edges of the pixel.

[0081] 10 is a diagram showing an example of the circuit configuration of a pixel provided in a solid-state imaging device according to the fourth embodiment. Note that the diagram shows an example of the configuration of a pixel 420 compatible with a floating diffusion holding type global shutter.

[0082] In the figure, this pixel 420 includes a capacitor 426 and an overflow control transistor 130' instead of the capacitor 126 and the overflow control transistor 130 of the first embodiment described above. Furthermore, this pixel 420 is obtained by removing the pass transistor 127 from the pixel 120 of the first embodiment described above. Other configurations of the pixel 420 of the fourth embodiment are similar to the configuration of the pixel 120 of the first embodiment described above.

[0083] The overflow control transistor 130' is connected between the cathode of the photodiode PD and the power supply potential VDD. Here, the overflow control transistor 130' can discharge the charge accumulated in the photodiode PD to the power supply potential VDD during the shutter period. At this time, the pixel 420 can achieve a floating diffusion hold type global shutter operation. In the floating diffusion hold type global shutter operation, the charge accumulated in the photodiode PD can be transferred to the floating diffusion FD1 simultaneously for all pixels. Then, the charge transferred to the floating diffusion FD1 can be read out row by row to achieve a global shutter operation.

[0084] One end of the capacitor 426 is connected to the power supply potential VDD, and the other end of the capacitor 426 is connected to the floating diffusion FD1 via the switching transistor 128. Here, the capacitance of the capacitor 426 can be added to or separated from the floating diffusion FD1 based on the on / off state of the switching transistor 128, thereby switching the conversion efficiency of the amplification transistor 124. Note that the capacitor 426 may not be provided.

[0085] FIG. 11 is a plan view showing an example of a pixel layout according to the fourth embodiment.

[0086] In the figure, this pixel 420 has an active region AK4, an element isolation region ISA1, and gate electrodes G21 to G23 instead of the active region AK1, element isolation region ISA1, and gate electrodes G1 to G3 of the first embodiment described above. Furthermore, this pixel 420 is obtained by removing the gate electrode G6 from the pixel 120 of the first embodiment described above. Furthermore, this pixel 420 is obtained by adding an impurity diffusion layer D25 to the pixel 120 of the first embodiment described above. Other configurations of the pixel 420 of the fourth embodiment are similar to those of the pixel 120 of the first embodiment described above.

[0087] The active region AK4 is provided on the surface side of the semiconductor substrate SUB and is isolated by an element isolation region ISA4. The gate electrode G21 can be used for the overflow control transistor 130'. The gate electrode G22 can be used for the transfer transistor 122. The gate electrode G23 can be used for the reset transistor 123. Here, the active region AK4 of the transfer transistor 122 is disposed in the center of the pixel 420. The active regions AK4 of the reset transistor 123 and the overflow control transistor 130' are disposed at the edges of the pixel 420. In this case, the active regions AK4 of the reset transistor 123 and the overflow control transistor 130' may be in contact with the pixel isolation region ISG. Parts of the edges of the gate electrodes G21 and G23 may be disposed on the pixel isolation region ISG. The remaining configurations of the active region AK4, element isolation region ISA4, and gate electrodes G21 to G23 are similar to the configurations of the active region AK1, element isolation region ISA1, and gate electrodes G1 to G3 in the first embodiment described above.

[0088] The impurity diffusion layer D25 is formed in the active region AK4. The impurity diffusion layer D25 may be disposed adjacent to the channel region below the gate electrode G21. A power supply potential VDD may be applied to the impurity diffusion layer D25.

[0089] As described above, in the floating diffusion holding type global shutter, in the fourth embodiment, the transfer transistor 122 is arranged in the center of the pixel, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the switching transistor 128, and the overflow control transistor 130' are arranged at the edge of the pixel. This makes it possible to eliminate the trade-off between the setting of the charge transfer path from the transfer transistor 122 to the floating diffusion FD1 and the pinning of the element isolation region ISA1, and to suppress a decrease in the dark current margin.

[0090] 5. Fifth Embodiment In the above-described fourth embodiment, in the floating diffusion holding type global shutter, the transfer transistor 122 is arranged in the center of the pixel, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the switching transistor 128, and the overflow control transistor 130' are arranged at the edge of the pixel. In this fifth embodiment, in the floating diffusion holding type global shutter, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the switching transistor 128 are arranged in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130' is arranged in a position away from the pixel isolation region ISG.

[0091] FIG. 12 is a plan view showing an example of a pixel layout according to the fifth embodiment.

[0092] In the figure, this pixel has an active region AK5, an element isolation region ISA5, and a gate electrode G21' instead of the active region AK4, element isolation region ISA4, and gate electrode G21 of the fourth embodiment. Other configurations of the pixel of the fifth embodiment are the same as those of the pixel of the fourth embodiment.

[0093] The active region AK5 is provided on the surface side of the semiconductor substrate SUB and is isolated by the element isolation region ISA5. The gate electrode G21' can be used for the overflow control transistor 130'. In this case, the active region AK5 and gate electrode G21' of the overflow control transistor 130' are arranged spaced apart from the pixel isolation region ISG. Other configurations of the active region AK5, element isolation region ISA5, and gate electrode G21' are similar to the configurations of the active region AK4, element isolation region ISA4, and gate electrode G21 of the fourth embodiment described above.

[0094] As described above, in the floating diffusion holding type global shutter of the fifth embodiment, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the switching transistor 128 are disposed in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130' is disposed in a position away from the pixel isolation region ISG. This makes it possible to realize pinning of the overflow control transistor 130' on the pixel isolation region ISG side, and to dispose the overflow control transistor 130' at the end of the pixel 120 while suppressing a decrease in the dark current margin.

[0095] 6. Sixth Embodiment In the above-described fifth embodiment, in the floating diffusion hold type global shutter, the reset transistor 123, the amplification transistor 124, the selection transistor 125, and the switching transistor 128 are arranged in positions in contact with the pixel isolation region ISG, and the overflow control transistor 130 is arranged in a position away from the pixel isolation region ISG. In this sixth embodiment, in the floating diffusion hold type global shutter, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the switching transistor 128, and the overflow control transistor 130 are arranged in positions away from the pixel isolation region ISG.

[0096] FIG. 13 is a plan view showing an example of a pixel layout according to the sixth embodiment.

[0097] In the figure, this pixel has an active region AK6, an element isolation region ISA6 and gate electrodes G23', G4', G5' and G7' instead of the active region AK5, element isolation region ISA5 and gate electrodes G23, G4, G5 and G7 of the fifth embodiment. Other configurations of the imaging device of the sixth embodiment are the same as those of the pixel of the fifth embodiment.

[0098] The active region AK6 is provided on the surface side of the semiconductor substrate SUB and is isolated by an element isolation region ISA6. The gate electrode G23' can be used for the reset transistor 123. In this case, the active region AK6 and gate electrode G23' of the reset transistor 123 are arranged spaced apart from the pixel isolation region ISG. Other configurations of the active region AK6, element isolation region ISA6, and gate electrode G23' are similar to the configurations of the active region AK5, element isolation region ISA5, and gate electrode G23 in the fifth embodiment described above.

[0099] As described above, in the floating diffusion holding type global shutter in the sixth embodiment, the reset transistor 123, the amplification transistor 124, the selection transistor 125, the switching transistor 128, and the overflow control transistor 130 are arranged at positions away from the pixel isolation region ISG. This makes it possible to arrange the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 at the end of the pixel 120 while suppressing a decrease in the dark current margin.

[0100] 7. Seventh Embodiment In the first embodiment described above, the FFTI is formed in the pixel isolation region ISG. In this seventh embodiment, the RDTI is formed in the pixel isolation region.

[0101] 14 is a cross-sectional view showing an example of the configuration of a pixel according to the seventh embodiment, which shows an example of the configuration of a part of one pixel of a back-illuminated image sensor.

[0102] In the figure, this pixel has a pixel isolation region ISG', gate electrodes G31 and G35, and impurity diffusion layers D11' and D15' instead of the pixel isolation region ISG, gate electrodes G1 and G5, and impurity diffusion layers D11 and D15 of the first embodiment. Other configurations of the pixel of the seventh embodiment are the same as those of the pixel of the first embodiment.

[0103] The pixel isolation region ISG' is formed in the semiconductor substrate SUB. An RDTI can be formed in the pixel isolation region ISG'. The pixel isolation region ISG' can be embedded in the semiconductor substrate SUB from the rear surface side of the semiconductor substrate SUB.

[0104] In the active region AK1, a well D10' is formed which is PN-junctioned with the semiconductor substrate SUB. In this case, the well D10' can be disposed on the pixel isolation region ISG' and on the impurity diffusion layer D3. Gate electrodes G31, G2, and G35 are formed on the active region AK1, each with a gate insulating film 511 interposed therebetween. An impurity diffusion layer D11' may be formed below the gate electrode G31, and an impurity diffusion layer D15' may be formed below the gate electrode G35. In this case, the impurity diffusion layers D11' and D15' may extend above the pixel isolation region ISG'.

[0105] As described above, in the seventh embodiment, the RDTI is formed in the pixel isolation region ISG'. This makes it possible to separate the pixels 120 while arranging the channel regions of the pixel transistors on the pixel isolation region ISG'. This makes it possible to increase the size of the pixel transistors without increasing the pixel size.

[0106] In the seventh embodiment described above, an example has been shown in which the gate electrodes G31 and G35 extend onto the pixel isolation region ISG'. However, the present embodiment is not necessarily limited to this example, and for example, the gate electrodes G3, G4, G6, and G7 of the first embodiment described above may be extended onto the pixel isolation region ISG'.

[0107] 8. Eighth Embodiment In the first embodiment described above, the transfer transistor 122 is arranged in the center of the pixel 120, and the reset transistor 123, the amplification transistor 124, the selection transistor 125, the pass transistor 127, the switching transistor 128, and the overflow control transistor 130 are arranged at the ends of the pixel 120. In this eighth embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0108] FIG. 15 is a perspective view showing an example of a stack of pixel array units according to the eighth embodiment.

[0109] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0110] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. The pixels 931 may be any of the pixels in the first to eighth embodiments described above. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0111] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0112] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0113] As described above, in the eighth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0114] 9. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0115] FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0116] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0117] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0118] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0119] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0120] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0121] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0122] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0123] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0124] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0125] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 16, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0126] FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0127] In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0128] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0129] 17 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0130] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0131] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0132] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0133] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0134] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging devices according to the first to eighth embodiments described above can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve image quality while suppressing a decrease in the reliability of the imaging unit 12031.

[0135] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0136] Note that the present technology may also be configured as follows: (1) An imaging device including pixels separated by a pixel isolation region, wherein the pixels include: a photoelectric conversion unit, a transfer transistor that transfers charge accumulated in the photoelectric conversion unit to a floating diffusion, an amplification transistor that outputs a signal according to the potential of the floating diffusion, a selection transistor that selects the output of the amplification transistor, a reset transistor that resets the floating diffusion, an overflow control transistor that can set a path for charge overflowing from the photoelectric conversion unit, an element isolation region that isolates the transfer transistor from the amplification transistor, the selection transistor, and the reset transistor, and a P-type impurity diffusion layer that isolates the transfer transistor from the overflow control transistor. (2) The imaging device described in (1), wherein the element isolation region isolates the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor from one another. (3) The imaging device according to (1) or (2), wherein the transfer transistor is arranged in a central portion of the pixel, and the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are arranged at edges of the pixel. (4) The imaging device according to any of (1) to (3), wherein the pixel further comprises: a capacitor that accumulates charge overflowing from the photoelectric conversion unit; and a pass transistor that sets a path for transferring the charge accumulated in the capacitor to the floating diffusion, and the pass transistor is arranged at an edge of the pixel. (5) The imaging device according to (4), wherein a drain of the overflow control transistor is connected to the capacitor. (6) The imaging device according to any of (1) to (5), wherein the pixel further comprises a switching transistor that switches the conversion efficiency of the amplification transistor, and the switching transistor is arranged at an edge of the pixel. (7) The imaging device according to any of (1) to (3), wherein a drain of the overflow control transistor is connected to a power supply potential.(8) The imaging device according to any one of (1) to (7), wherein the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are in contact with the pixel isolation region. (9) The imaging device according to any one of (1) to (7), wherein the amplification transistor, the selection transistor, and the reset transistor are in contact with the pixel isolation region, and the overflow control transistor is spaced apart from the pixel isolation region. (10) The imaging device according to any one of (1) to (7), wherein the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are spaced apart from the pixel isolation region. (11) The imaging device according to any one of (1) to (10), wherein the pixel isolation region is rear deep trench isolation (RDTI). (12) The imaging device according to any one of (1) to (10), wherein the pixel isolation region is full-thickness front deep trench isolation (FFTI).

[0137] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 120 Pixel PD Photodiode FD1 to FD3 Floating diffusion 122 Transfer transistor 123 Reset transistor 124 Amplification transistor 125 Selection transistor 126 Capacitor 127 Pass transistor 128 Switching transistor 131 Horizontal drive line 132 Vertical signal line SUB Semiconductor substrate ISG Pixel isolation region ISA1 to ISA6 Element isolation region G1 to G7 Gate electrode D1, D2 Impurity diffusion layer

Claims

1. An imaging device comprising pixels separated in a pixel isolation region, wherein each pixel includes a photoelectric conversion section, a transfer transistor for transferring charges accumulated in the photoelectric conversion section to a floating diffusion, an amplification transistor for outputting a signal corresponding to the potential of the floating diffusion, a selection transistor for selecting the output of the amplification transistor, a reset transistor for resetting the floating diffusion, an overflow control transistor capable of setting a path for charges overflowing from the photoelectric conversion section, an element isolation region for element-isolating the transfer transistor from the amplification transistor, the selection transistor, the reset transistor, and an P-type impurity diffusion layer for element-isolating the transfer transistor from the overflow control transistor.

2. The imaging device according to claim 1, wherein the element isolation region element-isolates the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor from each other.

3. The imaging device according to claim 1, wherein the transfer transistor is disposed at the central portion of the pixel, and the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are disposed at the edge portions of the pixel.

4. The pixel of the imaging device according to claim 1 further comprises a capacitor for accumulating charges overflowing from the photoelectric conversion section, and a path transistor for setting a path through which the charges accumulated in the capacitor are transferred to the floating diffusion, wherein the path transistor is disposed at the edge portion of the pixel.

5. The imaging device according to claim 4, wherein the drain of the overflow control transistor is connected to the capacitor.

6. The pixel of the imaging device according to claim 3 further comprises a switching transistor for switching the conversion efficiency of the amplification transistor, wherein the switching transistor is disposed at the edge portion of the pixel.

7. The imaging device according to claim, wherein the drain of the overflow control transistor is connected to a power supply potential.

8. The imaging device according to claim 1, wherein the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are in contact with the pixel isolation region.

9. The imaging device according to claim 1, wherein the amplification transistor, the selection transistor, and the reset transistor are in contact with the pixel isolation region, and the overflow control transistor is separated from the pixel isolation region.

10. The imaging device according to claim 1, wherein the amplification transistor, the selection transistor, the reset transistor, and the overflow control transistor are separated from the pixel isolation region.

11. The imaging device according to claim 1, wherein the pixel isolation region is RDTI (Rear Deep Trench Isolation).

12. The imaging device according to claim 1, wherein the pixel isolation region is FFTI (Full-thickness Front deep Trench Isolation).

Images