Circuit board, and semiconductor package comprising same

Abstract

A circuit board according to an embodiment of the present invention may comprise: a build-up structure including a build-up insulator and a build-up wiring body; a post bump disposed on a first pad of the build-up wiring body; and a bump pad disposed on a second pad of the build-up wiring body, wherein the thickness of the post bump can be greater than the thickness of the build-up structure.

Description

Circuit boards and semiconductor packages including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of electronic components on circuit boards of limited size. However, conventional semiconductor packages typically accommodate a single electronic component, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that incorporate multiple electronic components across multiple substrates have recently been developed. These semiconductor packages feature a structure in which multiple electronic components are interconnected horizontally and / or vertically on the circuit board. Consequently, semiconductor packages offer the advantages of efficiently utilizing the mounting area of ​​the electronic components and enabling high-speed signal transmission through short signal transmission paths between the components.

[0004] Meanwhile, a circuit board includes a build-up insulator including an insulating layer and a build-up wiring body arranged on the build-up insulator. For example, a circuit board may mean that a mounting position of each electronic component is predetermined for mounting at least one electronic component, and a build-up wiring body connected to the electronic component is arranged on the build-up insulator. The build-up wiring body includes a wiring layer arranged on the surface of each insulating layer and a via electrode for vertically connecting each wiring layer. The electronic component is mounted on the circuit board and can transmit and receive signals through the build-up wiring body.

[0005] The size of electronic components placed on circuit boards can increase or decrease depending on their intended use. This can lead to issues such as securing enough space for the electronic components. Furthermore, as the electronic components become thicker, the heat generated by the components can affect the motherboard on which they are placed.

[0006] One of the technical challenges of the present invention is to provide a circuit board in which the diameter and height of a post bump are formed to be greater than the height of a build-up structure.

[0007] In addition, another technical task of the invention is to provide a circuit board that reduces the detachment force of a post bump.

[0008] In addition, one of the technical challenges of the invention is to provide a circuit board that secures a space in which electronic components are placed and prevents heat generated from the electronic components from being transferred to the main board.

[0009] A circuit board according to an embodiment of the invention includes a build-up structure including a build-up insulator and a build-up wiring body, a post bump disposed on a first pad of the build-up wiring body, and a bump pad disposed on a second pad of the build-up wiring body, wherein a thickness of the post bump may be thicker than a thickness of the build-up structure.

[0010] Additionally, the thickness of the post bump may be at least 1.4 times the thickness of the build-up structure.

[0011] Additionally, the thickness of the post bump may be up to three times greater than the thickness of the build-up structure.

[0012] Additionally, the thickness of the post bump may be 0.2 ± 0.04 mm.

[0013] Additionally, the thickness of the above build-up structure may be 0.141±0.03 mm.

[0014] Additionally, the diameter of the post bump may be 0.25 ± 0.02 mm.

[0015] Additionally, the build-up structure may not include a core layer.

[0016] Additionally, the wiring layer includes a via hole, and the post bump can be connected to the via hole.

[0017] In addition, a semiconductor package according to an embodiment may include a build-up structure including a build-up insulator and a build-up wiring body, a post bump disposed on a first pad of the build-up wiring body, a bump pad disposed on a second pad of the build-up wiring body, and an electronic component disposed on the bump pad, and a thickness of the post bump may be thicker than a thickness of the build-up structure.

[0018] The thickness of the above post bump may be thicker than the thickness of the above electronic component.

[0019] The upper surface of the above post bump may be positioned higher than the upper surface of the electronic device.

[0020] The thickness of the above post bump may be at least 1.4 times the thickness of the above build-up structure.

[0021] The thickness of the above post bump may be up to three times greater than the thickness of the above build-up structure.

[0022] According to the circuit board of the embodiment of the invention, the post bump (150) is formed thicker than the build-up structure (100), thereby securing a space for arranging electronic components.

[0023] Additionally, according to the circuit board of the embodiment, since the distance between the electronic elements and the memory is increased, the influence of heat generated from the electronic elements on the memory can be reduced.

[0024] In addition, according to the circuit board of the embodiment, the diameter of the post bump (150) is formed to be larger than the height of the post bump (150), so that the electronic element placed on the post bump (150) can be firmly supported.

[0025] Figure 1 is an example of a semiconductor package according to an embodiment of the present invention.

[0026] Fig. 2 illustrates a circuit board according to an embodiment.

[0027] Figure 3 is an enlarged view of area A1 of Figure 2.

[0028] Figures 4(a) to 4(h) show a method for manufacturing a circuit board according to an embodiment of the invention in process order.

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described. Commonly used terms, such as terms defined in a dictionary, may have their meanings interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0032] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. may be used to describe components of embodiments of the present invention.

[0033] In this specification, for the convenience of explanation, components may be described in the horizontal direction and the vertical direction. The vertical direction means the top (above) or bottom (below) of each component, and the horizontal direction means the direction perpendicular to the vertical direction. In addition, the horizontal direction may include a first horizontal direction and a second horizontal direction. Here, when the horizontal direction follows a Cartesian coordinate system, the first horizontal direction may mean the X-axis, the second horizontal direction may mean the Y-axis, and the vertical direction may mean the Z-axis. When following a cylindrical coordinate system, the first horizontal direction may mean a direction along an azimuth, and the second horizontal direction may mean a direction toward a radius, and these may be selectively used in combination. In addition, the direction along an azimuth may be referred to as a circumferential direction, and the direction toward a radius may be referred to as a centrifugal direction.

[0034] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0035] Additionally, the statement that component A is exposed from component B should be understood to mean that component A is exposed from component B, not that component A is exposed from the entire product. That is, when it is stated that component A is exposed from component B, it should be understood to mean that component A is at least partially covered by component C.

[0036] Additionally, when it is described that a component A is in "contact" with a component B, it may include not only cases where that component is in "contact" with the other component directly, but also cases where that component is "contacted" by another component between that component and the other component. Thus, if a component A is to be understood to be in "direct contact" with a component B, it is described as being in "direct contact."

[0037] In addition, when it is written that configuration A is 'covered' by configuration B, it should be understood that configuration A is covered by configuration B, and that the part for the function and purpose to be solved is covered, and unless there are special circumstances, it should not be understood that the entire configuration A is covered by configuration B.

[0038] In addition, when it is described that configuration A is 'fixed' to configuration B, it should be understood that configuration A is not only fixed by being directly combined with configuration B, but also indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specified, taking into account the function and purpose to be solved, and when configuration A is only understood to be 'directly fixed' to configuration B, it is described as being 'directly fixed'.

[0039] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0040]

[0041] -Semiconductor package-

[0042] Before describing the embodiment, a semiconductor package including the circuit board of the embodiment will be briefly described. The semiconductor package includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various electronic components may be mounted on the semiconductor package.

[0043] Electronic components include active components and / or passive components. Active components may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of components are integrated into a single chip. Electronic components may be logic chips, memory chips, etc. Logic chips may be central processors (CPUs), graphics processors (GPUs), etc. For example, logic chips may be application processor (AP) chips that include at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a chip set that includes a specific combination of the components listed above.

[0044] The memory chip may be a stacked memory such as HBM. In addition, the memory chip includes memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory.

[0045] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0046] Additionally, the semiconductor package may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is obvious that the semiconductor package may be any other electronic device that processes data.

[0047]

[0048] Below, a circuit board according to an embodiment is described.

[0049] FIG. 1 is an example of a semiconductor package according to an embodiment of the present invention, and FIG. 2 shows a circuit board according to the embodiment.

[0050] Referring to FIGS. 1 and 2, a semiconductor package (1) according to an embodiment may include a circuit board (10) and an electronic component (20).

[0051] The circuit board (10) may include a build-up structure (100) and a post bump (150). The thickness of the post bump (150) may be equal to or greater than the thickness of the electronic component (20) disposed on the circuit board (10).

[0052] A circuit board (10) may be configured to allow at least one electronic component to be attached. In addition, the circuit board may be coupled to a main board of an electronic device. The main board may refer to a motherboard of the electronic device. The circuit board may be coupled with at least one electronic component and the motherboard to form a first package. In addition, the first package including the circuit board may be coupled with a second package. The second package may be a memory package. For example, the circuit board may be coupled with a memory substrate of the second package. For example, the circuit board may be coupled with an interposer to which the memory substrate is coupled.

[0053]

[0054] A build-up structure (100) according to an embodiment includes a build-up insulator (110), a build-up wiring body (120), and a protective layer (140). The build-up structure (100) can function as a laminated circuit for connecting to an electronic component / main board, etc.

[0055] The build-up structure (100) may include a build-up insulator (110). The build-up insulator (110) includes a single or multiple laminated insulating layers and provides insulating properties between the build-up wiring bodies. The build-up insulator (110) may include, but is not limited to, a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113).

[0056] Additionally, one of the insulating layers of the build-up insulator (110) may be a core layer. The first insulating layer (111) located at the center of the build-up insulator (111) may be a core layer, but is not limited thereto, and the circuit board (10) according to the embodiment may be a coreless board without a core layer.

[0057]

[0058] The build-up insulator (110) may include an upper build-up insulator disposed on the upper surface of the first insulating layer (111) and a lower build-up insulator disposed on the lower surface of the first insulating layer (111). For example, the build-up insulator (110) may include a second insulating layer (112), which is an upper build-up insulator disposed on the upper surface of the first insulating layer (111), and a third insulating layer (113), which is a lower build-up insulator disposed on the lower surface of the first insulating layer (111).

[0059]

[0060] The upper build-up insulator (112) and the lower build-up insulator (113) each have a function of arranging a wiring layer or via electrode of the build-up wiring body (120) and a function of securing insulation between circuits and controlling impedance or insertion loss by the circuit, and include an insulating layer including at least one of a thermosetting resin, a photocurable resin, or an optically isotropic film in consideration of dielectric constant, mechanical rigidity, and processability.

[0061] For example, the insulating layer of the build-up insulator (110) may be a thermosetting material, and may include, for example, one or more of Ajinomoto build-up film (ABF), epoxy resin, polyimide, phenolic resin, bismaleimide triazine (BT) resin, and silicone resin.

[0062] Also, for example, the insulating layer of the build-up insulator (110) may be a photocurable material, and may include, for example, one or more of a photocurable resin (PID: Photo Imageable Dielectric resin), a photosensitive polyimide, a liquid photoimageable solder resist (LPI), a photosensitive epoxy, or a photosensitive acrylic.

[0063] For example, photocurable resins can form fine patterns of through holes or openings through exposure and development processes, and can eliminate stoppers required in the cavity formation process. Meanwhile, the content of ceramic particles such as SiO2 provided in the insulating layer of the photocurable resin may be higher than the content of ceramic particles provided in the insulating layer of the thermosetting resin, and thus the interfaces of the photocurable resin and the thermosetting resin may be distinguishable. For example, when analyzing a photocurable resin by XPS (X-ray Photoelectron Spectroscopy), relatively high power peak values ​​may be detected in two of acrylic and epoxy. And when analyzing a thermosetting resin by XPS, a peak value may be detected only in epoxy.

[0064] Additionally, the insulating layer of the build-up insulator (110) may include an optically isotropic film, and may include, for example, one or more of COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0065] In addition, the insulation layer of the build-up insulator (110) may include a prepreg, thereby having a strength higher than a certain level that can improve the bending characteristics of the circuit board. The prepreg constituting the insulation layer may have a structure in which a glass fiber layer in the form of a fabric sheet, such as a glass fabric, is impregnated with epoxy resin or the like.

[0066]

[0067] The build-up wiring body (120) includes a wiring layer (121) arranged on the surface of each insulating layer and a via electrode (122) for vertically connecting each wiring layer (121). The wiring layer (121) can have the function of transmitting signals and / or power to electronic devices arranged on a circuit board and can perform an impedance matching function. The wiring layer (121) may be referred to as a wiring pattern layer, a metal wiring, or a wiring portion. The via electrode (122) may be referred to as a through electrode, a via, or a via portion.

[0068] A via electrode (122) can electrically connect wiring layers (121) arranged on different layers. The via electrode (122) can be formed by forming a through hole penetrating the first insulating layer (111), the second insulating layer (112), and the third insulating layer (113), and filling the inside of the formed through hole with a conductive material.

[0069] The through hole for forming the via electrode (122) can be formed by any one of mechanical processing, laser processing, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing can be used. When formed by laser processing, a UV or CO2 laser method can be used, and for chemical processing, a chemical agent including aminosilane, ketones, etc. can be used.

[0070] The metal material forming the via electrode (122) may be any one material selected from among copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material filling may utilize any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and dispensing.

[0071]

[0072] Any one of the above-described build-up wiring bodies (120) may have an ETS (Embedded Trace Substrate) structure. For example, a build-up wiring body arranged on the upper surface of a circuit board (10) may have an ETS structure. For example, a build-up wiring body arranged on the upper surface of a circuit board (10) may be arranged in a recess provided on the upper surface of a second uppermost insulating layer (112). The ETS structure may also be referred to as a buried structure. The ETS structure is advantageous for miniaturization compared to a build-up wiring body having a general protruding structure. Accordingly, the embodiment enables the formation of electrodes corresponding to the size and pitch of terminals provided in an electronic device. Through this, the embodiment can improve the circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through an electronic device, thereby minimizing signal transmission loss.

[0073] In addition, the build-up wiring body (120) may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). In addition, the build-up wiring body (120) may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding strength.

[0074]

[0075] Next, the wiring layer (121) according to the embodiment includes a via electrode (122) and / or a pad (124) and / or a trace (or connection pattern) (125) for connecting to an electronic component and / or a capacitor. The trace (125) may be a long signal wiring line connecting between a plurality of pads.

[0076] At this time, the pads (124, 125) of the wiring layer (121) include connection pads (125) or connecting pads. The connection pads (125) may be mounting pads on which electronic components or semiconductor chips are mounted, or terminal pads connected to an external substrate. The connection pads are contact portions that come into contact with via electrodes, and may include side extensions for alignment margins. The wiring layer (121) may be formed by a manufacturing process of a circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0077]

[0078] Next, the circuit board (10) according to the embodiment includes a protective layer (140) disposed on a wiring layer (121, 124, 125) of the uppermost or lowermost insulating layer. For example, the protective layer (140) may include a first protective layer (141) disposed on the uppermost insulating layer and a second protective layer (142) disposed under the lowermost insulating layer.

[0079] The protective layer (140) can prevent problems such as oxidation or peeling of the build-up structure (100) due to external moisture or contaminants. The protective layer can be formed of a material with low wettability to solder to prevent short circuits between adjacent solders when connecting the build-up structure (100) to an electronic component or main board, thereby preventing bridging and short circuits between adjacent solders.

[0080] The protective layer (140) includes an insulating material, and the protective layer (140) includes various materials that can be cured by heating or light irradiation after being applied to protect the surfaces of the insulating layers and the surfaces of the wiring layers. The protective layer (140) may be a resist layer, and for example, the protective layer (140) may be a solder resist layer that includes an organic polymer material. As an example, the protective layer (140) includes an epoxy acrylate series resin. In detail, the protective layer (140) includes a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic series monomer, and the like. However, the embodiment is not limited thereto, and the protective layer (140) may be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0081]

[0082] Figure 3 is an enlarged view of area A1 of Figure 2.

[0083] Referring to FIGS. 2 and 3, the post bump (150) according to the embodiment may be provided to have the horizontal width described above in consideration of securing the integrity of signal and / or power transmission, mechanical rigidity, and stress with the build-up structure. The post bump (150) operates to smoothly transmit power and / or signals when another upper circuit board is placed on the electronic component and / or circuit board, thereby enabling smooth operation of the electronic component and / or connecting member.

[0084] The post bump (150) according to the embodiment is electrically connected to the first pad (124), which is a connection pad, and the first pad (124) is connected to the via electrode (122).

[0085] The diameter (D) of the post bump (150) according to the embodiment may be larger than the height (H) of the post bump (150). For example, the height (H) of the post bump (150) may be 0.2±0.04 mm, and the diameter (D) of the post bump (150) may be 0.25±0.02 mm. As a result, the electronic component connected to the post bump (150) may be firmly supported.

[0086] The height (H) of the post bump (150) may be greater than the height (h1) of the build-up structure (100). The height (H) of the post bump (150) may be 1.4 to 3 times less than the height (h1) of the build-up structure (100). For example, the height (h1) of the build-up structure (100) may have 0.141±0.03 mm. Since the height (H) of the post bump (150) is formed to be greater than the height (h1) of the build-up structure (100), the distance between the electronic component connected to the connection pad (125) of the circuit board and the main board connected to the post bump increases, so that the influence of heat applied to the main board from the electronic component can be reduced.

[0087] The post bump (150) may have a diameter (d2) of the lower portion (151) of the post bump due to the first protective layer (141) that is smaller than or equal to the diameter (D) of the upper portion (152) of the post bump. For example, the diameter (d2) of the lower portion (151) of the post bump may be 0.2 to 0.25 mm. This may prevent a short circuit between the post bump (150) and the first pad (124), and improve the reliability of the electrical connection. In addition, the detachment force of the post bump (150) may be reduced.

[0088] Additionally, the width (d1) of the first pad (124) may be larger than the diameter (d2) of the lower portion (151) of the post bump, but is not limited thereto. For example, the width (d1) of the first pad (124) may have a value of 0.29±0.05 mm.

[0089]

[0090] Figures 4(a) to 4(h) show a method for manufacturing a circuit board according to an embodiment of the invention in process order.

[0091] Below, the process of forming the build-up structure (100) and post bump (150) of the circuit board will be described.

[0092] Referring to Fig. 4(a), the embodiment prepares a build-up insulator (110). Preferably, the step of preparing the build-up insulator (110) may refer to a process of laminating first, second, and third insulating layers (111, 112, 113). Next, the embodiment may form a metal layer (120a) on the build-up insulator (110). The first metal layer (120a) may refer to a copper foil layer disposed on the build-up insulator (110). Alternatively, the first metal layer (120a) may be an electroless plating layer formed by performing electroless plating. For example, the first metal layer (120a) may be a chemical copper plating layer. Alternatively, the first metal layer (120a) may include both a copper foil layer and a chemical copper plating layer.

[0093] After forming the first metal layer (120a), a first mask (200) is formed on the first metal layer (120a). Thereafter, a build-up wiring body (120) is formed using the first metal layer (120a) as a seed layer.

[0094] Next, referring to FIG. 4(b), the embodiment can proceed with a process of removing the first mask (200). Thereafter, the exposed first metal layer (120a) can be removed by flash etching.

[0095] Next, referring to FIG. 4(c), the embodiment may proceed with a process of forming a first protective layer (141). At this time, the first protective layer (141) may expose a portion of the upper portion of the build-up wiring body (120) through an exposure and development process. Here, the build-up wiring body (120) may have a first pad (124) and a second pad (125).

[0096] Next, referring to FIG. 4(d), the embodiment can form a second metal layer (120b) on the first protective layer (141), the first pad (124), and the second pad (125). The second metal layer (120b) can be a chemically conductive seed layer, but is not limited thereto.

[0097] Next, referring to FIG. 4(e), in an embodiment, a second mask (300) may be placed on a second metal layer (120b). The second mask (300) may be a dry film, but is not limited thereto. The second mask (300) may open an area vertically overlapping with the first pad (124) by controlling exposure and development conditions. Depending on the height of the second mask (300), the height of the post bump (150) formed in a subsequent process may be determined. For example, the thickness of the second mask (300) layer may be 0.17 mm to 0.25 mm.

[0098] Next, referring to FIG. 4(f), the embodiment can proceed with a process of forming a post bump (150) using a second metal layer (120b) as a seed layer in an open area.

[0099] Next, referring to FIG. 4(g), the embodiment may proceed with a process of removing the second mask (300). Thereafter, the embodiment may proceed with a process of removing the exposed second metal layer (120b) by etching.

[0100] Next, referring to FIG. 4(h), the embodiment may perform a process of forming an oxide layer (155) on the post bump (150) and the second pad (125). At this time, the oxide layer (155) may be an OSP (Organic Solderability Preservative). The oxide layer (155) is an organic coating layer for protecting the post bump (150) and the second pad (125), and can prevent oxidation and maintain high reliability during soldering. That is, even if the height (H) and diameter (D) of the post bump (150) according to the embodiment are formed thicker than the height of the build-up structure (100), it can be protected by the oxide layer (155), and thus stability can be secured during soldering.

[0101]

[0102] The circuit board or semiconductor package according to the embodiment may be applied to any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package).

[0103] Additionally, the circuit board or semiconductor package may be applied to, but is not limited to, smart phones, personal digital assistants, digital video cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smart watches, automotives, etc.

[0104]

[0105] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up structure including a build-up insulator and a build-up wiring body; A post bump arranged on the first pad of the above build-up wiring body; and An electronic component bump pad disposed on the second pad of the above-mentioned build-up wiring body; A circuit board wherein the thickness of the above post bump is thicker than the thickness of the above build-up structure.

2. In paragraph 1, A circuit board wherein the thickness of the above post bump is at least 1.4 times the thickness of the above build-up structure.

3. In paragraph 2, A circuit board wherein the thickness of the above post bump is at most three times greater than the thickness of the above build-up structure.

4. In paragraph 1, A circuit board having a thickness of the above post bump of 0.2 ± 0.04 mm.

5. In paragraph 4, A circuit board having a thickness of the above build-up structure of 0.141±0.03 mm.

6. In paragraph 4, The diameter of the above post bump is 0.25 ± 0.02 mm. Circuit board.

7. In paragraph 1, The above wiring layer includes a via hole, The above post bump is connected to the via hole. Circuit board.

8. A build-up structure including a build-up insulator and a build-up wiring body; A post bump arranged on the first pad of the above build-up wiring body; A bump pad arranged on the second pad of the above build-up wiring body; and An electronic component disposed on the above bump pad; A semiconductor package wherein the thickness of the above post bump is thicker than the thickness of the above build-up structure.

9. In paragraph 8, A semiconductor package, wherein the upper surface of the above post bump is positioned higher than the upper surface of the above electronic component.

10. In paragraph 8, A semiconductor package, wherein the thickness of the above post bump is 1.4 to 3 times the thickness of the above build-up structure.

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