Circuit board and semiconductor package comprising same

Abstract

A circuit board according to an embodiment comprises: a build-up structure including a plurality of insulating layers stacked in the vertical direction; a protective layer disposed on the build-up structure and having a through-hole penetrating through an upper surface and a lower surface thereof; and a plurality of bonding portions disposed inside the through-hole of the protective layer and spaced apart from each other along the circumference of the inner wall of the through-hole.

Description

Circuit board and semiconductor package including same

[0001] The present invention relates to a circuit board, and more particularly to a circuit board having improved electrical reliability and a semiconductor package including the same.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to accommodate a greater number of semiconductor devices on a limited-size semiconductor package substrate. However, conventional semiconductor packages typically consist of a single semiconductor device, limiting their ability to achieve desired performance.

[0003] Accordingly, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been developed. These semiconductor packages have a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the substrate. Accordingly, these semiconductor packages have the advantage of efficiently utilizing the mounting area of ​​the semiconductor devices and enabling high-speed signal transmission through short signal transmission paths between the semiconductor devices.

[0004] In addition, semiconductor packages applied to products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers are expanding their concept to semiconductor chiplets as the number of semiconductor elements and / or the size of each semiconductor element increases in line with the trend toward high integration, or as the functional parts of semiconductor elements are divided.

[0005] Meanwhile, as the number and / or types of semiconductor devices and / or semiconductor chiplets mounted on circuit boards diversify, the semiconductor devices and / or semiconductor chiplets are mounted on circuit boards in various ways. For example, semiconductor devices with relatively fine electrodes can be mounted on circuit boards using connecting members such as micro balls, and semiconductor devices with relatively large electrodes can be mounted on circuit boards using connecting members such as solder paste.

[0006] At this time, when mounting a semiconductor element using a connecting member such as solder paste, the solder paste may be applied to the pads provided on the circuit board and then a reflow process may be performed. At this time, the solder paste includes flux, and the flux described above may flow around the pads during the reflow process. The flux flow may contaminate the surface of the circuit board or cause an electrical short circuit problem that electrically connects adjacent pads. Therefore, after the reflow process, a deflux process is performed to remove the flux described above.

[0007] At this time, the thickness of recent semiconductor packages has been decreasing, which may lead to a decrease in the vertical distance between the pads on the circuit board and the electrodes of the semiconductor device. If the vertical distance described above is reduced, the solution for the deflux process may not sufficiently penetrate the space between the circuit board and the semiconductor device, which may result in electrical and / or mechanical reliability issues due to incomplete removal of the flux.

[0008] At this time, the above-described problem can be solved by increasing the vertical distance between the pad and the terminal of the semiconductor device to ensure sufficient penetration of the solution for the deflux process. However, as described above, semiconductor devices using micro balls can also be mounted on a single circuit board along with semiconductor devices using solder paste. In addition, if the vertical distance between the pad and the terminal of the semiconductor device is increased to improve the penetration of the above-described deflux solution, the size of the micro balls (e.g., width in the horizontal direction and thickness in the vertical direction) may increase, which may also increase the pitch of the pads provided on the circuit board. In this case, the area of ​​the circuit board may increase, making it difficult to miniaturize the semiconductor package, or it may be difficult to arrange all the pads connected to the electrodes of the semiconductor device within a limited space.

[0009] Accordingly, a method is required that can increase the vertical distance between the pad and the semiconductor element to a certain level or more when a connecting member such as solder paste is placed while implementing the fine pitch of the pads provided on the circuit board.

[0010] The embodiment provides a circuit board of a novel structure and a semiconductor package including the same.

[0011] In addition, the embodiment provides a circuit board capable of securing a penetration space for a solution for defluxing and a semiconductor package including the same.

[0012] In addition, the embodiment provides a circuit board and a semiconductor package including the same that can prevent flux that has escaped from an adhesive member from remaining.

[0013] In addition, the embodiment provides a circuit board and a semiconductor package including the same that can increase the vertical distance from a semiconductor element while implementing a fine pitch of pads.

[0014] In addition, the embodiment provides a circuit board having a structure capable of improving the injection characteristics of a molding member and a semiconductor package including the same.

[0015] The technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiment belongs from the description below.

[0016] A circuit board according to an embodiment includes a build-up structure including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up structure and having a through hole penetrating an upper surface and a lower surface; and a plurality of bonding portions disposed on the inner side of the through hole of the protective layer and spaced apart from each other along the perimeter of an inner wall of the through hole.

[0017] Additionally, the vertical thickness of each of the plurality of bonding portions is greater than the vertical thickness of the protective layer.

[0018] Additionally, the spacing between the plurality of bonding portions along the perimeter of the inner wall of the through hole is greater than the vertical thickness of the protective layer.

[0019] In addition, each of the plurality of bonding portions includes a first portion penetrating the protective layer along the vertical direction, and a second portion disposed on the first portion and protruding onto the protective layer, and a spacing distance between the plurality of bonding portions along the perimeter of the inner wall of the through hole is greater than a thickness of the second portion in the vertical direction.

[0020] Additionally, the vertical thickness of the second part is different from the vertical thickness of the protective layer.

[0021] Additionally, the vertical thickness of the second part is greater than the vertical thickness of the protective layer.

[0022] Additionally, the vertical thickness of the second part is between 1.2 and 5 times the vertical thickness of the protective layer.

[0023] Additionally, at least one of the plurality of bonding portions is in contact with the inner wall of the through hole of the protective layer.

[0024] In addition, the plurality of bonding portions include a first bonding portion and a second bonding portion spaced apart from each other along a first horizontal direction, the first bonding portion and the second bonding portion include a first side facing each other along the first horizontal direction, and a second side excluding the first side, and at least a portion of the second side of each of the first bonding portion and the second bonding portion is in contact with an inner wall of a through hole of the protective layer.

[0025] Additionally, the first side surface of each of the first bonding portion and the second bonding portion is spaced apart from the inner wall of the through hole of the protective layer.

[0026] In addition, the plurality of bonding portions further include a third bonding portion and a fourth bonding portion spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction, and the third bonding portion and the fourth bonding portion include a third side facing each other along the second horizontal direction, and a fourth side excluding the third side, and the third side of each of the third bonding portion and the fourth bonding portion is spaced apart from the inner wall of the through hole of the protective layer, and at least a portion of the fourth side of each of the third bonding portion and the fourth bonding portion is in contact with the inner wall of the through hole of the protective layer.

[0027] In addition, the build-up structure includes a wiring layer disposed on a lower surface of the protective layer, the wiring layer includes a plurality of pads overlapping the through hole along the vertical direction, the plurality of bonding portions are disposed on the plurality of pads, and the plurality of pads are spaced apart from each other along the perimeter of the inner wall of the through hole.

[0028] Additionally, the area of ​​the upper surface of at least one bonding portion among the plurality of bonding portions is smaller than the area of ​​the upper surface of at least one pad among the plurality of pads.

[0029] Meanwhile, a semiconductor package according to an embodiment includes a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a pad portion disposed on an upper surface of the build-up insulating layer; a protective layer disposed on the build-up insulating layer and having a through hole overlapping the pad portion along a vertical direction; and a plurality of bonding portions disposed on the pad portion and spaced apart from each other along a perimeter of an inner wall of the through hole.

[0030] Additionally, the vertical thickness of each of the plurality of bonding portions is greater than the vertical thickness of the protective layer.

[0031] Additionally, the spacing between the plurality of bonding portions along the perimeter of the inner wall of the through hole is greater than the vertical thickness of the protective layer.

[0032] In addition, it further includes a semiconductor element disposed on the plurality of bonding portions.

[0033] Additionally, the semiconductor device includes a plurality of terminals, each of the plurality of terminals including a region overlapping the plurality of bonding portions along the vertical direction, and a conductive adhesive member disposed in the overlapping region.

[0034] In addition, the plurality of bonding portions include a first bonding portion and a second bonding portion spaced apart from each other along a first horizontal direction, and a third bonding portion and a fourth bonding portion spaced apart from each other along a second horizontal direction perpendicular to the first horizontal direction, and the first bonding portion and the second bonding portion include a first side facing each other along the first horizontal direction, and a second side excluding the first side, and the third bonding portion and the fourth bonding portion include a third side facing each other along the second horizontal direction, and a fourth side excluding the third side, and at least a portion of the second side of each of the first bonding portion and the second bonding portion is in contact with an inner wall of a through hole of the protective layer, and at least a portion of the fourth side of each of the third bonding portion and the fourth bonding portion is in contact with an inner wall of a through hole of the protective layer.

[0035] Additionally, the first side of each of the first bonding portion and the second bonding portion is spaced apart from the inner wall of the through hole of the protective layer, and the third side of each of the third bonding portion and the fourth bonding portion is spaced apart from the inner wall of the through hole of the protective layer.

[0036] A circuit board according to an embodiment includes a build-up structure including a plurality of insulating layers stacked in a vertical direction, a protective layer disposed on the build-up structure and having a through hole, and a plurality of bonding portions disposed on the inner side of the through hole of the protective layer. At this time, the plurality of bonding portions may be disposed spaced apart from each other along the perimeter of the inner wall of the through hole on the inner side of the protective layer. Therefore, the embodiment can stably mount a semiconductor element on the circuit board by using the above-described plurality of bonding portions, and further increases the vertical distance between the upper surface of the build-up structure and the lower surface of the semiconductor element so that a sufficient space is secured through which a solution for deflux can penetrate.

[0037] That is, the bonding portion can have the function of maintaining a vertical distance between the upper surface of the build-up structure and the lower surface of the semiconductor element at a predetermined distance. In addition to the function of stable electrical connection with the terminal of the semiconductor element, the bonding portion can have the function of allowing the deflux solution to easily penetrate into the space between the upper surface of the build-up structure and the lower surface of the semiconductor element, thereby preventing the flux from remaining on the build-up structure.

[0038] In addition, the bonding portion can allow the molding member to easily flow into the space between the upper surface of the build-up structure and the lower surface of the semiconductor element, thereby stably molding the semiconductor element onto the molding member. Accordingly, the embodiment can stably protect the semiconductor element from external substances such as moisture, and enable the semiconductor element to operate more stably.

[0039] In addition, the vertical thickness of the protective layer may be smaller than the vertical thickness of the protrusion of the bonding portion protruding above the protective layer, thereby solving a reliability problem in which semiconductor devices are not stably bonded due to an increase in stress applied to the bonding portion. Furthermore, the embodiment can prevent an increase in the width and thickness of the adhesive material in an area where a bonding method using micro balls is used, thereby improving the circuit integration by minimizing the pitch of the pads in the bonding area using micro balls. Through this, the embodiment can ensure that a sufficient space is secured for the solution for defluxing to penetrate, thereby solving an electrical short circuit problem and / or a surface contamination problem that may occur due to residual flux.

[0040] In addition, the plurality of bonding portions are arranged to be spaced apart from each other along the direction in which the perimeter of the inner wall of the through hole of the protective layer extends, thereby ensuring a sufficient spacing distance between the plurality of bonding portions along the perimeter direction of the inner wall of the through hole.

[0041] Through this, the embodiment ensures that a sufficient gap between the plurality of bonding portions is secured inside the through-hole of the protective layer. Accordingly, the embodiment can secure not only a vertical gap between the upper surface of the build-up structure and the lower surface of the semiconductor element, but also a horizontal gap between the plurality of bonding portions, thereby facilitating the penetration of the deflux solution and further preventing the flux from remaining on the build-up structure.

[0042] Furthermore, the plurality of bonding portions are spaced apart from each other and arranged along a direction in which the inner wall of the through hole of the protective layer extends, and thus at least one of the plurality of bonding portions may include a portion that is in contact with the inner wall of the through hole. Preferably, a portion of each side surface of the plurality of bonding portions may be in contact with the inner wall of the through hole of the protective layer. Therefore, the embodiment can enable the plurality of bonding portions to be supported by the protective layer in a process of mounting a semiconductor device. Therefore, the embodiment can prevent the bonding portions from being separated due to various heat cycles that occur during a manufacturing process of the circuit board and / or the semiconductor package, and / or during an operation of the semiconductor package, thereby further improving the electrical reliability and / or physical reliability of the circuit board and / or the semiconductor package.

[0043] Furthermore, the embodiment can provide that a portion of each side surface of the plurality of bonding portions is spaced apart from the inner wall of the through hole of the protective layer, thereby preventing stress due to various heat cycles from acting on the bonding portion. Accordingly, the embodiment can prevent cracks from occurring in the bonding portion, thereby further improving the electrical reliability and / or physical reliability of the circuit board and / or semiconductor package.

[0044] Figure 1a is a perspective view schematically showing a circuit board according to an embodiment.

[0045] FIG. 1b is a cross-sectional view taken along the AA' direction of the circuit board of FIG. 1a according to the first embodiment.

[0046] FIG. 1c is a cross-sectional view taken along the BB' direction of the circuit board of FIG. 1a according to the first embodiment.

[0047] FIG. 1d is a cross-sectional view taken along the AA' direction of the circuit board of FIG. 1a according to the second embodiment.

[0048] Figure 2a (a) is a perspective view showing a two-phase MLCC.

[0049] Figure 2a (b) is a drawing showing a plan view after a two-phase MLCC is mounted on a circuit board.

[0050] Figure 2b (a) is a perspective view showing a three-phase MLCC.

[0051] Figure 2b (b) is a drawing showing a plan view after a three-phase MLCC is mounted on a circuit board.

[0052] Figure 3a is a plan view of a state before the protective layer and bonding portion are placed in one area (R1) of Figure 1b.

[0053] Figure 3b is a plan view of a state in which a protective layer having a through hole is arranged in Figure 3a.

[0054] Figure 3c is a plan view of a state in which a bonding portion is arranged on the inside of the through hole of the protective layer in Figure 3b.

[0055] Figure 3d is a plan view showing a modified example of the bonding portion illustrated in Figure 3c.

[0056] Fig. 4 is a perspective view schematically showing a semiconductor package according to the first embodiment.

[0057] Fig. 5 is a plan view of a state in which semiconductor elements are arranged on a circuit board in Fig. 3c.

[0058] Fig. 6a is a cross-sectional view taken along the CC' direction of Fig. 5.

[0059] Figure 6b is a cross-sectional view taken along the DD' direction of Figure 5.

[0060] Fig. 7 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0061] Fig. 8 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0062] Fig. 9 is a cross-sectional view showing a semiconductor package according to the fourth embodiment.

[0063] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0064] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0065] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by those of ordinary skill in the technical field to which the present invention pertains, unless explicitly and specifically defined and described, and commonly used terms, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology. In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention.

[0066] In this specification, singular forms may also include plural forms unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C,” it may include one or more of all combinations that can be combined with A, B, and C. In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0067] These terms are only intended to distinguish the component from other components, and are not intended to limit the nature, order, or sequence of the component by the term. In addition, when a component is described as being "connected," "coupled," or "connected" to another component, it may include not only cases where the component is directly connected, coupled, or connected to the other component, but also cases where the component is "connected," "coupled," or "connected" by another component between the component and the other component.

[0068] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it may include the meaning of the downward direction as well as the upward direction based on one component.

[0069] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0070] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0071]

[0072] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing symbols, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0073]

[0074] Before describing the embodiment, an electronic device (not shown) to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the electronic device is not limited thereto, and it goes without saying that the electronic device may be any other electronic device that processes data.

[0075] An electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to a semiconductor package of the embodiment. Furthermore, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion for electrically connecting the semiconductor element and the circuit board, a resin portion for filling the space between the semiconductor element and the circuit board, and a molding portion for entirely enclosing the semiconductor element.

[0076] Semiconductor devices may include active and / or passive components and may have various functions. Active devices may be in the form of integrated circuits (ICs) in which hundreds of transistors to millions of transistors are integrated into a single semiconductor device, and may be, for example, logic chips, memory chips, etc. For example, the logic chip may be an application processor (AP) device including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), etc., or a set of devices including a specific combination of the above. The memory chip may be a stacked memory such as HBM. In addition, the memory chip may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory. In addition, passive devices may be, for example, resistors, capacitors, and inductors, and are not limited to semiconductor materials, and may be, for example, MLCCs (Multi-Layer Ceramic Capacitors).

[0077] The semiconductor package of the embodiment may be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but is not limited thereto.

[0078]

[0079] FIG. 1a is a perspective view schematically showing a circuit board according to an embodiment, FIG. 1b is a cross-sectional view cut along the AA' direction of the circuit board of FIG. 1a according to the first embodiment, FIG. 1c is a cross-sectional view cut along the BB' direction of the circuit board of FIG. 1a according to the first embodiment, FIG. 1d is a cross-sectional view cut along the AA' direction of the circuit board of FIG. 1a according to the second embodiment, (a) of FIG. 2a is a perspective view showing a two-phase MLCC, (b) of FIG. 2a is a drawing showing a plan view after the two-phase MLCC is mounted on the circuit board, (a) of FIG. 2b is a perspective view showing a three-phase MLCC, and (b) of FIG. 2b is a drawing showing a plan view after the three-phase MLCC is mounted on the circuit board, and FIG. 3a is a state before a protective layer and a bonding portion are arranged in one area (R1) of FIG. 1b. FIG. 3 is a plan view, and FIG. 3b is a plan view in a state where a protective layer having a through hole is arranged in FIG. 3a, FIG. 3c is a plan view in a state where a bonding portion is arranged inside the through hole of the protective layer in FIG. 3b, FIG. 3d is a plan view showing a modified example of the bonding portion shown in FIG. 3c, FIG. 4 is a perspective view schematically showing a semiconductor package according to a first embodiment, FIG. 5 is a plan view in a state where a semiconductor element is arranged on a circuit board in FIG. 3c, FIG. 6a is a cross-sectional view taken along the CC' direction of FIG. 5, FIG. 6b is a cross-sectional view taken along the DD' direction of FIG. 5, FIG. 7 is a cross-sectional view showing a semiconductor package according to a second embodiment, FIG. 8 is a cross-sectional view showing a semiconductor package according to a third embodiment, and FIG. 9 is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0080]

[0081] Hereinafter, a circuit board and a semiconductor package including the same according to an embodiment will be specifically described with reference to FIGS. 1A to 9.

[0082] Before describing the embodiments, a circuit board and a semiconductor package may be defined in a first direction (1D), a second direction (2D), and a third direction (3D). The first direction (1D) may mean a first horizontal direction, an x-axis direction, a horizontal direction, or a length direction, and the first direction (1D), the first horizontal direction, the x-axis direction, the horizontal direction, and the length direction described below may be used with the same meaning. In addition, the second direction (2D) may mean a second horizontal direction, a y-axis direction, a vertical direction, or a width direction, and the second direction (2D), the second horizontal direction, the y-axis direction, the vertical direction, and the width direction described below may be used with the same meaning. In addition, the third direction (3D) may mean a vertical direction, a z-axis direction, or a thickness direction, and the third direction (3D), the vertical direction, the z-axis direction, and the thickness direction described below may be used with the same meaning.

[0083] Referring to FIGS. 1A, 1B and 1C, a circuit board (10) according to the first embodiment may include a build-up structure (100), a protective layer (140, 150) disposed on the upper surface and / or lower surface of the build-up structure (100), and a bonding portion (160) disposed on the inner side of a through hole (141) of the protective layer (140).

[0084] Here, the meaning of being arranged on one side and the other side should not be understood only as a configuration that is in direct contact with the one side and the other side, but should also be understood as having another configuration between one side of the build-up structure (100) and the first protective layer (140), and between the other side of the build-up structure (100) and the second protective layer (150).

[0085] The build-up structure (100) includes a build-up insulating layer (110), a wiring layer (120), and a through electrode (130).

[0086] The build-up insulating layer (110) may have a structure in which a plurality of insulating layers are laminated along the vertical direction. The build-up insulating layer (110) may include a first insulating layer (111) that is closest to the first protective layer (140) along the vertical direction, a second insulating layer (112) that is further away from the first protective layer (140) along the vertical direction than the first insulating layer (111), a third insulating layer (113) that is further away from the first protective layer (140) along the vertical direction than the second insulating layer (112), and a fourth insulating layer (114) that is further away from the first protective layer (140) along the vertical direction than the third insulating layer (113). In this case, the first insulating layer (111) may refer to the uppermost insulating layer positioned at the top in the build-up insulating layer (110) having a structure in which multiple layers are laminated, and the fourth insulating layer (114) may refer to the lowermost insulating layer positioned at the bottom in the build-up insulating layer (110) having a structure in which multiple layers are laminated. However, the embodiment is not limited thereto, and the build-up insulating layer (110) may further include a fifth insulating layer (not shown) positioned between the fourth insulating layer (114) and the second protective layer (125), a sixth insulating layer (not shown) positioned between the fifth insulating layer (not shown) and the second protective layer (125), etc.

[0087] The first to fourth insulating layers (111, 112, 113, 114) are arranged to vertically insulate between the first to fifth wiring layers (121, 122, 123, 124, 125) to be described later. For example, the first to fourth insulating layers (111, 112, 113, 114) may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photo-curable insulating material (Photo Image-able Dielectric, PID) for forming a fine pattern may be used.

[0088] At least one of the first to fourth insulating layers (111, 112, 113, 114) may include an insulating material different from at least one other. For example, at least one of the first to fourth insulating layers (111, 112, 113, 114) may include a reinforcing member (114R). In one embodiment, the reinforcing member (114R) may mean glass fiber. In another embodiment, the reinforcing member (114R) may mean GCP (Glass Core Primer). The reinforcing member (114R) may be provided in at least one of the first to fourth insulating layers (111, 112, 113, 114) to improve the rigidity of the circuit board (10).

[0089] The reinforcing member (114R) can prevent the circuit board (10) from being significantly bent in a specific direction, thereby improving the positional alignment of the wiring layer (120) and the through-electrode (130), thereby improving the electrical reliability and / or mechanical reliability of the circuit board (10) and the semiconductor package. In addition, the reinforcing member (114R) can improve the rigidity of the circuit board (10), thereby improving the processability in the process of mounting a semiconductor element on the circuit board (10), and improving the product yield. Therefore, the reinforcing member (114R) can enable the semiconductor element to be stably mounted on the circuit board (10) and can enable the semiconductor element to operate stably. Through this, electronic products such as servers to which the semiconductor package is applied can be stably operated, thereby improving the operational reliability.

[0090] As illustrated in FIG. 1b or FIG. 1c, the reinforcing member (114R) may be provided on the fourth insulating layer (114). That is, the circuit board (10) may be manufactured in a state in which a carrier member (not shown) is disposed, and the fourth insulating layer (114) may be the layer furthest from the carrier member. At this time, when the reinforcing member (114R) is disposed on the fourth insulating layer (114), the circuit board (10) may be further prevented from being bent in a specific direction during the process of removing the carrier member. However, the embodiment is not limited thereto, and the reinforcing member (114R) may be provided on an insulating layer other than the fourth insulating layer (114). For example, the reinforcing members (114R) may be alternately disposed in the vertical direction within the first to fourth insulating layers (111, 112, 113, 114), thereby further improving the rigidity of the circuit board (10).

[0091] The wiring layer (120) may include a first wiring layer (121) that is most adjacent to the first protective layer (140) in the vertical direction, a second wiring layer (122) that is further away from the first protective layer (140) than the first wiring layer (121), a third wiring layer (123) that is further away from the first protective layer (140) than the second wiring layer (122), a fourth wiring layer (124) that is further away from the first protective layer (140) than the third wiring layer (121), and a fifth wiring layer (125) that is further away from the first protective layer (140) than the fourth wiring layer (124).

[0092] The wiring layer (120) may have, for example, an ETS (Embedded Trace Substrate) structure to implement a fine pattern. Specifically, the wiring layer arranged on the uppermost or lowermost side among the first to fifth wiring layers (121, 122, 123, 124, 125) may be embedded in the build-up insulating layer (110). Here, being embedded means that at least a portion of a side of the wiring layer having the ETS structure is covered with the build-up insulating layer (110). The first wiring layer (121) may be embedded in the first insulating layer (121). The first wiring layer (121) is a wiring layer that is closest to a semiconductor element arranged on a circuit board (10). At this time, when manufacturing the first wiring layer (121) using the ETS method, the pads and traces constituting the first wiring layer (121) can be stably protected by an insulating layer, enabling miniaturization and improving the circuit integration of the first wiring layer (121). Accordingly, it is possible to more easily electrically connect to the semiconductor element placed on the circuit board (10), and the semiconductor element can be made to operate more stably.

[0093] In addition, according to an embodiment having an ETS structure, a concave recess may be provided on the upper surface of the first insulating layer (111) toward the lower surface of the first build-up insulating layer (110), and the first wiring layer (121) may be disposed within the recess of the first insulating layer (111). In addition, the second wiring layer (122) may be disposed within the recess provided on the upper surface of the second insulating layer (112), the third wiring layer (123) may be disposed within the recess provided on the upper surface of the third insulating layer (113), the fourth wiring layer (124) may be disposed within the recess provided on the upper surface of the fourth insulating layer (114), and the fifth wiring layer (125) may protrude below the lower surface of the fourth insulating layer (114). Accordingly, as described above, the circuit integration can be improved by miniaturizing the first to fifth wiring layers (121, 122, 123, 124, 125), the first to fifth wiring layers (121, 122, 123, 124, 125) can be protected from external contaminants such as moisture, and the reliability of the semiconductor package can be improved.

[0094] The first to fifth wiring layers (121, 122, 123, 124, 125) may each include traces for transmitting signals and / or power, and pads for connecting the traces of each of the first to fifth wiring layers (121, 122, 123, 124, 125) to other components. For example, referring to FIG. 1B or FIG. 1C, the first wiring layer (121) and the second wiring layer (122) are connected by the first through electrode (131). At this time, in order for the traces of the first through electrode (131) and the second wiring layer (122) to be connected, the second wiring layer (122) may include a pad connected to the first through electrode (131). Although FIGS. 1b and 1c only illustrate pads of the first wiring layer (121), the first wiring layer (121) may further include traces connecting a plurality of pads.

[0095] The first to fifth wiring layers (121, 122, 123, 124, 125) can function to electrically connect with semiconductor elements placed on a circuit board (10). Each of the first to fifth wiring layers (121, 122, 123, 124, 125) can be freely designed taking impedance into consideration.

[0096] The first wiring layer (121) may include a plurality of pads (121a, 121b, 121c, 121d). The plurality of pads (121a, 121b, 121c, 121d) of the first wiring layer (121) may mean electrodes connected to terminals of semiconductor elements mounted on a circuit board (10).

[0097] At this time, although FIG. 1b and / or FIG. 1c illustrate that the first wiring layer (121) includes four pads (121a, 121b, 121c, 121d), it is not limited thereto. That is, FIG. 1b and FIG. 1c may illustrate a portion (R1) of the entire area of ​​the circuit board (10), and the first wiring layer (121) may further include additional pads connected to other semiconductor elements in other areas than the first area.

[0098] The plurality of pads (121a, 121b, 121c, 121d) may refer to a portion of the plurality of wiring patterns of the first wiring layer (121) that overlaps along a vertical direction with the through hole (141) of the first protective layer (140) to be described later. Accordingly, at least two of the plurality of pads (121a, 121b, 121c, 121d) may refer to a plurality of regions that overlap along a vertical direction with the through hole (141) of the first protective layer (140) to be described later in a single integrated wiring pattern that is connected to each other.

[0099] In addition, a through electrode (130) may be disposed within the build-up insulating layer (110) to connect each of the first to fifth wiring layers (121, 122, 123, 124, 125). The through electrode (130) may include first to fourth through electrodes (131, 132, 133, 134). For example, the first through electrode (131) is disposed between the first wiring layer (121) and the second wiring layer (122), the second through electrode (132) is disposed between the second wiring layer (122) and the third wiring layer (123), the third through electrode (133) is disposed between the third wiring layer (123) and the fourth wiring layer (124), and the fourth through electrode (134) is disposed between the fourth wiring layer (124) and the fifth wiring layer (125). The first to fifth wiring layers (121, 122, 123, 124, 125) are electrically connected to each other through the first to fourth through electrodes (131, 132, 133, 134).

[0100] The first to fourth through-hole electrodes (131, 132, 133, 134) can be formed simultaneously in the process of arranging the second to fifth wiring layers (122, 123, 124, 125). For example, in the process of arranging the second wiring layer (122) under the first wiring layer (121), a through-hole can be formed in the first insulating layer (111) to expose a portion of the first wiring layer (121), thereby forming the second wiring layer (122) together with the first through-hole electrode (131) filling the through-hole of the first insulating layer (111). Therefore, the first through-hole electrode (131) can be distinguished as a protrusion of the second wiring layer (122). Likewise, each of the second to fourth through-hole electrodes (132, 133, 134) is distinguished by a protrusion of each of the third to fifth wiring layers (123, 234, 125) and can be connected to another wiring layer disposed on each wiring layer.

[0101] In addition, since the first to fifth wiring layers (121, 122, 123, 124, 125) are sequentially laminated along the vertical direction on the lower surface of the first protective layer (140), the inclination directions of each of the first to fourth through-electrodes (131, 132, 133, 134) may be the same. For example, each of the first to fourth through-electrodes (131, 132, 133, 134) provided in the build-up structure (100) may have an inclination that becomes wider as it goes toward the second protective layer (150).

[0102] The protective layer (140, 150) may include a first protective layer (140) disposed on the upper surface of the build-up structure (100) and / or a second protective layer (150) disposed on the lower surface of the build-up structure (100). The first protective layer (140) may protect the upper surface of the first wiring layer (121) and / or the first insulating layer (111) from external moisture or contaminants. In addition, when a semiconductor element is disposed on the circuit board (10) using a material such as solder, the first protective layer (140) functions to prevent short circuits between solders due to low wettability with the solder. The first protective layer (140) may use a photocurable insulating material, and for example, a solder resist may be used. However, the embodiment is not limited thereto, and the first protective layer (140) may include a thermocurable insulating material that is the same insulating material as the build-up insulating layer (110). The first protective layer (140) may have the same insulating material as the first insulating layer (111), and may be provided as, for example, ABF (Ajinomoto Build-up Film) from Ajinomoto Corporation.

[0103] The first protective layer (140) may have a through hole (141). The through hole (141) may penetrate the first protective layer (140) from the upper surface of the first protective layer (140) toward the lower surface of the first protective layer (140). For example, the first protective layer (140) may have a through hole (141) that exposes at least a portion of the upper surface of the build-up structure (100). The build-up structure (100) may provide a space in which at least one semiconductor element is arranged, and the first protective layer (140) may include a through hole (141) that overlaps the above-described space of the build-up structure (100) along a vertical direction. For example, the protective layer (140) may have a plurality of pads (121a, 121b, 121c, 121d) of the first wiring layer (121) and a through hole (141) that overlaps along the vertical direction.

[0104] For example, the first protective layer (140) may have one through hole (141) having an area larger than the sum of the areas of the plurality of pads (121a, 121b, 121c, 121d), and the plurality of pads (121a, 121b, 121c, 121d) may be exposed upward from the first protective layer (140) through the one through hole (141).

[0105] A plurality of bonding portions (160) may be arranged on the build-up structure (100). For example, the bonding portions (160) may be bonding electrodes arranged on a plurality of pads (121a, 121b, 121c, 121d). The bonding portions (160) may protrude with a certain thickness on the build-up structure (100). Accordingly, the embodiment can secure a space between the semiconductor element and the build-up structure (100) while allowing the semiconductor element to be mounted on the bonding portions (160).

[0106] The vertical thickness of the bonding portion (160) may be greater than the vertical thickness of the first protective layer (141). Through this, the embodiment can secure a space between the build-up structure (100) and the semiconductor element along the vertical direction by using the bonding portion (160), while also securing a space between the semiconductor element and the first protective layer (141). Therefore, the embodiment can increase the vertical distance between the upper surface of the build-up structure and the lower surface of the semiconductor element by using the bonding portion (160), thereby ensuring that sufficient space is secured for the solution for defluxing to penetrate through this.

[0107] That is, the bonding portion (160) typically functions as a bump that allows the semiconductor element to be stably mounted on the circuit board. In addition, the bonding portion (160) of the embodiment can function to maintain a vertical distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element at a predetermined distance. Therefore, the bonding portion (160) can function to allow the deflux solution to easily penetrate into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element, thereby preventing the flux from remaining on the build-up structure (100). Furthermore, the bonding portion (160) can allow the molding member, which will be described later, to easily flow into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element, thereby allowing the semiconductor element to be stably molded with the molding member. Therefore, the embodiment can stably protect the semiconductor element from external substances such as moisture, and can enable the semiconductor element to operate more stably.

[0108] Specifically, a plurality of bonding portions (160) are provided on the inner side of the through holes (141) of the first protective layer (140) and are spaced apart from each other. For example, a plurality of bonding portions (160) may be arranged on the build-up structure (100) and are spaced apart from each other. For example, the bonding portion (160) may include a plurality of bonding portions (161, 162, 163, 164) arranged on a plurality of pads (121a, 121b, 121c, 121d). The number of the plurality of bonding portions (161, 162, 163, 164) may correspond to the number of pads (121a, 121b, 121c, 121d).

[0109] At this time, the number of terminals provided in the semiconductor element is increasing, and the spacing between the plurality of terminals is decreasing accordingly. Accordingly, the number of pads (121a, 121b, 121c, 121d) is increasing, and the spacing between the pads (121a, 121b, 121c, 121d) is decreasing. Furthermore, the planar area of ​​the through hole (141) of the first protective layer (140) is also decreasing. Accordingly, the process reliability in the process of performing defluxing after arranging the semiconductor element inside the through hole (141), which is a limited space, may be deteriorated.

[0110] For example, conventionally, a defluxing process is performed by infiltrating a defluxing solution between the pads, with all pads connected to the terminals of the semiconductor element being arranged inside the through hole (141). However, as the number of pads increases and the gap between the pads narrows accordingly, the space through which the defluxing solution can infiltrate decreases, and thus the electrical reliability and / or physical reliability of the circuit board and semiconductor package may deteriorate.

[0111] Accordingly, the embodiment increases the vertical separation distance between the build-up structure (100) and the semiconductor element by using the bonding portion (160). Furthermore, the embodiment optimally arranges a plurality of bonding portions (161, 162, 163, 164) within a limited space to further secure a space through which the deflux solution can penetrate. The arrangement structure of the plurality of bonding portions (161, 162, 163, 164) will be described in more detail below.

[0112] At this time, the circuit board according to the embodiments of FIGS. 1b and 1c may be a coreless board without a core layer. For example, the circuit board of the first embodiment may be a circuit board manufactured using the ETS (Embedded Trace Substrate) method, and accordingly, the first to fourth insulating layers (111, 112, 113, 114) may have a structure in which they are sequentially laminated in a vertical direction from the top to the bottom.

[0113] In contrast, according to the embodiment of FIG. 1d, the circuit board may be a core board having a core layer. For example, the circuit board of the second embodiment may be a circuit board manufactured using the SAP method or the MSAP method.

[0114] In this case, as illustrated in FIG. 1d, the circuit board may have a core insulating layer (110a), a core layer (CS), a first build-up layer (UB) disposed on the lower surface of the core layer (CS), and a second build-up layer (LB) disposed on the lower surface of the core layer (CS).

[0115] The core layer (CS) may include a core insulating layer (110a), an upper core wiring layer (110b), a lower core wiring layer (110c), a core through-electrode (110d), and an insulating member (110e).

[0116] The core insulating layer (110a) is composed of a resin such as epoxy resin or BT (bismaleimide triazine) and a reinforcing member (110aR) such as glass fiber, and has the function of improving the rigidity of the circuit board. That is, as the number of terminals of semiconductor devices arranged on the circuit board increases, the wiring becomes more complex, and accordingly, the thickness of the first and second build-up insulating layers (110b, 110c) tends to increase. Accordingly, the core insulating layer (110a) of the present embodiment may have a thickness of 120 μm to 1200 μm in order to improve the overall rigidity of the circuit board and prevent excessive signal loss. A via hole penetrating one surface and the other surface may be formed in the core insulating layer (110a). The via hole of the core insulating layer (110a) may be formed using a mechanical drilling process or a CO2 laser, etc. When a via hole of the core insulating layer (110a) is formed using a mechanical drill, the inclination of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core insulating layer (110a), and when a via hole of the core insulating layer (110a) is formed using a CO2 laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions alternately stacked along the vertical direction. Here, the concave portion may mean a concave region that is concave in a direction away from the horizontal center of the via hole provided in the core insulating layer (110a), and the convex portion may mean a region that protrudes and / or is convex toward the horizontal center of the via hole provided in the core insulating layer (110a). In addition, the concave portions and the convex portions may be alternately provided on the inner wall forming the via hole of the core insulating layer (110a) along the vertical direction. Here, "alternately provided" may mean that a convex portion is provided between multiple concave portions, or that a concave portion is provided between multiple convex portions. In the case of via holes formed using a mechanical drilling process, the path for transmitting electrical signals may be shortened, which may be advantageous for electrical properties, but may also increase the process cost.In addition, when forming concave and convex portions on the inner wall of a via hole using a CO2 laser, the thickness of the core penetration electrode (110d) provided on the inner wall of the via hole can be increased in a subsequent process, which has the advantage of lowering the impedance and lowering the process cost. Accordingly, the processing method of the via hole provided in the core insulating layer (110a) can be freely and selectively used depending on the application field of the semiconductor package.

[0117] A core through electrode (110d) may be placed within the through hole of the core insulating layer (110a). The core through electrode (110d) functions to electrically connect the first build-up layer (UB) and the second build-up layer (LB). Therefore, it is desirable for the core through electrode (110d) to densely fill the via hole for resistance or heat dissipation. However, when the thickness of the core insulating layer (110a) becomes thick as described above, it may become difficult for the core through electrode (110d) to densely fill the via hole. For example, when attempting to fill the via hole provided in the thick core insulating layer (110a) as described above according to the plating process, a void may occur within the core through electrode (110d). The void expands due to heat generated during the operation of the semiconductor package, which may deteriorate the mechanical reliability of the circuit board. Accordingly, a core through-electrode (110d) having a predetermined thickness is arranged on the inner wall of the via hole of the core insulating layer (110a). The thickness of the core through-electrode (110d) refers to the thickness in the horizontal direction perpendicular thereto, not the thickness in the vertical direction in which the first build-up layer (UB), the core insulating layer (110a), and the second build-up layer (LB) are laminated. The thickness of the core through-electrode (110d) may be arranged to have a thickness of 5 μm to 20 μm in order to prevent a voltage drop that occurs as the thickness of the core insulating layer (110a) increases and to prevent the occurrence of voids. It is difficult to densely fill the inner side of the core through-electrode (110d) with metal through a process such as plating, resulting in the creation of empty spaces. The empty spaces may cause problems in that it is difficult to evenly arrange the upper core wiring layer (110b) and the lower core wiring layer (110c).

[0118] Accordingly, the insulating member (110e) can be placed on the inner side of the core through-hole electrode (110d), thereby ensuring the flatness of the core layer (CS). For example, the insulating member (110e) can be placed in the via hole of the core insulating layer (110a), and the core through-hole electrode (110d) can surround the side of the insulating member (110e) and be placed between the inner wall of the via hole and the outer surface of the insulating member (110e).

[0119] The upper surface of the insulating member (110e) may be on the same plane as the upper surface of the core insulating layer (110a), or may be disposed closer to the first build-up layer (UB) in the vertical direction than the upper surface of the core insulating layer (110a). The lower surface of the insulating member (110e) may be on the same plane as the lower surface of the core insulating layer (110a), or may be disposed closer to the second build-up layer (LB) in the vertical direction than the lower surface of the core insulating layer (110a). This can be freely designed to address flatness during lamination of the first build-up layer (UB) and the second build-up layer (LB).

[0120] An upper core wiring layer (110b) is arranged on the upper surface of the core insulation layer (110a), and a lower core wiring layer (110c) is arranged on the lower surface of the core insulation layer (110a). In addition, the upper core wiring layer (110b) and the lower core wiring layer (110c) are electrically connected to each other through a core penetration electrode (100d).

[0121] A first build-up layer (UB) is disposed on one surface of the core layer (CS). The first build-up layer (UB) includes a plurality of upper insulating layers (110f), a plurality of upper circuit layers (120-1), a plurality of upper through-electrodes (130-2), a first protective layer (140a), and a bonding portion (160). A second build-up layer (LB) is disposed on the other surface of the core layer (CS). The second build-up layer (LB) includes a plurality of lower insulating layers (110g), a plurality of lower circuit layers (120-2), a plurality of lower through-electrodes (130-3), and a second protective layer (150a). The insulating layers (110f, 110g), circuit layers (120-1, 120-2), through-electrodes (130-2, 130-3), bonding portions (160a), and protective layers (140a, 150a) of the first build-up layer (UB) and the second build-up layer (LB) may correspond to the build-up insulating layer (110), wiring layer (120), through-electrodes (130), bonding portions (160), and protective layers (140, 150) described in the first embodiment, and a detailed description thereof will be omitted. Hereinafter, the detailed structure of the present invention will be described based on the coreless substrate illustrated in FIGS. 1b and 1c.

[0122] The circuit board (10) described above can provide a space for mounting a semiconductor element. At this time, the types of semiconductor elements mounted on the circuit board (10) can be diverse, and the method for mounting the semiconductor elements on the circuit board (10) can also be diverse depending on the type of semiconductor element. For example, in the case of a semiconductor element having a relatively large terminal size or a low terminal density, a bonding method using an adhesive material such as a general solder paste can be used.

[0123] The bonding method using solder paste can be performed by applying an adhesive such as solder paste having flux inside on pads (121a, 121b, 121c, 121d), and then performing a reflow process while placing a semiconductor element on the adhesive element. At this time, as the reflow process progresses, the flux provided inside the adhesive element may flow, and the flowed flux may contact other adjacent pads, causing an electrical short-circuit problem, and may contact the upper surface of the build-up insulating layer, causing a contamination problem on the surface of the circuit board. Therefore, after the reflow process is performed, a deflux process for removing the above-described flux can be performed. The deflux process can be performed by removing the above-described flux by infiltrating a defluxing solution into the space between the circuit board and the semiconductor element. At this time, the deflux process may completely remove the flux or leave it on the build-up structure (100) depending on whether there is sufficient space for the above-described solution to penetrate.

[0124] At this time, the size of the space through which the solution for the deflux process can penetrate can be determined by the horizontal distance between terminals provided in the semiconductor element and the vertical distance between the semiconductor element and the build-up structure (100). At this time, the vertical distance between the semiconductor element and the build-up structure (100) can be determined by the vertical thickness of the first protective layer (140) disposed on the build-up structure (100).

[0125] However, as circuit boards and / or semiconductor packages become thinner and thinner, the vertical thickness of the first protective layer (140) is becoming thinner, and this limits the ability to increase the vertical distance between the semiconductor element and the build-up structure (100). Furthermore, semiconductor elements may also be mounted on the circuit board using a bonding method other than a solder paste bonding method. For example, in the case of a semiconductor element having a relatively high-density terminal, thermal compression bonding (hereinafter referred to as TC bonding) may be used to reduce the amount of solder used, or a bonding method may be used using an adhesive material having conductive balls inside. At this time, when using a TC bonding method or a bonding method using an adhesive material equipped with a conductive ball, as the thickness of the first protective layer (140) in the vertical direction increases, the width in the horizontal direction and the thickness in the vertical direction of the adhesive material increase, and as a result, the pitch between the pads (121a, 121b, 121c, 121d) may increase.

[0126] At this time, as the functions provided by semiconductor devices have increased and the performance of semiconductor devices has improved in recent years, the number of I / O terminals provided in semiconductor devices has also increased. Accordingly, as the width and / or pitch of the I / O terminals provided in the semiconductor devices have become finer, and as the thickness of the first protective layer (140) in the vertical direction increases, the size of the adhesive member has increased. In the process of connecting the I / O terminals of the semiconductor devices, an electrical short circuit may occur in which a plurality of connecting members come into contact with each other. Due to this, there is a limit to increasing the vertical distance between the semiconductor device and the build-up structure (100) due to the constraints on the thickness of the first protective layer (140) in the vertical direction.

[0127] Furthermore, the horizontal distance between terminals provided in a semiconductor device may be determined by the number and / or density of terminals provided in the semiconductor device. The number of terminals provided in a semiconductor device may vary depending on the type of semiconductor device. As the number of terminals provided in a semiconductor device increases, the horizontal distance between adjacent terminals may decrease, which may make it difficult to secure sufficient space for the solution for the deflux process to penetrate.

[0128] Recently, there has been a trend toward placing capacitors adjacent to semiconductor devices to improve power droop characteristics when transmitting power to them. However, when capacitors are placed as discrete devices, such as in chip form, there is a problem of increased inductance. For example, when considering the case where the capacitor is an MLCC, the conventional two-terminal capacitor can be replaced with a four-terminal capacitor to lower the equivalent inductance, thereby improving the power transmission characteristics transmitted to the semiconductor chip.

[0129] Referring to Fig. 2a, a conventional MLCC may have two terminals. Fig. 2a (a) is a perspective view showing a two-phase MLCC, and Fig. 2a (b) is a plan view showing a two-phase MLCC mounted on a circuit board. The MLCC has an element body (20), a first terminal (21) provided on a first surface of the element body (20), and a second terminal (22) provided on a second surface opposite to the first surface of the element body (20). In this case, since the MLCC may have only two terminals (21, 22), the horizontal distance between the two terminals (21, 22) may be greater than in the case where the MLCC has a larger number of terminals.

[0130] Accordingly, when the MLCC is mounted on the circuit board (10), the flux can be completely removed because sufficient space can be secured for the solution to penetrate corresponding to the distance in the horizontal direction between the two terminals (21, 22).

[0131] Referring to Fig. 2b, the MLCC may have four terminals. Fig. 2b (a) is a perspective view showing a three-phase MLCC, and Fig. 2b (b) is a diagram showing a plan view after the three-phase MLCC is mounted on a circuit board. The MLCC may have an element body (30), a first terminal (31) provided on a first surface of the element body (30), a second terminal (32) provided on a second surface opposite to the first surface of the element body (30), a third terminal (33) provided on a third surface between the first and second surfaces of the element body (30), and a fourth terminal (34) provided on a fourth surface opposite to the third surface of the element body (30). In this case, since the MLCC has four terminals (31, 32, 33, 34), the horizontal distance between the four terminals (31, 32, 33, 34) may be smaller than the horizontal distance in the case where it has only two terminals (21, 22).

[0132] Accordingly, when the MLCC is mounted on the circuit board (10), it may be difficult to secure sufficient space for the solution for defluxing to penetrate because the horizontal distance between the four terminals (31, 32, 33, 34) is relatively small, and thus the flux remaining on the build-up structure (100) may not be completely removed, which may cause an electrical short circuit problem or a contamination problem on the surface of the circuit board, or may cause voids to be generated during subsequent processes such as underfill or molding, which may lower the reliability of the semiconductor package.

[0133] To this end, the embodiment can place a bonding portion (160) on the inside of the through hole (141) of the first protective layer (140), and increase the vertical distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element by using the above-described bonding portion (160), thereby ensuring sufficient space for the solution for defluxing to penetrate.

[0134] That is, the bonding portion (160) can have a function of securing a vertical distance greater than a predetermined distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element. The bonding portion (160) can have a function of allowing a deflux solution to easily penetrate into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element, thereby preventing the flux from remaining on the build-up structure (100). In addition, the bonding portion (160) can have a function of allowing a molding member, which will be described later, to easily flow into the space between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element.

[0135] At this time, the bonding portion (160) may protrude to a certain height above the first protective layer (140). For example, the vertical thickness of the bonding portion (160) and the vertical thickness of the first protective layer (140) may be different.

[0136] At this time, the bonding portion (160) may include first to fourth bonding portions (161, 162, 163, 164) each connected to four terminals of the semiconductor element.

[0137] Additionally, the first bonding portion (161) may include a first portion (161-1) positioned on the inside of the through hole (141) of the first protective layer (140), and a second portion (161-2) protruding above the first portion (161-1).

[0138] The first portion (161-1) of the first bonding portion (161) may overlap with the first protective layer (140) along the horizontal direction. The first portion (161-1) of the first bonding portion (161) may be a penetration portion penetrating the first protective layer (140) along the vertical direction. The second portion (161-2) of the first bonding portion (161) may not overlap with the first protective layer (140) along the horizontal direction. The second portion (161-2) of the first portion (161-1) may be a protrusion portion disposed on the first portion (161-1) and protruding onto the first protective layer (140).

[0139] And, the first bonding portion (161) may be larger than the thickness (H1) of the first protective layer (140) by the vertical thickness (H2) of the second portion (161-2).

[0140] At this time, the vertical thickness (H1) of the first protective layer (140) may be different from the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161). Preferably, the vertical thickness (H1) of the first protective layer (140) may be smaller than the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161).

[0141] If the vertical thickness (H1) of the first protective layer (140) is greater than the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161), the stress generated by the heat cycle due to the first protective layer (140) may increase, which may cause the circuit board to warp significantly in a specific direction. In addition, if the vertical thickness (H1) of the first protective layer (140) is greater than the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161), the width and thickness of the adhesive material in the area where the bonding method using the micro balls described above is used may increase, which may make it difficult to refine the pitch of the pads. In addition, if the thickness (H2) of the second portion (161-2) of the first bonding portion (161) is smaller than the thickness (H1) of the first protective layer (140), it may be difficult to secure sufficient space for the solution for defluxing to penetrate, and this may cause electrical short-circuiting problems and / or surface contamination problems due to residual flux.

[0142] For example, the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161) may range from 1.2 to 5 times the vertical thickness (H1) of the first protective layer (140). If the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161) is less than 1.2 times the vertical thickness (H1) of the first protective layer (140), the effect realized by the arrangement of the bonding portion may be insufficient, and an electrical short circuit problem and / or a surface contamination problem may occur due to residual flux. If the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161) is greater than five times the vertical thickness (H1) of the first protective layer (140), the vertical distance between the build-up structure (100) and the semiconductor element may increase excessively, so that the signal transmission distance of the semiconductor element may increase, and thus the signal transmission characteristics may deteriorate. If the vertical thickness (H2) of the second portion (161-2) of the first bonding portion (161) is greater than five times the vertical thickness (H1) of the first protective layer (140), the vertical thickness of the circuit board (10) may increase.

[0143] Furthermore, each of the second to fourth bonding portions (162, 163, 164) may include a first portion and a second portion corresponding to the first portion (161-1) and the second portion (161-2) of the first bonding portion (161).

[0144] In addition, the area of ​​the upper surface of the bonding portion (160) may be different from the area of ​​the upper surfaces of the pads (121a, 121b, 121c, 121d). For example, the bonding portions (160) may be provided in multiple numbers, and the area of ​​the upper surface of each of the multiple bonding portions (160) may be smaller than the area of ​​the upper surface of the pads (121a, 121b, 121c, 121d). Through this, the embodiment can minimize the area where the bonding portion (160) is arranged inside the through hole (141) of the first protective layer (140). Therefore, the embodiment can secure the maximum space through which the deflux solution can penetrate within a limited space, thereby further improving the electrical reliability and / or mechanical reliability of the circuit board and / or semiconductor package.

[0145] That is, when mounting a semiconductor element using solder on a circuit board, the bonding portion (160) can be placed thicker than the first protective layer (140) to improve the Z-height and facilitate penetration of a solution for deflux when mounting an MLCC.

[0146] Hereinafter, the arrangement structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the bonding portion (160) of the build-up structure (100) of the embodiment will be described in more detail. At this time, the circuit board of the embodiment can provide a space in which a semiconductor element is mounted, and for example, can provide a space in which a three-phase MLCC having four terminals is mounted. Hereinafter, the arrangement structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the bonding portion (160) of the build-up structure (100) in the space in which the three-phase MLCC is mounted will be described. However, the embodiment is not limited thereto, and the structure of the pads (121a, 121b, 121c, 121d), the first protective layer (140), and the bonding portion (160) of the build-up structure (100) described later may also be implemented in a space where other passive components and / or active components other than MLCCs are placed.

[0147] Referring to FIG. 3A, a wiring layer (120) may be arranged on a build-up insulating layer (110). In particular, a first wiring layer (121) provided on the upper surface of the build-up insulating layer (110) is provided on the uppermost side of the circuit board (10). The first wiring layer (121) may have a wiring pattern (121W) connected to a semiconductor element. That is, the wiring pattern (121W) may represent wiring patterns used as pads connected to terminals of a semiconductor element among the first wiring layers (121) provided on the upper surface of the build-up insulating layer (110).

[0148] The wiring pattern (121W) of the first wiring layer (121) may include a first wiring pattern (121W1), a second wiring pattern (121W2), and a third wiring pattern (121W3). The second wiring pattern (121W2) and the third wiring pattern (121W3) may be spaced apart from each other along the second horizontal direction (2D) on the upper surface of the build-up insulating layer (110). In addition, the first wiring pattern (121W1) may be provided to surround the second wiring pattern (121W2) and the third wiring pattern (121W3) at a position spaced apart from the second wiring pattern (121W2) and the third wiring pattern (121W3).

[0149] Referring to FIG. 3B, a first protective layer (140) may be disposed on the build-up insulating layer (110). The first protective layer (140) may have a through hole (141) penetrating from the upper surface of the first protective layer (140) to the lower surface of the first protective layer (140). At least a portion of the through hole (141) may overlap along a vertical direction with the upper surface of the wiring pattern (121W), and another portion may overlap along a vertical direction with the upper surface of the build-up insulating layer (110) in an area where the wiring pattern (121W) is not disposed. In addition, each of the first wiring pattern (121W1), the second wiring pattern (121W2), and the third wiring pattern (121W3) may have a pad that overlaps along a vertical direction with the through hole (141) of the first protective layer (140).

[0150] For example, the first wiring pattern (121W1) may overlap with the through hole (141) in a vertical direction at different locations. For example, the first wiring pattern (121W1) may have a first pad (121a) that overlaps with the through hole (141) in a vertical direction on a first side of the through hole (141). In addition, the first wiring pattern (121W1) may have a second pad (121b) that overlaps with the through hole (141) in a vertical direction on a second side of the through hole (141). The first pad (121a) and the second pad (121b) are part of the first wiring pattern (121W1), and thus, the first pad (121a) and the second pad (121b) may be connected to each other.

[0151] Additionally, the second wiring pattern (121W2) may include a third pad (121c) that overlaps the through hole (141) along a vertical direction on the third side of the through hole (141). Additionally, the third wiring pattern (121W3) may include a fourth pad (121d) that overlaps the through hole (141) along a vertical direction on the fourth side of the through hole (141).

[0152] That is, a part of the through hole (141) of the first protective layer (140) can overlap with the wiring pattern (121W) of the first wiring layer (121) in the vertical direction, and the area in the wiring pattern (121W) that overlaps with the through hole (141) in the vertical direction can be used as a pad (121a, 121b, 121c, 121d) connected to a terminal of a semiconductor element.

[0153] Additionally, at least a portion of the through hole (141) of the first protective layer (140) may not overlap with or may be misaligned with the wiring pattern (121W) in the vertical direction. That is, at least a portion of the upper surface of the build-up insulating layer (110) may overlap with the through hole (141) of the first protective layer (140) in the vertical direction without overlapping with (or misaligning with) the wiring pattern (121W) in the vertical direction.

[0154] For example, one through hole (141) provided in the first protective layer (140) may expose the pads (121a, 121b, 121c, 121d) respectively, and may expose the upper surface of the build-up insulating layer (110) provided between the pads (121a, 121b, 121c, 121d) from the first protective layer (140). However, the embodiment is not limited thereto, and as another example, the through hole (141) of the first protective layer (140) may have a plurality of hole parts spaced apart from each other in the horizontal direction, and each of the plurality of hole parts may overlap each of the pads (121a, 121b, 121c, 121d) in the vertical direction. However, when the through hole (141) of the first protective layer (140) is provided with a plurality of hole parts spaced apart from each other, it may be difficult to secure a space for the deflux solution to penetrate inside the through hole (141). Therefore, the first protective layer (140) may be provided with one through hole (141), and one through hole (141) may expose different areas of the wiring pattern (121W) of the first wiring layer (121). Through this, pads (121a, 121b, 121c, 121d) spaced apart from each other may be provided within one through hole (141) provided in the first protective layer (140).

[0155] For example, the area between the first pad (121a) and the second pad (121b), and / or the area between the third pad (121c) and the fourth pad (121d) may overlap with the through hole (141) of the first protective layer (140) in the vertical direction. Accordingly, the vertical distance between the circuit board and the semiconductor element in the area between the above-described pads (121a, 121b, 121c, 121d) may be the vertical distance between the upper surface of the build-up insulating layer (110) and the upper surface of the semiconductor element.

[0156] Accordingly, the embodiment can increase the vertical distance between the circuit board and the semiconductor element in the area between the pads (121a, 121b, 121c, 121d), thereby allowing the solution for defluxing to penetrate more easily into the above-described area, thereby allowing the flux to be more completely removed. Accordingly, the embodiment can solve the electrical reliability problem that may occur due to the flux not being completely removed, and further can solve the surface contamination problem that may occur due to the flux remaining. Accordingly, the embodiment can improve the electrical reliability of the circuit board, and can allow the semiconductor element placed on the circuit board to be placed more stably. Furthermore, the embodiment can allow the semiconductor element to operate more stably, and can allow products such as servers to which the semiconductor package is applied to operate more stably.

[0157] Referring to FIG. 3c, a bonding portion (160) may be arranged on the inner side of the through hole (141) of the first protective layer (140). For example, a plurality of bonding portions (161, 162, 163, 164) may be arranged on pads (121a, 121b, 121c, 121d) on the inner side of the through hole (141) of the first protective layer (140).

[0158] That is, a first bonding portion (161) may be placed on a first pad (121a), a second bonding portion (162) may be placed on a second pad (121b), a third bonding portion (163) may be placed on a third pad (121c), and a fourth bonding portion (164) may be placed on a fourth pad (121d).

[0159] The first to fourth bonding portions (161, 162, 163, 164) may be respectively arranged on the first to fourth pads (121a, 121b, 121c, 121d) that are spaced apart from each other. Accordingly, the first to fourth bonding portions (161, 162, 163, 164) may be arranged spaced apart from each other inside the through hole (141) of the first protective layer (140).

[0160] At this time, the first to fourth bonding portions (161, 162, 163, 164) may be arranged spaced apart from each other along the perimeter of the through hole (141) on the inner side of the through hole (141). For example, each of the first to fourth bonding portions (161, 162, 163, 164) may be arranged adjacent to the perimeter of the through hole (141). For example, the first protective layer (140) may include an inner wall (140S) forming the through hole (141). In addition, the first to fourth bonding portions (161, 162, 163, 164) may be arranged along the perimeter of the inner wall (140S) of the first protective layer (140). Here, being arranged along the perimeter may mean that each of the first to fourth bonding portions (161, 162, 163, 164) is arranged close to the inner wall (140S) of the through hole (141) of the first protective layer (140).

[0161] Here, the perimeter may refer to the perimeter of the lower end of the inner wall (140S) of the first protective layer (140), but is not limited thereto. For example, the first to fourth bonding portions (161, 162, 163, 164) may be spaced apart from each other and arranged along the perimeter of the upper end of the inner wall (140S) of the through hole (141) of the first protective layer (140). The first to fourth bonding portions (161, 162, 163, 164) may be spaced apart from each other and arranged along the perimeter direction along which the upper or lower end of the inner wall (140S) of the through hole (141) of the first protective layer (140) extends.

[0162] Through this, the embodiment ensures that a sufficient spacing between the first to fourth bonding portions (161, 162, 163, 164) is secured inside the through hole (141) of the first protective layer (140). Specifically, when the first to fourth bonding portions (161, 162, 163, 164) are irregularly arranged inside the through hole (141), the spacing between adjacent bonding portions may be narrower than when the first to fourth bonding portions (161, 162, 163, 164) are provided along the circumferential direction of the inner wall (140S). Due to this, it may be difficult to secure a horizontal spacing between the first to fourth bonding portions (161, 162, 163, 164), and it may be difficult to secure a space through which a solution for deflux can penetrate.

[0163] At this time, the fact that the first to fourth bonding portions (161, 162, 163, 164) are arranged along the periphery of the inner wall (140S) of the through hole (141) of the first protective layer (140) may mean that the first to fourth pads (121a, 121b, 121c, 121d) arranged on the inner side of the through hole (141) are arranged along the periphery direction of the inner wall (140S) of the through hole (141).

[0164] Accordingly, the embodiment may be configured such that the first to fourth pads (121a, 121b, 121c, 121d) are spaced apart from each other along the perimeter of the inner wall (140S) of the through hole (141) of the first protective layer (140) according to the design of the through hole (141) of the first protective layer (140), and further, the first to fourth bonding portions (161, 162, 163, 164) may be spaced apart from each other along the perimeter of the inner wall (140S) of the through hole (141) of the first protective layer (140) on the first to fourth pads (121a, 121b, 121c, 121d).

[0165] Through this, the embodiment can secure a vertical separation distance between the upper surface of the build-up structure (100) and the lower surface of the semiconductor element, while securing a horizontal separation distance between the first to fourth bonding portions (161, 162, 163, 164), thereby ensuring sufficient space for the solution for deflux to penetrate.

[0166] In addition, the embodiment can sufficiently secure a separation distance between the first to fourth bonding portions (161, 162, 163, 164) along the circumferential direction of the inner wall (140S) of the through hole (141) of the protective layer (140). For example, the separation distance between the first to fourth bonding portions (161, 162, 163, 164) along the circumferential direction of the inner wall (140S) of the through hole (141) may be greater than the vertical thickness (H1) of the protective layer (140). Furthermore, the distance between the first to fourth bonding portions (161, 162, 163, 164) along the circumferential direction of the inner wall (140S) of the through hole (141) may be greater than the vertical thickness of the second portion (161-2) of each of the first to fourth bonding portions (161, 162, 163, 164). Through this, the embodiment can more sufficiently secure a space through which the deflux solution can penetrate.

[0167] In addition, the first to fourth bonding portions (161, 162, 163, 164) are arranged along the perimeter of the inner wall (140S) of the through hole (141), so that at least a portion of the first to fourth bonding portions (161, 162, 163, 164) can come into contact with the inner wall (140S) of the through hole (141) of the first protective layer (140).

[0168] For example, at least one of the first to fourth bonding portions (161, 162, 163, 164) may be in contact with the inner wall (140S) of the through hole (141) of the first protective layer (140). Preferably, at least a portion of each of the first to fourth bonding portions (161, 162, 163, 164) may be in contact with the inner wall (140S) of the through hole (141) of the first protective layer (140).

[0169] Specifically, the bonding portion (160) may include a first bonding portion (161) and a second bonding portion (162) facing each other in the first horizontal direction (1D).

[0170] The first bonding portion (161) and the second bonding portion (162) may include first side surfaces (161S1, 162S1) facing each other in the first horizontal direction (1D), and second side surfaces (161S2, 162S2) excluding the first side surfaces (161S1, 162S1). At this time, each of the first bonding portion (161) and the second bonding portion (162) may have a rectangular shape when viewed from a planar perspective in the horizontal direction. Therefore, each of the first bonding portion (161) and the second bonding portion (162) may have four side surfaces. In this case, the first side surfaces (161S1, 162S1) of the first bonding portion (161) and the second bonding portion (162) may refer to one side surface facing each other in the first horizontal direction (1D) among the four side surfaces of each of the first bonding portion (161) and the second bonding portion (162). In addition, the second side surfaces (161S2, 162S2) of the first bonding portion (161) and the second bonding portion (162) may refer to the remaining three side surfaces, excluding the first side surfaces (161S1, 162S1), among the four side surfaces of each of the first bonding portion (161) and the second bonding portion (162).

[0171] And, at least a portion of the second side surfaces (161S2, 162S2) of the first bonding portion (161) and the second bonding portion (162) can be in contact with the first protective layer (140). That is, at least a portion of the second side surface (161S2) of the first bonding portion (161) can be in contact with the inner wall (140S) of the first protective layer (140). In addition, at least a portion of the second side surface (162S2) of the second bonding portion (162) can be in contact with the inner wall (140S) of the first protective layer (140).

[0172] At this time, the width of the first horizontal direction (1D) of the first bonding portion (161) may be smaller than the width of the first pad (121a) in the first horizontal direction (1D). In addition, the width of the second horizontal direction (2D) of the first bonding portion (161) may be smaller than the width of the first pad (121a) in the second horizontal direction (2D). Through this, at least a portion of the second side surface (161S2) of the first bonding portion (161) may be spaced apart from the inner wall (140S) of the first protective layer (140) along the second horizontal direction (2D).

[0173] Additionally, the width of the second bonding portion (162) in the first horizontal direction (1D) may be smaller than the width of the second pad (121b) in the first horizontal direction (1D). Additionally, the width of the second bonding portion (162) in the second horizontal direction (2D) may be smaller than the width of the second pad (121b) in the second horizontal direction (2D). Accordingly, at least a portion of the second side surface (162S2) of the second bonding portion (162) may be spaced apart from the inner wall (140S) of the first protective layer (140) along the second horizontal direction (2D).

[0174] Through this, the embodiment can make at least a part of the second side surface (161S2, 162S2) of the first bonding portion (161) and the second bonding portion (162) come into contact with the first protective layer (140), and through this, in the process of mounting the semiconductor element, at least a part of the first bonding portion (161) and the second bonding portion (162) can be supported by the first protective layer (140). Therefore, the embodiment can prevent the first bonding portion (161) and the second bonding portion (162) from being separated from various heat cycles occurring during the manufacturing process of the circuit board and / or the semiconductor package, and / or the operation of the semiconductor package, and through this, the electrical reliability and / or the physical reliability of the circuit board and / or the semiconductor package can be further improved.

[0175] Furthermore, the embodiment can allow at least a portion of the second side surfaces (161S2, 162S2) of the first bonding portion (161) and the second bonding portion (162) to be spaced apart from the first protective layer (140), thereby preventing stress due to various heat cycles from acting on the first bonding portion (161) and the second bonding portion (162). Accordingly, the embodiment can prevent cracks from occurring in the first bonding portion (161) and the second bonding portion (162), thereby further improving the electrical reliability and / or physical reliability of the circuit board and / or the semiconductor package.

[0176] Additionally, the bonding portion (160) may include a third bonding portion (163) and a fourth bonding portion (164) facing each other in the second horizontal direction (2D).

[0177] The third bonding portion (163) and the fourth bonding portion (164) may include third side surfaces (163S1, 164S1) facing each other in the first horizontal direction (1D), and fourth side surfaces (163S2, 164S2) excluding the third side surfaces (163S1, 164S1). At this time, each of the third bonding portion (163) and the fourth bonding portion (164) may have a rectangular shape when viewed from a planar perspective in the horizontal direction. Therefore, each of the third bonding portion (163) and the fourth bonding portion (164) may have four side surfaces. In this case, the third side surfaces (163S1, 164S1) of the third bonding portion (163) and the fourth bonding portion (164) may refer to one side facing each other in the second horizontal direction (2D) among the four side surfaces of each of the third bonding portion (163) and the fourth bonding portion (164). In addition, the fourth side surfaces (163S2, 164S2) of the third bonding portion (163) and the fourth bonding portion (164) may refer to the remaining three side surfaces excluding the third side surfaces (163S1, 164S1) among the four side surfaces of each of the third bonding portion (163) and the fourth bonding portion (164).

[0178] And, at least a portion of the fourth side surface (163S2, 164S2) of the third bonding portion (163) and the fourth bonding portion (164) can be in contact with the first protective layer (140). That is, at least a portion of the fourth side surface (163S2) of the third bonding portion (163) can be in contact with the inner wall (140S) of the first protective layer (140). In addition, at least a portion of the fourth side surface (164S2) of the fourth bonding portion (164) can be in contact with the inner wall (140S) of the first protective layer (140).

[0179] At this time, the width of the third bonding portion (163) in the first horizontal direction (1D) may be smaller than the width of the third pad (121c) in the first horizontal direction (1D). In addition, the width of the third bonding portion (163) in the second horizontal direction (2D) may be smaller than the width of the third pad (121c) in the second horizontal direction (2D). Through this, at least a portion of the fourth side surface (163S2) of the third bonding portion (163) may be spaced apart from the inner wall (140S) of the first protective layer (140) along the second horizontal direction (2D).

[0180] Additionally, the width of the fourth bonding portion (164) in the first horizontal direction (1D) may be smaller than the width of the fourth pad (121d) in the first horizontal direction (1D). Additionally, the width of the fourth bonding portion (164) in the second horizontal direction (2D) may be smaller than the width of the fourth pad (121d) in the second horizontal direction (2D). Accordingly, at least a portion of the fourth side surface (164S2) of the fourth bonding portion (164) may be spaced apart from the inner wall (140S) of the first protective layer (140) along the second horizontal direction (2D).

[0181] Through this, the embodiment can make at least a part of the fourth side surface (163S2, 164S2) of the third bonding portion (163) and the fourth bonding portion (164) come into contact with the first protective layer (140), and through this, in the process of mounting the semiconductor element, at least a part of the third bonding portion (163) and the fourth bonding portion (164) can be supported by the first protective layer (140). Therefore, the embodiment can prevent the third bonding portion (163) and the fourth bonding portion (164) from being separated from various heat cycles occurring during the manufacturing process of the circuit board and / or the semiconductor package, and / or the operation of the semiconductor package, and through this, the electrical reliability and / or the physical reliability of the circuit board and / or the semiconductor package can be further improved.

[0182] Furthermore, the embodiment can allow at least a portion of the fourth side surfaces (163S2, 164S2) of the third bonding portion (163) and the fourth bonding portion (164) to be spaced apart from the first protective layer (140), thereby preventing stresses due to various heat cycles from acting on the third bonding portion (163) and the fourth bonding portion (164). Accordingly, the embodiment can prevent cracks from occurring in the third bonding portion (163) and the fourth bonding portion (164), thereby further improving the electrical reliability and / or physical reliability of the circuit board and / or the semiconductor package.

[0183] In addition, according to the embodiment of FIG. 3D, the width of the first horizontal direction (1D) of the first bonding portion (161) may be smaller than the width of the first pad (121a) in the first horizontal direction (1D). In addition, the width of the second horizontal direction (2D) of the first bonding portion (161) may be the same as the width of the first pad (121a) in the second horizontal direction (2D). Through this, the second side surface (161S2) of the first bonding portion (161) may be in contact with the inner wall (140S) of the first protective layer (140) as a whole.

[0184] Accordingly, the width of the second bonding portion (162) in the first horizontal direction (1D) may be smaller than the width of the second pad (121b) in the first horizontal direction (1D). In addition, the width of the second bonding portion (162) in the second horizontal direction (2D) may be the same as the width of the second pad (121b) in the second horizontal direction (2D). Through this, the second side surface (162S2) of the second bonding portion (162) may be in contact with the inner wall (140S) of the first protective layer (140) as a whole.

[0185] Accordingly, the embodiment can make the second side surfaces (161S2, 162S2) of the first bonding portion (161) and the second bonding portion (162) come into contact with the first protective layer (140) as a whole, thereby enabling the first bonding portion (161) and the second bonding portion (162) to be positioned more stably in the process of mounting the semiconductor element. Accordingly, the embodiment can prevent the first bonding portion (161) and the second bonding portion (162) from being separated due to various heat cycles occurring during the manufacturing process of the circuit board and / or the semiconductor package, and / or the operation of the semiconductor package, thereby further improving the electrical reliability and / or the physical reliability of the circuit board and / or the semiconductor package.

[0186]

[0187] Referring to FIGS. 4 and 5, the semiconductor package of the embodiment may include a circuit board and a semiconductor element (300) disposed on the circuit board.

[0188] The circuit board may include a build-up structure (100), a first protective layer (140), and a second protective layer (150), and a plurality of bonding portions (160) spaced apart from each other may be arranged along the perimeter of the inner wall (140S) of the through hole (141) on the inner side of the through hole (141) of the first protective layer (140).

[0189] In addition, the build-up structure (100) may include a build-up insulating layer (110) and a plurality of pads (121a, 121b, 121c, 121d). In addition, the first protective layer (140) may be disposed on the build-up insulating layer (110) and may have a through hole (141) that overlaps the plurality of pads (121a, 121b, 121c, 121d) in a vertical direction.

[0190] Additionally, a plurality of bonding portions (161, 162, 163, 164) are arranged on a plurality of pads (121a, 121b, 121c, 121d).

[0191] A semiconductor element (300) may be placed on a build-up structure (100). The semiconductor element (300) may include an element body (301) and first to fourth terminals (302, 303, 304, 305). Each of the first to fourth terminals (302, 303, 304, 305) may be electrically connected to a plurality of bonding portions (161, 162, 163, 164) placed on pads (121a, 121b, 121c, 121d) and adhesive members (410, 420, 430, 440).

[0192] The semiconductor element (300) includes a region overlapping with a plurality of bonding portions (161, 162, 163, 164) along the vertical direction. That is, each of the first to fourth terminals (302, 303, 304, 305) of the semiconductor element (300) may include a region (OR1, OR2, OR3, OR4) overlapping with a plurality of bonding portions (161, 162, 163, 164) along the vertical direction. Here, the semiconductor element (300) includes active elements such as a CPU, a Memory, a GPU, an FPGA, and should be interpreted to mean not only elements made of a semiconductor material such as silicon (Si), but also capacitors and electronic elements such as MLCC.

[0193] By way of example, the first terminal (302) of the semiconductor device (300) includes a first overlapping region (OR1) that overlaps the first bonding portion (161) along the vertical direction. The second terminal (303) of the semiconductor device (300) includes a second overlapping region (OR2) that overlaps the second bonding portion (162) along the vertical direction. The third terminal (304) of the semiconductor device (300) includes a third overlapping region (OR3) that overlaps the third bonding portion (163) along the vertical direction. The fourth terminal (305) of the semiconductor device (300) includes a fourth overlapping region (OR4) that overlaps the fourth bonding portion (164) along the vertical direction.

[0194] Through this, referring to FIGS. 6A and 6B, the first terminal (302) and the first bonding portion (161) of the semiconductor element (300) can be electrically coupled through the first adhesive member (410). In addition, the second terminal (303) and the second bonding portion (162) of the semiconductor element (300) can be electrically coupled through the second adhesive member (420). In addition, the third terminal (304) and the third bonding portion (163) of the semiconductor element (300) can be electrically coupled through the third adhesive member (430). The fourth terminal (305) and the fourth bonding portion (164) of the semiconductor element (300) can be electrically coupled through the fourth adhesive member (440).

[0195] Accordingly, the semiconductor element (300) can be spaced apart vertically from the upper surface of the build-up insulating layer (110) by the thickness of the bonding portion (160) when placed on the bonding portion (160). Therefore, the embodiment can secure a sufficient space for the solution for defluxing to penetrate by the thickness of the bonding portion (160) compared to a structure that does not include the bonding portion (160), thereby improving the problem of voids occurring during subsequent processes such as underfill and / or molding, and thus significantly improving the electrical reliability and / or mechanical reliability of the circuit board and the semiconductor package.

[0196] Furthermore, the embodiment includes first to fourth bonding portions (161, 162, 163, 164) spaced apart from each other and arranged along the perimeter of the inner wall (140S) of the through hole (141) of the first protective layer (140).

[0197] Accordingly, the embodiment can sufficiently secure not only the vertical separation distance described above, but also the separation distance between the first to fourth bonding portions (161, 162, 163, 164). Through this, it is possible to facilitate the penetration of the solution for deflux into the space between the first bonding portion (161) and the third bonding portion (163), the space between the second bonding portion (162) and the third bonding portion (163), the space between the first bonding portion (161) and the fourth bonding portion (164), and the space between the second bonding portion (162) and the fourth bonding portion (164) along the perimeter of the inner wall (140S) of the through hole (141) of the first protective layer (140), and it is possible to enable the MLCC to be stably mounted.

[0198]

[0199] Referring to FIG. 7, a semiconductor package according to the second embodiment may include a build-up structure (500), a first semiconductor element (540), and a second semiconductor element (560).

[0200] The first semiconductor element (540) and the second semiconductor element (560) may be mounted on the build-up structure (500) using different bonding methods. For example, the first semiconductor element (540) may be mounted on the build-up structure (500) through a first adhesive member (530) using solder paste. In this case, the build-up structure (500) may have a first pad portion (501) on the upper surface, and the first adhesive member (530) may be disposed on the first pad portion (501). In addition, a protective layer (510) having a through hole overlapping the first pad portion (501) in a vertical direction may be disposed on the build-up structure (500), and a bonding portion (520) may be disposed on the first pad portion (501) on the inner side of the through hole of the protective layer (510). Accordingly, the first semiconductor element (540) can be electrically coupled to the bonding portion (520) through the first adhesive member (450).

[0201] Additionally, the second semiconductor element (560) may be mounted on the build-up structure (500) via a second adhesive member (550) using TC bonding and / or micro balls. In this case, a second pad portion (502) may be further provided on the build-up structure (500), and the second adhesive member (560) may be placed on the second pad portion (502).

[0202] At this time, the second semiconductor element (560) may not overlap or may be misaligned with the bonding portion (520) in the vertical direction. For example, the bonding portion (520) may not be provided around the area where the second semiconductor element (560) is mounted and / or around the second pad portion (502). Therefore, the embodiment can reduce the size of the second adhesive member (550), and thereby make it possible to refine the pitch of the second pad portion (502).

[0203] Additionally, the semiconductor package may further include a molding member (570). The molding member (570) may be provided to surround the first semiconductor element (540) and the second semiconductor element (550).

[0204]

[0205] Referring to FIG. 8, a semiconductor package may include a build-up structure (600), and a first semiconductor element (640), a second semiconductor element (670), and a third semiconductor element (675) may be mounted on the build-up structure (600).

[0206] The first semiconductor element (640) may be mounted on the build-up structure (600) in a different bonding manner from the second semiconductor element (670) and the third semiconductor element (680). For example, the first semiconductor element (640) may be mounted on the build-up structure (600) through a first adhesive member (630) using solder paste. In this case, a first pad portion (601) may be provided on the upper surface of the build-up structure (600), and the first adhesive member (630) may be disposed on the first pad portion (601). In addition, a protective layer (610) having a through hole overlapping the first pad portion (601) in a vertical direction may be disposed on the build-up structure (600), and a bonding portion (620) may be disposed on the first pad portion (601) on the inner side of the through hole of the protective layer (610). Accordingly, the first semiconductor element (640) can be electrically coupled to the bonding portion (620) through the first adhesive member (650).

[0207] Additionally, the second and third semiconductor elements (670, 675) may be mounted on the build-up structure (600) via a second adhesive member (650) using TC bonding and / or micro balls. In this case, the build-up structure (600) may further include second and third pad portions (602, 603), and the second adhesive member (560) may be placed on the second and third pad portions (602, 603).

[0208] At this time, the second and third semiconductor elements (670, 675) may not overlap or may be misaligned with the bonding portion (620) in the vertical direction. For example, the bonding portion (620) may not be provided around the area where the second and third semiconductor elements (670, 675) are mounted and / or around the second and third pad portions (602, 603). Therefore, the embodiment can reduce the size of the second adhesive member (650), and thereby make it possible to refine the pitch of the second and third pad portions (602, 603).

[0209] In addition, the circuit board may further include a connecting member (680) embedded in the build-up structure (600). Recently, as the number of signals that semiconductor devices must process increases, the size of semiconductor devices is trending toward larger areas, but this larger area of ​​semiconductor devices is causing problems in lowering the yield of semiconductor devices. Therefore, there is a trend to divide the pattern size or functional part of the semiconductor device, place chiplets on the circuit board, and embed connecting members (680) that have the function of electrically connecting them in the circuit board. However, the connecting members (680) are not limited thereto, and may connect semiconductor devices with other functions, such as memory.

[0210] The connecting member (680) may be disposed within the insulating layer adjacent to the protective layer (610) in the build-up structure (600). In this case, the signal transmission distance between the second and third semiconductor elements (670, 675) and the connecting member (680) can be reduced, which is advantageous in preventing signal loss. That is, the connecting member (680) electrically connects a plurality of semiconductor elements disposed on the circuit board, and thus, reducing the signal transmission distance while being adjacent to the plurality of semiconductor elements can be advantageous in reducing signal transmission loss.

[0211] In addition, a third connecting member (690) is arranged on the lower surfaces of the second and third pad portions (602, 603). The third connecting member (690) may be solder, but is not limited thereto. The connecting member (680) has a pad portion, and the pad portion of the connecting member (680) is electrically connected to the second and third pad portions (602, 603) through the third connecting member (690).

[0212] The connecting member (680) may function to electrically connect the second and third semiconductor elements (670, 675). In this case, the connecting member (680) may be a bridge die. For example, the connecting member (680) partially overlaps the second and third semiconductor elements (670, 675) in the vertical direction, respectively. In addition, the connecting member (680) electrically connects a portion of the terminals of each of the second and third semiconductor elements (670, 675) to each other. The connecting member (680) may be formed of a material similar to the semiconductor element, such as silicon, or may be formed of an organic material such as a photosensitive resin or a thermosetting resin. A plurality of semiconductor elements having different functions, such as a chiplet unit separated according to function and / or pitch, or a CPU and a GPU, or a GPU and an HBM, may be mounted on a circuit board, and the connecting member (680) may function to horizontally electrically connect them.

[0213] The connecting member (680) may be an organic bridge that can smoothly supply power from the bottom to the top while minimizing the loss of the supplied power. In this case, in the case of an inorganic bridge including a silicon substrate, power can be supplied through a TSV (Through Silicon Via), but there is a problem that the process cost for TSV processing increases and the product yield decreases. Therefore, the connecting member (680) of the embodiment is preferably an organic bridge.

[0214]

[0215] According to the embodiment of FIG. 9, the circuit board described above can be used as an interposer (700) provided between the semiconductor package substrate and the semiconductor element of the semiconductor package.

[0216] That is, as the terminal density of semiconductor devices increases, the wiring becomes more complex, and accordingly, the thickness of the circuit board increases. However, as the thickness increases, the yield of the circuit board may decrease. Therefore, the circuit board may be divided into an interposer (700) and a semiconductor package substrate (720) and used, and the above-described circuit board may be used not only as a semiconductor package substrate (720) but also as an interposer (700).

[0217] A semiconductor package substrate (720) is placed on the lower surface of the interposer (700). The semiconductor package substrate (720) can electrically connect the main board of an electronic device and the interposer.

[0218] At this time, a fourth connecting member (710) may be placed between the interposer and the semiconductor package substrate (720), through which the interposer and the semiconductor package substrate (720) may be electrically coupled.

[0219]

[0220] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0221] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0222] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0223] Although the above has been described focusing on embodiments, these are merely examples and are not intended to limit the embodiments. Those skilled in the art to which the embodiments pertain will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. A build-up structure comprising a plurality of insulating layers stacked along a vertical direction; A protective layer disposed on the above build-up structure and having a through hole penetrating the upper and lower surfaces; and A circuit board comprising a plurality of bonding portions arranged on the inner side of the through hole of the protective layer and spaced apart from each other along the perimeter of the inner wall of the through hole.

2. In paragraph 1, A circuit board, wherein the vertical thickness of each of the plurality of bonding portions is greater than the vertical thickness of the protective layer.

3. In paragraph 1, A circuit board, wherein the spacing between the plurality of bonding portions along the perimeter of the inner wall of the through hole is greater than the vertical thickness of the protective layer.

4. In paragraph 3, Each of the plurality of bonding portions includes a first portion penetrating the protective layer along the vertical direction, and a second portion disposed on the first portion and protruding above the protective layer, A circuit board, wherein the distance between the plurality of bonding portions along the perimeter of the inner wall of the through hole is greater than the vertical thickness of the second portion.

5. In paragraph 4, A circuit board in which the vertical thickness of the second portion is different from the vertical thickness of the protective layer.

6. In paragraph 5, A circuit board in which the vertical thickness of the second part is greater than the vertical thickness of the protective layer.

7. In paragraph 5, A circuit board in which the vertical thickness of the second part is between 1.2 and 5 times the vertical thickness of the protective layer.

8. In paragraph 1, A circuit board, wherein at least one of the plurality of bonding portions is in contact with the inner wall of the through hole of the protective layer.

9. In paragraph 8, The above plurality of bonding portions include a first bonding portion and a second bonding portion spaced apart from each other along a first horizontal direction, The first bonding portion and the second bonding portion include a first side facing each other along the first horizontal direction, and a second side excluding the first side, A circuit board, wherein at least a portion of the second side surface of each of the first bonding portion and the second bonding portion is in contact with the inner wall of the through hole of the protective layer.

10. In paragraph 9, A circuit board, wherein the first side surface of each of the first bonding portion and the second bonding portion is spaced apart from the inner wall of the through hole of the protective layer.

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