Light-emitting die and manufacturing method therefor, and display substrate and display apparatus

Abstract

Disclosed are a light-emitting die and a manufacturing method therefor, and a display substrate and a display apparatus. The light-emitting die comprises: a plurality of light-emitting bodies arranged on a substrate, wherein the plurality of light-emitting bodies are sequentially arranged in a direction away from the substrate, and light emission wavelengths of the plurality of light-emitting bodies sequentially increase in a first direction; transflective layers, wherein a transflective layer is arranged between every two adjacent light-emitting bodies, the transflective layers are used for reflecting light emitted by the light-emitting bodies which are located on the side of the transflective layers in a second direction and are adjacent to the transflective layers, and transmitting light emitted by the light-emitting bodies which are located on the side of the transflective layers in the first direction, one of the first direction and the second direction being a direction approaching the substrate, and the other one being the direction that is away from the substrate; and reflective electrodes, which are arranged on the side of the plurality of light-emitting bodies in the first direction, wherein the reflective electrodes are used for reflecting light emitted by the light-emitting bodies which are adjacent thereto.

Description

Light-emitting chip and manufacturing method thereof, display substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a light-emitting chip and a manufacturing method thereof, a display substrate, and a display device. Background Art

[0002] Micro-inorganic light-emitting diodes include MiniLED and MicroLED. MiniLED refers to light-emitting diode (LED) chips with a grain size of approximately 100 to 300 microns. MicroLED refers to LED chips with a grain size of less than 100 microns. MiniLED / MicroLED display devices offer advantages such as low power consumption, high brightness, high resolution, high color saturation, fast response, long life, and high efficiency. Furthermore, multiple Mini-LED / Micro-LED display devices can be seamlessly spliced ​​together to create ultra-large display products, which have broad application prospects in large-scale display areas such as command and monitoring centers, commercial centers, high-end conferences, and cinemas.

[0003] Summary of the Invention

[0004] In a first aspect, the present disclosure provides a light-emitting chip, comprising:

[0005] A plurality of light-emitting bodies are provided on a substrate, wherein the plurality of light-emitting bodies are sequentially arranged in a direction away from the substrate; and along a first direction, the light-emitting wavelengths of the plurality of light-emitting bodies sequentially increase;

[0006] a transflective layer; wherein the transflective layer is disposed between each two adjacent light-emitting bodies, the transflective layer being configured to reflect light emitted by a light-emitting body adjacent to the transflective layer and located on one side of the transflective layer along the second direction, and to transmit light emitted by each light-emitting body located on one side of the transflective layer along the first direction; one of the first direction and the second direction being a direction close to the substrate, and the other being a direction away from the substrate;

[0007] The reflective electrode is arranged on one side of the plurality of light-emitting bodies along the first direction, and is used for reflecting the light emitted by the light-emitting bodies adjacent to the reflective electrode.

[0008] In some embodiments, the light-emitting body includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed in a direction away from the substrate;

[0009] The light-emitting chip further includes:

[0010] an insulating layer, the insulating layer being located on a side of the plurality of light-emitting bodies away from the substrate;

[0011] a plurality of connecting electrodes, located on a side of the insulating layer away from the substrate, the connecting electrodes being electrically connected to the light-emitting body via via holes at least penetrating the insulating layer;

[0012] The first semiconductor layer and the second semiconductor layer are both electrically connected to the connection electrode, and the first semiconductor layer and the second semiconductor layer in the same light-emitting body are connected to different connection electrodes.

[0013] In some embodiments, in at least two adjacent light-emitting bodies, the second semiconductor layer in the one close to the substrate and the first semiconductor layer in the one far from the substrate are connected to the same switching electrode.

[0014] In some embodiments, the light-emitting chip further includes a transmissive electrode, the transmissive electrode being located on a side of the plurality of light-emitting bodies away from the reflective electrode and being electrically connected to an adjacent light-emitting body;

[0015] The plurality of connection electrodes include a first connection electrode and a second connection electrode. The first connection electrode is electrically connected to the transmission electrode through a first via hole; and the second connection electrode is electrically connected to the reflection electrode through a second via hole.

[0016] In some embodiments, the plurality of light-emitting bodies include: a first light-emitting body, a second light-emitting body, and a third light-emitting body, which are sequentially arranged in a direction away from the substrate;

[0017] The multiple connecting electrodes include a third connecting electrode and a fourth connecting electrode, the third connecting electrode is electrically connected to the second semiconductor layer of the first light-emitting body through a third via hole, and is electrically connected to the first semiconductor layer of the second light-emitting body through a fourth via hole; the fourth connecting electrode is electrically connected to the second semiconductor layer of the second light-emitting body through a fifth via hole, and is electrically connected to the first semiconductor layer of the third light-emitting body through a sixth via hole.

[0018] In some embodiments, the plurality of light-emitting bodies include: a first light-emitting body, a second light-emitting body, and a third light-emitting body, which are sequentially arranged in a direction away from the substrate;

[0019] The first light emitting body further includes a first conductive layer, and the first conductive layer is located on a side of the second semiconductor layer away from the substrate;

[0020] The second light-emitting body further includes a second conductive layer and a third conductive layer, the second conductive layer is located on a side of the first semiconductor layer of the second light-emitting body close to the substrate, and the third conductive layer is located on a side of the second semiconductor layer of the second light-emitting body away from the substrate;

[0021] The third light-emitting body further includes a fourth conductive layer, and the fourth conductive layer is located on a side of the first semiconductor layer of the third light-emitting body close to the substrate;

[0022] The multiple connecting electrodes include a third connecting electrode and a fourth connecting electrode, the third connecting electrode is electrically connected to the first conductive layer through a third via hole, and is electrically connected to the second conductive layer through a fourth via hole; the fourth connecting electrode is electrically connected to the third conductive layer through a fifth via hole, and is electrically connected to the fourth conductive layer through a sixth via hole.

[0023] In some embodiments, the insulating layer includes a passivation layer and a planarization layer, and the planarization layer is located on a side of the passivation layer away from the substrate.

[0024] In some embodiments, the first direction is a direction away from the substrate, and the second direction is a direction close to the substrate.

[0025] In a second aspect, the present disclosure further provides a method for manufacturing a light-emitting chip, comprising:

[0026] forming an epitaxial layer on a first substrate, wherein the epitaxial layer includes a plurality of light-emitting main layers stacked in sequence, and a transflective material layer located between two adjacent light-emitting main layers;

[0027] transferring the epitaxial layer onto a substrate, and forming a reflective electrode layer on one side of the epitaxial layer along a first direction;

[0028] Performing a patterning process on the multiple light-emitting body layers to form multiple light-emitting bodies of the light-emitting chip; performing a patterning process on the transflective material layer to form a transflective layer of the light-emitting chip; performing a patterning process on the reflective electrode layer to form a reflective electrode of the light-emitting chip;

[0029] Among them, along the first direction, the light-emitting wavelengths of the multiple light-emitting entities increase successively; the transflective layer is used to reflect the emitted light of the light-emitting entity located on the side of the reflective layer along the second direction and adjacent to the reflective layer, and transmit the emitted light of each light-emitting entity located on the side of the transflective layer along the first direction; one of the first direction and the second direction is a direction close to the substrate, and the other is a direction away from the substrate; the reflective electrode is used to reflect the emitted light of the light-emitting entity adjacent to it.

[0030] In some embodiments, the step of transferring the epitaxial layer onto a substrate comprises:

[0031] Bonding the epitaxial layer to the base through bonding glue, wherein the base is located on a side of the epitaxial layer away from the first substrate;

[0032] The first substrate is removed.

[0033] In some embodiments, the step of transferring the epitaxial layer onto a substrate comprises:

[0034] Bonding the epitaxial layer to a second substrate through a temporary bonding adhesive, wherein the second substrate is located on a side of the epitaxial layer away from the first substrate;

[0035] removing the first substrate;

[0036] Bonding the epitaxial layer to the substrate via bonding glue, wherein the substrate is located on a side of the epitaxial layer away from the second substrate;

[0037] The second substrate is removed.

[0038] In some embodiments, the light-emitting body includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially disposed in a direction away from the substrate;

[0039] The production method further comprises:

[0040] forming an insulating layer on a side of the plurality of light-emitting bodies away from the substrate;

[0041] forming a plurality of connecting electrodes on a side of the insulating layer away from the substrate, wherein the connecting electrodes are electrically connected to the light-emitting body through via holes penetrating the insulating layer;

[0042] The first semiconductor layer and the second semiconductor layer are both electrically connected to the connection electrode, and the first semiconductor layer and the second semiconductor layer in the same light-emitting body are connected to different connection electrodes.

[0043] In some embodiments, the manufacturing method further comprises:

[0044] forming a transmissive electrode, the transmissive electrode being located on a side of the plurality of light-emitting bodies away from the reflective electrode and being electrically connected to an adjacent light-emitting body;

[0045] The plurality of connecting electrodes include a first connecting electrode and a second connecting electrode. The first connecting electrode is electrically connected to the transmissive electrode through a first via hole; and the second connecting electrode is electrically connected to the reflective electrode through a second via hole.

[0046] In a third aspect, the present disclosure further provides a display substrate, which includes a driving backplane and a plurality of light-emitting chips arranged on the driving backplane, and the light-emitting chips are the light-emitting chips mentioned above.

[0047] In a fourth aspect, the present disclosure further provides a display device, which includes the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following detailed description, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0049] FIG1 is a top view of a light-emitting chip provided in some embodiments of the present disclosure.

[0050] FIG2 is a cross-sectional view taken along line AA' in FIG1.

[0051] FIG3 is a cross-sectional view taken along line BB' in FIG1 .

[0052] FIG4 is a cross-sectional view along line AA′ in FIG1 provided in some other embodiments of the present disclosure.

[0053] FIG5 is a cross-sectional view along line BB′ in FIG1 provided in some other embodiments of the present disclosure.

[0054] FIG6 is a flow chart of a method for manufacturing a light-emitting chip provided in some embodiments of the present disclosure.

[0055] 7A to 7F are schematic structural diagrams of the light-emitting chip manufacturing process provided by some embodiments of the present disclosure.

[0056] 8A to 8E are schematic structural diagrams of the light-emitting chip manufacturing process provided in other embodiments of the present disclosure.

[0057] 9A to 9I are schematic structural diagrams of the light-emitting chip manufacturing process provided in some other embodiments of the present disclosure.

[0058] FIG10 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure.

[0059] 11 and 12 are schematic diagrams of two display substrates provided in other embodiments of the present disclosure.

[0060] FIG13 is a schematic diagram of a display substrate provided in some other embodiments of the present disclosure.

[0061] 14A to 14H are schematic structural diagrams of the display substrate shown in FIG. 11 during the manufacturing process.

[0062] 15A to 15G are schematic diagrams of some structures during the manufacturing process of the display substrate shown in FIG. 11 .

[0063] 16A to 16I are schematic structural diagrams of the display substrate shown in FIG. 11 during the manufacturing process.

[0064] 17A to 17J are schematic structural diagrams of the display substrate shown in FIG. 12 during the manufacturing process. DETAILED DESCRIPTION

[0065] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0066] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0068] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0069] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0070] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0071] Currently, the manufacturing process for display substrates using MiniLED or MicroLED light-emitting chips involves first fabricating the light-emitting chips on a sapphire or silicon substrate. Afterwards, the light-emitting chips of different colors (for example, red, green, and blue) are transferred to a driver backplane in batches. This method easily results in a low transfer yield and makes it difficult to achieve high resolution.

[0072] FIG1 is a top view of a light-emitting chip provided in some embodiments of the present disclosure, FIG2 is a cross-sectional view along line AA' in FIG1 , and FIG3 is a cross-sectional view along line BB' in FIG1 . As shown in FIG1 to FIG3 , the light-emitting chip includes: a plurality of light-emitting bodies 110, a transflective layer 104, and a reflective electrode 105. The plurality of light-emitting bodies 110 are disposed on a substrate 101 and are sequentially arranged in a direction away from the substrate 101. The substrate 101 may be a glass substrate 101. Along a first direction, the emission wavelengths of the plurality of light-emitting bodies 110 increase sequentially. For example, the emission colors of the plurality of light-emitting bodies 110 arranged along the first direction are red, green, and blue, respectively.

[0073] A transflective layer 104 is disposed between two adjacent light-emitting bodies 110. This layer is configured to reflect light emitted from the light-emitting body 110 adjacent to the light-emitting body 110 located on the side of the light-emitting layer 104 along the second direction, and to transmit light emitted from the light-emitting bodies 110 located on the side of the light-emitting layer 104 along the first direction. The transflective layer 104 can have an AlN / GaN stacked structure, with its thickness and number of layers controlling its reflectivity for light of different wavelengths.

[0074] The reflective electrode 105 is disposed on one side of the plurality of light-emitting bodies 110 along the first direction, and is configured to reflect light emitted from an adjacent light-emitting body 110. The reflective electrode 105 may reflect light emitted from only one adjacent light-emitting body 110, or may reflect visible light of all wavelengths.

[0075] The first direction and the second direction are opposite to each other, with one of the first direction and the second direction being a direction away from the substrate 101, and the other being a direction toward the substrate 101. The disclosed embodiment is described using the first direction as a direction away from the substrate 101 as an example. In Figures 2 and 3, one side of a structure along the first direction is considered the upper side of the structure, and one side of a structure along the second direction is considered the lower side of the structure. In this case, after the light-emitting chip is transferred to the driver backplane, the light-emitting chip emits light facing away from the driver backplane to prevent the circuitry in the driver backplane from blocking the light from the light-emitting chip.

[0076] In the embodiment of the present disclosure, a plurality of light-emitting bodies 110 are stacked, and a transflective layer 104 is provided between adjacent light-emitting bodies 110. The transflective layer 104 can reflect the light emitted by the adjacent light-emitting body 110 below and transmit the light emitted by each light-emitting body 110 above the transflective layer 104. A reflective electrode 105 is provided above the plurality of light-emitting bodies 110. The reflective electrode 105 can reflect the light emitted by the adjacent light-emitting body 110 below. Therefore, taking the first direction as the direction away from the substrate 101 as an example, in Figures 2 and 3, the light emitted by the light-emitting body 110 will be reflected by the adjacent transflective layer 104 (or reflective electrode 105) above and emitted through the substrate 101. Moreover, since the light-emitting wavelength of the light-emitting body 110 that is farther away from the substrate 101 is longer, and the light with a longer wavelength does not affect the light-emitting body 110 with a shorter wavelength, different light-emitting bodies will not interfere with each other. It can be seen that the embodiment of the present disclosure can enable the same light-emitting device to emit light of multiple colors; compared with the occupied area of ​​multiple light-emitting devices emitting monochromatic light, the occupied area of ​​the stacked arrangement of multiple light-emitting bodies 110 in the embodiment of the present disclosure is smaller, which is conducive to achieving high resolution of the display product.

[0077] In some examples, each light-emitting body 110 includes a light-emitting portion. For example, the multiple light-emitting portions of the multiple light-emitting bodies 110 include a red light-emitting portion, a green light-emitting portion, and a blue light-emitting portion. In other examples, each light-emitting body 110 includes multiple light-emitting portions that are arranged in sequence in a direction away from the substrate 101 and emit the same light-emitting color. For example, the light-emitting device includes three light-emitting bodies 110, the light-emitting body 110 closest to the substrate 101 includes two blue light-emitting portions, the light-emitting body 110 farthest from the substrate 101 includes two red light-emitting portions, and the middle light-emitting body 110 includes two green light-emitting portions. In still other examples, at least one light-emitting body 110 among the multiple light-emitting bodies 110 includes multiple light-emitting portions, and the remaining light-emitting bodies 110 include one light-emitting portion. For example, the light-emitting device includes three light-emitting bodies 110, the light-emitting body 110 closest to the substrate 101 includes one blue light-emitting portion, the light-emitting body 110 farthest from the substrate 101 includes one red light-emitting portion, and the middle light-emitting body 110 includes two green light-emitting portions. The embodiments of the present disclosure are described as follows: each light-emitting body 110 includes one light-emitting portion.

[0078] Each light emitting portion includes a first semiconductor layer 14, a light emitting layer 15, and a second semiconductor layer 16, which are sequentially arranged in a direction away from the substrate 101. One of the first semiconductor layer 14 and the second semiconductor layer 16 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. The N-type semiconductor layer may be a layer containing In x Al y Ga 1-x-y The n-type nitride semiconductor layer may be composed of N (0≤x<1, 0≤y<1, 0≤x+y<1), and the n-type impurity may be silicon. For example, the first semiconductor layer 14 may include n-type GaN. The p-type semiconductor layer may include In x Al y Ga 1-x-y N (0 ≤ x < 1, 0 ≤ y < 1, 0 ≤ x + y < 1) composition p-type nitride semiconductor layer, the p-type impurity can be magnesium. For example, the P-type semiconductor layer can be a single layer structure, but as in some example embodiments, it can have a multilayer structure containing different components. The light emitting layer 15 can have a multi-quantum well (MQW) structure, in which quantum well layers and quantum barrier layers are alternately stacked with each other. For example, the quantum well layer and the quantum barrier layer can respectively include In x Al y Ga 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) has different components. In one example, the quantum well layer may include In x Ga 1-xFor the component of N (0 < x ≤ 1), the quantum barrier layer may include GaN or AlGaN. The light-emitting layer 15 is not limited to the MQW structure and may have a single quantum well (SQW) structure.

[0079] In some embodiments, the light-emitting chip further includes: an insulating layer 106 and a plurality of connection electrodes (such as the first connection electrode 121, the second connection electrode 122, the third connection electrode 123, and the fourth connection electrode 124 in FIGS. 2 and 3). The insulating layer 106 is located on the side of the plurality of light-emitting bodies 110 away from the substrate 101. When the first direction is the direction away from the substrate 101, the insulating layer 106 is located on the side of the reflective electrode 105 away from the substrate 101. The plurality of connection electrodes are located on the side of the insulating layer 106 away from the substrate 101, and each connection electrode is electrically connected to the light-emitting body 110 through a via hole that at least penetrates the insulating layer 106.

[0080] Among them, both the first semiconductor layer 14 and the second semiconductor layer 16 are electrically connected to the connection electrodes, and the first semiconductor layer 14 and the second semiconductor layer 16 in the same light-emitting body are connected to different connection electrodes.

[0081] In some embodiments, the insulating layer 106 includes a passivation layer PVX1 and a planarization layer PLN. Among them, the passivation layer PVX1 can use inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, and the planarization layer PLN can use organic materials. By providing the planarization layer PLN, the connection electrodes can be located on a flat surface, which is beneficial for subsequent bonding with the driving backplane.

[0082] In some embodiments, as shown in FIGS. 2 and 3, among at least two adjacent light-emitting bodies 110, the second semiconductor layer 16 in the one closer to the substrate 101 and the first semiconductor layer 14 in the one farther from the substrate 101 are connected to the same connection electrode, so that the number of connection electrodes can be reduced and the overall structure of the light-emitting chip can be simplified. Of course, the connection electrodes connected to different light-emitting bodies 110 can also be independent of each other.

[0083] In some embodiments, as shown in FIGS. 2 and 3, the light-emitting chip further includes a transmissive electrode 103. The transmissive electrode 103 is located on the side of the plurality of light-emitting bodies 110 away from the reflective electrode 105 and is electrically connected to an adjacent light-emitting body 110. The plurality of connection electrodes include a first connection electrode 121 and a second connection electrode 122. The first connection electrode 121 is electrically connected to the transmissive electrode 103 through a first via hole V1; the second connection electrode 122 is electrically connected to the reflective electrode 105 through a second via hole V2.

[0084] In some embodiments, the multiple light-emitting bodies 110 of the light-emitting chip include a first light-emitting body 1101, a second light-emitting body 1102, and a third light-emitting body 1103, which are sequentially arranged in a direction away from the substrate 101. For example, the first light-emitting body 1101 is configured to emit blue light, the second light-emitting body 1102 is configured to emit green light, and the third light-emitting body 1103 is configured to emit blue light. In addition to the first and second connection electrodes 121 and 122 described above, the multiple connection electrodes may further include a third connection electrode 123 and a fourth connection electrode 124. The third connection electrode 123 is electrically connected to the second semiconductor layer 16 of the first light-emitting body 1101 through a third via V3 and to the first semiconductor layer 14 of the second light-emitting body 1102 through a fourth via V4. The fourth connection electrode 124 is electrically connected to the second semiconductor layer 16 of the second light-emitting body 1102 through a fifth via V5 and to the first semiconductor layer 14 of the third light-emitting body 1103 through a sixth via V6.

[0085] In one example, the first semiconductor layers 14 of the first light-emitting body 1101, the second light-emitting body 1102, and the third light-emitting body 1103 in Figures 2 and 3 are all P-type semiconductor layers, and the second semiconductor layers 16 are all N-type semiconductor layers. The N-type semiconductor layer of the first light-emitting body 1101 is electrically connected to the P-type semiconductor layer of the second light-emitting body 1102, and the N-type semiconductor layer of the second light-emitting body 1102 is electrically connected to the P-type semiconductor layer of the third light-emitting body 1103.

[0086] In another example, the first semiconductor layer 14 of the first light-emitting body 1101 in Figures 2 and 3 is a P-type semiconductor layer, and the second semiconductor layer 16 is an N-type semiconductor layer; the first semiconductor layer 14 of the second light-emitting body 1102 is an N-type semiconductor layer, and the second semiconductor layer 16 is a P-type semiconductor layer; the first semiconductor layer 14 of the third light-emitting body 1103 is a P-type semiconductor layer, and the second semiconductor layer 16 is an N-type semiconductor layer, so that the N-type semiconductor layers of the first light-emitting body 1101 and the second light-emitting body 1102 are connected, and the P-type semiconductor layers of the second light-emitting body 1102 and the third light-emitting body 1103 are connected.

[0087] In another example, the first semiconductor layer 14 of each light-emitting body 110 is an N-type semiconductor layer, the second semiconductor layer 16 is a P-type semiconductor layer, the P-type semiconductor layer of the first light-emitting body 1101 and the N-type semiconductor layer of the second light-emitting body 1102 are connected to the same connecting electrode; the P-type semiconductor layer of the second light-emitting body 1102 is electrically connected to the N-type semiconductor layer of the third light-emitting body 1103.

[0088] In another example, the first semiconductor layer 14 of the first light-emitting body 1101 and the first semiconductor layer 14 of the third light-emitting body 1103 are N-type semiconductor layers, the second semiconductor layer 16 of the first light-emitting body 1101 and the second semiconductor layer 16 of the third light-emitting body 1103 are P-type semiconductor layers, the first semiconductor layer 14 of the second light-emitting body 1102 is a P-type semiconductor layer and the second semiconductor layer 16 of the second light-emitting body 1102 is an N-type semiconductor layer, the P-type semiconductor layer of the first light-emitting body 1101 is electrically connected to the P-type semiconductor layer of the second light-emitting body 1102, and the N-type semiconductor layer of the second light-emitting body 1102 is electrically connected to the N-type semiconductor layer of the third light-emitting body 1103.

[0089] It should be noted that multiple light-emitting bodies 110 can also adopt other common connection electrode methods. For example, the N-type semiconductor layers of different light-emitting bodies 110 are connected to the same connection electrode, and the P-type semiconductor layers of different light-emitting bodies 110 are connected to different connection electrodes.

[0090] FIG4 is a cross-sectional view taken along line AA' in FIG1 , provided in other embodiments of the present disclosure, and FIG5 is a cross-sectional view taken along line BB' in FIG1 , provided in other embodiments of the present disclosure. The light-emitting chips shown in FIG4 and FIG5 are similar to the light-emitting chips shown in FIG2 and FIG3 , and include a first light-emitting body 1101, a second light-emitting body 1102, and a third light-emitting body 1103 sequentially arranged in a direction away from the substrate 101. Each light-emitting body 110 may include a first semiconductor layer 14, a light-emitting layer 15, and a second semiconductor layer 16. The difference from FIG2 and FIG3 is that in FIG4 and FIG5 , the first light-emitting body 1101 further includes a first conductive layer 111, which is located on the side of the second semiconductor layer 16 away from the substrate 101. The second light-emitting body 1102 further includes a second conductive layer 112 and a third conductive layer 113. The second conductive layer 112 is located on the side of the first semiconductor layer 14 of the second light-emitting body 1102 that is closer to the substrate 101, and the third conductive layer 113 is located on the side of the second semiconductor layer 16 of the second light-emitting body 1102 that is farther from the substrate 101. The third light-emitting body 1103 further includes a fourth conductive layer 114. The fourth conductive layer 114 is located on the side of the first semiconductor layer 14 of the third light-emitting body 1103 that is closer to the substrate 101.

[0091] The plurality of connection electrodes include a third connection electrode 123 and a fourth connection electrode 124. The third connection electrode 123 is electrically connected to the first conductive layer 111 through a third via hole V3 and to the second conductive layer 112 through a fourth via hole V4. This allows the third connection electrode 123 to be electrically connected to the second semiconductor layer 16 of the first light-emitting body 1101 through the first conductive layer 111 and to the first semiconductor layer 14 of the second light-emitting body 1102 through the second conductive layer 112. The fourth connection electrode 124 is electrically connected to the third conductive layer 113 through a fifth via hole V5 and to the fourth conductive layer 114 through a sixth via hole V6. This allows the fourth connection electrode 124 to be electrically connected to the second semiconductor layer 16 of the second light-emitting body 1102 through the third conductive layer 113 and to the first semiconductor layer 14 of the third light-emitting body 1103 through the fourth conductive layer 114.

[0092] The first conductive layer 111, the second conductive layer 112, the third conductive layer 113, and the fourth conductive layer 114 can all be obtained by heavily doping a semiconductor layer (e.g., a GaN layer). The provision of the first conductive layer 111 to the fourth conductive layer 114 can reduce the contact resistance between the connecting electrode and the light-emitting body 110.

[0093] In Figures 4 and 5 , the first semiconductor layers 14 of the first light-emitting body 1101, the second light-emitting body 1102, and the third light-emitting body 1103 are all P-type semiconductor layers, and the second semiconductor layers 16 are all N-type semiconductor layers. Alternatively, the first semiconductor layer 14 of the first light-emitting body 1101 is a P-type semiconductor layer, and the second semiconductor layer 16 is an N-type semiconductor layer; the first semiconductor layer 14 of the second light-emitting body 1102 is an N-type semiconductor layer, and the second semiconductor layer 16 is a P-type semiconductor layer; and the first semiconductor layer 14 of the third light-emitting body 1103 is a P-type semiconductor layer, and the second semiconductor layer 16 is an N-type semiconductor layer. This connects the N-type semiconductor layers of the first light-emitting body 1101 and the second light-emitting body 1102, and connects the P-type semiconductor layers of the second light-emitting body 1102 and the third light-emitting body 1103. Alternatively, the first semiconductor layer 14 of each light-emitting body is an N-type semiconductor layer, and the second semiconductor layer 16 is a P-type semiconductor layer; or, the first semiconductor layer 14 of the first light-emitting body 1101 and the first semiconductor layer 14 of the third light-emitting body 1103 are N-type semiconductor layers, the second semiconductor layer 16 of the first light-emitting body 1101 and the second semiconductor layer 16 of the third light-emitting body 1103 are P-type semiconductor layers, the first semiconductor layer 14 of the second light-emitting body 1102 is a P-type semiconductor layer, and the second semiconductor layer 16 of the second light-emitting body 1102 is an N-type semiconductor layer.

[0094] Of course, in Figures 4 and 5 , the connection electrodes connected to different light-emitting bodies 110 can also be independent of each other and no longer shared. Alternatively, the N-type semiconductor layer of each light-emitting body 110 can be electrically connected to the same connection electrode, and the P-type semiconductor layers of different light-emitting bodies can be electrically connected to different connection electrodes.

[0095] In the above-described embodiments of the present disclosure, as shown in Figures 2 to 5 , a bonding adhesive 102 is disposed between the plurality of light-emitting bodies 110 and the substrate 101. For example, the transmissive electrode 103 is located between the plurality of light-emitting bodies 110 and the substrate 101, and the reflective electrode 105 is located on a side of the plurality of light-emitting bodies 110 away from the substrate 101. In this case, the bonding adhesive 102 is disposed between the transmissive electrode 103 and the substrate 101.

[0096] In some embodiments, multiple light-emitting chips can be bonded to the same substrate 101, so that when the light-emitting chips are connected to the driving backplane, the multiple light-emitting chips can be transferred to the driving backplane at the same time and electrically connected to the driving backplane, thereby improving the transfer effect and transfer yield.

[0097] FIG6 is a flow chart of a method for manufacturing a light-emitting chip provided in some embodiments of the present disclosure. As shown in FIG6 , the method for manufacturing a light-emitting chip includes the following steps S1 to S3:

[0098] S1. Form an epitaxial layer on a first substrate, wherein the epitaxial layer includes a plurality of light-emitting body layers stacked in sequence, and a transflective material layer located between every two adjacent light-emitting bodies.

[0099] The first substrate may be a sapphire substrate.

[0100] S2. Transferring the epitaxial layer onto the substrate and forming a reflective electrode layer on one side of the epitaxial layer along a first direction. When the first direction is a direction away from the substrate, step S2 includes: transferring the epitaxial layer onto the substrate, and then forming the reflective electrode layer on the side of the epitaxial layer away from the substrate. When the first direction is a direction close to the substrate, step S2 includes: forming the reflective electrode layer on the side of the epitaxial layer away from the first substrate, and then transferring the epitaxial layer and the reflective electrode layer onto the substrate so that the reflective electrode layer is located between the epitaxial layer and the substrate.

[0101] S3. Patterning the multiple light-emitting body layers to form multiple light-emitting bodies of the light-emitting chip; patterning the transflective material layer to form a transflective layer of the light-emitting chip; and patterning the reflective electrode layer to form a reflective electrode of the light-emitting chip.

[0102] In which, along the first direction, the light-emitting wavelengths of multiple light-emitting entities increase successively; the reflective layer is used to reflect the emission light of the light-emitting entities located on the side of the reflective layer along the second direction and adjacent to each other, and to transmit the emission light of each light-emitting entity located on the side of the reflective layer along the first direction; the first direction is opposite to the second direction; and the reflective electrode is used to reflect the emission light of adjacent light-emitting entities.

[0103] In the embodiment of the present disclosure, an epitaxial layer is first grown on a first substrate and then transferred to the base 101, so that the large-area processing capability of the panel process can be utilized to pattern the epitaxial layer, thereby reducing the processing and manufacturing cost of the light-emitting chip.

[0104] The following describes the method for manufacturing the light-emitting chip in the embodiment of the present disclosure by taking the first direction as the direction away from the substrate as an example.

[0105] Figures 7A to 7F are schematic diagrams of the structure of the light-emitting chip manufacturing process provided in some embodiments of the present disclosure. The process shown in Figures 7A to 7F is used to manufacture the light-emitting chips shown in Figures 2 and 3. As shown in Figures 7A to 7F, in some embodiments, the light-emitting chip manufacturing method includes the following steps S101 to S106.

[0106] S101 , as shown in FIG7A , a buffer layer BFL, an epitaxial layer and a transmissive electrode layer 103 a are sequentially formed on a first substrate SUB1 .

[0107] The epitaxial layer includes multiple light-emitting main layers and a transflective material layer 104a located between each adjacent light-emitting main layer. Each light-emitting main layer includes a second semiconductor material layer 16a, a light-emitting material layer 15a, and a first semiconductor material layer 14a, arranged in sequence away from the first substrate SUB1. The wavelength of light emitted by the multiple light-emitting main layers gradually decreases as they move away from the first substrate SUB1.

[0108] S102 , transferring the epitaxial layer onto the substrate 101 , which is a glass substrate.

[0109] Step S102 specifically includes:

[0110] As shown in FIG7B , a substrate 101 is positioned on a side of the transmissive electrode layer 103a away from the first substrate SUB1, and the transmissive electrode layer 103a is bonded to the substrate 101 using bonding adhesive 102. Subsequently, as shown in FIG7C , the first substrate SUB1 is removed. During the removal of the first substrate SUB1, a laser lift-off method can be used to remove the first substrate SUB1 and the buffer layer BFL, exposing the epitaxial layer.

[0111] S103 , as shown in FIG7C , forming a reflective electrode layer 105 a on a side of the epitaxial layer away from the substrate 101 .

[0112] S104. As shown in FIG7D , the reflective electrode layer 105a is patterned to form the reflective electrode 105 of the light-emitting chip. The epitaxial layer is patterned to form a plurality of light-emitting bodies 110 of the light-emitting chip and a transflective layer 104 located between adjacent light-emitting bodies 110. The transmissive electrode layer 103a is patterned to form a transmissive electrode 103. The transmissive electrode 103 is located on a side of the plurality of light-emitting bodies 110 away from the reflective electrode 105 and is electrically connected to an adjacent light-emitting body 110.

[0113] S105, as shown in FIG7E, forming an insulating layer 106, and forming a plurality of via holes penetrating the insulating layer 106. The insulating layer 106 may include a passivation layer PVX1 and a planarization layer PLN.

[0114] S106 , as shown in FIG7F , a plurality of connection electrodes are formed on a side of the insulating layer 106 away from the substrate 101 , and the connection electrodes are electrically connected to the light-emitting body through via holes.

[0115] The first semiconductor layer 14 and the second semiconductor layer 16 are both electrically connected to the connection electrode, and the first semiconductor layer 14 and the second semiconductor layer 16 in the same light-emitting body are connected to different connection electrodes.

[0116] The plurality of connection electrodes include a first connection electrode 121 and a second connection electrode 122 . The first connection electrode 121 is electrically connected to the transmissive electrode 103 through a first via hole V1 . The second connection electrode 122 is electrically connected to the reflective electrode 105 through a second via hole V2 .

[0117] Taking the example of multiple light-emitting bodies 110 including a first light-emitting body 1101, a second light-emitting body 1102 and a third light-emitting body 1103 arranged in sequence along a direction away from the substrate 101, the multiple connecting electrodes, in addition to the above-mentioned first connecting electrode 121 and the second connecting electrode 122, may also include: a third connecting electrode 123 and a fourth connecting electrode 124, the third connecting electrode 123 being electrically connected to the second semiconductor layer 16 of the first light-emitting body 1101 through the third via hole V3, and being electrically connected to the first semiconductor layer 14 of the second light-emitting body 1102 through the fourth via hole V4; the fourth connecting electrode 124 being electrically connected to the second semiconductor layer 16 of the second light-emitting body 1102 through the fifth via hole V5, and being electrically connected to the first semiconductor layer 14 of the third light-emitting body 1103 through the sixth via hole V6.

[0118] One of the first semiconductor layer 14 and the second semiconductor layer 16 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. For details, please refer to the above description of FIG. 2 and FIG. 3 .

[0119] Figures 8A to 8E are schematic diagrams of the structure of the light-emitting chip manufacturing process provided in other embodiments of the present disclosure. The process shown in Figures 8A to 8F is used to manufacture the light-emitting chips shown in Figures 4 and 5. As shown in Figures 8A to 8E, in other embodiments, the light-emitting chip manufacturing method includes the following steps S201 to S206:

[0120] S201 , as shown in FIG8A , a buffer layer BFL, an epitaxial layer and a transmissive electrode layer 103 a are sequentially formed on a first substrate SUB1 .

[0121] The epitaxial layer includes multiple light-emitting main layers and a transflective material layer 104a located between each adjacent light-emitting main layer. Each light-emitting main layer includes a second semiconductor material layer 16a, a light-emitting material layer 15a, and a first semiconductor material layer 14a, arranged in sequence away from the first substrate SUB1. The wavelength of light emitted by the multiple light-emitting main layers gradually decreases as they move away from the first substrate SUB1.

[0122] Taking the example of multiple light-emitting main layers including a first light-emitting main layer, a second light-emitting main layer and a third light-emitting main layer arranged in sequence along a direction away from the substrate 101, the first light-emitting main layer may also include a first conductive material layer 111a, which is located on the side of the second semiconductor material layer 16a away from the light-emitting material layer 15a; the second light-emitting main layer also includes a second conductive material layer 112a and a third conductive material layer 113a, the second conductive material layer 112a is located on the side of the first semiconductor layer 14 of the second light-emitting main layer away from the light-emitting material layer 15a, and the third conductive material layer 113a is located on the side of the second semiconductor material layer 16a of the second light-emitting main layer away from the light-emitting material layer 15a; the third light-emitting main layer also includes a fourth conductive material layer 114a, which is located on the side of the first semiconductor material layer 14a of the third light-emitting main layer away from the light-emitting material layer 15a.

[0123] S202 , transferring the epitaxial layer onto the substrate 101 , which is a glass substrate 101 .

[0124] Step S202 specifically includes:

[0125] As shown in FIG8B , a substrate 101 is disposed on a side of the transmissive electrode layer 103a away from the first substrate SUB1, and the transmissive electrode layer 103a is bonded to the substrate 101 using bonding adhesive 102. The first substrate SUB1 is then removed. Laser lift-off can be used to remove the first substrate SUB1 and the buffer layer BFL, exposing the epitaxial layer.

[0126] S203 , as shown in FIG8C , forming a reflective electrode layer 105 a on a side of the epitaxial layer away from the substrate 101 .

[0127] S204. As shown in FIG8D , the reflective electrode layer 105a is patterned to form the reflective electrode 105 of the light-emitting chip. The epitaxial layer is patterned to form a plurality of light-emitting bodies 110 of the light-emitting chip and a transflective layer 104 located between adjacent light-emitting bodies 110. The transmissive electrode layer 103a is patterned to form a transmissive electrode 103. The transmissive electrode 103 is located on a side of the plurality of light-emitting bodies 110 away from the reflective electrode 105 and is electrically connected to an adjacent light-emitting body 110.

[0128] The light-emitting body includes a first semiconductor layer 14 formed by patterning a first semiconductor material layer 14a, a light-emitting layer 15 formed by patterning a light-emitting material layer 15a, and a second semiconductor layer 16 formed by patterning a second semiconductor material layer 16a. The first conductive material layer 111a is patterned to form a first conductive layer 111, the second conductive material layer 112a is patterned to form a second conductive layer 112, and the third conductive material layer 113a is patterned to form a third conductive layer 113.

[0129] S205, as shown in FIG8E, forming an insulating layer 106, and forming a plurality of via holes penetrating the insulating layer 106. The insulating layer 106 may include a passivation layer PVX1 and a planarization layer PLN.

[0130] S206 , as shown in FIG8E , a plurality of connection electrodes are formed on a side of the insulating layer 106 away from the substrate 101 , and the connection electrodes are electrically connected to the light-emitting body through via holes.

[0131] The first semiconductor layer 14 and the second semiconductor layer 16 are both electrically connected to the connection electrode, and the first semiconductor layer 14 and the second semiconductor layer 16 in the same light-emitting body are connected to different connection electrodes.

[0132] The multiple connection electrodes include a first connection electrode 121, a second connection electrode 122, a third connection electrode 123, and a fourth connection electrode 124. The first connection electrode 121 is electrically connected to the transmissive electrode 103 through a first via hole V1; the second connection electrode 122 is electrically connected to the reflective electrode 105 through a second via hole V2. The third connection electrode 123 is electrically connected to the first conductive layer 111 of the first light-emitting body 1101 through a third via hole V3, and is electrically connected to the second conductive layer 112 of the second light-emitting body 1102 through a fourth via hole V4. The fourth connection electrode 124 is electrically connected to the third conductive layer 113 of the second light-emitting body 1102 through a fifth via hole V5, and is electrically connected to the fourth conductive layer 114 of the third light-emitting body 1103 through a sixth via hole V6.

[0133] One of the first semiconductor layer 14 and the second semiconductor layer 16 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. For details, please refer to the above description of FIG. 4 and FIG. 5 .

[0134] Figures 9A to 9I are schematic diagrams of the structure of the light-emitting chip manufacturing process provided in some other embodiments of the present disclosure. The process shown in Figures 9A to 9I is used to manufacture the light-emitting chips shown in Figures 2 and 3. As shown in Figures 9A to 9I, in another embodiment, the light-emitting chip manufacturing method includes S301 to S306.

[0135] S301 , as shown in FIG9A , a buffer layer BFL and an epitaxial layer are sequentially formed on a first substrate SUB1 .

[0136] The epitaxial layer includes multiple light-emitting main layers and a transflective material layer 104a located between each adjacent light-emitting main layer. Each light-emitting main layer includes a second semiconductor material layer 16a, a light-emitting material layer 15a, and a first semiconductor material layer 14a, arranged in sequence away from the first substrate SUB1. The wavelength of light emitted by the multiple light-emitting main layers gradually increases as they move away from the first substrate SUB1.

[0137] S302 , transferring the epitaxial layer onto the substrate 101 , which is a glass substrate 101 .

[0138] Step S302 specifically includes:

[0139] S302a, as shown in FIG9B , sets the second substrate SUB2 on the side of the epitaxial layer away from the first substrate SUB1, and uses a temporary bonding adhesive 109 to bond the epitaxial layer to the second substrate SUB2. S302b, as shown in FIG9C , removes the first substrate SUB1. When removing the first substrate SUB1, a laser lift-off method can be used to remove the first substrate SUB1, and the buffer layer BFL can be removed to expose the epitaxial layer. S302c, as shown in FIG9E , sets the base 101 on the side of the epitaxial layer away from the second substrate SUB2, and bonds the epitaxial layer to the base 101 via a bonding adhesive 102; thereafter, removes the second substrate SUB2. When removing the second substrate SUB2, the temporary bonding adhesive 109 can be debonded by laser irradiation, thereby separating the second substrate SUB2 from the bonding adhesive 102 layer.

[0140] In some embodiments, the method for manufacturing a light-emitting chip further includes: between steps S302b and S302c, as shown in FIG9D , forming a transmissive electrode layer 103a on a side of the epitaxial layer away from the second substrate SUB2. In this case, in step S302c, a bonding adhesive 102 is disposed between the transmissive electrode layer 103a and the base 101.

[0141] S303 , as shown in FIG9F , forming a reflective electrode layer 105 a on a side of the epitaxial layer away from the substrate 101 .

[0142] S304. As shown in FIG9G , the reflective electrode layer 105a is patterned to form the reflective electrode 105 of the light-emitting chip. The epitaxial layer is patterned to form a plurality of light-emitting bodies 110 of the light-emitting chip and a transflective layer 104 located between adjacent light-emitting bodies 110. The transmissive electrode layer 103a is patterned to form a transmissive electrode 103. The transmissive electrode 103 is located on a side of the plurality of light-emitting bodies 110 away from the reflective electrode 105 and is electrically connected to an adjacent light-emitting body 110.

[0143] S305, as shown in FIG9H, forming an insulating layer 106, and forming a plurality of via holes penetrating the insulating layer 106. The insulating layer 106 may include a passivation layer PVX1 and a planarization layer PLN.

[0144] S306 , as shown in FIG9I , a plurality of connection electrodes are formed on a side of the insulating layer 106 away from the substrate 101 , and the connection electrodes are electrically connected to the light-emitting body through via holes.

[0145] The first semiconductor layer 14 and the second semiconductor layer 16 are both electrically connected to the connection electrode, and the first semiconductor layer 14 and the second semiconductor layer 16 in the same light-emitting body are connected to different connection electrodes.

[0146] The plurality of connection electrodes include a first connection electrode 121 and a second connection electrode 122 . The first connection electrode 121 is electrically connected to the transmissive electrode 103 through a first via hole V1 . The second connection electrode 122 is electrically connected to the reflective electrode 105 through a second via hole V2 .

[0147] Taking the example of multiple light-emitting bodies 110 including a first light-emitting body 1101, a second light-emitting body 1102 and a third light-emitting body 1103 arranged in sequence along a direction away from the substrate 101, the multiple connecting electrodes, in addition to the above-mentioned first connecting electrode 121 and the second connecting electrode 122, may also include: a third connecting electrode 123 and a fourth connecting electrode 124, the third connecting electrode 123 being electrically connected to the second semiconductor layer 16 of the first light-emitting body 1101 through the third via hole V3, and being electrically connected to the first semiconductor layer 14 of the second light-emitting body 1102 through the fourth via hole V4; the fourth connecting electrode 124 being electrically connected to the second semiconductor layer 16 of the second light-emitting body 1102 through the fifth via hole V5, and being electrically connected to the first semiconductor layer 14 of the third light-emitting body 1103 through the sixth via hole V6.

[0148] One of the first semiconductor layer 14 and the second semiconductor layer 16 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. For details, please refer to the above description of FIG. 2 and FIG. 3 .

[0149] It should be noted that the epitaxial layer formed in the above step S301 may also include a first conductive material layer 111a, a second conductive material layer 112a, a third conductive material layer 113a and a fourth conductive material layer 114a, so that after the patterning process, a first conductive layer 111, a second conductive layer 112, a third conductive layer 113 and a fourth conductive layer 114 are formed respectively, and the third connecting electrode 123 formed in S306 is connected to the first conductive layer 111 and the second conductive layer 112, and the fourth connecting electrode 124 is connected to the third conductive layer 113 and the fourth conductive layer 114.

[0150] FIG10 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure. The display substrate includes a driving backplane and a plurality of light-emitting chips 10 disposed on the driving backplane. The light-emitting chips 10 are the light-emitting chips of any of the above embodiments.

[0151] The driving backplane may include a base substrate SUB and a driving circuit layer TL provided on the base substrate SUB, and the light emitting chip 10 is electrically connected to the driving circuit layer TL.

[0152] In the process of manufacturing the display substrate, after the plurality of light-emitting chips 10 are transferred to the driving backplane, the base 101 may be removed or retained.

[0153] Figures 11 and 12 are schematic diagrams of two display substrates provided in other embodiments of the present disclosure. As shown in Figure 11, the display substrate includes: a base substrate SUB, a driving circuit layer arranged on the base substrate SUB, and a plurality of light-emitting chips 10. The driving circuit layer may include a driving circuit connected to the light-emitting chips 10 in a one-to-one correspondence. The driving circuit is used to provide a driving signal to the light-emitting chip 10 to drive the light-emitting chip 10 to emit light.

[0154] In some embodiments, the driving circuit includes a thin film transistor 20, which includes a gate 21, an active layer 22, a source 23, and a drain 24. The orthographic projections of the gate 21 and the active layer 22 of the thin film transistor 20 on the substrate SUB do not overlap with the orthographic projections of the light-emitting chip 10 on the substrate SUB.

[0155] In some embodiments, the thin film transistor 20 further includes a light-shielding member 25, and the gate electrode 21 and the active layer 22 have an overlapping area in their orthographic projections on the substrate SUB; the light-emitting chip 10 is connected to the drain electrode 24 of the thin film transistor 20; the light-shielding member 25 is arranged between the active layer 22 and the substrate SUB, and the orthographic projection of the light-shielding member 25 on the substrate SUB covers the overlapping area to prevent light from irradiating the active layer 22 and affecting the electrical characteristics of the thin film transistor 20.

[0156] In some embodiments, the light shielding member 25 may be electrically connected to the source 23 to prevent the light shielding member 25 from floating and generating parasitic capacitance between the light shielding member 25 and the source 23 .

[0157] In some embodiments, as shown in FIG11 , a bonding adhesive layer 30 is disposed between the light-emitting chip 10 and the thin-film transistor 20 and the substrate SUB. The light-emitting chip 10 includes a first electrode 11, a first semiconductor layer 14, a light-emitting layer 15, a second semiconductor layer 16, and a second semiconductor layer 16, disposed along a side away from the substrate SUB. One of the first semiconductor layer 14 and the second semiconductor layer 16 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. Specific materials are described above and are not further described here. In one example, the first electrodes 11 of multiple light-emitting chips 10 are electrically connected together.

[0158] In one example, the light-emitting chip 10 further includes a current spreading layer 13 located between the P-type semiconductor layer and the light-emitting layer 15. The material of the current spreading layer 13 includes, for example, indium tin oxide (ITO). As shown in FIG11 , the first semiconductor layer 14 is a P-type semiconductor layer, and the light-emitting chip 10 further includes the current spreading layer 13 located between the first electrode 11 and the first semiconductor layer 14. Alternatively, as shown in FIG12 , the second semiconductor layer 16 is a P-type semiconductor layer, and the light-emitting chip 10 further includes the current spreading layer 13 located between the second semiconductor layer 16 and the second electrode 12.

[0159] In some embodiments, a passivation layer PVX2, a gate insulating layer GI, and an interlayer dielectric layer ILD are further provided on the side of the second semiconductor layer 16 away from the substrate SUB. A light shielding member 25 is located between the passivation layer PVX2 and the substrate SUB. The active layer 22 is located on the side of the passivation layer PVX2 away from the substrate SUB. The gate insulating layer GI is located on the side of the active layer 22 away from the substrate SUB. The gate 21 is located on the side of the gate insulating layer GI away from the substrate SUB. The interlayer dielectric layer ILD covers the gate 21. The source 23 and drain 24 of the thin-film transistor 20 are both electrically connected to the active layer 22 through vias. The second electrode 12 of the light-emitting chip 10 is located in the interlayer dielectric layer ILD and is electrically connected to the second semiconductor layer 16 via vias that penetrate the interlayer dielectric layer ILD, the gate insulating layer GI, and the passivation layer PVX2. The second electrode 12 of the light-emitting chip 10 is also electrically connected to the drain 24.

[0160] In some embodiments, the light emitting chip 10 can emit light either toward or away from the substrate SUB. For example, as shown in Figures 11 and 12 , if the first electrode 11 is a transmissive electrode and the second electrode 12 is a reflective electrode, the light emitting chip 10 emits light toward the substrate SUB. In this case, a redundant electrode 26 can be disposed between the light shielding member 25 and the substrate SUB, co-located with the first electrode 11. Alternatively, the redundant electrode 26 can be omitted.

[0161] As shown in Figures 11 and 12, the light-emitting chip 10 is configured to emit light of a first color. The display substrate further includes a plurality of light-emitting portions 40, each located on the light-emitting side of the plurality of light-emitting chips 10. Each light-emitting portion 40 corresponds to a light-emitting chip 10. The plurality of light-emitting portions 40 include a plurality of first light-emitting portions 41, a plurality of second light-emitting portions 42, and a plurality of third light-emitting portions 43. The first light-emitting portions 41 are configured to transmit the first color light emitted by the light-emitting chip 10; the second light-emitting portions 42 are configured to convert the first color light into light of a second color; and the third light-emitting portions 43 are configured to convert the first color light into light of a third color. Each filter portion 50 is disposed on a side of a light-emitting portion 40 away from the light-emitting chip 10. The color of the filter portion 50 is the same as the color of the light emitted by the corresponding light-emitting portion.

[0162] In some examples, the material of the second light exit portion 42 and the third light exit portion 43 can include quantum dot material. The first color light is blue light, the second color light is red light, and the third color light is green light. In some examples, multiple light exit portions 40 form multiple repeating units, each repeating unit including a first light exit portion 41, a second light exit portion 42, and a third light exit portion 43.

[0163] In some embodiments, as shown in Figures 11 and 12, the display substrate further includes: a receiving layer 60, an encapsulation layer 62, a light shielding layer 61, and a first planarization layer. The receiving layer 60 has multiple receiving portions, and each light exit portion 40 is disposed in a receiving portion. The encapsulation layer 62 is located on the side of the receiving layer 60 away from the substrate. The light shielding layer 61 is located on the side of the encapsulation layer 62 away from the substrate. The light shielding layer 61 has multiple hollow portions, and the orthographic projection of each filter portion 50 on the substrate overlaps with the orthographic projection of a hollow portion on the substrate. The light shielding layer 61 is used to prevent crosstalk between adjacent light-emitting chips 10. The first planarization layer PLN1 is located on the side of the filter portion 50 and the light shielding layer 61 away from the base substrate SUB.

[0164] In some embodiments, as shown in Figures 11 and 12, the light-emitting chip 10 is used to emit light toward the base substrate SUB. In this case, the accommodating layer 60, the multiple light-emitting portions 40, the multiple filter portions 50, the encapsulation layer 62, and the light-shielding layer 61 are all located on a side of the base substrate SUB away from the light-emitting chip 10. A second planarization layer PLN2 may be provided on the side of the light-emitting chip 10 and the thin-film transistor 20 away from the base substrate SUB.

[0165] Figure 13 is a schematic diagram of a display substrate provided in other embodiments of the present disclosure. The display substrate shown in Figure 13 is similar to that in Figure 11, except that, in Figure 13, the second electrode 12 of the light-emitting chip 10 is a transmissive electrode, the first electrode 11 is a reflective electrode, and the light-emitting direction of the light-emitting chip 10 is a direction away from the base substrate SUB; in this case, the first electrode 11 of the light-emitting chip 10 and the light-shielding member 25 of the thin film transistor 20 can be arranged in the same layer to simplify the preparation process.

[0166] In Figure 13 , the second planarization layer PLN2 is disposed on the side of the light-emitting chip 10 and thin-film transistor 20 away from the base substrate SUB. The light-emitting portion 40 and the accommodating layer 60 are disposed on the side of the second planarization layer PLN2 away from the base substrate SUB. The encapsulation layer 62 is disposed on the side of the accommodating layer 60 and the light-emitting portion away from the base substrate SUB. The light filter 50 and the light shielding layer 61 are disposed on the side of the encapsulation layer 62 away from the base substrate SUB. The first planarization layer PLN1 is disposed on the side of the light filter 50 and the light shielding layer 61 away from the base substrate SUB.

[0167] In Figure 13, when the first semiconductor layer 14 is a P-type semiconductor layer, a current expansion layer 13 can be set between the first semiconductor layer 14 and the first electrode 11; when the second semiconductor layer 16 is a P-type semiconductor layer, the second electrode 12 can be made of indium tin oxide, and the second electrode 12 is used as the current expansion layer 13.

[0168] The following describes a method for manufacturing the display substrate shown in FIG11. FIG14A to FIG14H are schematic structural diagrams of the display substrate shown in FIG11 during the manufacturing process. As shown in FIG14A to FIG14H, in one implementation, the method for manufacturing the display substrate shown in FIG11 includes S401 to S407:

[0169] S401: A buffer layer (not shown) and an epitaxial layer are formed on a first substrate SUB1. The epitaxial layer includes, arranged in order away from the first substrate SUB1, a second semiconductor material layer 16a, a light-emitting material layer 15a, a first semiconductor material layer 14a, a current spreading material layer 13a, and a first electrode layer 11a. In this step, the first electrode layer 11a is made of a transparent conductive material.

[0170] S402 , transferring the epitaxial layer to the substrate SUB. Specifically, as shown in FIG14B , the substrate SUB with the bonding layer 30 formed thereon is positioned opposite to the epitaxial layer, so that the epitaxial layer is fixed to the substrate SUB via the bonding layer 30 .

[0171] S403 , as shown in FIG14C , remove the first substrate SUB1 .

[0172] S404 , as shown in FIG. 14D , patterning the epitaxial layer to form the first electrode 11 , the current spreading layer 13 , the first semiconductor layer 14 , the light emitting layer 15 , the second semiconductor layer 16 and the redundant electrode 26 of the light emitting chip 10 .

[0173] S405: As shown in FIG14E , a light shielding member 25, a passivation layer PVX2, an active layer 22, a gate insulating layer GI, a gate electrode 21, and an interlayer dielectric layer ILD are sequentially formed. Subsequently, as shown in FIG14F , the second electrode 12, the source electrode 23, and the drain electrode 24 of the light-emitting chip 10 are simultaneously formed. The source electrode 23 and the drain electrode 24 are both electrically connected to the active layer 22, and the second electrode 12 is electrically connected to the drain electrode 24. Subsequently, as shown in FIG14G , a second planarization layer PLN2 is formed on the side of the light-emitting chip 10 and the thin film transistor 20 away from the substrate SUB.

[0174] S406. As shown in FIG14H , a receiving layer 60 having a plurality of receiving portions is formed on a side of the base substrate SUB away from the light-emitting chip 10, and a light-emitting portion is formed in the receiving portion; thereafter, an encapsulation layer 62 is formed; and then a light-shielding layer 61 and a plurality of filter portions 50 are formed on a side of the encapsulation layer 62 away from the base substrate SUB.

[0175] S407 , forming a first planarization layer PLN1 on a side of the light shielding layer 61 and the filter portion 50 away from the base substrate SUB.

[0176] Here, step S405 may be performed before steps S406 and S407, or after steps S406 and S407.

[0177] FIG15A to FIG15G are schematic diagrams of a portion of the structure during the manufacturing process of the display substrate shown in FIG11. As shown in FIG15A to FIG15G, in another implementation, the manufacturing method of the display substrate shown in FIG11 includes S501 to S507 and S405 to S407:

[0178] S501 , as shown in FIG15A , a buffer layer and an epitaxial layer are formed on a first substrate SUB1 , wherein the epitaxial layer includes: a first semiconductor material layer 14 a , a light emitting material layer 15 a , and a second semiconductor material layer 16 a , which are sequentially arranged in a direction away from the first substrate SUB1 .

[0179] S502: Transfer the epitaxial layer to a second substrate SUB2. Specifically, as shown in FIG15B , the second substrate SUB2, which has a temporary bonding layer 30 formed thereon, is positioned opposite the epitaxial layer so that the epitaxial layer is fixed to the second substrate SUB2 via the temporary bonding layer 30. The second substrate SUB2 may be a silicon substrate.

[0180] S503 , as shown in FIG15C , remove the first substrate SUB1 .

[0181] S504, as shown in Figure 15D, a current spreading material layer 13a and a first electrode layer 11a are formed on the side of the epitaxial layer away from the second substrate SUB2. The first electrode layer 11a in this step is made of a transparent conductive material.

[0182] S505 , as shown in FIG. 15E , the base substrate SUB formed with the bonding adhesive layer 30 is disposed opposite to the first electrode layer 11 a , so that the first electrode layer 11 a is fixed on the base substrate SUB through the bonding adhesive layer 30 .

[0183] S506, as shown in FIG15F, removing the second substrate SUB2. The second substrate SUB2 can be removed by wet etching.

[0184] S507. As shown in FIG15G , the second semiconductor material layer 16a, the light-emitting material layer 15a and the first semiconductor material layer 14a are patterned to form the second semiconductor layer 16, the light-emitting layer 15 and the first semiconductor layer 14 of the light-emitting chip 10; the current spreading material layer 13a is patterned to form the current spreading layer 13; and the first electrode layer 11a is patterned to form the first electrode 11 of the light-emitting chip 10 and the redundant electrode 26 corresponding to the thin film transistor 20.

[0185] Afterwards, the above steps S405 to S407 are performed.

[0186] The following describes a method for manufacturing the display substrate shown in FIG13. FIG16A to FIG16I are schematic diagrams of the structure of the display substrate shown in FIG11 during the manufacturing process. As shown in FIG16A to FIG16I, in one implementation, the method for manufacturing the display substrate shown in FIG13 includes S601 to S610:

[0187] S601: As shown in FIG16A , a buffer layer and an epitaxial layer are formed on a first substrate SUB1. The epitaxial layer includes, arranged in order away from the first substrate SUB1, a second semiconductor material layer 16a, a light-emitting material layer 15a, a first semiconductor material layer 14a, a current spreading material layer 13a, and a first electrode layer 11a. In this step, the first electrode layer 11a is made of a reflective conductive material.

[0188] S602 , transferring the epitaxial layer to the substrate SUB. Specifically, as shown in FIG16B , the substrate SUB with the bonding layer 30 formed thereon is arranged opposite to the epitaxial layer, so that the epitaxial layer is fixed to the substrate SUB via the bonding layer 30 .

[0189] S603 , as shown in FIG16C , remove the first substrate SUB1 .

[0190] S604. As shown in FIG16D , the second semiconductor material layer 16a, the light-emitting material layer 15a, the first semiconductor material layer 14a, and the current spreading material layer are patterned to form the second semiconductor layer 16, the light-emitting layer 15, the first semiconductor layer 14, and the current spreading layer 13 of the light-emitting chip 10; the first electrode layer 11a is patterned to form the first electrode 11 of the light-emitting chip 10 and the light-shielding member 25 of the thin film transistor 20.

[0191] S605 , as shown in FIG16E , a passivation layer PVX2 , an active layer 22 , a gate insulating layer GI, a gate electrode 21 , and an interlayer dielectric layer ILD are formed in sequence.

[0192] S606 , as shown in FIG. 16F , forming the source electrode 23 and the drain electrode 24 of the light emitting chip 10 , wherein the source electrode 23 and the drain electrode 24 are both electrically connected to the active layer 22 .

[0193] S607 , as shown in FIG. 16F , forming a via hole at a position corresponding to the second semiconductor layer 16 of the light emitting chip 10 , and forming a second electrode 12 , the second electrode 12 being electrically connected to the second semiconductor layer 16 through the via hole, and also electrically connected to the drain electrode 24 .

[0194] S608 , as shown in FIG16G , forming a second planarization layer PLN2 on a side of the light emitting chip 10 and the thin film transistor 20 away from the base substrate SUB.

[0195] S609. As shown in FIG16H , a receiving layer 60 having a plurality of receiving portions is formed on the side of the second planarization layer PLN2 away from the base substrate SUB, and a light emitting portion is formed in the receiving portion; thereafter, a packaging layer 62 is formed; and then a light shielding layer 61 and a plurality of filtering portions 50 are formed on the side of the packaging layer 62 away from the base substrate SUB.

[0196] S610 , as shown in FIG16I , a first planarization layer PLN1 is formed on a side of the light shielding layer 61 and the filter portion 50 away from the base substrate SUB.

[0197] In another implementation, the method for manufacturing a display substrate shown in FIG13 includes S701 to S707 and S605 to S611:

[0198] S701 , referring to FIG. 15A , a buffer layer and an epitaxial layer are formed on a first substrate SUB1 . The epitaxial layer includes: a first semiconductor material layer 14 a , a light emitting material layer 15 a , and a second semiconductor material layer 16 a , which are sequentially arranged in a direction away from the first substrate SUB1 .

[0199] S702: Transfer the epitaxial layer to a second substrate SUB2. Specifically, as shown in FIG15B , the second substrate SUB2, which is provided with a temporary bonding adhesive layer 31, is positioned opposite the epitaxial layer so that the epitaxial layer is fixed to the second substrate SUB2 via the temporary bonding adhesive layer 31. The second substrate SUB2 may be a silicon substrate.

[0200] S703 , referring to FIG. 15C , remove the first substrate SUB1 .

[0201] S704, as shown in Figure 15D, a current spreading material layer 13a and a first electrode layer 11a are formed on the side of the epitaxial layer away from the second substrate SUB2. The first electrode layer 11a in this step is made of a reflective material.

[0202] S705 , referring to FIG. 15E , the base substrate SUB formed with the bonding adhesive layer 30 is disposed opposite to the first electrode layer 11 a , so that the first electrode layer 11 a is fixed on the base substrate SUB through the bonding adhesive layer 30 .

[0203] S706 , as shown in FIG15F , removing the second substrate SUB2 , wherein the second substrate SUB2 can be removed by wet etching.

[0204] S707. Referring to FIG. 16D , the second semiconductor material layer 16a, the light-emitting material layer 15a and the first semiconductor material layer 14a are patterned to form the second semiconductor layer 16, the light-emitting layer 15 and the first semiconductor layer 14 of the light-emitting chip 10; the current spreading material layer 13a is patterned to form the current spreading 13; and the first electrode layer 11a is patterned to form the first electrode 11 and the light-shielding member 25 of the light-emitting chip 10.

[0205] Then, the above steps S605 to S611 are performed.

[0206] 17A to 17J are schematic structural diagrams of the display substrate shown in FIG. 12 during the manufacturing process. As shown in FIG. 17A to 17J , the manufacturing method of the display substrate shown in FIG. 12 includes:

[0207] S801 , as shown in FIG17A , a buffer layer and an epitaxial layer are formed on a first substrate SUB1 , wherein the epitaxial layer includes: a first semiconductor material layer 14 a , a light emitting material layer 15 a , and a second semiconductor material layer 16 a , which are sequentially arranged in a direction away from the first substrate SUB1 .

[0208] S802: Transfer the epitaxial layer to a second substrate SUB2. Specifically, as shown in FIG17B , the second substrate SUB2, which is provided with a temporary bonding adhesive layer 30, is positioned opposite the epitaxial layer so that the epitaxial layer is fixed to the second substrate SUB2 via the temporary bonding adhesive layer 30. The second substrate SUB2 may be a silicon substrate.

[0209] S803 , as shown in FIG17C , remove the first substrate SUB1 .

[0210] S804: As shown in FIG17D , a first electrode layer 11a is formed on the side of the epitaxial layer away from the second substrate SUB2. The first electrode layer 11a in this step is made of a transparent conductive material.

[0211] S805 , as shown in FIG. 17E , the base substrate SUB formed with the bonding adhesive layer 30 is disposed opposite to the first electrode layer 11 a , so that the first electrode layer 11 a is fixed on the base substrate SUB through the bonding adhesive layer 30 .

[0212] S806, as shown in FIG17F, removing the second substrate SUB2. The second substrate SUB2 can be removed by wet etching.

[0213] S807. As shown in FIG17G , the second semiconductor material layer 16a, the light-emitting material layer 15a and the first semiconductor material layer 14a are patterned to form the second semiconductor layer 16, the light-emitting layer 15 and the first semiconductor layer 14 of the light-emitting chip 10; the first electrode layer 11a is patterned to form the first electrode 11 of the light-emitting chip 10 and the redundant electrode 26 corresponding to the thin film transistor 20.

[0214] S808 , as shown in FIG17H , forming a current spreading layer 13 on a side of the second semiconductor layer 16 away from the substrate SUB.

[0215] S809. As shown in FIG17I , a light shielding member 25, a passivation layer PVX2, an active layer 22, a gate insulating layer GI, a gate electrode 21, and an interlayer dielectric layer ILD are sequentially formed. Subsequently, the second electrode 12, the source electrode 23, and the drain electrode 24 of the light-emitting chip 10 are simultaneously formed. The source electrode 23 and the drain electrode 24 are both electrically connected to the active layer 22, and the second electrode 12 is electrically connected to the drain electrode 24. Subsequently, a second planarization layer PLN2 is formed on the side of the light-emitting chip 10 and the thin-film transistor 20 away from the substrate SUB.

[0216] S810. As shown in FIG17J , a receiving layer 60 having multiple receiving portions is formed on a side of the base substrate SUB away from the light-emitting chip 10, and a light-emitting portion is formed in the receiving portion. Subsequently, an encapsulation layer 62 is formed. A light-shielding layer 61 and multiple light-filtering portions 50 are formed on a side of the encapsulation layer 62 away from the base substrate SUB. A first planarization layer PLN1 is formed on a side of the light-shielding layer 61 and the light-filtering portions 50 away from the base substrate SUB.

[0217] It should be noted that, in the manufacturing process of the display substrate shown in FIG. 13 , an epitaxial layer may also be grown on the first substrate SUB1 and then transferred to the base substrate SUB without passing through the second substrate SUB2 .

[0218] It should also be noted that when the second semiconductor layer 16 is a P-type semiconductor layer and the light emitting direction of the light emitting chip 10 is away from the base substrate SUB, the second electrode 12 can be made of a transparent conductive material and used as a current spreading layer. At this time, the manufacturing method of the display substrate is similar to the manufacturing method of the display substrate shown in Figure 13, and will not be repeated here.

[0219] In the method for manufacturing a display substrate shown in Figures 11 to 13, an epitaxial layer is grown on a first substrate SUB1, and then the epitaxial layer is transferred to a base substrate SUB of the display substrate, and the light-emitting chip 10 and the thin film transistor 20 are prepared on the base substrate SUB without the need for a solid crystal process and a bonding process between the light-emitting chip 10 and the driving circuit layer, which can improve production efficiency and yield and reduce production costs.

[0220] An embodiment of the present disclosure further provides a display device, comprising the display substrate in any of the above embodiments.

[0221] A display device may include any device or product with a display function. For example, a display device may be a smartphone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0222] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A light-emitting chip, comprising: A plurality of light-emitting bodies are provided on a substrate, wherein the plurality of light-emitting bodies are sequentially arranged in a direction away from the substrate; and along a first direction, the light-emitting wavelengths of the plurality of light-emitting bodies sequentially increase; a transflective layer; wherein the transflective layer is disposed between each two adjacent light-emitting bodies, the transflective layer being configured to reflect light emitted by a light-emitting body adjacent to the transflective layer and located on one side of the transflective layer along the second direction, and to transmit light emitted by each light-emitting body located on one side of the transflective layer along the first direction; one of the first direction and the second direction being a direction close to the substrate, and the other being a direction away from the substrate; The reflective electrode is arranged on one side of the plurality of light-emitting bodies along the first direction, and is used for reflecting the light emitted by the light-emitting bodies adjacent to the reflective electrode.

2. The light-emitting chip according to claim 1, wherein: The light-emitting body comprises a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially arranged in a direction away from the substrate; The light-emitting chip further includes: an insulating layer, the insulating layer being located on a side of the plurality of light-emitting bodies away from the substrate; a plurality of connecting electrodes, located on a side of the insulating layer away from the substrate, the connecting electrodes being electrically connected to the light-emitting body via via holes at least penetrating the insulating layer; The first semiconductor layer and the second semiconductor layer are both electrically connected to the connection electrode, and the first semiconductor layer and the second semiconductor layer in the same light-emitting body are connected to different connection electrodes.

3. The light-emitting chip according to claim 2, wherein: In at least two adjacent light-emitting bodies, the second semiconductor layer in the one close to the substrate and the first semiconductor layer in the one far from the substrate are connected to the same switching electrode.

4. The light-emitting chip according to claim 2 or 3, wherein: The light emitting chip further includes a transmissive electrode, the transmissive electrode being located on a side of the plurality of light emitting bodies away from the reflective electrode and being electrically connected to an adjacent light emitting body; The plurality of connection electrodes include a first connection electrode and a second connection electrode, the first connection electrode being electrically connected to the transmissive electrode through a first via hole; The second connecting electrode is electrically connected to the reflective electrode through a second via hole.

5. The light-emitting chip according to any one of claims 2 to 4, wherein: The plurality of light-emitting bodies include: a first light-emitting body, a second light-emitting body and a third light-emitting body arranged in sequence in a direction away from the substrate; The multiple connecting electrodes include a third connecting electrode and a fourth connecting electrode, the third connecting electrode is electrically connected to the second semiconductor layer of the first light-emitting body through a third via hole, and is electrically connected to the first semiconductor layer of the second light-emitting body through a fourth via hole; the fourth connecting electrode is electrically connected to the second semiconductor layer of the second light-emitting body through a fifth via hole, and is electrically connected to the first semiconductor layer of the third light-emitting body through a sixth via hole.

6. The light-emitting chip according to any one of claims 2 to 4, wherein: The plurality of light-emitting bodies include: a first light-emitting body, a second light-emitting body and a third light-emitting body arranged in sequence in a direction away from the substrate; The first light emitting body further includes a first conductive layer, and the first conductive layer is located on a side of the second semiconductor layer away from the substrate; The second light-emitting body further includes a second conductive layer and a third conductive layer, the second conductive layer is located on a side of the first semiconductor layer of the second light-emitting body close to the substrate, and the third conductive layer is located on a side of the second semiconductor layer of the second light-emitting body away from the substrate; The third light-emitting body further includes a fourth conductive layer, and the fourth conductive layer is located on a side of the first semiconductor layer of the third light-emitting body close to the substrate; The multiple connecting electrodes include a third connecting electrode and a fourth connecting electrode, the third connecting electrode is electrically connected to the first conductive layer through a third via hole, and is electrically connected to the second conductive layer through a fourth via hole; the fourth connecting electrode is electrically connected to the third conductive layer through a fifth via hole, and is electrically connected to the fourth conductive layer through a sixth via hole.

7. The light-emitting chip according to any one of claims 2 to 6, wherein: The insulating layer includes a passivation layer and a planarization layer, and the planarization layer is located on a side of the passivation layer away from the substrate.

8. The light-emitting chip according to any one of claims 1 to 7, wherein: The first direction is a direction away from the substrate, and the second direction is a direction close to the substrate.

9. A method for manufacturing a light-emitting chip, comprising: forming an epitaxial layer on a first substrate, wherein the epitaxial layer includes a plurality of light-emitting main layers stacked in sequence, and a transflective material layer located between two adjacent light-emitting main layers; transferring the epitaxial layer onto a substrate, and forming a reflective electrode layer on one side of the epitaxial layer along a first direction; performing a patterning process on the plurality of light-emitting body layers to form a plurality of light-emitting bodies of the light-emitting chip; Performing a patterning process on the transflective material layer to form a transflective layer of the light-emitting chip; performing a patterning process on the reflective electrode layer to form a reflective electrode of the light-emitting chip; Among them, along the first direction, the light-emitting wavelengths of the multiple light-emitting entities increase successively; the transflective layer is used to reflect the emitted light of the light-emitting entity located on the side of the reflective layer along the second direction and adjacent to the reflective layer, and transmit the emitted light of each light-emitting entity located on the side of the transflective layer along the first direction; one of the first direction and the second direction is a direction close to the substrate, and the other is a direction away from the substrate; the reflective electrode is used to reflect the emitted light of the light-emitting entity adjacent to it.

10. The production method according to claim 9, wherein: The step of transferring the epitaxial layer onto a substrate comprises: Bonding the epitaxial layer to the base through bonding glue, wherein the base is located on a side of the epitaxial layer away from the first substrate; The first substrate is removed.

11. The production method according to claim 9, wherein: The step of transferring the epitaxial layer onto a substrate comprises: Bonding the epitaxial layer to a second substrate through a temporary bonding adhesive, wherein the second substrate is located on a side of the epitaxial layer away from the first substrate; removing the first substrate; Bonding the epitaxial layer to the substrate via bonding glue, wherein the substrate is located on a side of the epitaxial layer away from the second substrate; The second substrate is removed.

12. The production method according to claim 9, wherein: The light-emitting body comprises a first semiconductor layer, a light-emitting layer, and a second semiconductor layer sequentially arranged in a direction away from the substrate; The production method further comprises: forming an insulating layer on a side of the plurality of light-emitting bodies away from the substrate; forming a plurality of connecting electrodes on a side of the insulating layer away from the substrate, wherein the connecting electrodes are electrically connected to the light-emitting body through via holes penetrating the insulating layer; The first semiconductor layer and the second semiconductor layer are both electrically connected to the connection electrode, and the first semiconductor layer and the second semiconductor layer in the same light-emitting body are connected to different connection electrodes.

13. The production method according to claim 12, wherein: The production method further comprises: forming a transmissive electrode, the transmissive electrode being located on a side of the plurality of light-emitting bodies away from the reflective electrode and being electrically connected to an adjacent light-emitting body; The plurality of connecting electrodes include a first connecting electrode and a second connecting electrode. The first connecting electrode is electrically connected to the transmissive electrode through a first via hole; and the second connecting electrode is electrically connected to the reflective electrode through a second via hole.

14. A display substrate, wherein: The invention comprises a driving backplane and a plurality of light-emitting chips arranged on the driving backplane, wherein the light-emitting chips are the light-emitting chips according to any one of claims 1 to 8.

15. A display device, wherein: The display substrate according to claim 14 is included.

Images