Display substrate and display device

Abstract

A display substrate and a display device, which relate to the technical field of display. The display substrate comprises a base substrate, wherein the base substrate comprises a display area and a non-display area, and the display area comprises a plurality of sub-pixels. The display substrate comprises a thin-film transistor array, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a third conductive layer which are stacked in sequence on one side of the base substrate, wherein the thin-film transistor array comprises a plurality of switch transistors corresponding to different sub-pixels, the second conductive layer comprises a plurality of first electrodes corresponding to different sub-pixels, and the first electrode and the switch transistor located at the same sub-pixel are connected by means of a first adapter hole; the first conductive layer is connected to the third conductive layer, the orthographic projections of the first conductive layer and the first electrodes on the base substrate overlap to form a first storage capacitor, and the orthographic projections of the third conductive layer and the first electrodes on the base substrate overlap to form a second storage capacitor; and the first conductive layer and the second conductive layer are arranged in different layers.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous advancement of display technology, liquid crystal displays (LCDs) have been successfully applied to display devices such as laptops, monitors, and televisions. For each sub-pixel in an LCD, the liquid crystal molecules in the sub-pixel change their alignment under the action of an electric field, thereby adjusting the brightness of the sub-pixel.

[0003] Overview

[0004] The present disclosure provides a display substrate, comprising a base substrate, the base substrate comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of sub-pixels; the display substrate comprising a thin film transistor array, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer stacked sequentially on one side of the base substrate;

[0005] The thin film transistor array includes a plurality of switching transistors corresponding to different sub-pixels, the second conductive layer includes a plurality of first electrodes corresponding to different sub-pixels, and the first electrodes located in the same sub-pixel are connected to the switching transistors via a first transfer hole;

[0006] The first conductive layer is connected to the third conductive layer, and the first conductive layer overlaps with the orthographic projection of the first electrode on the base substrate to form a first storage capacitor. The third conductive layer overlaps with the orthographic projection of the first electrode on the base substrate to form a second storage capacitor. The first conductive layer and the second conductive layer are arranged in different layers.

[0007] In some embodiments, the first conductive layer includes a first solid material portion, the first solid material portion encloses a plurality of first openings, different first openings are spaced apart from each other, and the first openings are used to avoid the first transfer holes.

[0008] In some embodiments, the first solid material portion is an integrated structure interconnected within the entire display area.

[0009] In some embodiments, the display area further includes a first trace, and the orthographic projection of the first solid material portion on the base substrate covers the orthographic projection of the first trace on the base substrate; in a direction perpendicular to the base substrate, the first conductive layer is located between the first trace and the first electrode.

[0010] In some embodiments, the orthographic projections of the first solid material portion and the first opening on the base substrate cover the entire display area.

[0011] In some embodiments, the third conductive layer includes a second solid material portion, which encloses a plurality of first slits, and the first slits located in different sub-pixels are separated by the second solid material portion. The plurality of first slits located in the same sub-pixel are arranged along a first direction, and the first slits overlap with the light-transmitting area of ​​the sub-pixel.

[0012] In some embodiments, the display area further includes a plurality of first routing lines and a plurality of second routing lines arranged in different directions, and the orthographic projections of the first routing lines and the second routing lines on the substrate intersect with each other and define the plurality of sub-pixels;

[0013] An extending direction of the first slit is parallel to an extending direction of the first wiring or the second wiring.

[0014] In some embodiments, the second solid material portion includes a plurality of first extension strips arranged along the first direction, wherein the first extension strips are located between two adjacent first slits;

[0015] The multiple first extension strips include a first sub-extension strip and a second sub-extension strip, the first sub-extension strip is located between two adjacent first slits belonging to the same sub-pixel, the second sub-extension strip is located between two adjacent first slits belonging to different sub-pixels, and the width of the first sub-extension strip along the first direction is less than or equal to the width of the second sub-extension strip along the first direction.

[0016] In some embodiments, the third conductive layer includes a third solid material portion, which encloses a plurality of second openings, different second openings are located in different sub-pixels and are separated by the third solid material portion, and the orthographic projection of the second openings on the base substrate covers the light-transmitting area of ​​the sub-pixel.

[0017] In some embodiments, the solid material portion of the third conductive layer is an integrated structure interconnected throughout the display area.

[0018] In some embodiments, an orthographic projection of the third conductive layer on the base substrate covers at least a portion of the first via.

[0019] In some embodiments, a third opening is provided on the third conductive layer, and an orthographic projection of the third opening on the base substrate covers an orthographic projection of the first transfer hole on the base substrate.

[0020] In some embodiments, the first conductive layer and the third conductive layer are connected via a second transfer hole, and the second transfer hole is projected on the base substrate within a non-light-transmitting area of ​​the display region.

[0021] In some embodiments, orthographic projections of the first via and the second via on the base substrate do not overlap.

[0022] In some embodiments, the plurality of sub-pixels are arranged in an array along row and column directions, and the plurality of second transfer holes are arranged in an array along row and column directions;

[0023] The arrangement period of the second transfer holes along the row direction is equal to the arrangement period of the sub-pixels along the row direction, and the arrangement period of the second transfer holes along the column direction is equal to the arrangement period of the sub-pixels along the column direction.

[0024] In some embodiments, the first electrode is a solid block structure, and an orthographic projection of the solid block structure on the base substrate at least partially covers the light-transmitting area of ​​the sub-pixel.

[0025] In some embodiments, the first electrode includes a fourth solid material portion, the fourth solid material portion encloses a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along the second direction, and the second slits overlap with the light-transmitting area of ​​the sub-pixel.

[0026] In some embodiments, the orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of ​​the sub-pixel;

[0027] The first electrode is a solid block structure, and the orthographic projection of the solid block structure on the base substrate covers the light-transmitting area of ​​the sub-pixel;

[0028] The third conductive layer includes a second solid material portion, which encloses a plurality of first slits. The plurality of first slits in the same sub-pixel are arranged along a first direction, and the first slits overlap with a light-transmitting area of ​​the sub-pixel.

[0029] In some embodiments, the orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of ​​the sub-pixel;

[0030] The first electrode includes a fourth solid portion, the fourth solid portion enclosing a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along a second direction, and the second slits overlap with the light-transmitting area of ​​the sub-pixel;

[0031] The third conductive layer includes a third solid material portion, which encloses a plurality of second openings. Different second openings are located in different sub-pixels and are separated by the third solid material portion. The orthographic projection of the second openings on the base substrate covers the light-transmitting area of ​​the sub-pixel.

[0032] In some embodiments, the orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of ​​the sub-pixel;

[0033] The first electrode includes a fourth solid portion, the fourth solid portion enclosing a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along a second direction, the second slits overlap with the light-transmitting area of ​​the sub-pixel, and the fourth solid portion includes a plurality of second extension strips, the second extension strips being located between two adjacent second slits arranged along the second direction;

[0034] The third conductive layer includes a second solid material portion, the second solid material portion encloses a plurality of first slits, the plurality of first slits located in the same sub-pixel are arranged along the first direction, the first slits overlap with the light-transmitting area of ​​the sub-pixel, and the second solid material portion includes a plurality of first extension strips, the first extension strips are located between two adjacent first slits arranged along the first direction;

[0035] The second direction is parallel to the first direction, the extension directions of the second extension strips and the first extension strips are parallel to each other, and the orthographic projections of the second extension strips and the first extension strips on the base substrate are alternately arranged in sequence in the first direction.

[0036] In some embodiments, a gap exists between the second extension strip and the first extension strip that are adjacent to each other in the first direction.

[0037] The present disclosure provides a display panel, comprising: an opposing substrate, a liquid crystal layer, and a display substrate as described in any embodiment, wherein the liquid crystal layer is located between the opposing substrate and the display substrate, and the third conductive layer is arranged close to the liquid crystal layer.

[0038] The present disclosure provides a display panel, comprising:

[0039] A display substrate, comprising a base substrate, the base substrate comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of sub-pixels; the display substrate comprising a thin film transistor array, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially stacked on one side of the base substrate, the thin film transistor array comprising a plurality of switching transistors corresponding to different sub-pixels, the second conductive layer comprising a plurality of first electrodes corresponding to different sub-pixels, the first electrode in the same sub-pixel being connected to the switching transistor via a first transfer hole;

[0040] a second dielectric layer, located on one side of the display substrate and disposed close to the second conductive layer, comprising liquid crystal molecules; and

[0041] an opposing substrate, comprising a third conductive layer, and disposed on a side of the second dielectric layer facing away from the display substrate;

[0042] In which, the first conductive layer and the third conductive layer are connected to the same signal input terminal, the first conductive layer and the first electrode have an orthographic projection overlapped on the base substrate to form a first storage capacitor, and the third conductive layer and the first electrode have an orthographic projection overlapped on the base substrate to form a second storage capacitor.

[0043] The present disclosure provides a display device, comprising:

[0044] The display panel according to any one of the embodiments; and

[0045] The driving circuit is connected to the display panel and is used to drive the display panel to display an image.

[0046] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below.

[0047] BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for the description of the embodiments or related technologies. Obviously, the drawings described below are some embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. It should be noted that the scales in the drawings are for illustration only and do not represent the actual scale.

[0049] FIG1 shows a curve showing the relationship between storage capacitance and pixel voltage retention rate;

[0050] FIG2 shows a curve showing the change in brightness of a sub-pixel with different storage capacitors over time when the refresh rate of the display panel switches from 60 Hz to 1 Hz;

[0051] FIG3 shows a curve showing the relationship between the low-frequency flicker value and the storage capacitance;

[0052] FIG4 exemplarily shows a schematic planar structural diagram of a display substrate provided by the present disclosure;

[0053] FIG5 exemplarily shows a schematic cross-sectional structure diagram of a display substrate provided by the present disclosure along line bb′;

[0054] FIG6 exemplarily shows a schematic cross-sectional structure diagram of a display substrate provided by the present disclosure taken along line cc';

[0055] FIG7 exemplarily shows a schematic planar structural diagram of the first conductive layer;

[0056] FIG8 exemplarily shows a schematic planar structure diagram of a first third conductive layer;

[0057] FIG9 exemplarily shows a schematic planar structural diagram of a second third conductive layer;

[0058] FIG10 exemplarily shows a schematic planar structure diagram of a third type of third conductive layer;

[0059] FIG11 exemplarily shows a schematic planar structure diagram of a first type of second conductive layer;

[0060] FIG12 exemplarily shows a schematic planar structure diagram of a second type of second conductive layer;

[0061] FIG13 exemplarily shows a plan view of each film layer and stacked layer in a sub-pixel in the first display substrate;

[0062] FIG14 exemplarily shows a schematic cross-sectional structure diagram of the first display substrate along line aa′;

[0063] FIG15 exemplarily shows a plan view of each film layer and stacked layer in a sub-pixel in the second display substrate;

[0064] FIG16 exemplarily shows a schematic cross-sectional structure diagram of a second display substrate along line aa′;

[0065] FIG17 exemplarily shows a plan view of each film layer and stacked layer in a sub-pixel in a third display substrate;

[0066] FIG18 exemplarily shows a schematic cross-sectional structure diagram of a third display substrate along line aa′;

[0067] FIG19 exemplarily shows a schematic cross-sectional structure diagram of a display panel provided by the present disclosure;

[0068] FIG20 exemplarily shows a schematic cross-sectional structure diagram of another display panel provided by the present disclosure.

[0069] Detailed description

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0071] In static images, document reading, and other display scenarios where frame rates are not critical, users can select the appropriate frequency based on their needs. The system can also detect the monitor's usage and decide whether to switch to a lower refresh rate. Lowering the refresh rate can reduce power consumption and extend battery life. For example, reducing the refresh rate from 60Hz to 20Hz can reduce power consumption from 1.2W to 1.01W.

[0072] However, when the refresh rate is very low, the pixel voltage may drop significantly during the hold phase, causing the sub-pixel brightness to change and produce noticeable flicker. After the sub-pixel's switching transistor is turned off, the sub-pixel charging is completed. Because the insulation between the first electrode and the common electrode, between adjacent sub-pixels, and within the liquid crystal cell is not ideal, when the refresh rate is very low and the hold phase is very long, the pixel voltage is difficult to maintain, and even a very small leakage current can cause a significant drop in the pixel voltage.

[0073] 1 shows a relationship curve between storage capacitance and pixel voltage retention rate. It can be seen from FIG1 that as the storage capacitance Cst increases, the pixel voltage retention rate VHR increases, that is, in the retention stage, the pixel voltage change rate decreases.

[0074] Figure 2 shows the variation of sub-pixel brightness LV over time t at different storage capacitors Cst when the refresh rate of the display panel switches from 60Hz to 1Hz. Figure 2 shows that the larger the storage capacitor Cst, the smaller the change in brightness LV after switching to 1Hz. Figure 3 shows the relationship between the low-frequency flicker value (flicker) and the storage capacitor Cst. Figure 3 shows that the larger the storage capacitor Cst, the smaller the flicker value (flicker) after switching to 1Hz.

[0075] Therefore, increasing the storage capacitor Cst is an effective means to improve the pixel voltage retention rate, reduce the brightness change of the sub-pixel during the retention phase, and reduce the flicker value.

[0076] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, channel region, and source. In this disclosure, the channel region refers to the region through which current primarily flows.

[0077] In the present disclosure, the transistor may be a thin film transistor or a field effect transistor, etc. The present disclosure is described using a thin film transistor as an example.

[0078] In the present disclosure, the first electrode may be a drain and the second electrode may be a source, or vice versa. The functions of "source" and "drain" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in the present disclosure, "source" and "drain" may be interchanged.

[0079] In the related art, the pixel circuit of a liquid crystal display (LCD) panel includes one or two transistors, which is relatively simple. Therefore, it can achieve an ultra-high pixel density (Pixels Per Inch, PPI), that is, the number of pixels per inch. Liquid crystal display panels have multiple display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In the ADS mode, the first electrode and the common electrode are both located on one side of the display substrate. In the TN mode and VA mode, the first electrode and the common electrode are respectively arranged on opposite sides of the liquid crystal layer, with the first electrode located on one side of the display substrate and the common electrode located on the opposite side of the substrate. The operating principle of the ADS mode is that the liquid crystal molecules are in a plane parallel to the base substrate. When there is no voltage, light passes through the lower polarizer and forms linear polarization parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. When voltage is applied, a transverse electric field forms across the liquid crystal, causing the liquid crystal molecules to align along the electric field. Light passing through the lower polarizer and liquid crystal layer becomes elliptically polarized, allowing it to pass through the upper polarizer. The operating principle of TN mode is that in the absence of voltage, the liquid crystal molecules are twisted into a 90° alignment by the alignment films. Light passes through the lower polarizer and liquid crystal molecules and then exits through the upper polarizer. When voltage is applied, most of the liquid crystal molecules, except for those near the upper and lower alignment films, align perpendicularly. Light passing through the lower polarizer passes through the liquid crystal layer undeflected. However, since its polarization axis is parallel to the upper polarizer's, it is absorbed and prevented from exiting. The operating principle of VA mode is that the liquid crystal molecules are oriented perpendicularly to the substrate. In the absence of voltage, light passing through the lower polarizer becomes linearly polarized, parallel to the short axis of the liquid crystal molecules. This polarization axis cannot be rotated, so it is absorbed by the upper polarizer and prevented from exiting. When voltage is applied, the liquid crystal molecules are deflected along the electric field, causing light to become elliptically polarized after passing through the lower polarizer and liquid crystal layer, allowing it to exit through the upper polarizer.

[0080] The structure of the display substrate is introduced below using the ADS mode as an example.

[0081] The present disclosure provides a display substrate, as shown in FIG4 , comprising a base substrate 51, the base substrate 51 including a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a plurality of sub-pixels PX, which are arranged in an array, for example, along row directions ro and column directions co.

[0082] For example, as shown in FIG4 , the display area AA further includes a plurality of second traces SC and a plurality of first traces DT arranged in different directions. The orthographic projections of the second traces SC and the first traces DT on the base substrate 51 intersect with each other and define a plurality of sub-pixels PX. The plurality of second traces SC are, for example, arranged in the column direction co and extend in the row direction ro, and the plurality of first traces DT are, for example, arranged in the row direction ro and extend in the column direction co.

[0083] As shown in FIG5 , the display substrate further includes: a thin film transistor array 52 , a first conductive layer 53 , a first dielectric layer 54 , a second conductive layer 55 , a second dielectric layer 56 and a third conductive layer 57 stacked sequentially on one side of a base substrate 51 , and the thin film transistor array 52 is arranged close to the base substrate 51 .

[0084] As shown in FIG4 , the thin film transistor array 52 includes a plurality of switching transistors T1 corresponding to different sub-pixels PX, with different switching transistors T1 being disposed in different sub-pixels PX. The second conductive layer 55 includes a plurality of first electrodes 551 corresponding to different sub-pixels PX, with different first electrodes 551 being spaced apart from each other and located in different sub-pixels PX.

[0085] As shown in FIG. 5 , the first electrode 551 located in the same sub-pixel PX is connected to the switch transistor T1 through the first via H1 .

[0086] Illustratively, the gate G of the switching transistor T1 is connected to the second trace SC, which provides a control signal to the gate G. The control signal is used to control the on / off state of the switching transistor T1. The first electrode S of the switching transistor T1 is connected to the first electrode 551, and the second electrode D of the switching transistor T1 is connected to the first trace DT. The first trace DT provides a drive signal to the second electrode D. When the switching transistor T1 is in the on state, the drive signal is written from the second electrode D of the switching transistor T1 to the first electrode S of the switching transistor T1, and then to the first electrode 551.

[0087] In the present disclosure, the first conductive layer 53 and the third conductive layer 57 are arranged in different layers, and the first conductive layer 53 and the third conductive layer 57 are connected, that is, the voltage on the first conductive layer 53 and the third conductive layer 57 is the same, for example, both are a common voltage.

[0088] As shown in FIG5 , the first conductive layer 53 overlaps with the orthographic projection of the first electrode 551 on the base substrate 51 to form a first storage capacitor Cst1 , and the third conductive layer 57 overlaps with the orthographic projection of the first electrode 551 on the base substrate 51 to form a second storage capacitor Cst2 .

[0089] For each sub-pixel PX, the first conductive layer 53 and the first electrode 551 of the sub-pixel PX form a first storage capacitor Cst1, and the third conductive layer 57 and the first electrode 551 of the sub-pixel PX form a second storage capacitor Cst2. The total storage capacitance of the sub-pixel PX is Cst=Cst1+Cst2.

[0090] The display substrate provided by the present disclosure can increase the total storage capacitance of the sub-pixels, improve the pixel voltage retention rate of the sub-pixels, help achieve ultra-low refresh rate display, and help high PPI display substrates be compatible with ultra-low refresh rate display.

[0091] As shown in Figure 5, the switching transistor T1 includes an active layer ACT. For example, the active layer ACT is made of an oxide semiconductor material such as IGZO, and may also include materials such as amorphous silicon or low-temperature polysilicon. Using an oxide semiconductor material for the active layer ACT reduces the off-state current of the switching transistor T1, further improving the pixel voltage retention ratio and helping to achieve a low refresh rate.

[0092] For example, as shown in FIG5 , the thin film transistor array 52 includes a first metal layer M1, a gate insulating layer GI, a semiconductor layer 58, and a second metal layer M2 stacked in sequence, wherein the first metal layer M1 is arranged close to the base substrate 51, the first metal layer M1 includes a second trace SC and a gate G of the switching transistor T1, the semiconductor layer 58 includes an active layer ACT of the switching transistor T1, and the second metal layer M2 includes a first trace DT, a first electrode S, and a second electrode D of the switching transistor T1.

[0093] Exemplarily, as shown in FIG5 , a third dielectric layer 59 and a planar layer PLN are further stacked between the second metal layer M2 and the first conductive layer 53 , and the third dielectric layer 59 is disposed close to the second metal layer M2 .

[0094] As shown in FIG5 , the first via H1 sequentially penetrates the first dielectric layer 54, the first conductive layer 53, the planar layer PLN, and the third dielectric layer 59. The first via H1 includes a through hole H11 disposed on the third dielectric layer 59, a through hole H12 disposed on the planar layer PLN, and a through hole H13 disposed on the first dielectric layer 54. The through hole H11 disposed on the third dielectric layer 59 and the through hole H13 disposed on the first dielectric layer 54 are formed using the same process and are located in the same position.

[0095] For example, as shown in FIG4 , the orthographic projection of the active layer ACT on the base substrate 51 overlaps the orthographic projection of the first trace DT connected to the active layer ACT on the base substrate 51 in the row direction ro. For example, the orthographic projection of the active layer ACT on the base substrate 51 is located on both sides of the orthographic projection of the first trace DT on the base substrate 51. In FIG4 , the active layer ACT extends from the left side of the first trace DT to the right side of the first trace DT. This ensures better contact between the active layer ACT and the first trace DT, preventing poor contact caused by process fluctuations.

[0096] For example, to improve the light transmittance of the display substrate, the first conductive layer 53, the second conductive layer 55, and the third conductive layer 57 are all made of transparent conductive materials, such as metal oxides such as ITO, IZO, IGZO, IGO, and ZTO. Transparent conductive materials have a higher transmittance to visible light than metal materials.

[0097] In some embodiments, as shown in FIG5 a, the orthographic projection of the third conductive layer 57 on the base substrate 51 covers at least a portion of the orthographic projection of the first via H1 on the base substrate 51. For example, in FIG5 a, the orthographic projection of the third conductive layer 57 on the base substrate 51 completely covers the orthographic projection of the first via H1 on the base substrate 51.

[0098] Since the orthographic projection of the first electrode 551 on the base substrate 51 covers the orthographic projection of the first transfer hole H1 on the base substrate 51, by setting the orthographic projection of the third conductive layer 57 on the base substrate 51 to cover the orthographic projection of the first transfer hole H1 on the base substrate 51, the orthographic projections of the first electrode 551 and the third conductive layer 57 on the base substrate 51 overlap at the first transfer hole H1, which can further increase the storage capacitance.

[0099] In other embodiments, as shown in FIG5 b, the third conductive layer 57 does not overlap with the orthographic projection of the first transfer hole H1 on the base substrate 51. For example, in FIG5 b, a third opening OP3 is provided on the third conductive layer 57, and the orthographic projection of the third opening OP3 on the base substrate 51 overlaps the orthographic projection of the first transfer hole H1 on the base substrate 51.

[0100] Since the first transfer hole H1 is relatively deep, the second dielectric layer 56 formed in the first transfer hole H1 is prone to defects, which may cause a short circuit between the third conductive layer 57 and the first electrode 551. By setting the orthographic projections of the third conductive layer 57 and the first transfer hole H1 on the base substrate 51 to have no overlap, that is, by setting the third opening OP3 at a position corresponding to the first transfer hole H1 in the third conductive layer 57, a short circuit can be avoided.

[0101] In some embodiments, as shown in Figures 4 and 6, the first conductive layer 53 and the third conductive layer 57 are connected via a second transfer hole H2, and the second transfer hole H2 is projected on the base substrate 51 within the display area AA. Furthermore, the second transfer hole H2 is projected on the base substrate 51 within the non-transparent area NTA of the display area AA.

[0102] In some embodiments, as shown in FIG. 4 , the orthographic projections of the first transfer hole H1 and the second transfer hole H2 on the base substrate 51 do not overlap.

[0103] 4 and 6 , the orthographic projection of the second transfer hole H2 on the base substrate 51 is located within the orthographic projection area of ​​the second trace SC. Of course, the orthographic projection of the second transfer hole H2 on the base substrate 51 may also be located within the orthographic projection area of ​​the first trace DT, which is not limited in this disclosure.

[0104] Exemplarily, as shown in FIG4 , each sub-pixel PX is provided with a second transfer hole H2 .

[0105] Exemplarily, as shown in FIG4 , a plurality of second transfer holes H2 are arranged in an array along the row direction ro and the column direction co, and an arrangement period of the second transfer holes H2 along the row direction ro is equal to an arrangement period of the sub-pixels PX along the row direction ro, and an arrangement period of the second transfer holes H2 along the column direction co is equal to an arrangement period of the sub-pixels PX along the column direction co.

[0106] In some embodiments, as shown in FIG. 7 , the first conductive layer 53 includes a first solid portion 71 , which encloses a plurality of first openings OP1 . Different first openings OP1 are spaced apart from each other, and the first openings OP1 are used to avoid the first transfer holes H1 .

[0107] As shown in Figures 5 and 7, since the first transfer hole H1 passes through the first conductive layer 53, in order to prevent the first electrode 551 and the first conductive layer 53 from short-circuiting at the first transfer hole H1, the hole wall of the first opening OP1 is located outside the first transfer hole H1, and the hole wall of the first opening OP1 expands outward relative to the hole wall of the first transfer hole H1.

[0108] In some embodiments, as shown in FIG. 7 , the first solid portion 71 is an integrated structure interconnected within the entire display area AA.

[0109] In some embodiments, as shown in FIG14 , the display area AA further includes a first trace DT. The orthographic projection of the first solid portion 71 on the base substrate 51 covers the orthographic projection of the first trace DT on the base substrate 51. In a direction perpendicular to the base substrate 51, the first conductive layer 53 is located between the first trace DT and the first electrode 551. In this way, the first solid portion 71 can completely shield the coupling between the first trace DT and the first electrode 551.

[0110] In some embodiments, as shown in FIG. 7 , the orthographic projections of the first solid portion 71 and the first opening OP1 on the base substrate 51 cover the entire display area AA.

[0111] That is, except for the first opening OP1 region, the first solid portion 71 is disposed in both the light-transmitting area TA and the non-light-transmitting area NTA of the sub-pixel PX, thereby increasing the first storage capacitor Cst1 to the greatest extent.

[0112] In some embodiments, as shown in Figure 8 or Figure 9, the third conductive layer 57 includes a second solid material portion 81, and the second solid material portion 81 encloses a plurality of first slits SL1. The first slits SL1 located in different sub-pixels PX are not connected to each other and are separated by the second solid material portion 81. The plurality of first slits SL1 located in the same sub-pixel PX are arranged along the first direction f1, and the first slits SL1 overlap with the light-transmitting area TA of the sub-pixel PX.

[0113] As shown in FIG. 8 or FIG. 9 , the plurality of first slits SL1 are spaced apart from each other, and different first slits SL1 in the same sub-pixel PX are not connected to each other and are separated by the second solid portion 81 .

[0114] 8 or 9 , different sub-pixels PX include the same number of first slits SL1 . For example, in FIG8 , each sub-pixel PX includes three first slits SL1 , and in FIG9 , each sub-pixel PX includes four first slits SL1 .

[0115] In some embodiments, as shown in FIG. 8 , different first slits SL1 have the same width along the first direction f1.

[0116] In some embodiments, as shown in FIG9 , at least two first slits SL1 have different widths along the first direction f1. As shown in FIG9 , the multiple first slits SL1 located in the same sub-pixel PX include a first sub-slit 91 and a second sub-slit 92 . The width of the first sub-slit 91 along the first direction f1 is smaller than the width of the second sub-slit 92 along the first direction f1, and the second sub-slits 92 are symmetrically arranged on both sides of the multiple first sub-slits 91 (two as shown in FIG9 ).

[0117] In some embodiments, as shown in FIG. 8 or FIG. 9 , the second solid portion 81 includes a plurality of first extension strips 82 arranged along the first direction f1 , and the first extension strip 82 is located between two adjacent first slits SL1 arranged along the first direction f1 .

[0118] For example, as shown in FIG8 or FIG9 , at least two first extension strips 82 have different widths along the first direction f1. The plurality of first extension strips 82 include a first sub-extension strip 821 and a second sub-extension strip 822. The first sub-extension strip 821 is located between two adjacent first slits SL1 belonging to the same sub-pixel PX, and the second sub-extension strip 822 is located between two adjacent first slits SL1 belonging to different sub-pixels PX. The width of the first sub-extension strip 821 along the first direction f1 is less than or equal to the width of the second sub-extension strip 822 along the first direction f1.

[0119] Exemplarily, as shown in FIG. 8 or FIG. 9 , the second sub-extension strips 822 are symmetrically arranged on both sides of a plurality of first sub-extension strips 821 (two as shown in FIG. 8 , three as shown in FIG. 9 ).

[0120] As shown in FIG. 9 , the first sub-slit 91 is a gap between two first sub-extension strips 821 , and the second sub-slit 92 is a gap between the first sub-extension strip 821 and the second sub-extension strip 822 .

[0121] In some embodiments, as shown in FIG8 or FIG9 , the extension direction of the first slit SL1 is parallel to the extension direction of the first trace DT. In this case, the first direction f1 is, for example, parallel to the row direction ro. Of course, the extension direction of the first slit SL1 may also be parallel to the extension direction of the second trace SC. In this case, the first direction f1 is, for example, parallel to the column direction co.

[0122] In some embodiments, as shown in FIG10 , the third conductive layer 57 includes a third solid material portion 101 , which encloses a plurality of second openings OP2 , wherein different second openings OP2 are located in different sub-pixels PX and are separated by the third solid material portion 101 , and the orthographic projection of the second openings OP2 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX.

[0123] That is, the orthographic projection of the third material portion 101 on the base substrate 51 does not overlap with the light-transmitting area TA of the sub-pixel PX. By setting a second opening OP2 at a position corresponding to the light-transmitting area TA of the sub-pixel PX in the third conductive layer 57, the transmittance of the display substrate can be further improved.

[0124] In some embodiments, as shown in FIG. 8 to FIG. 10 , the solid portion of the third conductive layer 57 is an integrated structure interconnected within the entire display area AA.

[0125] In Figures 8 and 9 , the solid portion of the third conductive layer 57 is the second solid portion 81, which is interconnected and integrated throughout the display area AA. In Figure 10 , the solid portion of the third conductive layer 57 is the third solid portion 101, which is interconnected and integrated throughout the display area AA.

[0126] In order to further increase the storage capacitance, as shown in FIG. 8 and FIG. 9 , the orthographic projection of the third conductive layer 57 on the base substrate 51 may cover the non-light-transmitting area NTA in the display area AA.

[0127] In some embodiments, as shown in FIG11 , the first electrode 551 is a solid block structure 111, and the solid block structure 111 at least partially covers the light-transmitting area TA of the sub-pixel PX when projected on the base substrate 51. Furthermore, the solid block structure 111 can completely cover the light-transmitting area TA of the sub-pixel PX when projected on the base substrate 51.

[0128] In some embodiments, as shown in FIG12 , the first electrode 551 includes a fourth material portion 121 , which encloses a plurality of second slits SL2 . The plurality of second slits SL2 within the same first electrode 551 are arranged along the second direction f2 , and the second slits SL2 overlap with the light-transmitting area TA of the sub-pixel PX.

[0129] As shown in FIG. 12 , the plurality of second slits SL2 are spaced apart from each other. Different second slits SL2 in the same sub-pixel PX are not connected to each other and are separated by the fourth material portion 121 .

[0130] Exemplarily, as shown in Fig. 12 , different sub-pixels PX include the same number of second slits SL2 . For example, in Fig. 12 , each sub-pixel PX includes three second slits SL2 .

[0131] Exemplarily, as shown in FIG. 12 , different second slits SL2 have the same width along the second direction f2.

[0132] Exemplarily, the extending direction of the second slit SL2 is parallel to the extending direction of the first trace DT. In this case, the second direction f2 is parallel to the row direction ro.

[0133] The display substrate provided by the present disclosure is exemplarily described below with reference to Figures 13 to 18. In Figures 13, 15, and 17, Figure a is a plan view of the first metal layer M1 in a sub-pixel PX, including the second trace SC and the gate G of the switching transistor T1, Figure b is a plan view of the gate insulating layer GI in a sub-pixel PX, Figure c is a plan view of the semiconductor layer 58 in a sub-pixel PX, including the active layer ACT, Figure d is a plan view of the second metal layer M2 in a sub-pixel PX, including the first trace DT, the first electrode S and the second electrode D of the switching transistor T1, Figure e is a plan view of the third dielectric layer 59 in a sub-pixel PX, provided with a through hole H11, and Figure f is a plan view of the planar layer PLN in a sub-pixel. Figure 14 is a top view of the first conductive layer 53 within a sub-pixel PX, with a through hole H12 provided. Figure g is a top view of the first conductive layer 53 within a sub-pixel PX, with a first opening OP1 provided. Figure h is a top view of the first dielectric layer 54 within a sub-pixel PX, with a through hole H13 provided. Figure i is a top view of the second conductive layer 55 within a sub-pixel PX. Figure j is a top view of the second dielectric layer 56 within a sub-pixel PX, with a second transfer hole H2 provided. The second transfer hole H2 passes through the second dielectric layer 56 and the first dielectric layer 54. Figure k is a top view of the third conductive layer 57 within a sub-pixel PX. Figure m is a top view of the display substrate within a sub-pixel PX. Figures 14, 5, and 6 are schematic cross-sectional views of the structures along the aa', bb', and cc' positions in Figure 13, respectively. Figures 16, 5, and 6 are schematic cross-sectional views of the structures along the aa', bb', and cc' positions in Figure 15, respectively. FIG18 , FIG5 and FIG6 are schematic cross-sectional views of the structures along positions aa′, bb′ and cc′ in FIG17 , respectively.

[0134] In the first example, as shown in FIG. 13 and FIG. 14 , the orthographic projection of the first conductive layer 53 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX.

[0135] As shown in FIG. 13 and FIG. 14 , the first electrode 551 is a solid block structure 111 . The solid block structure 111 is projected onto the base substrate 51 to cover the light-transmitting area TA of the sub-pixel PX.

[0136] As shown in Figures 13 and 14, the third conductive layer 57 includes a second solid material portion 81, which encloses a plurality of first slits SL1. The plurality of first slits SL1 located in the same sub-pixel PX are arranged along a first direction f1 (such as a row direction ro), and the first slits SL1 overlap with the light-transmitting area TA of the sub-pixel PX.

[0137] As shown in Figure 13, the first slit SL1 overlaps with the orthographic projection of the solid block structure 111 on the base substrate 51. In this way, the second solid material portion 81 located between the first slit SL1 and the first electrode 551 of the solid block structure 111 form a horizontal electric field (i.e., an electric field parallel to the plane of the base substrate 51) to drive the liquid crystal molecules to deflect.

[0138] In the second example, as shown in FIG. 15 and FIG. 16 , the orthographic projection of the first conductive layer 53 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX.

[0139] As shown in Figures 15 and 16, the first electrode 551 includes a fourth solid material portion 121, which encloses a plurality of second slits SL2. The plurality of second slits SL2 located in the same first electrode 551 are arranged along the second direction f2, and the second slits SL2 overlap with the light-transmitting area TA of the sub-pixel PX.

[0140] As shown in Figures 15 and 16, the third conductive layer 57 includes a third solid material portion 101, which encloses a plurality of second openings OP2. Different second openings OP2 are located in different sub-pixels PX and are separated by the third solid material portion 101. The orthographic projection of the second openings OP2 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX.

[0141] In this example, since the orthographic projection of the first conductive layer 53 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX, the fourth solid material portion 121 located between the second slits SL2 and the first conductive layer 53 form a horizontal electric field (i.e., an electric field parallel to the plane of the base substrate 51) to drive the liquid crystal molecules to deflect.

[0142] In the third example, as shown in FIG. 17 and FIG. 18 , the orthographic projection of the first conductive layer 53 on the base substrate 51 covers the light-transmitting area TA of the sub-pixel PX.

[0143] As shown in Figures 17 and 18, the first electrode 551 includes a fourth solid material portion 121, which encloses a plurality of second slits SL2. The plurality of second slits SL2 located in the same first electrode 551 are arranged along the second direction f2, and the second slits SL2 overlap with the light-transmitting area TA of the sub-pixel PX. The fourth solid material portion 121 includes a plurality of second extension strips 171, and the second extension strip 171 is located between two adjacent second slits SL2 arranged along the second direction f2.

[0144] As shown in FIG17 and FIG18, the third conductive layer 57 includes a second solid portion 81, and the second solid portion 81 surrounds and forms a plurality of first slits SL1. The plurality of first slits SL1 located in the same sub-pixel PX are

[0145] The first slits SL1 are arranged along the first direction f1 , and overlap with the light-transmitting area TA of the sub-pixel PX. The second solid portion 81 includes a plurality of first extension strips 82 , and the first extension strips 82 are located between two adjacent first slits SL1 arranged along the first direction f1 .

[0146] The second direction f2 is parallel to the first direction f1 , the extension directions of the second extension strips 171 and the first extension strips 82 are parallel to each other, and the orthographic projections of the second extension strips 171 and the first extension strips 82 on the base substrate 51 are alternately arranged in the first direction f1 .

[0147] In this example, the second extension strips 171 between the second slits SL2 and the first extension strips 82 between the first slits SL1 form a horizontal electric field (ie, an electric field parallel to the plane of the base substrate 51 ) to drive the liquid crystal molecules to deflect.

[0148] Exemplarily, as shown in FIG18 , the second extension bar 171 and the first extension bar 82 that are close to each other have a gap in the first direction f1, that is, the second extension bar 171 and the first extension bar 82 that are close to each other are separated from each other in the first direction f1, so as to avoid the second extension bar 171 and the first extension bar 82 overlapping to produce steps.

[0149] In the present disclosure, the orthographic projection of the first conductive layer 53 on the base substrate 51 refers to the orthographic projection of the actual material portion of the first conductive layer 53 on the base substrate 51, the orthographic projection of the second conductive layer 55 on the base substrate 51 refers to the orthographic projection of the actual material portion of the second conductive layer 55 on the base substrate 51, and the orthographic projection of the third conductive layer 57 on the base substrate 51 refers to the orthographic projection of the actual material portion of the third conductive layer 57 on the base substrate 51.

[0150] The present disclosure provides a display panel, as shown in Figure 19, which includes: an opposing substrate 191, a liquid crystal layer 192, and a display substrate 193 provided as in any embodiment, wherein the liquid crystal layer 192 is located between the opposing substrate 191 and the display substrate 193, and the third conductive layer 57 is arranged close to the liquid crystal layer 192.

[0151] Those skilled in the art can understand that the display panel provided by the present disclosure has the advantages of the above-mentioned display substrate 193 .

[0152] The present disclosure provides a display panel, as shown in FIG4 and FIG20 , comprising: a display substrate 193, the display substrate comprising a base substrate 51, the base substrate 51 comprising a display area AA and a non-display area NA surrounding the display area AA. The display area AA comprises a plurality of sub-pixels PX, and the plurality of sub-pixels PX are arranged in an array, for example, along row directions ro and column directions co.

[0153] As shown in Figures 4 and 20, the display substrate 193 also includes: a thin film transistor array 52, a first conductive layer 53, a first dielectric layer 54 and a second conductive layer 55 stacked in sequence on one side of the base substrate 51, and the thin film transistor array 52 is arranged close to the base substrate 51.

[0154] As shown in FIG4 , the thin film transistor array 52 includes a plurality of switching transistors T1 corresponding to different sub-pixels PX, with different switching transistors T1 being disposed in different sub-pixels PX. The second conductive layer 55 includes a plurality of first electrodes 551 corresponding to different sub-pixels PX, with different first electrodes 551 being spaced apart from each other and located in different sub-pixels PX.

[0155] As shown in FIG. 5 , the first electrode 551 located in the same sub-pixel PX is connected to the switch transistor T1 through the first via H1 .

[0156] As shown in Figure 20, the display panel also includes: a second dielectric layer 56, located on one side of the display substrate 193, arranged close to the second conductive layer 55, and including liquid crystal molecules; and an opposing substrate 191, including a third conductive layer 57, arranged on the side of the second dielectric layer 56 away from the display substrate 193.

[0157] Among them, the first conductive layer 53 and the third conductive layer 57 are connected to the same signal input terminal, the first conductive layer 53 and the first electrode 551 have an orthographic projection overlap on the base substrate 51 to form a first storage capacitor Cst1, and the third conductive layer 57 and the first electrode 551 have an orthographic projection overlap on the base substrate 51 to form a second storage capacitor Cst2.

[0158] Exemplarily, the display panel provided by the present disclosure is a TN mode or a VA mode.

[0159] Exemplarily, for each sub-pixel PX, the first conductive layer 53 and the first electrode 551 of the sub-pixel PX form a first storage capacitor Cst1, and the third conductive layer 57 and the first electrode 551 of the sub-pixel PX form a second storage capacitor Cst2, and the total storage capacitance of the sub-pixel PX is Cst=Cst1+Cst2.

[0160] The display panel provided by the present disclosure can increase the storage capacitance of the sub-pixel PX, improve the pixel voltage retention rate of the sub-pixel PX, help achieve ultra-low refresh rate display, and help the high PPI display substrate 193 be compatible with ultra-low refresh rate display.

[0161] The present disclosure provides a display device, including a display panel as provided in any embodiment, and a driving circuit connected to the display panel, for driving the display panel to display an image.

[0162] Those skilled in the art will appreciate that the display device provided by the present disclosure has the advantages of the above-mentioned display panel.

[0163] The display device provided by the present disclosure can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0164] In the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0165] In the present disclosure, the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present disclosure.

[0166] In this disclosure, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, commodity, or apparatus that includes the element.

[0167] References in this disclosure to "one embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "an example," "an example," "some examples," and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0168] In this disclosure, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0169] When describing some embodiments, the expressions "coupled" and "connected" may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this disclosure.

[0170] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0171] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0172] As used in this disclosure, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0173] The use of "for" or "configured to" in this disclosure is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0174] The use of "based on" or "according to" in this disclosure is intended to be open and inclusive. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values. A process, step, calculation, or other action based on one or more stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond the stated values.

[0175] As used in this disclosure, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0176] As used in this disclosure, "parallel", "perpendicular", "equal", and "flush" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two being equal is less than or equal to 5% of either one. "Flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range of approximate flushness can be, for example, the distance between the two being flush is less than or equal to 5% of either one's size.

[0177] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0178] The present disclosure describes exemplary embodiments with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this disclosure, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, the base substrate including a display area and a non-display area surrounding the display area, the display area including a plurality of sub-pixels; the display substrate comprising a thin film transistor array, a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a third conductive layer stacked sequentially on one side of the base substrate; in, The thin film transistor array includes a plurality of switch transistors corresponding to different sub-pixels, the second conductive layer includes a plurality of first electrodes corresponding to different sub-pixels, and the first electrodes located in the same sub-pixel are connected to the switch transistors via a first transfer hole; The first conductive layer is connected to the third conductive layer, and the first conductive layer overlaps with the orthographic projection of the first electrode on the base substrate to form a first storage capacitor. The third conductive layer overlaps with the orthographic projection of the first electrode on the base substrate to form a second storage capacitor. The first conductive layer and the second conductive layer are arranged in different layers.

2. The display substrate according to claim 1, wherein The first conductive layer includes a first solid material portion, and the first solid material portion encloses a plurality of first openings. Different first openings are arranged at intervals from each other, and the first openings are used to avoid the first transfer holes.

3. The display substrate according to claim 2, wherein: The first solid material portion is an integrated structure interconnected within the entire display area.

4. The display substrate according to claim 2, wherein: The display area further includes a first wiring, and the orthographic projection of the first solid material portion on the base substrate covers the orthographic projection of the first wiring on the base substrate; in a direction perpendicular to the base substrate, the first conductive layer is located between the first wiring and the first electrode.

5. The display substrate according to claim 2, wherein: The orthographic projections of the first solid material portion and the first opening on the base substrate cover the entire display area. The display substrate according to claim 1 , wherein: The third conductive layer includes a second solid material portion, which encloses a plurality of first slits. The first slits located in different sub-pixels are separated by the second solid material portion. The plurality of first slits located in the same sub-pixel are arranged along a first direction, and the first slits overlap with the light-transmitting area of the sub-pixel.

7. The display substrate according to claim 6, wherein: The display area further includes a plurality of first routing lines and a plurality of second routing lines arranged in different directions, wherein the orthographic projections of the first routing lines and the second routing lines on the substrate intersect with each other and define the plurality of sub-pixels; An extending direction of the first slit is parallel to an extending direction of the first wiring or the second wiring.

8. The display substrate according to claim 6, wherein: The second solid material portion includes a plurality of first extension strips arranged along the first direction, wherein the first extension strips are located between two adjacent first slits; The multiple first extension strips include a first sub-extension strip and a second sub-extension strip, the first sub-extension strip is located between two adjacent first slits belonging to the same sub-pixel, the second sub-extension strip is located between two adjacent first slits belonging to different sub-pixels, and the width of the first sub-extension strip along the first direction is less than or equal to the width of the second sub-extension strip along the first direction.

9. The display substrate according to claim 1, wherein: The third conductive layer includes a third solid material portion, which encloses a plurality of second openings. Different second openings are located in different sub-pixels and are separated by the third solid material portion. The orthographic projection of the second openings on the base substrate covers the light-transmitting area of the sub-pixel.

10. The display substrate according to claim 1, wherein The solid material portion of the third conductive layer is an integrated structure interconnected within the entire display area.

11. The display substrate according to claim 1, wherein: An orthographic projection of the third conductive layer on the base substrate covers at least a portion of the first via hole.

12. The display substrate according to claim 1, wherein A third opening is provided on the third conductive layer, and an orthographic projection of the third opening on the base substrate covers an orthographic projection of the first transfer hole on the base substrate.

13. The display substrate according to claim 1, wherein The first conductive layer is connected to the third conductive layer via a second transfer hole, and the second transfer hole is projected on the base substrate within a non-light-transmitting area of the display region.

14. The display substrate according to claim 13, wherein: The orthographic projections of the first transfer hole and the second transfer hole on the base substrate do not overlap.

15. The display substrate according to claim 13, wherein: The plurality of sub-pixels are arranged in an array along the row direction and the column direction, and the plurality of second transfer holes are arranged in an array along the row direction and the column direction; The arrangement period of the second transfer holes along the row direction is equal to the arrangement period of the sub-pixels along the row direction, and the arrangement period of the second transfer holes along the column direction is equal to the arrangement period of the sub-pixels along the column direction.

16. The display substrate according to claim 1, wherein The first electrode is a solid block structure, and an orthographic projection of the solid block structure on the base substrate at least partially covers the light-transmitting area of the sub-pixel.

17. The display substrate according to claim 1, wherein The first electrode includes a fourth solid portion, the fourth solid portion encloses a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along a second direction, and the second slits overlap with the light-transmitting area of the sub-pixel.

18. The display substrate according to claim 1, wherein The orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of the sub-pixel; The first electrode is a solid block structure, and the orthographic projection of the solid block structure on the base substrate covers the light-transmitting area of the sub-pixel; The third conductive layer includes a second solid material portion, which encloses a plurality of first slits. The plurality of first slits in the same sub-pixel are arranged along a first direction, and the first slits overlap with a light-transmitting area of the sub-pixel.

19. The display substrate according to claim 1, wherein The orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of the sub-pixel; The first electrode includes a fourth solid portion, the fourth solid portion enclosing a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along a second direction, and the second slits overlap with the light-transmitting area of the sub-pixel; The third conductive layer includes a third solid material portion, which encloses a plurality of second openings. Different second openings are located in different sub-pixels and are separated by the third solid material portion. The orthographic projection of the second openings on the base substrate covers the light-transmitting area of the sub-pixel.

20. The display substrate according to claim 1, wherein The orthographic projection of the first conductive layer on the base substrate covers the light-transmitting area of the sub-pixel; The first electrode includes a fourth solid portion, the fourth solid portion enclosing a plurality of second slits, the plurality of second slits located in the same first electrode are arranged along a second direction, the second slits overlap with the light-transmitting area of the sub-pixel, and the fourth solid portion includes a plurality of second extension strips, the second extension strips being located between two adjacent second slits arranged along the second direction; The third conductive layer includes a second solid material portion, the second solid material portion encloses a plurality of first slits, the plurality of first slits located in the same sub-pixel are arranged along the first direction, the first slits overlap with the light-transmitting area of the sub-pixel, and the second solid material portion includes a plurality of first extension strips, the first extension strips are located between two adjacent first slits arranged along the first direction; The second direction is parallel to the first direction, the extension directions of the second extension strips and the first extension strips are parallel to each other, and the orthographic projections of the second extension strips and the first extension strips on the base substrate are alternately arranged in sequence in the first direction.

21. The display substrate according to claim 20, wherein: The second extension strip and the first extension strip that are close to each other have a gap in the first direction.

22. A display panel comprising: An opposing substrate, a liquid crystal layer, and the display substrate according to any one of claims 1 to 21, wherein the liquid crystal layer is located between the opposing substrate and the display substrate, and the third conductive layer is arranged close to the liquid crystal layer.

23. A display panel comprising: A display substrate, comprising a base substrate, the base substrate comprising a display area and a non-display area surrounding the display area, the display area comprising a plurality of sub-pixels; the display substrate comprising a thin film transistor array, a first conductive layer, a first dielectric layer, and a second conductive layer sequentially stacked on one side of the base substrate, the thin film transistor array comprising a plurality of switching transistors corresponding to different sub-pixels, the second conductive layer comprising a plurality of first electrodes corresponding to different sub-pixels, the first electrode in the same sub-pixel being connected to the switching transistor via a first transfer hole; a second dielectric layer, located on one side of the display substrate and disposed close to the second conductive layer, comprising liquid crystal molecules; and an opposing substrate, comprising a third conductive layer, and disposed on a side of the second dielectric layer facing away from the display substrate; The first conductive layer and the third conductive layer are connected to the same signal input terminal, and the first conductive layer and the first electrode have an orthographic projection overlapped on the substrate to form a first Storage capacitor, the third conductive layer overlaps with the orthographic projection of the first electrode on the base substrate to form a second storage capacitor.

24. A display device comprising: The display panel according to claim 22 or 23; as well as The driving circuit is connected to the display panel and is used to drive the display panel to display an image.

Images