Pixel circuit, display panel, and display apparatus

Abstract

The present disclosure provides a pixel circuit, a display panel, and a display apparatus. The pixel circuit comprises a light-emitting element, a driving circuit, and a compensation control circuit. The driving circuit is used for generating, under the control of the potential of a first node, a driving current for driving the light-emitting element. The compensation control circuit is electrically connected to a compensation control end. The compensation control circuit is further separately electrically connected to a first compensation node and a second compensation node, and is used for controlling the first compensation node to be in communication with the second compensation node under the control of a compensation control signal provided by the compensation control end. The second compensation node is a node in a compensation pixel circuit. The compensation pixel circuit is another pixel circuit in the display panel. The present disclosure enables threshold voltage compensation to be conveniently performed.

Description

Pixel circuit, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display panel, and a display device. Background Art

[0002] With the continuous updating and iteration of the OLED (organic light-emitting diode) industry, many pixel circuits suitable for various new functions have been proposed. However, the related pixel circuits cannot propose new compensation control circuits for threshold voltage compensation.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit applied to a display panel, the pixel circuit including a light-emitting element, a driving circuit, and a compensation control circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the light-emitting element via a third node, and the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[0006] The compensation control circuit is electrically connected to the compensation control terminal;

[0007] The compensation control circuit is also electrically connected to the first compensation node and the second compensation node respectively, and is used to control the communication between the first compensation node and the second compensation node under the control of the compensation control signal provided by the compensation control terminal;

[0008] The second compensation node is a node in a compensation pixel circuit; the compensation pixel circuit is another pixel circuit in the display panel.

[0009] Optionally, the first compensation node is the third node, and the second compensation node is the first node in the compensation pixel circuit.

[0010] Optionally, the first compensation node is the first node, and the second compensation node is a third node in the compensation pixel circuit.

[0011] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a first energy storage circuit;

[0012] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;

[0013] The first energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

[0014] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a first energy storage circuit, and a second energy storage circuit;

[0015] A first end of a first energy tank circuit is electrically connected to the first node, a second end of the first energy tank circuit is electrically connected to a fourth node, a first end of the second energy tank circuit is electrically connected to the fourth node, a second end of the second energy tank circuit is electrically connected to a DC voltage terminal, and the first energy tank circuit and the second energy tank circuit are configured to store electrical energy;

[0016] The data writing circuit is electrically connected to the writing control terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the fourth node under the control of the writing control signal provided by the writing control terminal.

[0017] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0018] The first light emitting control circuit is electrically connected to the first light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light emitting control signal provided by the first light emitting control terminal;

[0019] The third node is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit;

[0020] The second light emitting control circuit is electrically connected to the second light emitting control terminal, the third node, and the first electrode of the light emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light emitting element under the control of a second light emitting control signal provided by the second light emitting control terminal;

[0021] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0022] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes an on-off control circuit;

[0023] The on-off control circuit is electrically connected to the on-off control terminal, the first node and the control node respectively, and is used to control the connection between the first node and the control node under the control of the on-off control signal provided by the on-off control terminal;

[0024] The first compensation node is the third node, and the second compensation node is a control node in the compensation pixel circuit.

[0025] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0026] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0027] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0028] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the control node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of a first reset control signal provided by the first reset control terminal.

[0029] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0030] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset control terminal.

[0031] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0032] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0033] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit;

[0034] The third initialization circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively, and is also electrically connected to the second node or the third node, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node or the third node under the control of the third reset control signal provided by the third reset control terminal.

[0035] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a fourth initialization circuit;

[0036] The fourth initialization circuit is electrically connected to the fourth reset control terminal, the fourth initial voltage terminal and the fourth node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the fourth node under the control of a fourth reset control signal provided by the fourth reset control terminal.

[0037] Optionally, the driving circuit includes a driving transistor, and the compensation control circuit includes a first transistor;

[0038] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0039] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first compensation node, and the second electrode of the first transistor is electrically connected to the second compensation node.

[0040] Optionally, the data writing circuit includes a second transistor, and the first energy storage circuit includes a first capacitor;

[0041] A first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to a power supply voltage terminal;

[0042] A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

[0043] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, and the data writing circuit includes a second transistor;

[0044] A first end of a first capacitor is electrically connected to the first node, a second end of the first capacitor is electrically connected to a fourth node, a first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to a power supply voltage terminal;

[0045] A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the fourth node.

[0046] Optionally, the first light emitting control circuit includes a third transistor and a fourth transistor;

[0047] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0048] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0049] Optionally, the on-off control circuit includes a fifth transistor;

[0050] The gate of the fifth transistor is electrically connected to the on / off control terminal, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the control node.

[0051] Optionally, the first initialization circuit includes a sixth transistor;

[0052] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.

[0053] Optionally, the first initialization circuit includes a sixth transistor;

[0054] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the control node.

[0055] Optionally, the first initialization circuit includes a sixth transistor;

[0056] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

[0057] Optionally, the second initialization circuit includes a seventh transistor;

[0058] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0059] Optionally, the third initialization circuit includes an eighth transistor;

[0060] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node or the third node.

[0061] Optionally, the fourth initialization circuit includes a ninth transistor;

[0062] The gate of the ninth transistor is electrically connected to the fourth reset control terminal, the first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the fourth node.

[0063] In a second aspect, an embodiment of the present disclosure provides a display panel comprising multiple rows and columns of the above-mentioned pixel circuits.

[0064] Optionally, the pixel circuit and the compensation pixel circuit are located in the same row and are electrically connected to the first node of another pixel circuit separated by N pixel circuits;

[0065] N is a positive integer less than or equal to a number threshold, and the number threshold is a positive integer.

[0066] Optionally, the pixel circuit and the compensation pixel circuit are located in the same row and are adjacent to each other.

[0067] Optionally, the display panel according to at least one embodiment of the present disclosure includes a first pixel circuit and a second pixel circuit; the first compensation node in the first pixel circuit is the first third node, the first compensation node in the second pixel circuit is the second third node, the second compensation node in the first pixel circuit is the second first node; and the second compensation node in the second pixel circuit is the first first node;

[0068] The first pixel circuit includes a first on-off control circuit and a first compensation control circuit, and the second pixel circuit includes a second on-off control circuit and a second compensation control circuit;

[0069] The first on-off control circuit is electrically connected to the on-off control terminal, the first first node and the first control node respectively, and is used to control the connection between the first first node and the first control node under the control of the on-off control signal provided by the on-off control terminal;

[0070] The first on-off control circuit is electrically connected to the on-off control terminal, the second first node, and the second control node, respectively, and is configured to control the connection between the second first node and the second control node under the control of the on-off control signal;

[0071] The first compensation control circuit is electrically connected to the compensation control terminal, the first third node, and the second control node, respectively, and is configured to control the communication between the first third node and the second control node under the control of a compensation control signal provided by the compensation control terminal;

[0072] The second compensation control circuit is electrically connected to the compensation control terminal, the second third node and the first control node respectively, and is used to control the communication between the second third node and the first control node under the control of the compensation control signal;

[0073] The first third node is the third node in the first pixel circuit, the second third node is the third node in the second pixel circuit, the first first node is the first node in the first pixel circuit, and the second first node is the first node in the second pixel circuit.

[0074] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0080] FIG6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0081] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0082] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0083] FIG9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0084] FIG10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0085] FIG11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0086] FIG12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0087] FIG13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0088] FIG14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0089] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0090] FIG16 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0091] FIG17 is a timing diagram of the operation of at least one embodiment shown in FIG16;

[0092] FIG18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0093] FIG19 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0094] FIG20 is an operation timing diagram of at least one embodiment shown in FIG19 ;

[0095] FIG21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0096] FIG22 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0097] FIG23 is an operation timing diagram of at least one embodiment shown in FIG22 ;

[0098] FIG24 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0099] FIG25 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0100] FIG26 is an operation timing diagram of at least one embodiment shown in FIG25 ;

[0101] FIG27 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0102] FIG28 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0103] FIG29 is an operation timing diagram of at least one embodiment shown in FIG28;

[0104] FIG30 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0105] FIG31 is a circuit diagram of two pixel circuits in a display panel according to at least one embodiment of the present disclosure;

[0106] FIG. 32 is an operation timing diagram of at least one embodiment shown in FIG. 31 . DETAILED DESCRIPTION

[0107] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0108] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0109] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0110] The pixel circuit described in the embodiment of the present disclosure is applied to a display panel, and the pixel circuit includes a light-emitting element, a driving circuit, and a compensation control circuit;

[0111] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the light-emitting element via a third node, and the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the first node;

[0112] The compensation control circuit is electrically connected to the compensation control terminal;

[0113] The compensation control circuit is also electrically connected to the first compensation node and the second compensation node respectively, and is used to control the communication between the first compensation node and the second compensation node under the control of the compensation control signal provided by the compensation control terminal;

[0114] The second compensation node is a node in a compensation pixel circuit; the compensation pixel circuit is another pixel circuit in the display panel.

[0115] In the pixel circuit described in the embodiment of the present disclosure, the compensation control circuit controls the connection between the first compensation node and the second compensation node under the control of the compensation control signal, the second compensation node is a node in the compensation pixel circuit, and the compensation pixel circuit is another pixel circuit in the display panel.

[0116] In at least one embodiment of the present disclosure, the first compensation node is the third node, and the second compensation node is the first node in the compensation pixel circuit.

[0117] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure is applied to a display panel, and the pixel circuit includes a light-emitting element E1 , a driving circuit 10 , and a compensation control circuit 11 ;

[0118] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the light-emitting element E1 via the third node N3. The driving circuit 10 is configured to generate a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[0119] The compensation control circuit 11 is electrically connected to the compensation control terminal GB, the third node N3 and the second compensation node NJ, respectively, and is used to control the communication between the third node N3 and the second compensation node NJ under the control of the compensation control signal provided by the compensation control terminal GB;

[0120] The second compensation node NJ is a first node in a compensation pixel circuit; the compensation pixel circuit is another pixel circuit in the display panel.

[0121] During operation, during the compensation phase, the compensation control circuit 11, under the control of the compensation control signal, controls the connection between the third node N3 and the second compensation node NJ to perform threshold voltage compensation. The pixel circuit of the embodiment of the present disclosure can conveniently perform threshold voltage compensation and display light normally.

[0122] By adopting the pixel circuit described in at least one embodiment of the present disclosure, when displaying a monochrome image, the driving transistor in the pixel circuit that needs to display a dark color can be quickly turned on, thereby improving the display effect when displaying a monochrome image.

[0123] For example, when displaying a green picture, the pixel circuit on the left is a red pixel circuit, and the pixel circuit on the right is a green pixel circuit. The voltage value of the red data voltage corresponding to the red pixel circuit is 7V, and the voltage value of the green data voltage corresponding to the green pixel circuit is 2V. The potential of the gate of the driving transistor in the red pixel circuit will be set to a lower voltage value, and the driving transistor is a p-type transistor. The driving transistor in the red pixel circuit will turn on faster to improve the display effect when displaying a monochrome picture.

[0124] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, the compensation phase includes a data writing phase, which increases the duration of the compensation phase. In high-frequency display conditions, the compensation time can be increased, thereby improving display quality.

[0125] As shown in FIG2 , in at least one embodiment of the present disclosure, the display panel may include a first pixel circuit and a second pixel circuit;

[0126] The first pixel circuit includes a first light emitting element E11, a first driving circuit 101 and a first compensation control circuit 111;

[0127] The control end of the first driving circuit 101 is electrically connected to a first first node N11, the first end of the first driving circuit 101 is electrically connected to a first second node N12, and the second end of the first driving circuit 101 is electrically connected to the first light-emitting element E11 via a first third node N13. The first driving circuit 101 is configured to generate a driving current for driving the first light-emitting element E11 under the control of the potential of the first first node N11.

[0128] The first compensation control circuit 111 is electrically connected to the compensation control terminal GB, the first third node N13, and the second first node N21, respectively, and is configured to control the communication between the first third node N13 and the second first node N21 under the control of a compensation control signal provided by the compensation control terminal GB;

[0129] The second pixel circuit includes a second light emitting element E12, a second driving circuit 102 and a second compensation control circuit 112;

[0130] The control end of the second driving circuit 102 is electrically connected to the second first node N21, the first end of the second driving circuit 102 is electrically connected to the second second node N22, and the second end of the second driving circuit 102 is electrically connected to the second light-emitting element E12 via the second third node N23. The second driving circuit 102 is configured to generate a driving current for driving the second light-emitting element E12 under the control of the potential of the second first node N21.

[0131] The second compensation control circuit 112 is electrically connected to the compensation control terminal GB, the second third node N23 and the first first node N11 respectively, and is used to control the connection between the second third node N23 and the first first node N11 under the control of the compensation control signal provided by the compensation control terminal GB.

[0132] In at least one embodiment of the present disclosure, the first compensation node is the first node, and the second compensation node is a third node in the compensation pixel circuit.

[0133] As shown in FIG3 , the pixel circuit according to the embodiment of the present disclosure is applied to a display panel, and the pixel circuit includes a light-emitting element E1 , a driving circuit 10 , and a compensation control circuit 11 ;

[0134] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the light-emitting element E1 via the third node N3. The driving circuit 10 is configured to generate a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[0135] The compensation control circuit 11 is electrically connected to the compensation control terminal GB, the first node N1 and the second compensation node NJ, respectively, and is used to control the connection between the first node N1 and the second compensation node NJ under the control of the compensation control signal provided by the compensation control terminal GB;

[0136] The second compensation node NJ is a third node in a compensation pixel circuit; the compensation pixel circuit is another pixel circuit in the display panel.

[0137] As shown in FIG4 , in at least one embodiment of the present disclosure, the display panel may include a first pixel circuit and a second pixel circuit;

[0138] The first pixel circuit includes a first light emitting element E11, a first driving circuit 101 and a first compensation control circuit 111;

[0139] The control end of the first driving circuit 101 is electrically connected to a first first node N11, the first end of the first driving circuit 101 is electrically connected to a first second node N12, and the second end of the first driving circuit 101 is electrically connected to the first light-emitting element E11 via a first third node N13. The first driving circuit 101 is configured to generate a driving current for driving the first light-emitting element E11 under the control of the potential of the first first node N11.

[0140] The first compensation control circuit 111 is electrically connected to the compensation control terminal GB, the first first node N11, and the second third node N23, respectively, and is configured to control the communication between the first first node N11 and the second third node N23 under the control of the compensation control signal provided by the compensation control terminal GB;

[0141] The second pixel circuit includes a second light emitting element E12, a second driving circuit 102 and a second compensation control circuit 112;

[0142] The control end of the second driving circuit 102 is electrically connected to the second first node N21, the first end of the second driving circuit 102 is electrically connected to the second second node N22, and the second end of the second driving circuit 102 is electrically connected to the second light-emitting element E12 via the second third node N23. The second driving circuit 102 is configured to generate a driving current for driving the second light-emitting element E12 under the control of the potential of the second first node N21.

[0143] The second compensation control circuit 112 is electrically connected to the compensation control terminal GB, the second first node N21 and the first third node N13 respectively, and is used to control the connection between the second first node N21 and the first third node N13 under the control of the compensation control signal provided by the compensation control terminal GB.

[0144] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit and a first energy storage circuit;

[0145] The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal;

[0146] The first energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

[0147] In a specific implementation, the pixel circuit may further include a data writing circuit and a first energy storage circuit; the data writing circuit writes the data voltage into the second node under the control of a write control signal; the first energy storage circuit maintains the potential of the first node.

[0148] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit 51 and a first energy storage circuit 52 ;

[0149] The data writing circuit 51 is electrically connected to the writing control terminal GX, the data line DT and the second node N2, and is used to write the data voltage provided by the data line DT into the second node N2 under the control of the writing control signal provided by the writing control terminal GX;

[0150] The first energy storage circuit 52 is electrically connected to the first node N1 and is configured to maintain the potential of the first node N1.

[0151] The pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a first energy storage circuit and a second energy storage circuit;

[0152] A first end of a first energy tank circuit is electrically connected to the first node, a second end of the first energy tank circuit is electrically connected to a fourth node, a first end of the second energy tank circuit is electrically connected to the fourth node, a second end of the second energy tank circuit is electrically connected to a DC voltage terminal, and the first energy tank circuit and the second energy tank circuit are configured to store electrical energy;

[0153] The data writing circuit is electrically connected to the writing control terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the fourth node under the control of the writing control signal provided by the writing control terminal.

[0154] Optionally, the DC voltage terminal may be a power supply voltage terminal, but is not limited thereto.

[0155] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG3 , the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit 51 , a first energy storage circuit 52 , and a second energy storage circuit 53 ;

[0156] A first end of the first energy storage circuit 51 is electrically connected to the first node N1, a second end of the first energy storage circuit 51 is electrically connected to the fourth node N4, a first end of the second energy storage circuit 53 is electrically connected to the fourth node N4, and a second end of the second energy storage circuit 52 is electrically connected to the power supply voltage terminal VDD. The first energy storage circuit 51 and the second energy storage circuit 53 are used to store electrical energy;

[0157] The data writing circuit 52 is electrically connected to the writing control terminal GX, the data line DT and the fourth node N4 respectively, and is used to write the data voltage provided by the data line DT into the fourth node N4 under the control of the writing control signal provided by the writing control terminal GX.

[0158] The pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit and a second light emitting control circuit;

[0159] The first light emitting control circuit is electrically connected to the first light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light emitting control signal provided by the first light emitting control terminal;

[0160] The third node is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit;

[0161] The second light emitting control circuit is electrically connected to the second light emitting control terminal, the third node, and the first electrode of the light emitting element, respectively, and is configured to control the connection between the third node and the first electrode of the light emitting element under the control of a second light emitting control signal provided by the second light emitting control terminal;

[0162] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0163] In a specific implementation, the pixel circuit may include a first light-emitting control circuit and a second light-emitting control circuit, wherein the first light-emitting control circuit controls the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal; and the second light-emitting control circuit controls the connection between the third node and the first pole of the light-emitting element under the control of the second light-emitting control signal.

[0164] Optionally, the first light-emitting control end and the second light-emitting control end may be the same control end, but is not limited thereto; in a specific implementation, the first light-emitting control end and the second light-emitting control end may also be different light-emitting control ends.

[0165] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG5 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 71 and a second light emitting control circuit 72 ;

[0166] The first light emitting control circuit 71 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the second node N2, respectively, and is configured to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0167] The third node N3 is electrically connected to the first electrode of the light emitting element E1 through the second light emitting control circuit 72;

[0168] The second light emitting control circuit 72 is electrically connected to the second light emitting control terminal EM2, the third node N3, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2;

[0169] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1.

[0170] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0171] The pixel circuit according to at least one embodiment of the present disclosure further includes an on-off control circuit;

[0172] The on-off control circuit is electrically connected to the on-off control terminal, the first node and the control node respectively, and is used to control the connection between the first node and the control node under the control of the on-off control signal provided by the on-off control terminal;

[0173] The first compensation node is the third node, and the second compensation node is a control node in the compensation pixel circuit.

[0174] In a specific implementation, the pixel circuit may further include an on-off control circuit; the on-off control circuit controls the connectivity between the first node and the control node under the control of an on-off control signal; at this time, the first compensation node is the third node, and the second compensation node is the control node in the compensation pixel circuit.

[0175] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes an on-off control circuit 80 ;

[0176] The on-off control circuit 80 is electrically connected to the on-off control terminal TC, the first node N1 and the control node N0 respectively, and is used to control the connection between the first node N1 and the control node N0 under the control of the on-off control signal provided by the on-off control terminal TC.

[0177] As shown in FIG9 , in at least one embodiment of the present disclosure, the display panel may include a first pixel circuit and a second pixel circuit;

[0178] The first pixel circuit includes a first light emitting element E11, a first driving circuit 101, a first compensation control circuit 111 and a first on-off control circuit 801;

[0179] The control end of the first driving circuit 101 is electrically connected to a first first node N11, the first end of the first driving circuit 101 is electrically connected to a first second node N12, and the second end of the first driving circuit 101 is electrically connected to the first light-emitting element E11 via a first third node N13. The first driving circuit 101 is configured to generate a driving current for driving the first light-emitting element E11 under the control of the potential of the first first node N11.

[0180] The first compensation control circuit 111 is electrically connected to the compensation control terminal GB, the first third node N13, and the second control node N20, respectively, and is configured to control the connection between the first third node N13 and the second control node N20 under the control of the compensation control signal provided by the compensation control terminal GB;

[0181] The first on-off control circuit 801 is electrically connected to the on-off control terminal TC, the first first node N11, and the first control node N10, respectively, and is configured to control the connection between the first first node N11 and the first control node N10 under the control of the on-off control signal provided by the on-off control terminal TC;

[0182] The second pixel circuit includes a second light emitting element E12, a second driving circuit 102, a second compensation control circuit 112 and a second on-off control circuit 802;

[0183] The control end of the second driving circuit 102 is electrically connected to the second first node N21, the first end of the second driving circuit 102 is electrically connected to the second second node N22, and the second end of the second driving circuit 102 is electrically connected to the second light-emitting element E12 via the second third node N23. The second driving circuit 102 is configured to generate a driving current for driving the second light-emitting element E12 under the control of the potential of the second first node N21.

[0184] The second compensation control circuit 112 is electrically connected to the compensation control terminal GB, the second third node N23, and the first control node N10, respectively, and is configured to control the communication between the second third node N23 and the first control node N10 under the control of the compensation control signal provided by the compensation control terminal GB;

[0185] The second on-off control circuit 802 is electrically connected to the on-off control terminal TC, the second first node N21 and the second control node N20 respectively, and is used to control the connection between the second first node N21 and the second control node N20 under the control of the on-off control signal provided by the on-off control terminal TC.

[0186] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0187] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0188] In a specific implementation, the pixel circuit may include a first initialization circuit. Under the control of the first reset control signal, the first initialization circuit writes a first initial voltage into the first node to initialize the potential of the first node.

[0189] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0190] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the control node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of a first reset control signal provided by the first reset control terminal.

[0191] In a specific implementation, the pixel circuit may include a first initialization circuit, which, under the control of the first reset control signal, writes a first initial voltage into the control node to initialize the potential of the control node; when the on-off control circuit is turned on, the potential of the first node is initialized.

[0192] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit;

[0193] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset control terminal.

[0194] In a specific implementation, the pixel circuit may include a first initialization circuit, which writes a first initial voltage into the third node under the control of the first reset control signal.

[0195] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit;

[0196] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

[0197] In a specific implementation, the pixel circuit may further include a second initialization circuit, which, under the control of a second reset control signal, writes a second initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0198] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit;

[0199] The third initialization circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively, and is also electrically connected to the second node or the third node, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node or the third node under the control of the third reset control signal provided by the third reset control terminal.

[0200] In a specific implementation, the pixel circuit may further include a third initialization circuit, which, under the control of the third reset control signal, writes the third initial voltage provided by the third initial voltage terminal into the second node or the third node to improve hysteresis.

[0201] As shown in FIG10 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 81 ;

[0202] The first initialization circuit 81 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1;

[0203] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 82;

[0204] The second initialization circuit 82 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the first electrode of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2.

[0205] As shown in FIG11 , based on at least one embodiment of the pixel circuit shown in FIG10 , the pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 83 ;

[0206] The third initialization circuit 83 is electrically connected to the third reset control terminal R3 and the third initial voltage terminal I3 respectively. The third initialization circuit 83 is also electrically connected to the second node N2, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal provided by the third reset control terminal R3.

[0207] As shown in FIG12 , based on at least one embodiment of the pixel circuit shown in FIG7 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 81 ;

[0208] The first initialization circuit 81 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1, and the third node N3, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the first reset control signal provided by the first reset control terminal R1;

[0209] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 82;

[0210] The second initialization circuit 82 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2;

[0211] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 83;

[0212] The third initialization circuit 83 is electrically connected to the third reset control terminal R3 and the third initial voltage terminal I3 respectively. The third initialization circuit 83 is also electrically connected to the second node N2, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal provided by the third reset control terminal R3.

[0213] As shown in FIG13 , based on at least one embodiment of the pixel circuit shown in FIG8 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 81 ;

[0214] The first initialization circuit 81 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the control node N0, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node N0 under the control of the first reset control signal provided by the first reset control terminal R1;

[0215] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 82;

[0216] The second initialization circuit 82 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2;

[0217] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 83;

[0218] The third initialization circuit 83 is electrically connected to the third reset control terminal R3 and the third initial voltage terminal I3 respectively. The third initialization circuit 83 is also electrically connected to the second node N2, and is used to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of the third reset control signal provided by the third reset control terminal R3.

[0219] The pixel circuit according to at least one embodiment of the present disclosure further includes a fourth initialization circuit;

[0220] The fourth initialization circuit is electrically connected to the fourth reset control terminal, the fourth initial voltage terminal and the fourth node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the fourth node under the control of a fourth reset control signal provided by the fourth reset control terminal.

[0221] In a specific implementation, the pixel circuit may further include a fourth initialization circuit; and the fourth initialization circuit writes a fourth initial voltage into the fourth node under the control of the fourth reset control signal.

[0222] As shown in FIG14 , based on at least one embodiment of the pixel circuit shown in FIG6 , the pixel circuit according to at least one embodiment of the present disclosure further includes a first light emitting control circuit 71 and a second light emitting control circuit 72 ;

[0223] The first light emitting control circuit 71 is electrically connected to the first light emitting control terminal EM1, the power supply voltage terminal VDD, and the second node N2, respectively, and is configured to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of a first light emitting control signal provided by the first light emitting control terminal EM1;

[0224] The third node N3 is electrically connected to the first electrode of the light emitting element E1 through the second light emitting control circuit 72;

[0225] The second light emitting control circuit 72 is electrically connected to the second light emitting control terminal EM2, the third node N3, and the first electrode of the light emitting element E1, respectively, and is configured to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of a second light emitting control signal provided by the second light emitting control terminal EM2;

[0226] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0227] The pixel circuit according to at least one embodiment of the present disclosure further includes a first initialization circuit 81;

[0228] The first initialization circuit 81 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1;

[0229] The pixel circuit according to at least one embodiment of the present disclosure further includes a second initialization circuit 82;

[0230] The second initialization circuit 82 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2;

[0231] The pixel circuit according to at least one embodiment of the present disclosure further includes a third initialization circuit 83;

[0232] The third initialization circuit 83 is electrically connected to the third reset control terminal R3 and the third initial voltage terminal I3, respectively. The third initialization circuit 83 is also electrically connected to the second node N2, and is configured to write the third initial voltage Vinit3 provided by the third initial voltage terminal I3 into the second node N2 under the control of a third reset control signal provided by the third reset control terminal R3;

[0233] The pixel circuit according to at least one embodiment of the present disclosure further includes a fourth initialization circuit 84;

[0234] The fourth initialization circuit 83 is electrically connected to the fourth reset control terminal R4, the fourth initial voltage terminal I4 and the fourth node N4, respectively, and is configured to write the fourth initial voltage provided by the fourth initial voltage terminal I4 into the fourth node N4 under the control of a fourth reset control signal provided by the fourth reset control terminal R4.

[0235] Optionally, the driving circuit includes a driving transistor, and the compensation control circuit includes a first transistor;

[0236] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0237] The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first compensation node, and the second electrode of the first transistor is electrically connected to the second compensation node.

[0238] In at least one embodiment of the present disclosure, the compensation control circuit may include other electrical devices, such as capacitors, which can provide the threshold voltage of the driving transistor to the gate of the driving transistor in another pixel circuit.

[0239] Optionally, the data writing circuit includes a second transistor, and the first energy storage circuit includes a first capacitor;

[0240] A first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to a power supply voltage terminal;

[0241] A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

[0242] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, and the data writing circuit includes a second transistor;

[0243] A first end of a first capacitor is electrically connected to the first node, a second end of the first capacitor is electrically connected to a fourth node, a first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to a power supply voltage terminal;

[0244] A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the fourth node.

[0245] Optionally, the first light emitting control circuit includes a third transistor and a fourth transistor;

[0246] The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node;

[0247] The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

[0248] Optionally, the on-off control circuit includes a fifth transistor;

[0249] The gate of the fifth transistor is electrically connected to the on / off control terminal, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the control node.

[0250] Optionally, the first initialization circuit includes a sixth transistor;

[0251] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.

[0252] Optionally, the first initialization circuit includes a sixth transistor;

[0253] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the control node.

[0254] Optionally, the first initialization circuit includes a sixth transistor;

[0255] A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

[0256] Optionally, the second initialization circuit includes a seventh transistor;

[0257] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0258] Optionally, the third initialization circuit includes an eighth transistor;

[0259] The gate of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node or the third node.

[0260] Optionally, the fourth initialization circuit includes a ninth transistor;

[0261] The gate of the ninth transistor is electrically connected to the fourth reset control terminal, the first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the fourth node.

[0262] As shown in FIG15 , based on at least one embodiment of the pixel circuit shown in FIG10 , the light emitting element is an organic light emitting diode O1;

[0263] The driving circuit includes a driving transistor T0, and the compensation control circuit includes a first transistor T1;

[0264] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0265] The gate of the first transistor T1 is electrically connected to the first scanning terminal NG, the source of the first transistor T1 is electrically connected to the third node N3, and the drain of the first transistor T1 is electrically connected to the second compensation node NJ; the second compensation node NJ is the first node in the compensation pixel circuit;

[0266] The data writing circuit includes a second transistor T2, and the first energy storage circuit includes a first capacitor C1;

[0267] A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the power supply voltage terminal VDD;

[0268] The gate of the second transistor T2 is electrically connected to the second scanning terminal PG, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the second node N2;

[0269] The first light emitting control circuit includes a third transistor T3 and a fourth transistor T4;

[0270] The gate of the third transistor T3 is electrically connected to the light emitting control terminal EM, the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0271] The gate of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1;

[0272] The first initialization circuit includes a sixth transistor T6;

[0273] The gate of the sixth transistor T6 is electrically connected to the first reset control terminal R1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0274] The second initialization circuit includes a seventh transistor T7;

[0275] The gate of the seventh transistor T7 is electrically connected to the second scanning terminal PG, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;

[0276] The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal VSS.

[0277] In at least one embodiment shown in FIG. 15 , T1 and T6 are n-type transistors to reduce leakage of N1 , and the other transistors are p-type transistors.

[0278] In at least one embodiment shown in FIG15 , the first light-emitting control terminal and the second light-emitting control terminal are the same light-emitting control terminal, the compensation control terminal is the first scanning terminal, the write control terminal is the second scanning terminal, and the second reset control terminal is the second scanning terminal.

[0279] In at least one embodiment shown in FIG. 15 , Vinit1 may be greater than or equal to -5V and less than or equal to 0V, and Vinit2 may be greater than or equal to -5V and less than or equal to 0V; Vinit1 may be less than Vinit2; for example, Vinit1 may be -4V, and Vinit2 may be -2.8V.

[0280] In at least one embodiment shown in FIG. 15 , when T0 is replaced with an n-type transistor, Vinit1 may be greater than or equal to 0V and less than or equal to 8V.

[0281] As shown in FIG16 , at least one embodiment of the display panel may include a first pixel circuit and a second pixel circuit;

[0282] The first pixel circuit includes a first organic light emitting diode O11, a first first capacitor C11, a first driving transistor T01, a first first transistor T11, a first second transistor T12, a first third transistor T13, a first fourth transistor T14, a first sixth transistor T16 and a first seventh transistor T17;

[0283] The second pixel circuit includes a second organic light emitting diode O12, a second first capacitor C21, a second driving transistor T02, a second first transistor T21, a second second transistor T22, a second third transistor T23, a second fourth transistor T24, a second sixth transistor T26 and a second seventh transistor T27;

[0284] The gate of T01 is electrically connected to the first first node N11, the source of T01 is electrically connected to the first second node N12, and the drain of T01 is electrically connected to the first third node N13;

[0285] The gate of T11 is electrically connected to the first scanning terminal NG, the source of T11 is electrically connected to the first third node N13, and the drain of T11 is electrically connected to the second first node N21;

[0286] A first end of C11 is electrically connected to the first first node N11, and a second end of C11 is electrically connected to the power supply voltage terminal VDD;

[0287] The gate of T12 is electrically connected to the second scanning terminal PG, the source of T12 is electrically connected to the first data line DT1, and the drain of T12 is electrically connected to the first second node N12;

[0288] The gate of T13 is electrically connected to the light emitting control terminal EM, the source of T13 is electrically connected to the power supply voltage terminal VDD, and the drain of T13 is electrically connected to the first second node N12;

[0289] The gate of T14 is electrically connected to the light emitting control terminal EM, the source of T14 is electrically connected to the first third node N13, the drain of T14 is electrically connected to the anode of O11; the cathode of O11 is electrically connected to the low voltage terminal VSS;

[0290] The gate of T16 is electrically connected to the first reset control terminal R1, the source of T16 is electrically connected to the first initial voltage terminal I1, and the drain of T16 is electrically connected to the first first node N11;

[0291] The gate of T17 is electrically connected to the second scanning terminal PG, the source of T17 is electrically connected to the second initial voltage terminal I2, and the drain of T17 is electrically connected to the anode of O11;

[0292] The gate of T02 is electrically connected to the second first node N21, the source of T02 is electrically connected to the second second node N22, and the drain of T01 is electrically connected to the second third node N23;

[0293] The gate of T21 is electrically connected to the first scanning terminal NG, the source of T21 is electrically connected to the second third node N23, and the drain of T11 is electrically connected to the first first node N11;

[0294] A first end of C21 is electrically connected to the second first node N21, and a second end of C21 is electrically connected to the power supply voltage terminal VDD;

[0295] The gate of T22 is electrically connected to the second scanning terminal PG, the source of T22 is electrically connected to the second data line DT2, and the drain of T22 is electrically connected to the second second node N22;

[0296] The gate of T23 is electrically connected to the light emitting control terminal EM, the source of T23 is electrically connected to the power supply voltage terminal VDD, and the drain of T23 is electrically connected to the second second node N22;

[0297] The gate of T24 is electrically connected to the light emitting control terminal EM, the source of T24 is electrically connected to the second third node N23, the drain of T24 is electrically connected to the anode of O12; the cathode of O12 is electrically connected to the low voltage terminal VSS;

[0298] The gate of T26 is electrically connected to the first reset control terminal R1, the source of T26 is electrically connected to the first initial voltage terminal I1, and the drain of T26 is electrically connected to the second first node N21;

[0299] The gate of T27 is electrically connected to the second scanning terminal PG, the source of T27 is electrically connected to the second initial voltage terminal I2, and the drain of T27 is electrically connected to the anode of O12.

[0300] In at least one embodiment shown in FIG. 16 , T11 , T16 , T21 , and T26 are n-type transistors to reduce leakage of N11 and N21 , and the other transistors are p-type transistors.

[0301] As shown in FIG17 , when at least one embodiment of the pixel circuit shown in FIG16 of the present disclosure is in operation, a display cycle may include a first reset phase S1 , a compensation phase S2 , and a light emitting phase S3 ; the compensation phase S2 includes a data writing phase S0 ;

[0302] In the first reset phase S1, R1 provides a high voltage signal, T16 and T26 are turned on, I1 provides a first initial voltage Vinit1 to N11, and I1 provides a first initial voltage Vinit1 to N21, so that T01 and T02 can be turned on when the data writing phase S0 begins;

[0303] In the compensation stage S2, NG provides a high voltage signal, T11 and T21 are turned on, N13 and N21 are connected, and N23 and N11 are connected;

[0304] In the data writing phase S0, PG provides a low voltage signal, T12 is turned on, T22 is turned on, T17 is turned on, T27 is turned on, DT1 provides the first data voltage Vdata1 to N12, DT2 provides the second data voltage Vdata2 to N22, and I2 provides the second initial voltage Vinit2 to the anodes of O11 and O12 to clear the residual charge on the anodes of O11 and O12.

[0305] At the beginning of the data writing phase S0, T01 and T02 are turned on to charge C11 and C21 until the potential of N11 becomes Vdata1+Vth1, T01 is turned off, and until the potential of N21 becomes Vdata2+Vth2, T02 is turned off, Vth1 is the threshold voltage of T01, and Vth2 is the threshold voltage of T02;

[0306] In the light-emitting stage S3, T13, T14, T23 and T24 are turned on, T01 drives O11 to emit light, and T02 drives O12 to emit light.

[0307] In at least one embodiment of the present disclosure, the first pixel circuit and the second pixel circuit are located in the same row and are separated by N pixel circuits; or, the first pixel circuit and the second pixel circuit are located in the same row and are adjacent to each other; in this case, Vth1 and Vth2 are not much different and are almost equal;

[0308] N is a positive integer less than or equal to a number threshold, and the number threshold is a positive integer.

[0309] For example, the number threshold may be equal to 2, 3, or 4, but is not limited thereto.

[0310] The difference between at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is that:

[0311] At least one embodiment of the pixel circuit shown in FIG18 of the present disclosure further includes a third initialization circuit; the gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2;

[0312] The third initialization circuit includes an eighth transistor T8;

[0313] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal R2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the second node N2; the third initial voltage terminal I3 is used to provide a third initial voltage Vinit3.

[0314] In FIG18 , T8 is a p-type transistor, and the third reset control terminal is the second reset control terminal R2 .

[0315] In at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure, the drain of T8 may be electrically connected to the third node N3 instead, which may also improve the hysteresis phenomenon of T0.

[0316] In at least one embodiment shown in FIG. 18 , Vinit1 may be greater than or equal to -5V and less than or equal to 0V, and Vinit2 may be greater than or equal to -5V and less than or equal to 0V; for example, Vinit1 may be -4V, and Vinit2 may be -2.8V.

[0317] In at least one embodiment shown in FIG. 18 , when T0 is replaced with an n-type transistor, Vini,3 may be greater than or equal to 0V and less than or equal to 8V.

[0318] In at least one embodiment shown in FIG. 18 , Vinit3 may be greater than or equal to 0V and less than or equal to 8V; and Vinit1 is less than Vinit3.

[0319] In at least one embodiment shown in FIG. 18 , Vinit1 can be generally set below -3V, and Vinit3 can be generally set above 8V.

[0320] The difference between at least one embodiment shown in FIG19 and at least one embodiment shown in FIG16 is that: the gate of T17 is electrically connected to the second reset control terminal R2, and the gate of T27 is electrically connected to the second reset control terminal R2;

[0321] The first pixel circuit further includes a first third initialization circuit, and the second pixel circuit further includes a second third initialization circuit;

[0322] The first third initialization circuit includes a first eighth transistor T18;

[0323] The gate of T18 is electrically connected to the second reset control terminal R2, the source of T18 is electrically connected to the third initial voltage terminal I3, and the drain of T18 is electrically connected to the first second node N12;

[0324] The second third initialization circuit includes a second eighth transistor T28;

[0325] The gate of T28 is electrically connected to the second reset control terminal R2 , the source of T28 is electrically connected to the third initial voltage terminal I3 , and the drain of T28 is electrically connected to the second second node N12 .

[0326] In FIG19 , T18 and T28 are p-type transistors.

[0327] As shown in FIG20 , when at least one embodiment shown in FIG19 is in operation, the display cycle includes a first reset phase S1 , a compensation phase S2 , a second reset phase S4 and a light-emitting phase S3 ; the compensation phase S2 includes a data writing phase S0 ;

[0328] In the first reset phase S1, EM provides a high voltage signal, R1 provides a high voltage signal, NG provides a low voltage signal, PG provides a high voltage signal, R2 provides a high voltage signal, T16 and T26 are turned on, and I1 provides a first initial voltage Vinit1 to N11 and N21, so that T01 and T02 can be turned on when the data writing phase S0 begins;

[0329] In the compensation phase S2, NG provides a high voltage signal, T11 and T21 are turned on, so that N13 is connected to N21, and N23 is connected to N11.

[0330] In the data writing phase S0, PG provides a low voltage signal, T12 and T22 are turned on, DT1 provides the first data voltage Vdata1 to N12, and DT2 provides the second data voltage Vdata2 to N22;

[0331] At the beginning of the data writing phase S0, T01 and T02 are turned on, charging C11 and C21 until T01 is turned off, at which time the potential of N11 is Vdata1+Vth1, until T02 is turned off, at which time the potential of N21 is Vdata2+Vth2, where Vth1 is the threshold voltage of T01 and Vth2 is the threshold voltage of T02;

[0332] In the second reset phase S4, R2 provides a low voltage signal, T17 and T18 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O11 to clear the residual charge at the anode of O11, I3 provides a third initial voltage Vinit3 to N12 to improve the hysteresis of T01, I2 provides Vinit2 to the anode of O12 to clear the residual charge at the anode of O12, I3 provides a third initial voltage Vinit3 to N22 to improve the hysteresis of T02;

[0333] In the light-emitting stage S3, T13, T14, T23 and T24 are turned on, T01 drives O11 to emit light, and T02 drives O12 to emit light.

[0334] The difference between at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 18 of the present disclosure is that:

[0335] The drain of T6 is electrically connected to the third node N3 , and T6 is a p-type transistor.

[0336] In at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure, Vinit1 may be greater than or equal to -5V and less than or equal to 0V, and Vinit2 may be greater than or equal to -5V and less than or equal to 0V; Vinit1 may be less than Vinit2; for example, Vinit1 may be -4V, and Vinit2 may be -2.8V.

[0337] In at least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure, Vinit3 may be greater than or equal to 0V and less than or equal to 8V; and Vinit1 is less than Vinit3.

[0338] In at least one embodiment shown in FIG. 21 , when T0 is replaced with an n-type transistor, Vinit1 may be greater than or equal to 0V and less than or equal to 8V.

[0339] The difference between at least one embodiment shown in FIG22 and at least one embodiment shown in FIG19 is that:

[0340] The drain of T16 is electrically connected to the first third node N13, and the drain of T26 is electrically connected to the second third node N23;

[0341] T16 and T26 are p-type transistors.

[0342] As shown in FIG23 , when at least one embodiment shown in FIG22 of the present disclosure is in operation, a display cycle may include a compensation phase S2 , a second reset phase S4 , and a light-emitting phase S3 , wherein the compensation phase S2 includes a first reset phase S1 and a data writing phase S0 ;

[0343] In the compensation stage S2, NG provides a high voltage signal, T11 and T21 are turned on, N13 is connected to N21, and N23 is connected to N11;

[0344] In the first reset phase S1, R1 provides a low voltage signal, T16 and T26 are turned on, and I1 provides a first initial voltage Vinit1 to N13 and N23. Since T11 and T21 are turned on, Vinit1 can be written into N11 and N21.

[0345] In the data writing phase S0, PG provides a low voltage signal, DT1 writes the first data voltage Vdata1 to N12, and DT2 writes the second data voltage Vdata2 to N22;

[0346] At the beginning of the data writing phase S0, T01 and T02 are turned on, charging C11 and C21 until T01 is turned off. At this time, the potential of N11 is Vdata1+Vth1, until T02 is turned off. At this time, the potential of N21 is Vdata2+Vth2; Vth1 is the threshold voltage of T01, and Vth2 is the threshold voltage of T02;

[0347] In the second reset phase S4, R2 provides a low voltage signal, T17 and T18 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O11 to clear the residual charge at the anode of O11, I3 provides a third initial voltage Vinit3 to N12 to improve the hysteresis of T01, I2 provides Vinit2 to the anode of O12 to clear the residual charge at the anode of O12, I3 provides a third initial voltage Vinit3 to N22 to improve the hysteresis of T02;

[0348] In the light-emitting stage S3, EM provides a low voltage signal, T13, T14, T23 and T24 are turned on, T01 drives O11 to emit light, and T02 drives O12 to emit light.

[0349] The difference between at least one embodiment of the pixel circuit shown in FIG24 and at least one embodiment of the pixel circuit shown in FIG18 is that:

[0350] At least one embodiment of the pixel circuit shown in FIG24 further includes an on-off control circuit, wherein the on-off control circuit includes a fifth transistor T5;

[0351] The gate of the fifth transistor T5 is electrically connected to the first scanning terminal NG, the source of the fifth transistor T5 is electrically connected to the first node N1, and the drain of the fifth transistor T5 is electrically connected to the control node N0;

[0352] The gate of T1 is electrically connected to the second scanning terminal PG; the second compensation node NJ is electrically connected to the control node in the compensation pixel circuit;

[0353] The gate of T6, the gate of T7 and the gate of T8 are all electrically connected to the second reset control terminal R2;

[0354] T1 is a p-type transistor, T6 is a p-type transistor, and T5 is an n-type transistor.

[0355] In at least one embodiment of the pixel circuit shown in FIG. 24 of the present disclosure, Vinit1 may be greater than or equal to -5V and less than or equal to 0V, and Vinit2 may be greater than or equal to -5V and less than or equal to 0V; Vinit1 may be less than Vinit2; for example, Vinit1 may be -4V, and Vinit2 may be -2.8V.

[0356] In at least one embodiment of the pixel circuit shown in FIG. 24 of the present disclosure, Vinit3 may be greater than or equal to 0V and less than or equal to 8V; and Vinit1 is less than Vinit3.

[0357] In at least one embodiment shown in FIG. 24 , when T0 is replaced with an n-type transistor, Vinit1 may be greater than or equal to 0V and less than or equal to 8V.

[0358] The difference between at least one embodiment shown in FIG25 and at least one embodiment shown in FIG19 is that:

[0359] The first pixel circuit further includes a first on-off control circuit, wherein the first on-off control circuit includes a first fifth transistor T15;

[0360] The second pixel circuit further includes a second on-off control circuit, wherein the second on-off control circuit includes a second fifth transistor T25;

[0361] The gate of T15 is electrically connected to the first scanning terminal NG, the source of T15 is electrically connected to the first first node N11, and the drain of T15 is electrically connected to the first control node N01;

[0362] The gate of T25 is electrically connected to the first scanning terminal NG, the source of T25 is electrically connected to the second first node N21, and the drain of T25 is electrically connected to the second control node N02;

[0363] The gate of T11 is electrically connected to the second scanning terminal PG, and the gate of T21 is electrically connected to the second scanning terminal PG;

[0364] The drain of T11 is electrically connected to the second control node N02, and the drain of T21 is electrically connected to the first control node N01;

[0365] The gate of T16, the gate of T17, the gate of T18, the gate of T26, the gate of T27 and the gate of T28 are all electrically connected to the second reset control terminal R2;

[0366] T11 is a p-type transistor, T16 is a p-type transistor, and T15 is an n-type transistor;

[0367] T21 is a p-type transistor, T26 is a p-type transistor, and T25 is an n-type transistor.

[0368] As shown in FIG26 , when at least one embodiment shown in FIG25 of the present disclosure is in operation, a display cycle may include an on-off control phase S5 , a second reset phase S4 , and a light-emitting phase S3 , wherein the on-off control phase S5 includes a first reset phase S1 and a data writing phase S0 ;

[0369] In the on-off control stage S5, NG provides a high voltage signal, T15 and T25 are turned on, N11 is connected to N01, and N21 is connected to N02;

[0370] In the first reset phase S1, R2 provides a low voltage signal, T16 and T26 are turned on, and I1 provides a first initial voltage Vinit1 to N01 and N02. Since T15 and T25 are turned on, Vinit1 can be written to N11 and N21, so that when the data writing phase S0 is turned on, T01 and T02 can be turned on;

[0371] In the first reset phase S1 and the second reset phase S4, T17 is turned on, and I2 provides a second initial voltage Vinit2 to the anodes of O11 and O12 to clear the residual charge on the anodes of O11 and O12;

[0372] In the first reset phase S1, T18 and T28 are turned on, and I3 provides a third initial voltage Vinit3 to N12 and N22.

[0373] In the second reset phase S4, T18 and T28 are turned on, and I3 provides a third initial voltage Vinit3 to N12 and N22 to improve the hysteresis of T01 and the hysteresis of T02;

[0374] In the data writing phase S0, PG provides a low voltage signal, T11, T21, T12 and T22 are turned on, DT1 provides the first data voltage Vdata1 to N12, DT2 provides the second data voltage Vdata2 to N22, N13 is connected to N02, N23 is connected to N01, N13 is connected to N21, and N23 is connected to N11;

[0375] At the beginning of the data writing phase S0, T01 and T02 are turned on, charging C11 and C21 until T01 is turned off. At this time, the potential of N11 is Vdata1+Vth1, until T02 is turned off, until the potential of N21 is Vdata2+Vth2; Vth1 is the threshold voltage of T01, and Vth2 is the threshold voltage of T02;

[0376] In the light-emitting stage S3, EM provides a low voltage signal, T13, T14, T23 and T24 are turned on, T01 drives O11 to emit light, and T02 drives O12 to emit light.

[0377] The difference between at least one embodiment of the pixel circuit shown in FIG27 and at least one embodiment of the pixel circuit shown in FIG24 is that:

[0378] T5 is a p-type transistor, T6 is an n-type transistor, and T1 is an n-type transistor;

[0379] The gate of T5 is electrically connected to the second scanning terminal PG, the gate of T1 is electrically connected to the first scanning terminal NG, and the gate of T6 is electrically connected to the first reset control terminal R1; the gate of T3 is electrically connected to the first light-emitting control terminal EM1, and the gate of T4 is electrically connected to the second light-emitting control terminal EM2.

[0380] In at least one embodiment of the pixel circuit shown in Figure 27 of the present disclosure, Vinit1 can be greater than or equal to -5V and less than or equal to 0V, and Vinit2 can be greater than or equal to -5V and less than or equal to 0V; Vinit1 can be less than Vinit2; for example, Vinit1 can be -4V, and Vinit2 can be -2.8V.

[0381] In at least one embodiment of the pixel circuit shown in FIG. 27 of the present disclosure, Vinit3 may be greater than or equal to 0V and less than or equal to 8V; and Vinit1 is less than Vinit3.

[0382] In at least one embodiment shown in FIG. 27 , when T0 is replaced with an n-type transistor, Vinit1 may be greater than or equal to 0V and less than or equal to 8V.

[0383] The difference between at least one embodiment shown in FIG28 and at least one embodiment shown in FIG25 is that: T15 is a p-type transistor, T16 is an n-type transistor, and T11 is an n-type transistor; T25 is a p-type transistor, T26 is an n-type transistor, and T21 is an n-type transistor;

[0384] The gate of T15 is electrically connected to the second scanning terminal PG, the gate of T11 is electrically connected to the first scanning terminal NG, and the gate of T16 is electrically connected to the first reset control terminal R1; the gate of T13 is electrically connected to the first light-emitting control terminal EM1, and the gate of T14 is electrically connected to the second light-emitting control terminal EM2;

[0385] The gate of T25 is electrically connected to the second scanning terminal PG, the gate of T21 is electrically connected to the first scanning terminal NG, and the gate of T26 is electrically connected to the first reset control terminal R1; the gate of T23 is electrically connected to the first light-emitting control terminal EM1, and the gate of T24 is electrically connected to the second light-emitting control terminal EM2.

[0386] As shown in FIG29 , when at least one embodiment shown in FIG28 is in operation, the display cycle includes a first stage S01 , a second stage S02 , a third stage S03 , a data writing stage S0 , a fourth stage S04 and a light emitting stage S3 ;

[0387] In the first phase S01, EM1 and EM2 provide a high voltage signal, R2 provides a low voltage signal, T17, T18, T27, and T28 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O11 and O12 to clear the residual charge on the anodes of O11 and O12; I3 provides a third initial voltage Vinit3 to N12 and N22;

[0388] In the second phase S02 , EM1 and EM2 provide a high voltage signal, R1 provides a high voltage signal, T16 and T26 are turned on, and I1 provides a first initial voltage Vinit1 to N01 and N02 ;

[0389] In the second phase S02, when PG provides a low voltage signal, T15 and T25 are turned on, and I1 provides a first initial voltage Vinit1 to N11 and N21, so that T01 and T02 can be turned on when the data writing phase S0 begins;

[0390] In the third phase S03, NG provides a high voltage signal, R1 provides a high voltage signal, T16 is turned on, T26 is turned on, I1 provides a first initial voltage Vinit1 to N01 and N02, T11 and T21 are turned on, N13 is connected to N01, and N23 is connected to N02;

[0391] In the data writing phase S0, NG provides a high voltage signal, PG provides a low voltage signal, T11 and T12 are turned on, T15 and T25 are turned on, N13 is connected to N21, and N23 is connected to N11; T12 is turned on, T22 is turned on, DT1 provides the first data voltage Vdata1 to N12, and DT2 provides the second data voltage Vdata2 to N22;

[0392] At the beginning of the data writing phase S0, T01 and T02 are turned on, charging C11 and C21 until T01 is turned off. At this time, the potential of N11 is Vdata1+Vth1, until T02 is turned off. At this time, the potential of N21 is Vdata2+Vth2; Vth1 is the threshold voltage of T01, and Vth2 is the threshold voltage of T02;

[0393] In the fourth stage S04, R2 provides a low voltage signal, I2 provides a second initial voltage Vinit2 to the anodes of O11 and O12 to clear the residual charge of the anodes of O11 and O12; I3 provides a third initial voltage Vinit3 to N12 and N22 to improve the hysteresis of T01 and T02;

[0394] In the light-emitting stage S3, EM1 and EM2 provide low voltage signals, T13, T14, T23 and T24 are turned on, T01 drives O11 to emit light, and T02 drives O12 to emit light.

[0395] As shown in FIG30 , based on at least one embodiment of the pixel circuit shown in FIG14 , the light emitting element is an organic light emitting diode O1;

[0396] The driving circuit includes a driving transistor T0, and the compensation control circuit includes a first transistor T1;

[0397] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0398] The gate of the first transistor T1 is electrically connected to the first control terminal GT1, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the second compensation node NJ; the second compensation node NJ is electrically connected to the third node in the compensation pixel circuit;

[0399] The first energy storage circuit includes a first capacitor C1, the second energy storage circuit includes a second capacitor C2, and the data writing circuit includes a second transistor T2;

[0400] A first end of a first capacitor C1 is electrically connected to the first node N1, a second end of the first capacitor C1 is electrically connected to a fourth node N4, a first end of a second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to a power supply voltage terminal VDD;

[0401] The gate of the second transistor T2 is electrically connected to the second control terminal GT, the source of the second transistor T2 is electrically connected to the data line DT, and the drain of the second transistor T2 is electrically connected to the fourth node N4;

[0402] The first light emitting control circuit includes a third transistor T3 and a fourth transistor T4;

[0403] The gate of the third transistor T3 is electrically connected to the first light emitting control terminal EM1, the source of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the drain of the third transistor T3 is electrically connected to the second node N2;

[0404] The gate of the fourth transistor T4 is electrically connected to the second light emitting control terminal EM2, the source of the fourth transistor T4 is electrically connected to the third node N3, and the drain of the fourth transistor T4 is electrically connected to the anode of the organic light emitting diode O1;

[0405] The first initialization circuit includes a sixth transistor T6;

[0406] The gate of the sixth transistor T6 is electrically connected to the first reset control terminal R1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0407] The second initialization circuit includes a seventh transistor T7;

[0408] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;

[0409] The third initialization circuit includes an eighth transistor T8;

[0410] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal R2, the source of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain of the eighth transistor T8 is electrically connected to the second node N2; the third initial voltage terminal I3 is used to provide a third initial voltage Vinit3;

[0411] The fourth initialization circuit includes a ninth transistor T9;

[0412] A gate of the ninth transistor T9 is electrically connected to the first control terminal GT1 , a source of the ninth transistor T9 is electrically connected to the fourth initial voltage terminal I4 , and a drain of the ninth transistor T9 is electrically connected to the fourth node N4 .

[0413] In at least one embodiment shown in FIG. 30 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0414] In at least one embodiment shown in FIG. 30 , the compensation control terminal is the first control terminal GT1 , the write control terminal is the second control terminal GT, the third reset control terminal is the second reset control terminal R2 , and the fourth reset control terminal is the first control terminal GT1 .

[0415] As shown in FIG31 , at least one embodiment of the display panel may include a first pixel circuit and a second pixel circuit;

[0416] The first pixel circuit includes a first organic light emitting diode O11, a first driving transistor T01, a first first transistor T11, a first first capacitor C11, a first second capacitor C12, a first second transistor T12, a first third transistor T13, a first fourth transistor T14, a first sixth transistor T16, a first seventh transistor T17, a first eighth transistor T18 and a first ninth transistor T19;

[0417] The second pixel circuit includes a second organic light emitting diode O12, a second driving transistor T02, a second first transistor T21, a second first capacitor C21, a second second capacitor C22, a second second transistor T22, a second third transistor T23, a second fourth transistor T24, a second sixth transistor T26, a second seventh transistor T27, a second eighth transistor T28 and a second ninth transistor T29;

[0418] The gate of T01 is electrically connected to the first first node N11, the source of T01 is electrically connected to the first second node N12, and the drain of T01 is electrically connected to the first third node N13;

[0419] The gate of T11 is electrically connected to the first control terminal GT1, the source of T11 is electrically connected to the first first node N11, and the drain of T11 is electrically connected to the second third node N23;

[0420] A first end of C11 is electrically connected to a first first node N11, a second end of C11 is electrically connected to a first fourth node N14, a first end of the second capacitor C2 is electrically connected to the first fourth node N14, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0421] The gate of T12 is electrically connected to the second control terminal GT, the source of T12 is electrically connected to the first data line DT1, and the drain of T12 is electrically connected to the first fourth node N14;

[0422] The gate of T13 is electrically connected to the first light emitting control terminal EM1, the source of T13 is electrically connected to the power supply voltage terminal VDD, and the drain of T13 is electrically connected to the first second node N12;

[0423] The gate of T14 is electrically connected to the second light emitting control terminal EM2, the source of T14 is electrically connected to the first third node N13, the drain of T14 is electrically connected to the anode of O11; the cathode of O11 is electrically connected to the low voltage terminal VSS;

[0424] The gate of T16 is electrically connected to the first reset control terminal R1, the source of T16 is electrically connected to the first initial voltage terminal I1, and the drain of T16 is electrically connected to the first first node N11; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0425] The gate of T17 is electrically connected to the second reset control terminal R2, the source of T17 is electrically connected to the second initial voltage terminal I2, and the drain of T17 is electrically connected to the anode of O11;

[0426] The gate of T18 is electrically connected to the second reset control terminal R2, the source of T18 is electrically connected to the third initial voltage terminal I3, and the drain of T18 is electrically connected to the first second node N12; the third initial voltage terminal I3 is used to provide a third initial voltage Vinit3;

[0427] The gate of T19 is electrically connected to the first control terminal GT1, the source of T19 is electrically connected to the fourth initial voltage terminal I4, and the drain of T19 is electrically connected to the first fourth node N14;

[0428] The gate of T02 is electrically connected to the second first node N21, the source of T02 is electrically connected to the second second node N22, and the drain of T02 is electrically connected to the second third node N23;

[0429] The gate of T21 is electrically connected to the first control terminal GT1, the source of T21 is electrically connected to the second first node N21, and the drain of T21 is electrically connected to the first third node N13;

[0430] A first end of C21 is electrically connected to the second first node N21, a second end of C21 is electrically connected to the second fourth node N24, a first end of C22 is electrically connected to the second fourth node N24, and a second end of C22 is electrically connected to the power supply voltage terminal VDD;

[0431] The gate of T22 is electrically connected to the second control terminal GT, the source of T22 is electrically connected to the second data line DT2, and the drain of T22 is electrically connected to the second fourth node N24;

[0432] The gate of T23 is electrically connected to the first light emitting control terminal EM1, the source of T23 is electrically connected to the power supply voltage terminal VDD, and the drain of T23 is electrically connected to the second second node N22;

[0433] The gate of T24 is electrically connected to the second light emitting control terminal EM2, the source of T24 is electrically connected to the second third node N23, the drain of T24 is electrically connected to the anode of O12; the cathode of O12 is electrically connected to the low voltage terminal VSS;

[0434] The gate of T26 is electrically connected to the first reset control terminal R1, the source of T26 is electrically connected to the first initial voltage terminal I1, and the drain of T26 is electrically connected to the second first node N21; the first initial voltage terminal I1 is used to provide a first initial voltage Vinit1;

[0435] The gate of T27 is electrically connected to the second reset control terminal R2, the source of T27 is electrically connected to the second initial voltage terminal I2, and the drain of T27 is electrically connected to the anode of O12; the second initial voltage terminal I2 is used to provide a second initial voltage Vinit2;

[0436] The gate of T28 is electrically connected to the second reset control terminal R2, the source of T28 is electrically connected to the third initial voltage terminal I3, and the drain of T28 is electrically connected to the second second node N22; the third initial voltage terminal I3 is used to provide a third initial voltage Vinit3;

[0437] The gate of T29 is electrically connected to the first control terminal GT1, the source of T29 is electrically connected to the fourth initial voltage terminal I4, and the drain of T29 is electrically connected to the second fourth node N24; the fourth initial voltage terminal provides a fourth initial voltage Vinit4.

[0438] In at least one embodiment shown in FIG. 31 , all transistors are p-type transistors, but the present invention is not limited thereto.

[0439] In at least one embodiment shown in FIG. 31 , the compensation control terminal is the first control terminal GT1 , the write control terminal is the second control terminal GT, the third reset control terminal is the second reset control terminal R2 , and the fourth reset control terminal is the first control terminal GT1 .

[0440] In at least one embodiment shown in FIG. 31 , Vinit1, Vinit2, and Vinit4 can be greater than or equal to -5V and less than or equal to 0V, and Vinit3 can be greater than or equal to 0V and less than or equal to 8V. For example, Vinit1 and Vinit4 can be -4V, Vinit2 can be -3V, and Vinit3 can be 6.8V, but the present invention is not limited thereto.

[0441] As shown in FIG32 , when at least one embodiment shown in FIG31 is in operation, the display cycle includes a first stage S01 , a second stage S02 , a data writing stage S0 , a third stage S03 and a light emitting stage S3 ;

[0442] In the first phase S01, EM1 and EM2 provide a high voltage signal, R1 provides a low voltage signal, GT, GT1, R4 and R2 provide a high voltage signal, T16 and T26 are turned on, and I1 provides a first initial voltage Vinit1 to N11 and N21;

[0443] In the second phase S02, EM1 provides a low voltage signal, EM2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, GT1 provides a low voltage signal, R2 provides a high voltage signal, T13 and T23 are turned on, T19 and T29 are turned on, and I4 provides a fourth initial voltage Vinit4 to N14 and N24; T11 and T21 are turned on, N11 and N23 are connected, and N21 and N13 are connected; the voltage of N11 becomes Vdd+Vth1, and the voltage of N21 becomes Vdd+Vth2; Vdd is the voltage value of the power supply voltage signal provided by VDD, Vth1 is the threshold voltage of T01, and Vth2 is the threshold voltage of T02;

[0444] In the data writing phase S0, EM1 and EM2 provide a high voltage signal, R1 provides a high voltage signal, GT provides a low voltage signal, GT1 provides a high voltage signal, R4 provides a high voltage signal, R2 provides a high voltage signal, T12 and T22 are turned on, DT1 provides a first data voltage Vdata1 to N14, and DT2 provides a second data voltage Vdata2 to N24; the potential of N11 becomes Vdd+Vth1+(Vdata1-Vinit4)×C11z / Cn11z, T01 is turned off, the potential of N21 becomes Vdd+Vth2+(Vdata2-Vinit4)×C21z / Cn21z, and T02 is turned off; wherein C11z is the capacitance value of C11, C21z is the capacitance value of C21, Cn11z is the total capacitance value at N11, and Cn21z is the total capacitance value at N21;

[0445] In the third stage S03, EM1 and EM2 provide high voltage signals, R1 provides a high voltage signal, GT provides a high voltage signal, R2 provides a low voltage signal, GT1 provides a high voltage signal, T18 and T28 are turned on, T17 and T27 are turned on, I2 provides a second initial voltage Vinit2 to the anodes of O11 and O12 to clear the residual charge on the anodes of O11 and O12; I3 provides a third initial voltage Vinit3 to N12 and N22 to improve the hysteresis of T01 and T02;

[0446] In the light-emitting stage S3, EM1 and EM2 provide low voltage signals, T13 and T14 are turned on, T01 drives O11 to emit light, T23 and T24 are turned on, and T02 drives O12 to emit light.

[0447] The display panel described in at least one embodiment of the present disclosure includes multiple rows and columns of the above-mentioned pixel circuits.

[0448] In at least one embodiment of the present disclosure, the pixel circuit and the compensation pixel circuit are located in the same row and are separated by N pixel circuits;

[0449] N is a positive integer less than or equal to a number threshold, and the number threshold is a positive integer.

[0450] In at least one embodiment of the present disclosure, the pixel circuit and the compensation pixel circuit are located in the same row and are adjacent to each other.

[0451] The display panel according to at least one embodiment of the present disclosure includes a first pixel circuit and a second pixel circuit; the first compensation node in the first pixel circuit is a first third node, the first compensation node in the second pixel circuit is a second third node, the second compensation node in the first pixel circuit is the second first node; and the second compensation node in the second pixel circuit is the first first node.

[0452] The first pixel circuit includes a first on-off control circuit and a first compensation control circuit, and the second pixel circuit includes a second on-off control circuit and a second compensation control circuit;

[0453] The first on-off control circuit is electrically connected to the on-off control terminal, the first first node and the first control node respectively, and is used to control the connection between the first first node and the first control node under the control of the on-off control signal provided by the on-off control terminal;

[0454] The first on-off control circuit is electrically connected to the on-off control terminal, the second first node, and the second control node, respectively, and is configured to control the connection between the second first node and the second control node under the control of the on-off control signal;

[0455] The first compensation control circuit is electrically connected to the compensation control terminal, the first third node, and the second control node, respectively, and is configured to control the communication between the first third node and the second control node under the control of a compensation control signal provided by the compensation control terminal;

[0456] The second compensation control circuit is electrically connected to the compensation control terminal, the second third node and the first control node respectively, and is used to control the communication between the second third node and the first control node under the control of the compensation control signal;

[0457] The first third node is the third node in the first pixel circuit, the second third node is the third node in the second pixel circuit, the first first node is the first node in the first pixel circuit, and the second first node is the first node in the second pixel circuit.

[0458] In a specific implementation, when the first pixel circuit includes a first on-off control circuit and a first compensation control circuit, and the second pixel circuit includes a second on-off control circuit and a second compensation control circuit, the first compensation control circuit can control the connection between the first third node and the second control node under the control of the compensation control signal; the second compensation control circuit can control the connection between the second third node and the first control node under the control of the compensation control signal.

[0459] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0460] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, applied to a display panel, comprising a light-emitting element, a driving circuit, and a compensation control circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the light-emitting element via a third node, and the driving circuit is configured to generate a driving current for driving the light-emitting element under the control of the potential of the first node; The compensation control circuit is electrically connected to the compensation control terminal; The compensation control circuit is also electrically connected to the first compensation node and the second compensation node respectively, and is used to control the communication between the first compensation node and the second compensation node under the control of the compensation control signal provided by the compensation control terminal; The second compensation node is a node in a compensation pixel circuit; the compensation pixel circuit is another pixel circuit in the display panel.

2. The pixel circuit according to claim 1, wherein: The first compensation node is the third node, and the second compensation node is the first node in the compensation pixel circuit.

3. The pixel circuit according to claim 1, wherein: The first compensation node is the first node, and the second compensation node is the third node in the compensation pixel circuit.

4. The pixel circuit according to claim 2, wherein: Also includes a data writing circuit and a first energy storage circuit; The data writing circuit is electrically connected to the write control terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the write control signal provided by the write control terminal; The first energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

5. The pixel circuit according to claim 3, wherein: Also includes a data writing circuit, a first energy storage circuit and a second energy storage circuit; A first end of a first energy tank circuit is electrically connected to the first node, a second end of the first energy tank circuit is electrically connected to a fourth node, a first end of the second energy tank circuit is electrically connected to the fourth node, a second end of the second energy tank circuit is electrically connected to a DC voltage terminal, and the first energy tank circuit and the second energy tank circuit are configured to store electrical energy; The data writing circuit is electrically connected to the writing control terminal, the data line and the fourth node respectively, and is used to write the data voltage provided by the data line into the fourth node under the control of the writing control signal provided by the writing control terminal.

6. The pixel circuit according to any one of claims 1 to 5, wherein: Also includes a first light emitting control circuit and a second light emitting control circuit; The first light emitting control circuit is electrically connected to the first light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light emitting control signal provided by the first light emitting control terminal; The third node is electrically connected to the first electrode of the light emitting element through the second light emitting control circuit; The second light emitting control circuit is electrically connected to the second light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is used to control the third node under the control of the second light emitting control signal provided by the second light emitting control terminal. The node is connected to the first electrode of the light emitting element; The second electrode of the light emitting element is electrically connected to the first voltage end.

7. The pixel circuit according to claim 1, wherein: Also includes an on-off control circuit; The on-off control circuit is electrically connected to the on-off control terminal, the first node and the control node respectively, and is used to control the connection between the first node and the control node under the control of the on-off control signal provided by the on-off control terminal; The first compensation node is the third node, and the second compensation node is a control node in the compensation pixel circuit.

8. The pixel circuit according to any one of claims 1 to 5, wherein: Also included is a first initialization circuit; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

9. The pixel circuit according to claim 7, wherein: Also included is a first initialization circuit; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the control node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of a first reset control signal provided by the first reset control terminal.

10. The pixel circuit according to any one of claims 1 to 5, wherein: Also included is a first initialization circuit; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset control terminal.

11. The pixel circuit according to claim 6, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal.

12. The pixel circuit according to any one of claims 1 to 5, wherein: Also included is a third initialization circuit; The third initialization circuit is electrically connected to the third reset control terminal and the third initial voltage terminal respectively, and is also electrically connected to the second node or the third node, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node or the third node under the control of the third reset control signal provided by the third reset control terminal.

13. The pixel circuit according to claim 5, wherein: Also comprising a fourth initialization circuit; The fourth initialization circuit is electrically connected to the fourth reset control terminal, the fourth initial voltage terminal and the fourth node respectively, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal into the fourth node under the control of a fourth reset control signal provided by the fourth reset control terminal.

14. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor, and the compensation control circuit includes a first transistor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The gate of the first transistor is electrically connected to the compensation control terminal, the first electrode of the first transistor is electrically connected to the first compensation node, and the second electrode of the first transistor is electrically connected to the second compensation node.

15. The pixel circuit according to claim 4, wherein: The data writing circuit includes a second transistor, and the first energy storage circuit includes a first capacitor; A first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to a power supply voltage terminal; A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the second node.

16. The pixel circuit according to claim 5, wherein: The first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, and the data writing circuit includes a second transistor; A first end of a first capacitor is electrically connected to the first node, a second end of the first capacitor is electrically connected to a fourth node, a first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to a power supply voltage terminal; A gate of the second transistor is electrically connected to the write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the fourth node.

17. The pixel circuit according to claim 6, wherein: The first light emitting control circuit includes a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the first light emitting control terminal, the first electrode of the third transistor is electrically connected to the power supply voltage terminal, and the second electrode of the third transistor is electrically connected to the second node; The gate of the fourth transistor is electrically connected to the second light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the third node, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light emitting element.

18. The pixel circuit according to claim 7, wherein: The on-off control circuit includes a fifth transistor; The gate of the fifth transistor is electrically connected to the on / off control terminal, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the control node.

19. The pixel circuit according to claim 8, wherein: The first initialization circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first node.

20. The pixel circuit according to claim 9, wherein: The first initialization circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the control node.

21. The pixel circuit according to claim 10, wherein: The first initialization circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected to the first reset control terminal, a first electrode of the sixth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the third node.

22. The pixel circuit according to claim 11, wherein: The second initialization circuit includes a seventh transistor; The gate of the seventh transistor is electrically connected to the second reset control terminal, the first electrode of the seventh transistor is electrically connected to the second initial voltage terminal, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

23. The pixel circuit according to claim 12, wherein: The third initialization circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the third reset control terminal, the first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and the second electrode of the eighth transistor is electrically connected to the second node or the third node.

24. The pixel circuit according to claim 12, wherein: The fourth initialization circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the fourth reset control terminal, the first electrode of the ninth transistor is electrically connected to the fourth initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the fourth node.

25. A display panel comprising a plurality of rows and columns of pixel circuits according to any one of claims 1 to 9.

26. The display panel according to claim 25, wherein: The pixel circuit and the compensation pixel circuit are located in the same row and are electrically connected to a first node of another pixel circuit that is N pixel circuits apart; N is a positive integer less than or equal to a number threshold, and the number threshold is a positive integer.

27. The display panel according to claim 25, wherein: The pixel circuit and the compensation pixel circuit are located in the same row and are adjacent to each other.

28. The display panel according to claim 25, wherein: including a first pixel circuit and a second pixel circuit; The first compensation node in the first pixel circuit is the first third node, the first compensation node in the second pixel circuit is the second third node, and the second compensation node in the first pixel circuit is the second first node; The second compensation node in the second pixel circuit is the first first node; The first pixel circuit includes a first on-off control circuit and a first compensation control circuit, and the second pixel circuit includes a second on-off control circuit and a second compensation control circuit; The first on-off control circuit is electrically connected to the on-off control terminal, the first first node and the first control node respectively, and is used to control the connection between the first first node and the first control node under the control of the on-off control signal provided by the on-off control terminal; The first on-off control circuit is electrically connected to the on-off control terminal, the second first node, and the second control node, respectively, and is configured to control the connection between the second first node and the second control node under the control of the on-off control signal; The first compensation control circuit is electrically connected to the compensation control terminal, the first third node, and the second control node, respectively, and is configured to control the communication between the first third node and the second control node under the control of a compensation control signal provided by the compensation control terminal; The second compensation control circuit is electrically connected to the compensation control terminal, the second third node and the first control node respectively. connection, for controlling the second third node to be connected to the first control node under the control of the compensation control signal; The first third node is the third node in the first pixel circuit, the second third node is the third node in the second pixel circuit, the first first node is the first node in the first pixel circuit, and the second first node is the first node in the second pixel circuit.

29. A display device comprising the display panel according to any one of claims 25 to 28.

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