Method and circuit for measuring temperature, improving amplitude, and alleviating phase noise of phase-locked loop

Abstract

The present invention relates to auxiliary technology of phase-locked loops, and disclosed is a method for measuring the temperature, improving the amplitude, and alleviating phase noise of a phase-locked loop. The present solution is provided to address the problem in the prior art of a tuning voltage deviating from a normal interval due to a temperature change. When the tuning voltage is stable, the effective width-to-length ratio of a cross-coupled pair in a VCO is adjusted on the basis of a relationship limit between the tuning voltage and a tuning interval. The advantages are that the temperature change can be measured on the basis of a change in the tuning voltage, and the effective width-to-length ratio at which the cross-coupled pair in the VCO is connected is changed in stages on the basis of the amplitude of the temperature change, so as to improve the amplitude and alleviate phase noise.

Description

A method and circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise Technical Field

[0001] The present invention relates to a phase-locked loop auxiliary technology, and in particular to a method and circuit for detecting the temperature of a phase-locked loop and improving the amplitude and phase noise. Background Art

[0002] Clock signals are widely used in various circuits. For digital circuits, whether synchronous or asynchronous, the correct execution of digital information processing, including calculations, transmission, and storage, requires a stable clock. A PLL (Phase Locked Loop) circuit is specifically designed to generate a new clock signal that is phase-synchronized with the input signal. Figure 1 shows the commonly used charge pump PLL circuit architecture. The input reference frequency is compared with the phase difference by a PFD (Phase Frequency Detector). A switch (CP) charges and discharges the LPF (Low Pass Filter) to output a tuning voltage (Vcont). This tuning voltage (Vcont) is used to adjust the resonant frequency of the VCO (Voltage Controlled Oscillator). The resonant signal is fed as the PLL output and then divided by a frequency divider before being fed together with the reference frequency into the PFD.

[0003] The purity of a PLL's output clock signal is characterized by clock jitter, which is further divided into deterministic spurious signals and random phase noise. High-speed applications place stringent requirements on clock jitter. For example, in ADC analog front-ends, where the signal frequency is high, ultra-low jitter is essential (A. Jerng and CG Sodini, "The impact of device type and sizing on phase noise mechanisms," in IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 360-369, Feb. 2005, doi: 10.1109 / JSSC.2004.841035).

[0004] The basic structure of the LC-VCO based on LC-controlled resonance is shown in Figure 2. To ensure oscillation, the equivalent parallel resistance R P Need to meet: R P =2 / gm. Where gm is the transconductance.

[0005] The size selection of the cross-coupling M0P / M0N pair is related to the phase noise and amplitude of the oscillator. When the width-to-length ratio of the cross-coupling M0P / M0N pair is too small, on the one hand, the drain-source voltage drop of the cross-coupling M0P / M0N pair is large, limiting the output amplitude; on the other hand, it cannot provide a sufficiently large gm, which may cause oscillation failure. When the width-to-length ratio of the cross-coupling M0P / M0N pair is too large, the output amplitude is too large, causing the cross-coupling M0P / M0N pair to enter the linear region for part of the oscillation period, up-converting the flicker noise and deteriorating the phase noise [1].

[0006] The LC-VCO's oscillation characteristics are affected by temperature. As the ambient temperature rises, the oscillation frequency increases, the resonant cavity Q deteriorates, the equivalent parallel resistance Rp decreases, and phase noise deteriorates. Compared to normal temperature, the cross-coupled M0P / M0N pair must provide a larger gm to ensure VCO startup, meaning a larger width-to-length ratio. As the ambient temperature decreases, the oscillation frequency decreases, the resonant cavity Q improves, the equivalent parallel resistance Rp increases, and the amplitude increases, causing the cross-coupled M0P / M0N pair to fall into the linear region, deteriorating phase noise. In this case, the width-to-length ratio of the cross-coupled M0P / M0N pair should be reduced (Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. Cambridge: Cambridge University Press, 2020).

[0007] When the phase-locked loop is locked, the VCO's input tuning voltage is within the normal tuning range. When the external temperature rises, the VCO's oscillation frequency increases, and the tuning voltage decreases, thereby lowering the oscillation frequency. When the external temperature drops, the VCO's oscillation frequency decreases, and the tuning voltage increases, thereby raising the oscillation frequency. If the temperature fluctuates significantly, the oscillation frequency fluctuates greatly, and the tuning voltage deviates from the normal range. Summary of the Invention

[0008] The present invention aims to provide a method for detecting temperature of a phase-locked loop and improving amplitude and phase noise, so as to solve the problems existing in the above-mentioned prior art.

[0009] The method for detecting temperature of a phase-locked loop and improving amplitude and phase noise described in the present invention adjusts the effective width-to-length ratio of a cross-coupling pair in a VCO according to the relationship between the tuning voltage and the tuning interval when the tuning voltage is stable.

[0010] The tuning voltage stability means that the change of the tuning voltage after a certain delay is smaller than the reference voltage.

[0011] When the tuning voltage is greater than the upper limit of the tuning interval, the effective width-to-length ratio of the cross-coupling pair is reduced; when the tuning voltage is less than the lower limit of the tuning interval, the effective width-to-length ratio of the cross-coupling pair is increased.

[0012] The tuning interval is provided with a first upper limit and a second upper limit; the first upper limit is smaller than the second upper limit, and the effective width-to-length ratio of the cross-coupling pair is correspondingly reduced in two steps.

[0013] The tuning interval is provided with a first lower limit and a second lower limit; the first lower limit is greater than the second lower limit, and the effective width-to-length ratio of the cross-coupling pair is correspondingly increased in two steps.

[0014] The circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise described in the present invention has the following structure:

[0015] The tuning voltage is respectively connected to the first comparator inverting input terminal, the second comparator non-inverting input terminal, the third comparator inverting input terminal, the fourth comparator non-inverting input terminal, the delay unit input terminal, and the subtraction unit inverting input terminal;

[0016] The output of the delay unit is connected to the non-inverting input of the subtraction unit; the output of the subtraction unit is connected to the inverting input of the fifth comparator, and the non-inverting input of the fifth comparator is connected to the reference voltage;

[0017] The non-inverting input terminal of the first comparator is connected to the first lower limit voltage, and the output terminal of the first comparator is connected to the first input terminal of the first AND gate;

[0018] The inverting input terminal of the second comparator is connected to the first upper limit voltage, and the output terminal of the second comparator is connected to the first input terminal of the second AND gate;

[0019] The non-inverting input terminal of the third comparator is connected to the second lower limit voltage, and the output terminal of the third comparator is connected to the first input terminal of the third AND gate;

[0020] The inverting input terminal of the fourth comparator is connected to the second upper limit voltage, and the output terminal of the fourth comparator is connected to the first input terminal of the fourth AND gate;

[0021] The output terminal of the fifth comparator is respectively connected to the second input terminal of the first AND gate, the second input terminal of the second AND gate, the third input terminal of the third AND gate, and the fourth input terminal of the fourth AND gate;

[0022] The output terminal of the first AND gate outputs a first control signal;

[0023] The second AND gate output terminal outputs a second control signal;

[0024] The output terminal of the third AND gate outputs a third control signal;

[0025] The output terminal of the fourth AND gate outputs a fourth control signal;

[0026] The drain of the first transistor, the drain of the second transistor, the drain of the third transistor, and the drain of the fourth transistor are respectively short-circuited with the drain of the second output transistor in the VCO;

[0027] The source of the first transistor, the source of the second transistor, the source of the third transistor, and the source of the fourth transistor are respectively short-circuited with the source of the second output transistor in the VCO;

[0028] The drain of the fifth transistor, the drain of the sixth transistor, the drain of the seventh transistor, and the drain of the eighth transistor are respectively short-circuited with the drain of the first output transistor in the VCO;

[0029] The source of the fifth transistor, the source of the sixth transistor, the source of the seventh transistor, and the source of the eighth transistor are respectively short-circuited with the source of the first output transistor in the VCO;

[0030] The first transistor and the fifth transistor are turned on when the first control signal is low, the second transistor and the sixth transistor are turned on when the third control signal is low, the third transistor and the seventh transistor are turned on when the second control signal is high, and the fourth transistor and the eighth transistor are turned on when the fourth control signal is high;

[0031] The second upper limit voltage is greater than the first upper limit voltage, greater than the first lower limit voltage, and greater than the second lower limit voltage.

[0032] The source of the ninth transistor, the source of the tenth transistor, the source of the eleventh transistor, and the source of the twelfth transistor are respectively short-circuited with the drain of the first output transistor in the VCO;

[0033] The source of the thirteenth transistor, the source of the fourteenth transistor, the source of the fifteenth transistor, and the source of the sixteenth transistor are respectively short-circuited with the drain of the second output transistor in the VCO;

[0034] The source of the seventeenth transistor, the source of the eighteenth transistor, the source of the nineteenth transistor, the source of the twentieth transistor, the source of the twenty-first transistor, the source of the twenty-second transistor, the source of the twenty-third transistor, and the source of the twenty-fourth transistor are grounded respectively;

[0035] The drain of the ninth transistor and the drain of the seventeenth transistor are short-circuited with the gate of the first transistor respectively;

[0036] The drain of the tenth transistor and the drain of the eighteenth transistor are short-circuited with the gate of the second transistor respectively;

[0037] The drain of the eleventh transistor and the drain of the nineteenth transistor are respectively short-circuited with the gate of the third transistor;

[0038] The drain of the twelfth transistor and the drain of the twentieth transistor are respectively short-circuited with the gate of the fourth transistor;

[0039] The drain of the thirteenth transistor and the drain of the twenty-first transistor are respectively short-circuited with the gate of the fifth transistor;

[0040] The drain of the fourteenth transistor and the drain of the twenty-second transistor are short-circuited with the gate of the sixth transistor respectively;

[0041] The drain of the fifteenth transistor and the drain of the twenty-third transistor are respectively short-circuited with the gate of the seventh transistor;

[0042] The drain of the sixteenth transistor and the drain of the twenty-fourth transistor are short-circuited with the gate of the eighth transistor respectively;

[0043] The gates of the ninth transistor and the thirteenth transistor are respectively connected to the first control signal, and the gates of the seventeenth transistor and the twenty-first transistor are respectively connected to the inverse signal of the first control signal;

[0044] The gate of the nineteenth transistor and the gate of the twenty-third transistor are respectively connected to the second control signal, and the gate of the eleventh transistor and the gate of the fifteenth transistor are respectively connected to the inverse signal of the second control signal;

[0045] The gates of the tenth transistor and the fourteenth transistor are connected to the third control signal respectively, and the gates of the eighteenth transistor and the twenty-second transistor are connected to the inverse signal of the third control signal respectively;

[0046] The gate of the twentieth transistor and the gate of the twenty-fourth transistor are respectively connected to the fourth control signal, and the gate of the twelfth transistor and the gate of the sixteenth transistor are respectively connected to the inverse signal of the fourth control signal.

[0047] The effective width-to-length ratios of the first transistor, the third transistor, the fifth transistor, and the seventh transistor are respectively 1 / 4 of the first output transistor, and the effective width-to-length ratios of the first output transistor and the second output transistor are equal.

[0048] The effective width-to-length ratios of the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are respectively 1 / 2 of that of the first output transistor.

[0049] The method for detecting temperature in a phase-locked loop and improving amplitude and phase noise described in the present invention has the advantages of being able to detect temperature changes based on changes in tuning voltage, and of changing the width-to-length ratio of the VCO cross-coupling pair in stages according to the magnitude of the temperature change to improve amplitude and phase noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of a principle framework of a phase-locked loop in the prior art.

[0051] FIG2 is a schematic diagram of the structure of a VCO in the prior art.

[0052] FIG3 is a schematic flow chart of the method of the present invention.

[0053] FIG4 is a schematic diagram of the structure of the detection control module of the circuit in the present invention.

[0054] FIG5 is a schematic diagram of the structure of the temperature compensation module of the circuit of the present invention.

[0055] Reference numerals:

[0056] M0N-first output transistor, M0P-second output transistor;

[0057] M01 to M24 - first to twenty-fourth transistors;

[0058] COM1 to COM5 - first to fifth comparators;

[0059] AND1 to AND4 - first to fourth AND gates;

[0060] S1 to S4 - first to fourth control signals;

[0061] VH0-first upper limit voltage, VH1-second upper limit voltage;

[0062] VL0-first lower limit voltage, VL1-second lower limit voltage;

[0063] VOP-positive output voltage, VON-negative output voltage, Vcont-tuning voltage, Vref-reference voltage. Modes for Carrying Out the Invention

[0064] As shown in Figure 3, the present invention discloses a method for detecting temperature in a phase-locked loop (PLL) and improving amplitude and phase noise. When the tuning voltage Vcont is stable, the effective width-to-length ratio of the cross-coupling pairs in the VCO is adjusted based on the relationship between the tuning voltage Vcont and the tuning range. Stable tuning voltage Vcont refers to a situation where the change in tuning voltage Vcont after a certain delay is less than the reference voltage Vref. Specifically, when the tuning voltage Vcont is greater than the upper limit of the tuning range, the effective width-to-length ratio of the cross-coupling pairs is reduced. When the tuning voltage Vcont is less than the lower limit of the tuning range, the effective width-to-length ratio of the cross-coupling pairs is increased. The tuning range has a first upper limit and a second upper limit. If the first upper limit is less than the second upper limit, the effective width-to-length ratio of the cross-coupling pairs is correspondingly reduced in two steps. The tuning range has a first lower limit and a second lower limit. If the first lower limit is less than the second lower limit, the effective width-to-length ratio of the cross-coupling pairs is correspondingly increased in two steps.

[0065] The circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise described in the present invention can be used to implement the method, as shown in Figures 4 and 5. The specific structure is as follows:

[0066] The tuning voltage Vcont is respectively connected to the inverting input terminals of the first comparator COM1, the second comparator COM2, the third comparator COM3, the fourth comparator COM4, ​​the delay unit input terminal, and the subtraction unit inverting input terminal.

[0067] The output of the delay unit is connected to the non-inverting input of the subtraction unit. The output of the subtraction unit is connected to the inverting input of the fifth comparator COM5, and the non-inverting input of the fifth comparator COM5 is connected to the reference voltage Vref.

[0068] The non-inverting input terminal of the first comparator COM1 is connected to the first lower limit voltage VL0 , and the output terminal of the first comparator COM1 is connected to the first input terminal of the first AND gate AND1 .

[0069] The inverting input terminal of the second comparator COM2 is connected to the first upper limit voltage VH0 , and the output terminal of the second comparator COM2 is connected to the first input terminal of the second AND gate AND2 .

[0070] The non-inverting input terminal of the third comparator COM3 is connected to the second lower limit voltage VL1 , and the output terminal of the third comparator COM3 is connected to the first input terminal of the third AND gate AND3 .

[0071] The inverting input terminal of the fourth comparator COM4 is connected to the second upper limit voltage VH1 , and the output terminal of the fourth comparator COM4 is connected to the first input terminal of the fourth AND gate AND4 .

[0072] The output terminal of the fifth comparator COM5 is respectively connected to the second input terminal of the first AND gate AND1, the second input terminal of the second AND gate AND2, the third input terminal of the third AND gate AND3, and the fourth input terminal of the fourth AND gate AND4.

[0073] The output terminal of the first AND gate AND1 outputs a first control signal S1.

[0074] The output terminal of the second AND gate AND2 outputs a second control signal S2.

[0075] The output terminal of the third AND gate AND3 outputs a third control signal S3.

[0076] The output terminal of the fourth AND gate AND4 outputs a fourth control signal S4.

[0077] The drain of the first transistor M01 , the drain of the second transistor M02 , the drain of the third transistor M03 , and the drain of the fourth transistor M04 are short-circuited with the drain of the second output transistor M0P in the VCO respectively.

[0078] The source of the first transistor M01, the source of the second transistor M02, the source of the third transistor M03, and the source of the fourth transistor M04 are short-circuited with the source of the second output transistor M0P in the VCO respectively.

[0079] The drain of the fifth transistor M05 , the drain of the sixth transistor M06 , the drain of the seventh transistor M07 , and the drain of the eighth transistor M08 are respectively short-circuited with the drain of the first output transistor M0N in the VCO.

[0080] The source of the fifth transistor M05 , the source of the sixth transistor M06 , the source of the seventh transistor M07 , and the source of the eighth transistor M08 are short-circuited with the source of the first output transistor M0N in the VCO respectively.

[0081] The sources of the first transistor M01 to the eighth transistor M08 are all short-connected to the tail current source.

[0082] The first transistor M01 and the fifth transistor M05 are turned on when the first control signal S1 is low, the second transistor M02 and the sixth transistor M06 are turned on when the third control signal S3 is low, the third transistor M03 and the seventh transistor M07 are turned on when the second control signal S2 is high, and the fourth transistor M04 and the eighth transistor M08 are turned on when the fourth control signal S4 is high.

[0083] The second upper limit voltage VH1 is greater than the first upper limit voltage VH0 , greater than the first lower limit voltage VL0 , and greater than the second lower limit voltage VL1 .

[0084] Specifically, this embodiment also provides a signal access structure:

[0085] The source of the ninth transistor M09 , the source of the tenth transistor M10 , the source of the eleventh transistor M11 , and the source of the twelfth transistor M12 are short-circuited with the drain of the first output transistor M0N in the VCO respectively.

[0086] The source of the thirteenth transistor M13, the source of the fourteenth transistor M14, the source of the fifteenth transistor M15, and the source of the sixteenth transistor M16 are short-circuited with the drain of the second output transistor M0P in the VCO respectively.

[0087] The source of the seventeenth transistor M17 , the source of the eighteenth transistor M18 , the source of the nineteenth transistor M19 , the source of the twentieth transistor M20 , the source of the twenty-first transistor M21 , the source of the twenty-second transistor M22 , the source of the twenty-third transistor M23 , and the source of the twenty-fourth transistor M24 are grounded respectively.

[0088] The drain of the ninth transistor M09 and the drain of the seventeenth transistor M17 are short-circuited with the gate of the first transistor M01 , respectively.

[0089] The drain of the tenth transistor M10 and the drain of the eighteenth transistor M18 are short-circuited with the gate of the second transistor M02 , respectively.

[0090] The drain of the eleventh transistor M11 and the drain of the nineteenth transistor M19 are short-circuited with the gate of the third transistor M03 , respectively.

[0091] The drain of the twelfth transistor M12 and the drain of the twentieth transistor M20 are short-circuited with the gate of the fourth transistor M04 respectively.

[0092] The drain of the thirteenth transistor M13 and the drain of the twenty-first transistor M21 are short-circuited with the gate of the fifth transistor M05 , respectively.

[0093] The drain of the fourteenth transistor M14 and the drain of the twenty-second transistor M22 are short-circuited with the gate of the sixth transistor M06 , respectively.

[0094] The drain of the fifteenth transistor M15 and the drain of the twenty-third transistor M23 are short-circuited with the gate of the seventh transistor M07 respectively.

[0095] The drain of the sixteenth transistor M16 and the drain of the twenty-fourth transistor M24 are short-circuited with the gate of the eighth transistor M08 respectively.

[0096] The gates of the ninth transistor M09 and the thirteenth transistor M13 are respectively connected to the first control signal S1 , and the gates of the seventeenth transistor M17 and the twenty-first transistor M21 are respectively connected to the inverse signal of the first control signal S1 .

[0097] The gates of the nineteenth transistor M19 and the twenty-third transistor M23 are respectively connected to the second control signal S2 , and the gates of the eleventh transistor M11 and the fifteenth transistor M15 are respectively connected to the inverse signal of the second control signal S2 .

[0098] The gates of the tenth transistor M10 and the fourteenth transistor M14 are connected to the third control signal S3 , respectively. The gates of the eighteenth transistor M18 and the twenty-second transistor M22 are connected to the inverse signal of the third control signal S3 , respectively.

[0099] The gates of the twentieth transistor M20 and the twenty-fourth transistor M24 are connected to the fourth control signal S4 , respectively. The gates of the twelfth transistor M12 and the sixteenth transistor M16 are connected to the inverse signal of the fourth control signal S4 , respectively.

[0100] Depending on the actual application scenario, those skilled in the art can reasonably adjust the width-to-length ratio of each transistor to achieve different width-to-length ratio adjustments. This embodiment provides a preferred ratio method: the effective width-to-length ratio of the first transistor M01, the third transistor M03, the fifth transistor M05, and the seventh transistor M07 is respectively 1 / 4 of the first output transistor M0N, and the effective width-to-length ratio of the first output transistor M0N and the second output transistor M0P is equal. The effective width-to-length ratio of the second transistor M02, the fourth transistor M04, the sixth transistor M06, and the eighth transistor M08 is respectively 1 / 2 of the first output transistor M0N.

[0101] A method for phase-locked loop temperature detection and improvement of amplitude and phase noise, and the circuit working principle are as follows:

[0102] First, determine whether the tuning voltage is stable. If so, determine whether it is within the normal range [VL, VH]. If it exceeds the upper limit VH, it is determined that the temperature has dropped. In this case, the cross-coupling tube size should be reduced to prevent deterioration of phase noise. If it is below the lower limit VL, it is determined that the temperature has risen, and the resonant cavity Q value has deteriorated. In this case, the cross-coupling tube size should be increased to increase the amplitude and ensure oscillation. Both the upper limit VH and the lower limit VL can be set to multiple levels to improve control accuracy. In this embodiment, both the upper and lower limits are set to two levels.

[0103] The specific implementation circuit of temperature detection is shown in FIG4 . On the one hand, it is necessary to determine whether the tuning voltage Vcont is stable, and on the other hand, it is necessary to determine whether the tuning voltage Vcont is within the normal tuning range [first lower limit voltage VL0 , first upper limit voltage VH0 ].

[0104] The stability of the tuning voltage Vcont is detected using a delay unit, a subtraction unit, and a fifth comparator COM5. Both the delay unit and the subtraction unit are functional modules of the prior art. The tuning voltage Vcont at the previous moment is subtracted from the next moment, and the subtraction result is then compared with the reference voltage Vref. If the value is less than the reference voltage Vref, the fifth comparator COM5 outputs a 1, indicating that the tuning voltage Vcont is stable and no longer changing. If the value is greater than the reference voltage Vref, the fifth comparator COM5 outputs a 0, indicating that the tuning voltage Vcont is still changing and requires waiting.

[0105] After the tuning voltage Vcont stabilizes, the first comparator COM1, the second comparator COM2, the third comparator COM3, and the fourth comparator COM4 compare the tuning voltage Vcont with the tuning voltage. If the tuning voltage Vcont is less than the first lower limit voltage VL0, the first comparator COM1 outputs a high level. If the tuning voltage Vcont is less than the second lower limit voltage VL1, the first comparator COM1 and the third comparator COM3 both output high levels. If the tuning voltage Vcont is greater than the first upper limit voltage VH0, the second comparator COM2 outputs a high level. If the tuning voltage Vcont is greater than the second upper limit voltage VH1, the second comparator COM2 and the fourth comparator COM4 both output high levels.

[0106] After logic processing through four AND gates, a first control signal S1, a second control signal S2, a third control signal S3, and a fourth control signal S4 are output respectively. The logical relationship of the outputs is shown in Table 1.

[0107] Table 1

[0108]

[0109] The array switch structure of the cross-coupled pairs in the VCO is shown in Figure 5. The first transistor M01, the second transistor M02, the fifth transistor M05, and the sixth transistor M06 are turned on at room temperature and turned off at low temperatures. The third transistor M03, the fourth transistor M04, the seventh transistor M07, and the eighth transistor M08 are turned off at room temperature and turned on at high temperatures.

[0110] This embodiment provides a specific effective width-to-length ratio relationship:

[0111] The effective width-to-length ratio of the first output transistor M0N and the second output transistor M0P is set to 4 unit width-to-length ratios. The effective width-to-length ratios of the first transistor M01, the third transistor M03, the fifth transistor M05, and the seventh transistor M07 are all 1 unit width-to-length ratio. The effective width-to-length ratios of the second transistor M02, the fourth transistor M04, the sixth transistor M06, and the eighth transistor M08 are all 2 unit width-to-length ratios. The first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4 are used to control the conduction and closing of the first transistor M01 to the eighth transistor M08 to achieve effective coupling connection or disconnection. The logical relationship and the change in the effective width-to-length ratio are shown in Table 2.

[0112] Table 2

[0113]

[0114] Technical effect verification:

[0115] The above circuit was designed using the SMIC 55nm process in Cadence Virtuoso. The simulation results are shown in Table 3. Compared to traditional fixed cross-coupled pairs, temperature-adjustable cross-coupled pair arrays optimize phase noise, increase amplitude, and ensure oscillation start. Phase noise is optimized at low temperatures of 0°C and -40°C, while amplitude is increased and oscillation start is guaranteed at high temperatures of 85°C and 125°C.

[0116]

[0117] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

Claims

1. A circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise, characterized in that: The structure is as follows: The tuning voltage (Vcont) is respectively connected to the inverting input terminal of the first comparator (COM1), the non-inverting input terminal of the second comparator (COM2), the inverting input terminal of the third comparator (COM3), the non-inverting input terminal of the fourth comparator (COM4), the input terminal of the delay unit, and the inverting input terminal of the subtraction unit; The output of the delay unit is connected to the non-inverting input of the subtraction unit; the output of the subtraction unit is connected to the inverting input of the fifth comparator (COM5), and the non-inverting input of the fifth comparator (COM5) is connected to the reference voltage (Vref); The non-inverting input terminal of the first comparator (COM1) is connected to the first lower limit voltage (VL0), and the output terminal of the first comparator (COM1) is connected to the first input terminal of the first AND gate (AND1); The inverting input terminal of the second comparator (COM2) is connected to the first upper limit voltage (VH0), and the output terminal of the second comparator (COM2) is connected to the first input terminal of the second AND gate (AND2); The non-inverting input terminal of the third comparator (COM3) is connected to the second lower limit voltage (VL1), and the output terminal of the third comparator (COM3) is connected to the first input terminal of the third AND gate (AND3); The inverting input terminal of the fourth comparator (COM4) is connected to the second upper limit voltage (VH1), and the output terminal of the fourth comparator (COM4) is connected to the first input terminal of the fourth AND gate (AND4); The output end of the fifth comparator (COM5) is respectively connected to the second input end of the first AND gate (AND1), the second input end of the second AND gate (AND2), the third input end of the third AND gate (AND3), and the fourth input end of the fourth AND gate (AND4); The output terminal of the first AND gate (AND1) outputs a first control signal (S1); The output terminal of the second AND gate (AND2) outputs a second control signal (S2); The output terminal of the third AND gate (AND3) outputs a third control signal (S3); The output terminal of the fourth AND gate (AND4) outputs a fourth control signal (S4); The drain of the first transistor (M01), the drain of the second transistor (M02), the drain of the third transistor (M03), and the drain of the fourth transistor (M04) are respectively short-circuited with the drain of the second output transistor (M0P) in the VCO; The source of the first transistor (M01), the source of the second transistor (M02), the source of the third transistor (M03), and the source of the fourth transistor (M04) are respectively short-circuited with the source of the second output transistor (M0P) in the VCO; The drain of the fifth transistor (M05), the drain of the sixth transistor (M06), the drain of the seventh transistor (M07), and the drain of the eighth transistor (M08) are respectively short-circuited with the drain of the first output transistor (M0N) in the VCO; The source of the fifth transistor (M05), the source of the sixth transistor (M06), the source of the seventh transistor (M07), and the source of the eighth transistor (M08) are respectively short-circuited with the source of the first output transistor (M0N) in the VCO; The first transistor (M01) and the fifth transistor (M05) are turned on when the first control signal (S1) is low, the second transistor (M02) and the sixth transistor (M06) are turned on when the third control signal (S3) is low, the third transistor (M03) and the seventh transistor (M07) are turned on when the second control signal (S2) is high, and the fourth transistor (M04) and the eighth transistor (M08) are turned on when the fourth control signal (S4) is high; The second upper limit voltage ( VH1 ) is greater than the first upper limit voltage ( VH0 ), greater than the first lower limit voltage ( VL0 ), and greater than the second lower limit voltage ( VL1 ).

2. A circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise according to claim 1, characterized in that: The source of the ninth transistor (M09), the source of the tenth transistor (M10), the source of the eleventh transistor (M11), and the source of the twelfth transistor (M12) are respectively short-circuited with the drain of the first output transistor (M0N) in the VCO; The source of the thirteenth transistor (M13), the source of the fourteenth transistor (M14), the source of the fifteenth transistor (M15), and the source of the sixteenth transistor (M16) are respectively short-circuited with the drain of the second output transistor (M0P) in the VCO; The source of the seventeenth transistor (M17), the source of the eighteenth transistor (M18), the source of the nineteenth transistor (M19), the source of the twentieth transistor (M20), the source of the twenty-first transistor (M21), the source of the twenty-second transistor (M22), the source of the twenty-third transistor (M23), and the source of the twenty-fourth transistor (M24) are grounded respectively; The drain of the ninth transistor (M09) and the drain of the seventeenth transistor (M17) are respectively short-circuited with the gate of the first transistor (M01); The drain of the tenth transistor (M10) and the drain of the eighteenth transistor (M18) are respectively short-circuited with the gate of the second transistor (M02); The drain of the eleventh transistor (M11) and the drain of the nineteenth transistor (M19) are respectively short-circuited with the gate of the third transistor (M03); The drain of the twelfth transistor (M12) and the drain of the twentieth transistor (M20) are short-circuited with the gate of the fourth transistor (M04) respectively; The drain of the thirteenth transistor (M13) and the drain of the twenty-first transistor (M21) are short-circuited with the gate of the fifth transistor (M05) respectively; The drain of the fourteenth transistor (M14) and the drain of the twenty-second transistor (M22) are short-circuited with the gate of the sixth transistor (M06) respectively; The drain of the fifteenth transistor (M15) and the drain of the twenty-third transistor (M23) are short-circuited with the gate of the seventh transistor (M07) respectively; The drain of the sixteenth transistor (M16) and the drain of the twenty-fourth transistor (M24) are short-circuited with the gate of the eighth transistor (M08) respectively; The gates of the ninth transistor (M09) and the thirteenth transistor (M13) are respectively connected to the first control signal (S1), and the gates of the seventeenth transistor (M17) and the twenty-first transistor (M21) are respectively connected to the inverse signal of the first control signal (S1); The gates of the nineteenth transistor (M19) and the twenty-third transistor (M23) are respectively connected to the second control signal (S2), and the gates of the eleventh transistor (M11) and the fifteenth transistor (M15) are respectively connected to the inverse signal of the second control signal (S2); The gate of the tenth transistor (M10) and the gate of the fourteenth transistor (M14) are respectively connected to the third control signal (S3), and the gate of the eighteenth transistor (M18) and the gate of the twenty-second transistor (M22) are respectively connected to the inverse signal of the third control signal (S3); The gates of the twentieth transistor (M20) and the twenty-fourth transistor (M24) are connected to the fourth control signal (S4), respectively. The gates of the twelfth transistor (M12) and the sixteenth transistor (M16) are connected to the inverse signal of the fourth control signal (S4).

3. A circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise according to claim 2, characterized in that: The effective width-to-length ratios of the first transistor (M01), the third transistor (M03), the fifth transistor (M05) and the seventh transistor (M07) are respectively 1 / 4 of the first output transistor (M0N), and the effective width-to-length ratios of the first output transistor (M0N) and the second output transistor (M0P) are equal.

4. A circuit for detecting temperature in a phase-locked loop and improving amplitude and phase noise according to claim 3, characterized in that: The effective width-to-length ratios of the second transistor (M02), the fourth transistor (M04), the sixth transistor (M06) and the eighth transistor (M08) are respectively 1 / 2 of that of the first output transistor (M0N).

5. A method for detecting temperature in a phase-locked loop and improving amplitude and phase noise, characterized in that: Based on the circuit according to any one of claims 1 to 4, when the tuning voltage (Vcont) is stable, the effective width-to-length ratio of the cross-coupling pairs in the VCO is adjusted according to the relationship between the tuning voltage (Vcont) and the tuning interval.

6. A method for detecting temperature in a phase-locked loop and improving amplitude and phase noise according to claim 5, characterized in that: The stability of the tuning voltage (Vcont) means that the change of the tuning voltage (Vcont) after a certain delay is less than the reference voltage (Vref).

7. A method for detecting temperature in a phase-locked loop and improving amplitude and phase noise according to claim 5, characterized in that: When the tuning voltage (Vcont) is greater than the upper limit of the tuning interval, the effective width-to-length ratio of the cross-coupling pair is reduced; when the tuning voltage (Vcont) is less than the lower limit of the tuning interval, the effective width-to-length ratio of the cross-coupling pair is increased.

8. A method for detecting temperature of a phase-locked loop and improving amplitude and phase noise according to claim 7, characterized in that: The tuning interval is provided with a first upper limit and a second upper limit; the first upper limit is smaller than the second upper limit, and the effective width-to-length ratio of the cross-coupling pair is correspondingly reduced in two steps.

9. The method for detecting temperature of a phase-locked loop and improving amplitude and phase noise according to claim 7, characterized in that: The tuning interval is provided with a first lower limit and a second lower limit; the first lower limit is greater than the second lower limit, and the effective width-to-length ratio of the cross-coupling pair is correspondingly increased in two steps.

Images