Solar cell and manufacturing method therefor, and photovoltaic module

Abstract

The present application discloses a solar cell and a manufacturing method therefor, and a photovoltaic module. The solar cell comprises: a semiconductor substrate, wherein the semiconductor substrate has a first surface and a second surface which are opposite; a doped semiconductor layer provided on the first surface of the semiconductor substrate; a dielectric layer arranged on the side of the doped semiconductor layer facing away from the semiconductor substrate, wherein the dielectric layer comprises a plurality of openings, the openings expose a partial area of the doped semiconductor layer, and a plurality of holes are formed in the side, facing away from the semiconductor substrate, of the part of the doped semiconductor layer exposed to the openings; and electrodes arranged on the side of the dielectric layer away from the semiconductor substrate, wherein the electrodes pass through the openings in the dielectric layer and are electrically connected to the doped semiconductor layer. The present application reduces the risk that the electrodes are separated from the doped semiconductor layer, and improves the structural reliability of the solar cell.

Description

Solar cell and manufacturing method thereof, and photovoltaic module

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410160240.1 filed on February 4, 2024, Chinese Patent Application No. 202510082596.2 filed on January 17, 2025, Chinese Patent Application No. 202510081229.0 filed on January 17, 2025, Chinese Patent Application No. 202510080848.8 filed on January 17, 2025, and Chinese Patent Application No. 202510081825.9 filed on January 17, 2025, and the entire contents of these Chinese patent applications are incorporated herein by reference. Technical Field

[0003] The present application relates to the technical field of solar cells, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0004] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells convert sunlight into electricity. Specifically, they utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0005] The traditional high-temperature metallization process involves sintering a high-temperature silver paste on a dielectric layer such as silicon nitride. The paste can penetrate the silicon nitride interface and form good metal contact with the underlying doped semiconductor layer. However, due to the high cost of high-temperature silver paste, the industry has been actively researching other metallization processes in recent years. Summary of the Invention

[0006] The present application aims to provide a solar cell and its manufacturing method, as well as a photovoltaic module, which are used to reduce the cost of the metallization process, increase the bonding force between the electrode and the doped semiconductor layer on the semiconductor substrate, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural stability of the solar cell.

[0007] According to a first aspect of the present application, a solar cell is provided, comprising: a semiconductor substrate having a first surface and a second surface opposite to each other; a doped semiconductor layer disposed on the first surface of the semiconductor substrate; a dielectric layer disposed on a side of the doped semiconductor layer facing away from the semiconductor substrate; the dielectric layer comprising a plurality of openings, the openings exposing a portion of the doped semiconductor layer; a plurality of holes formed on a side of the doped semiconductor layer exposed in the openings facing away from the semiconductor substrate; and an electrode disposed on a side of the dielectric layer facing away from the semiconductor substrate, the electrode passing through the opening in the dielectric layer and electrically connected to the doped semiconductor layer.

[0008] In a second aspect, a photovoltaic assembly is provided, comprising a plurality of cell strings, wherein the cell strings comprise a plurality of solar cells and a plurality of interconnecting members, wherein the interconnecting members are used to connect the plurality of solar cells in series; wherein the solar cells are the solar cells described in any one of the items of the present application.

[0009] In a third aspect, a method for manufacturing a solar cell is provided, comprising: providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other; forming a doped semiconductor layer on the first surface and / or the second surface; forming a dielectric layer on a side of the doped semiconductor layer facing away from the semiconductor substrate; forming a through opening in the dielectric layer so that at least a portion of the doped semiconductor layer is exposed from the opening; forming a plurality of holes on a side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate; forming an electrode in the opening, and electrically connecting the electrode to the doped semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0011] FIG1 is a schematic cross-sectional view of a first structure of a solar cell provided in an embodiment of the present application;

[0012] FIG2 is a schematic cross-sectional view of a second structure of a solar cell provided in an embodiment of the present application;

[0013] FIG3 is a schematic diagram of a solar cell after laser mold opening according to an embodiment of the present application;

[0014] FIG4 is a schematic cross-sectional view of a first structure of a back-contact solar cell provided in an embodiment of the present application;

[0015] FIG5 is a schematic cross-sectional view of a second structure of a back-contact solar cell provided in an embodiment of the present application;

[0016] FIG6 is a schematic cross-sectional view of a third structure of a back-contact solar cell provided in an embodiment of the present application;

[0017] FIG7 is a schematic cross-sectional view of a fourth structure of a back-contact solar cell provided in an embodiment of the present application;

[0018] FIG8-1 is a SEM image of an opening surface of a solar cell provided in an embodiment of the present application;

[0019] FIG8-2 is a scanning electron microscope topographic image of a solar cell provided in an embodiment of the present application, viewed from above at the opening;

[0020] FIG8-3 is a scanning electron microscope topographic image of an N-type doped semiconductor layer of a solar cell provided in an embodiment of the present application, viewed from above at an opening;

[0021] FIG8-4 is a scanning electron microscope topographic image of a P-type doped semiconductor layer of a solar cell provided in an embodiment of the present application, viewed from above at an opening;

[0022] FIG8-5 is a scanning electron microscope image of an N-type doped semiconductor layer at an opening of a solar cell provided in an embodiment of the present application;

[0023] FIG8-6 is a scanning electron microscope image of a P-type doped semiconductor layer at an opening of a solar cell provided in an embodiment of the present application;

[0024] FIG8-7 is a scanning electron microscope image of an N-type doped semiconductor layer at an opening of another solar cell provided in an embodiment of the present application;

[0025] FIG8-8 is a scanning electron microscope image of the P-type doped semiconductor layer at the opening of another solar cell provided in an embodiment of the present application;

[0026] 8-9 are ECV test diagrams of the doping concentration distribution of the N-type doped semiconductor layer along the thickness direction provided by the embodiments of the present application;

[0027] 8-10 are ECV test diagrams of the doping concentration distribution of the P-type doped semiconductor layer along the thickness direction provided by the embodiments of the present application;

[0028] 8-11 are cross-sectional structural diagrams of solar cells provided in embodiments of the present application;

[0029] FIG8-12 is a partial enlarged view of the edge area A of the opening shown in FIG8-3;

[0030] Figures 8-13 are oxygen element scanning images of the laser-molded surface of a solar cell provided in an embodiment of the present application;

[0031] FIG9-1 is a schematic cross-sectional view of a third structure of a solar cell provided in an embodiment of the present application;

[0032] FIG9-2 is a schematic cross-sectional view of a fifth structure of a back-contact solar cell provided in an embodiment of the present application;

[0033] FIG10 is a first structural diagram of a solar cell during the manufacturing process according to an embodiment of the present invention;

[0034] FIG11 is a second structural diagram of a solar cell during the manufacturing process according to an embodiment of the present invention;

[0035] FIG12 is a third structural diagram of a solar cell during the manufacturing process according to an embodiment of the present invention;

[0036] FIG13 is a fourth structural diagram of a solar cell during the manufacturing process according to an embodiment of the present invention;

[0037] FIG14 is a fifth structural diagram of a solar cell during the manufacturing process according to an embodiment of the present invention;

[0038] FIG15 is a sixth structural diagram of a solar cell during the manufacturing process provided by an embodiment of the present invention.

[0039] Figure 11 is a semiconductor substrate, 12 is a doped semiconductor layer, 12-1 is a first doped semiconductor layer, 12-2 is a second doped semiconductor layer, 13 is a dielectric layer, 14 is an opening, 14-1 is a first opening, 14-2 is a second opening, 15 is a hole, 15-1 is a first hole, 15-2 is a second hole, 16 is an annular protrusion, 16-1 is an annular protrusion of the first hole, 16-2 is an annular protrusion of the second hole, 17 is an electrode, 17A is a first electrode, 17B is a second electrode, 17-1 is a connecting electrode, 17-2 is a conductive contact layer, 18 is a groove, 19 is a second passivation layer, 20 is a first passivation layer, 21 is a discontinuous protrusion, 22 is a pore, 23 is a pit, and 24 is a crack. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of the present application.

[0041] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present application. These figures are not drawn to scale, and for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] In the context of this application, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0045] Existing solar cells typically include a semiconductor substrate, a doped semiconductor layer, a dielectric layer, and electrodes. The doped semiconductor layer is formed on the light-facing and / or light-reflecting surfaces of the semiconductor substrate. The dielectric layer is formed on the side of the doped semiconductor layer facing away from the semiconductor substrate and serves as a surface passivation layer and / or anti-reflection layer. The surface passivation layer is used to passivate surface defects on the side of the doped semiconductor layer facing away from the semiconductor substrate, thereby reducing the carrier recombination efficiency of the doped semiconductor layer. The anti-reflection layer is used to reduce the reflection of incident light and increase the light absorption rate of the semiconductor substrate. The electrode at least partially penetrates the dielectric layer and is in electrical contact with the doped semiconductor layer to conduct the carriers collected by the doped semiconductor layer to form a photocurrent.

[0046] In actual applications, the electrodes can be formed using processes such as screen printing, electroplating, or physical vapor deposition. Currently, screen printing is commonly used to form electrodes, using high-temperature silver paste as the material for manufacturing the electrodes. However, the high cost of high-temperature silver paste makes the manufacturing cost of the electrodes very high in the overall manufacturing cost of solar cells, in addition to the cost of the semiconductor substrate itself. Therefore, reducing the cost of electrode manufacturing has become an urgent problem that needs to be solved in the industry.

[0047] To address this issue, the industry performs mold opening at the interface of dielectric layers, such as silicon nitride, to remove part of the dielectric layer to form a contact window for the exposed doped semiconductor layer, and uses a low-temperature metallization process to make electrodes, such as using a low-temperature paste instead of a high-temperature silver paste, or using an electroplating process to form electrodes. However, the bonding strength between the electrodes formed by the current low-temperature metallization process and the doped semiconductor layer is lower than the bonding strength provided by the fusion crystal formed by the glass body inside the silver paste and the silicon interface in the manufacture of high-temperature silver paste. This leads to a higher risk of the electrode detaching from the doped semiconductor layer, reducing the structural reliability of the solar cell.

[0048] In order to solve the above technical problems, an embodiment of the present application provides a solar cell. In terms of the type of cell, the solar cell provided in an embodiment of the present application includes but is not limited to any of the following photovoltaic cells that can convert light energy into electrical energy. For example, the solar cell provided in an embodiment of the present application can be any of the following solar cells: a tunneling oxide passivated contact cell (Topcon), a doped polycrystalline silicon full back contact cell (TBC), a composite passivated back contact cell (HPBC), a bifacial hybrid cell, etc.

[0049] In terms of the electrode formation position, the solar cell provided in one embodiment of the present application can be a back-contact cell, as shown in Figure 1, in which case the positive electrode and negative electrode of the solar cell are both formed on the backlight side of the semiconductor substrate. Alternatively, the solar cell provided in one embodiment of the present application can also be a double-sided contact cell, as shown in Figure 2, in which case the positive electrode and negative electrode of the solar cell are respectively formed on the light-facing side and the backlight side of the semiconductor substrate.

[0050] 1 to 3 , a solar cell provided in one embodiment of the present application includes a semiconductor substrate 11 , a doped semiconductor layer 12 , a dielectric layer 13 , and an electrode 17 .

[0051] Here, the semiconductor substrate 11 has a first surface and a second surface relative to each other. The first surface of the semiconductor substrate 11 can correspond to the backlight surface of the solar cell, and in this case, the second surface of the semiconductor substrate 11 corresponds to the light-facing surface of the solar cell. The embodiment of the present application does not specifically limit the surface morphology of the first surface and the second surface of the semiconductor substrate 11. For example, as shown in Figure 2, the first surface and the second surface of the semiconductor substrate 11 are both planes. For another example, as shown in Figure 1, the second surface of the semiconductor substrate 11 can also be a velvet surface, and the first surface of the semiconductor substrate 11 is at least partially plane. For another example, the first surface and the second surface of the semiconductor substrate 11 are both velvet surfaces.

[0052] In one embodiment, the semiconductor substrate 11 may be a silicon substrate. The conductivity type of the semiconductor substrate 11 may be N-type or P-type, or the semiconductor substrate 11 may be close to the intrinsic conductivity type, and the crystal type may be single crystal or polycrystalline.

[0053] The doped semiconductor layer 12 can be disposed on the first surface of the semiconductor substrate 11. It is understood that the doped semiconductor layer 12 can also be disposed on the second surface of the semiconductor substrate 11, or that doped semiconductor layers can be disposed on both the first and second surfaces of the semiconductor substrate 11, as shown in FIG2 . The doped semiconductor layer 12 in this application can also be referred to as a conductive doping layer.

[0054] The formation position of the doped semiconductor layer 12 on the semiconductor substrate 11 can be determined according to the type of solar cell. It should be noted that the doped semiconductor layer 12 in the embodiment of the present application refers to a doped semiconductor layer having a hole formed on the side of the opening of the dielectric layer away from the semiconductor substrate, which can also be called a first doped semiconductor layer; in some examples, the doped semiconductor layer 12 in the embodiment of the present application refers to a semiconductor layer having a hole formed on the side of the opening of the dielectric layer away from the semiconductor substrate, and a ring-shaped protrusion is formed on the edge of the hole. The third doped semiconductor layer described below, unlike the doped semiconductor layer (i.e., the first doped semiconductor layer), refers to a semiconductor layer without a hole.

[0055] For example, when the solar cell provided in the embodiment of the present application is a double-sided contact cell, the doped semiconductor layer 12 may be formed only on one side of the first surface or the second surface of the semiconductor substrate 11. In this case, the conductivity type of the doped semiconductor layer 12 may be opposite to the conductivity type of the semiconductor substrate 11. In this case, the solar cell further includes a third doped semiconductor layer formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12 and having the same conductivity type as the semiconductor substrate. Alternatively, when the doped semiconductor layer is formed only on one side of the first surface or the second surface of the semiconductor substrate 11, the conductivity type of the doped semiconductor layer may also be the same as the conductivity type of the semiconductor substrate 11, and the solar cell further includes a third doped semiconductor layer formed on the side of the semiconductor substrate away from the doped semiconductor layer, and the conductivity type of the third doped semiconductor layer is opposite to that of the semiconductor substrate. Of course, when the solar cell provided in the embodiment of the present application is a double-sided contact cell, the solar cell may also not include the above-mentioned third doped semiconductor layer.

[0056] Alternatively, the doped semiconductor layer 12 may also be formed on both the first and second surfaces of the semiconductor substrate 11 . In this case, the two doped semiconductor layers 12 located on the first and second surfaces of the semiconductor substrate 11 have opposite conductivity types.

[0057] When the solar cell provided in the embodiment of the present application is a double-sided contact cell, the doped semiconductor layer 12 can be arranged on the entire surface of the first surface and / or the second surface of the semiconductor substrate 11, or can be arranged in a local area of ​​the first surface and / or the second surface of the semiconductor substrate 11.

[0058] For another example, when the solar cell provided in the embodiment of the present application is a back-contact cell, the doped semiconductor layer 12 is formed on one side of the first surface of the semiconductor substrate 11. The conductivity type of the doped semiconductor layer 12 may be the same as that of the semiconductor substrate 11. In this case, the solar cell further includes a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12. The conductivity type of the third doped semiconductor layer is opposite to that of the semiconductor substrate 11. Alternatively, the conductivity type of the doped semiconductor layer 12 may be opposite to that of the semiconductor substrate 11. In this case, the solar cell may include a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12. The conductivity type of the third doped semiconductor layer is the same as that of the semiconductor substrate 11. Of course, when the solar cell provided in the embodiment of the present application is a back-contact cell, the solar cell may also not include the third doped semiconductor layer. Alternatively, the conductivity types of the doped semiconductor layers 12 located in different regions on the first surface of the semiconductor substrate 11 are opposite, and the different doped semiconductor layers 12 of opposite conductivity types are alternately distributed.

[0059] When the solar cell further includes a third doped semiconductor layer, the conductivity type of the third doped semiconductor layer can be determined based on actual needs, as long as the conductivity type of the doped semiconductor layer 12 is opposite to that of the third doped semiconductor layer. For example, the materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be semiconductor materials such as silicon, germanium, silicon carbide, or gallium arsenide. In terms of the internal arrangement of the materials, they can be amorphous, microcrystalline, single crystal, nanocrystalline, or polycrystalline. The materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be the same or different.

[0060] The dielectric layer 13 is disposed on the side of the doped semiconductor layer 12 facing away from the semiconductor substrate 11. A plurality of openings 14 are defined through the dielectric layer 13. The openings 14 may also be referred to as conductive windows in this application. The openings 14 expose at least a portion of the doped semiconductor layer 12. A plurality of holes 15 are formed in the portion of the doped semiconductor layer 12 exposed in the openings 14, facing away from the semiconductor substrate 11.

[0061] It should be noted that in the embodiment of the present application, the hole does not penetrate the doped semiconductor layer and is a blind hole.

[0062] The dielectric layer 13 can passivate the surface of the doped semiconductor layer 12 and reduce the carrier recombination rate. Because the dielectric layer 13 is a non-conductive insulating layer, an opening 14 is provided through the dielectric layer 13. The opening 14 in the present application may be a circular, square, or elliptical shape or other shape. The opening 14 exposes at least a portion of the doped semiconductor layer 12. In addition, a plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11. In this manner, an electrode can be formed at the opening 14 using a low-temperature metallization process, which can reduce the cost of the metallization process. In addition, because a plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11, the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11 has an uneven surface feature, which helps to increase the roughness and specific surface area of ​​the surface of the doped semiconductor layer 12 located at the opening. Based on this, compared with the existing solar cell in which the electrode 17 is formed on the doped semiconductor layer with a relatively flat surface, the solar cell provided in the embodiment of the present application has the electrode 17 formed on the doped semiconductor layer 12 with an uneven surface. The contact area between the portion of the doped semiconductor layer 12 exposed in the opening 14 and the electrode 17 is larger, which is beneficial to increasing the bonding force between the electrode 17 and the doped semiconductor layer 12, enhancing the connection strength between the two, reducing the risk of the electrode 17 detaching from the doped semiconductor layer 12, and improving the structural reliability of the solar cell; at the same time, due to the large contact area, the contact resistance between the electrode 17 and the doped semiconductor layer 12 can also be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0063] The dielectric layer 13 can be a single-layer structure or a multi-layer structure. In some examples, the dielectric layer 13 can include a surface passivation layer, and can also include other possible layers such as an anti-reflection layer, or can include a surface passivation layer and an anti-reflection layer that are stacked. The embodiment of the present application does not specifically limit the structure of the dielectric layer 13, and it can be arranged according to the needs of the solar cell. For example, for a TBC cell, the dielectric layer 13 on the backlight side can include a surface passivation layer and an anti-reflection layer that are stacked; for a Topcon cell, the dielectric layer 13 on the backlight side can include an anti-reflection layer, and can also include a surface passivation layer, or can also include a surface passivation layer and an anti-reflection layer that are stacked; the dielectric layer on the light-facing side of both the TBC cell and the Topcon cell can include a surface passivation layer and an anti-reflection layer that are stacked.

[0064] The material of the dielectric layer 13 is an insulating material. In some examples, when the dielectric layer includes a surface passivation layer, the material of the dielectric layer 13 may include at least one of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. In some examples, when the dielectric layer includes a stacked surface passivation layer and an anti-reflection layer, the material of the surface passivation layer may include one or more of aluminum oxide, silicon oxide, and intrinsic amorphous silicon, and the material of the anti-reflection layer may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In some examples, the material of the dielectric layer 13 includes silicon nitride. In this case, because silicon nitride has a high resistivity, when the material of the dielectric layer 13 includes silicon nitride, it is beneficial to improve the insulation performance of the dielectric layer 13 and has a good passivation effect. Therefore, the dielectric layer 13 including silicon nitride passivates the surface of the doped semiconductor layer 12, which is beneficial to reducing the carrier recombination rate. In addition, because silicon nitride also has a good anti-reflection effect, it can improve the photoelectric conversion efficiency of the solar cell.

[0065] In some embodiments, the solar cell may further include a first passivation layer 20 located between the semiconductor substrate 11 and the doped semiconductor layer 12. The first passivation layer 20 may passivate at least the corresponding surfaces of the semiconductor substrate 11 and the doped semiconductor layer 12, thereby reducing the rate at which carriers recombine on the surface of the semiconductor substrate 11. Furthermore, the doped semiconductor layer 12 formed on the first passivation layer 20 can selectively collect carriers of the corresponding conductivity type within the semiconductor substrate 11, thereby further improving the photoelectric conversion efficiency of the solar cell provided by the embodiments of the present application.

[0066] The first passivation layer 20 can be a single layer or multiple layers, or can be composed of different materials in different regions. The material of the first passivation layer 20 can be determined based on the material of the doped semiconductor layer 12. For example, when the material of the doped semiconductor layer 12 includes one or more of doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon, the first passivation layer 20 can be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of at least two of the three. In this case, the doped semiconductor layer 12 and the first passivation layer 20 can form a heterogeneous contact structure.

[0067] For another example, when the doped semiconductor layer 12 is a doped polysilicon layer, the first passivation layer 20 may be a tunneling passivation layer. In this case, the doped semiconductor layer 12 and the first passivation layer 20 may form a tunneling passivation contact structure. Furthermore, the material of the tunneling passivation layer may include any dielectric material having a tunneling passivation effect. For example, the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0068] In some embodiments, the doped semiconductor layer 12 is formed only on one side of the first surface or the second surface of the semiconductor substrate 11. The solar cell may further include a second passivation layer 19 formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, which can passivate the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, thereby reducing the rate of carrier recombination on the surface of the semiconductor substrate 11 and further improving the photoelectric conversion efficiency of the solar cell. Specifically, the embodiment of the present application does not specifically limit the material and thickness of the second passivation layer 19, which can refer to the material of the above-mentioned dielectric layer. For example, the material of the second passivation layer 19 may include any one or more insulating materials such as silicon oxide, aluminum oxide, silicon nitride, etc.

[0069] Referring to Figures 4 to 7, in some embodiments of the present application, the solar cell is a back-contact cell. The solar cell provided in this embodiment includes: a semiconductor substrate 11, a first doped semiconductor layer 12-1, a second doped semiconductor layer 12-2, a dielectric layer 13, a first electrode 17A and a second electrode 17B. It should be noted that Figures 4 and 5 are only used to illustrate the structure of the solar cell, and do not limit the thickness of each layer and the surface morphology characteristics. Figures 6 and 7 are only used to illustrate the structure of the solar cell and the opening setting of the dielectric layer. The surface morphology characteristics of the area where the doped semiconductor layer is exposed to the opening are not limited. The specific surface morphology characteristics will be described in detail below.

[0070] This embodiment only describes the parts that are different from the above embodiments. The same parts can refer to the above embodiments. For example, the features of the semiconductor substrate 11 in this embodiment can refer to the features of the semiconductor substrate 11 in the above embodiments, which will not be repeated here.

[0071] For example, the first doped semiconductor layer 12-1 may be an N-type doped semiconductor layer, and the second doped semiconductor layer 12-2 may be a P-type doped semiconductor layer. In this application, the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 may also be referred to as the first conductive doping layer or the second conductive doping layer.

[0072] The solar cell provided in this embodiment is a back-contact cell, in which first doped semiconductor layers 12-1 and second doped semiconductor layers 12-2 are alternately arranged on one side of the first surface of the semiconductor substrate 11. The conductivity type of the first doped semiconductor layer 12-1 can be the same as the conductivity type of the semiconductor substrate 11, and the conductivity type of the second doped semiconductor layer 12-2 can be opposite to the conductivity type of the semiconductor substrate 11; alternatively, the conductivity type of the first doped semiconductor layer 12-1 can be opposite to the conductivity type of the semiconductor substrate 11, and the conductivity type of the second doped semiconductor layer 12-2 can be the same as the conductivity type of the semiconductor substrate 11.

[0073] The materials of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 can refer to the materials of the doped semiconductor layers in the above embodiments, which will not be described in detail here. The materials of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 can be the same or different.

[0074] In some examples, an isolation region is formed between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2, and the isolation region can be, for example, an isolation trench; in other examples, there is no isolation region between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2, that is, the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 are arranged in contact with each other, or there is an overlapping region between the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2.

[0075] The dielectric layer 13 is disposed on a side of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 facing away from the semiconductor substrate 11. The dielectric layer 13 includes a plurality of first openings 14-1 and a plurality of second openings 14-2. The first openings 14-1 expose a portion of the first doped semiconductor layer 12-1, and the second openings 14-2 expose a portion of the second doped semiconductor layer 12-2. The first openings 14-1 and the second openings 14-2 may also be referred to as first conductive windows and second conductive windows.

[0076] The structural features of the dielectric layer 13 may refer to the dielectric layer 13 in the aforementioned embodiment, and will not be described again here.

[0077] In some embodiments, the solar cell may further include a first passivation layer 20 located between the semiconductor substrate 11 and the doped semiconductor layer (i.e., the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2), as shown in FIG7 . The first passivation layer 20 can at least passivate the surfaces corresponding to the semiconductor substrate 11 and the doped semiconductor layer, thereby reducing the rate at which carriers recombine on the surface of the semiconductor substrate 11. Moreover, the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 can respectively selectively collect carriers of corresponding conductive types within the semiconductor substrate 11, so as to further improve the photoelectric conversion efficiency of the solar cell provided in the embodiment of the present application. In some embodiments, the first passivation layer 20 formed between the semiconductor substrate 11 and the first doped semiconductor layer 12-1, and the first passivation layer 20 formed between the semiconductor substrate 11 and the second doped semiconductor layer 12-2 can be formed simultaneously, or can be formed in different process steps. When formed in different process steps, the materials, thicknesses, etc. of the first passivation layer 20 formed between the semiconductor substrate 11 and the first doped semiconductor layer 12-1 and the first passivation layer 20 formed between the semiconductor substrate 11 and the second doped semiconductor layer 12-2 may be the same or different.

[0078] The first passivation layer 20 can be a single layer or a multilayer, or can be composed of different materials in different regions. The material of the first passivation layer 20 can be determined according to the material of the doped semiconductor layer. For example, when the first doped semiconductor layer and the second doped semiconductor layer are both doped polysilicon layers, the first passivation layer 20 can be a tunneling passivation layer. At this time, the first doped semiconductor layer and the first passivation layer 20 can constitute a tunneling passivation contact structure, and the second doped semiconductor layer and the first passivation layer can constitute a tunneling passivation contact structure. In addition, the material of the tunneling passivation layer can include any dielectric material with a tunneling passivation effect. For example, the material of the tunneling passivation layer can refer to the above and will not be repeated here.

[0079] In some embodiments, the solar cell of the embodiment of the present application may further include a surface passivation layer and an anti-reflection layer formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer, that is, formed on the second surface. The materials and functions of the surface passivation layer and the anti-reflection layer can be referred to above and will not be repeated here.

[0080] For any embodiment of the present application, the surface morphology of the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate (for example, roughness, contact area between the electrode and the doped semiconductor layer, etc.) directly affects the stability of the electrode structure. Therefore, reasonable morphological characteristics can solve or at least alleviate the problem of easy detachment of the electrode from the doped semiconductor layer, thereby ensuring the structural reliability of the solar cell.

[0081] It should be noted that the surface morphology of the portion of the doped semiconductor layer exposed in the opening on the side facing away from the semiconductor substrate can be controlled by controlling laser parameters such as laser energy, laser spot size, laser spot overlap, laser irradiation area, and laser energy at different positions. Of course, the surface morphology of the portion of the doped semiconductor layer exposed in the opening on the side facing away from the semiconductor substrate can also be controlled by adjusting the composition of the etching solution and etching conditions such as temperature and time.

[0082] For the convenience of description, the doped semiconductor layer in the following embodiments of the present application may include a doped semiconductor layer, or may include at least one of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2, and the characteristics of at least one of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2 are the same as the characteristics of the doped semiconductor layer described below; the opening in the following embodiments of the present application may include a type of opening, or may include at least one of the first opening 14-1 and the second opening 14-2, and the characteristics of at least one of the first opening 14-1 and the second opening 14-2 are the same as the characteristics of the opening described below ; The holes in the following embodiments of the present application may include a type of hole, or may include at least one of the first hole 15-1 and the second hole 15-2, and the characteristics of at least one of the first hole 15-1 and the second hole 15-2 are the same as the characteristics of the holes described below; the annular protrusions in the following embodiments of the present application may include a type of annular protrusion, or may include at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole, and the characteristics of at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole are the same as the characteristics of the annular protrusions described below.

[0083] 8-1 to 8-13 , for any embodiment of the present application, the portion of the doped semiconductor layer exposed in the opening on a side facing away from the semiconductor substrate may have one or more of the following morphological features.

[0084] For example, in the solar cell provided by the present application, a plurality of holes 15 are formed on the side of the doped semiconductor layer exposed at the opening away from the semiconductor substrate. The effect of forming a plurality of holes 15 on the side of the doped semiconductor layer exposed at the opening away from the semiconductor substrate is described in the above embodiment and will not be repeated here. In some examples, taking the doped semiconductor layer as a P-type polycrystalline silicon layer as an example, the contact resistance between the electrode and the doped semiconductor layer can be reduced to an average of 0.8 mΩ*cm2. Taking the doped semiconductor layer as an N-type polycrystalline silicon layer as an example, the contact resistance between the electrode and the doped semiconductor layer 12 can be reduced to an average of 0.35 mΩ*cm2.

[0085] It is understandable that the shape, size, number and morphology of the holes 15 will affect the surface roughness of the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. Therefore, the above-mentioned relevant information of the holes can be adjusted according to the actual application scenario.

[0086] Exemplarily, the hole 15 is a quasi-hemispherical hole. This quasi-hemispherical hole can be a strictly hemispherical hole, or it can be an approximately hemispherical hole, that is, it can have some small deformation relative to the hemispherical hole, for example, there is a deformation within the allowable tolerance range (for example, within 5% or 10%) relative to the hemispherical hole. In the case where the hole 15 is a quasi-hemispherical hole, the cross-sectional size of the hole opening is the largest along the depth direction of the hole 15, which facilitates filling the hole 15 with the conductive material used to manufacture the electrode, which is beneficial to improving the connection strength and contact performance between the electrode and the doped semiconductor layer, ensuring that the electrode and the doped semiconductor layer have a large bonding force and good contact performance.

[0087] In some examples, the maximum radial dimension of the holes 15 is nanometer-scale. In this case, the smaller maximum radial dimension of the holes helps prevent the doped semiconductor layer from being exposed in the opening on the side facing away from the semiconductor substrate. After forming a surface with holes, the remaining thickness of the doped semiconductor layer is smaller, ensuring that the doped semiconductor layer has a higher carrier diversion capability, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0088] In some other examples, the maximum radial dimension of the hole 15 is greater than 0 μm and less than or equal to 3 μm.

[0089] Considering that if the radial maximum dimension of the hole 15 is too large, for example, 4 μm, 5 μm or 10 μm or larger, the number of holes 15 will be reduced, which will reduce the specific surface area of ​​the doped semiconductor layer exposed in the opening portion, thereby reducing the contact area between the doped semiconductor layer and the electrode, and reducing the bonding force between the electrode and the doped semiconductor layer, the radial maximum dimension of the hole 15 in the present application is less than or equal to 3 μm.

[0090] Furthermore, considering that if the maximum radial dimension of the hole 15 is too small, the surface roughness of the doped semiconductor layer will be small, and when forming an electrode on the doped semiconductor layer, it will be difficult to fill the small hole 15 with the conductive material used to manufacture the electrode, and the connection strength and contact performance between the electrode and the doped semiconductor layer cannot be ensured, in some examples, the maximum radial dimension of the hole is greater than or equal to 0.02 μm. Optionally, the maximum radial dimension of the hole is greater than or equal to 0.02 μm and less than or equal to 0.1 μm.

[0091] The maximum radial dimension of the hole 15 may be, for example, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.4 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm or 3 μm.

[0092] The present application adopts the above-mentioned maximum radial size range of the hole 15, which is beneficial to increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, and reducing the risk of the electrode detaching from the doped semiconductor layer, thereby helping to improve the structural reliability of the solar cell.

[0093] Exemplarily, a ring-shaped raised portion 16 is formed around the edge of hole 15. The circular (or quasi-circular) area surrounded by the bright circle in FIG8-2 is hole 15, and the bright circle is the ring-shaped raised portion 16 formed around the edge of hole 15. In some examples, the ring-shaped raised portion 16 can be formed by melting and then solidifying the material of the doped semiconductor layer, similar to a circular crater. The ring-shaped raised portion 16 is raised relative to the area inside and / or outside the hole 15.

[0094] It can be understood that, since the annular protrusion 16 is formed by melting and then solidifying the doped semiconductor layer, when the doped semiconductor layer is a doped polysilicon layer, the material of the annular protrusion 16 includes silicon.

[0095] By adopting the above technical solution, the annular protrusion 16 can further enhance the uneven surface features formed on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate, which is beneficial to further increase the surface roughness and specific surface area of ​​the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. Based on this, since the electrode of the solar cell provided by the present application is formed on the doped semiconductor layer with an uneven surface, the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, which is beneficial to increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. In addition, since the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, the contact performance is improved, and the photoelectric conversion efficiency of the solar cell is further improved.

[0096] Exemplarily, the width of the annular raised portion 16 is greater than 0 μm and less than or equal to 0.3 μm. Considering that if the width of the annular raised portion 16 is too large, for example, 0.4 μm, 0.7 μm, or 1 μm or more, the specific surface area of ​​the doped semiconductor layer will not increase significantly, thereby reducing the surface roughness of the doped semiconductor layer and not being conducive to increasing the contact area between the electrode and the doped semiconductor layer, the width of the annular raised portion 16 of the present application is less than or equal to 0.3 μm.

[0097] Furthermore, considering that if the width of the annular protrusion 16 is too small, the annular protrusion is easily broken, resulting in no contribution to increasing the contact area between the electrode and the doped semiconductor layer, and the silicon in the annular protrusion 16 (i.e., the silicon in the doped semiconductor layer) is easily pulled off by the electrode, which is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer, in some examples, the width of the annular protrusion 16 is greater than or equal to 0.05 μm.

[0098] The width of the annular protrusion 16 may be, for example, 0.05 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm or 0.3 μm.

[0099] The width range of the above-mentioned annular protrusion 16 is beneficial to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0100] Exemplarily, the height of the annular protrusion 16 is greater than 0 μm and less than or equal to 0.5 μm. Considering that if the height of the annular protrusion 16 is too high, for example, 0.6 μm, 0.8 μm, 1 μm or more, the annular protrusion 16 is easily broken, resulting in no contribution to increasing the contact area between the electrode and the doped semiconductor layer, and the annular protrusion 16 is easily broken by the electrode, thus reducing the tensile force between the electrode and the doped semiconductor layer, which is not conducive to increasing the bonding force between the electrode and the doped semiconductor layer, the height of the annular protrusion 16 of the present application is less than or equal to 0.5 μm.

[0101] Furthermore, considering that if the height of the annular protrusion 16 is too low, it will not be conducive to increasing the surface roughness of the doped semiconductor layer, in some examples, the height of the annular protrusion 16 is greater than or equal to 0.001 μm.

[0102] The height of the annular protrusion 16 may be, for example, 0.001 μm, 0.005 μm, 0.008 μm, 0.01 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.2 μm, 0.3 μm or 0.5 μm.

[0103] The height range of the annular protrusion 16 is beneficial to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0104] Exemplarily, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion is less than or equal to 60. Considering that if this ratio is too large, for example, 80, 90, or 100 or more, that is, the maximum radial dimension of the hole 15 is large and the width of the annular protrusion 16 is small, and the maximum radial dimension of the hole 15 is large, the number of holes 15 will be reduced, and the width of the annular protrusion 16 is small, which will cause the specific surface area of ​​the doped semiconductor layer at the opening to decrease, thereby reducing the surface roughness of the doped semiconductor layer at the opening, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, in the present application, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 is less than or equal to 60.

[0105] Furthermore, if this ratio is too small, that is, if the width of the annular protrusion 16 is large and the maximum radial dimension of the hole 15 is small, the specific surface area of ​​the doped semiconductor layer will be reduced, thereby reducing the surface roughness of the doped semiconductor layer and hindering the increase in the contact area between the electrode and the doped semiconductor layer. Furthermore, a small maximum radial dimension of the hole 15 results in a smaller surface roughness of the doped semiconductor layer. Furthermore, when forming an electrode on the doped semiconductor layer, it is difficult to fill the small hole 15 with the conductive material used to manufacture the electrode, thus failing to ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the ratio of the maximum radial dimension of the hole to the width of the annular protrusion is greater than or equal to 0.06.

[0106] The ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 may be, for example, 0.06, 0.08, 0.1, 0.2, 0.3, 1, 10, 15, 18, 20, 30, 35, 40 or 60.

[0107] The ratio range of the radial maximum dimension of the above-mentioned hole 15 to the width of the annular protrusion 16 is beneficial to increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, and reducing the risk of the electrode detaching from the doped semiconductor layer, thereby helping to improve the structural reliability of the solar cell.

[0108] Exemplarily, the doping concentration of the doped semiconductor layer located in the opening and away from the semiconductor substrate is greater than the doping concentration of the doped semiconductor layer located in the opening and close to the semiconductor substrate.

[0109] With the above technical solution, the doping concentration of the doped semiconductor layer increases relatively as it moves away from the semiconductor substrate, i.e., the doping concentration is higher on the side of the doped semiconductor layer closer to the electrode. This reduces the contact resistance between the doped semiconductor layer and the electrode, thereby improving the photoelectric conversion efficiency of the solar cell. Furthermore, compared to a situation where the doping concentration on the side of the doped semiconductor layer closer to the electrode is the same as the doping concentration on the side of the doped semiconductor layer closer to the semiconductor substrate, the thickness of the doped semiconductor layer can be appropriately reduced due to the higher doping concentration on the side of the doped semiconductor layer closer to the electrode. This not only saves costs but also improves the manufacturing efficiency of the solar cell.

[0110] For example, the portion of the doped semiconductor layer exposed in the opening has a fifth surface roughness on a side facing away from the semiconductor substrate, and the portion of the doped semiconductor layer not exposed in the opening has a sixth surface roughness on a side facing away from the semiconductor substrate, where the fifth surface roughness is greater than the sixth surface roughness. The greater surface roughness of the portion of the doped semiconductor layer exposed in the opening can increase the contact area between the doped semiconductor layer and the electrode, which is beneficial for reducing the contact resistance between the electrode and the doped semiconductor layer, and is beneficial for increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. The lower roughness of the sixth surface can ensure good film formation quality of the doped semiconductor layer.

[0111] Exemplarily, the fifth surface roughness is in the range of 0 to 0.5 μm. Optionally, the fifth surface roughness is in the range of 0.3 μm to 0.5 μm. For example, the fifth surface roughness can be 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm, or 0.5 μm. The sixth surface roughness is in the range of 0 to 100 nm. In this case, the fifth surface roughness being within the above range can ensure the contact area between the electrode and the doped semiconductor layer exposed at the side of the opening facing away from the semiconductor substrate, ensuring high connection strength and good contact performance between the electrode and the doped semiconductor layer.

[0112] Exemplarily, the portion of the doped semiconductor layer exposed in the opening has a fifth surface roughness on a side facing away from the semiconductor substrate. Furthermore, the unexposed portion of the doped semiconductor layer not exposed in the opening includes a first unexposed portion at the edge of the dielectric layer opening and the remaining unexposed portion other than the first unexposed portion. The first unexposed portion has a seventh surface roughness on a side facing away from the semiconductor substrate, and the remaining unexposed portion has an eighth surface roughness on a side facing away from the semiconductor substrate, wherein the fifth surface roughness > the seventh surface roughness > the eighth surface roughness. The greater surface roughness of the portion of the doped semiconductor layer exposed in the opening can increase the contact area between the doped semiconductor layer and the electrode, facilitating reduction of contact resistance between the electrode and the doped semiconductor layer. It also increases the bonding strength between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. Furthermore, during electrode formation, electrode material may be formed on the first unexposed portion. Therefore, the seventh surface roughness of the first unexposed portion is greater than the eighth surface roughness, further enhancing the bonding strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode detaching from the doped semiconductor layer, and thereby improving the structural stability of the solar cell.

[0113] In the embodiments of the present application, surface roughness may refer to the arithmetic mean deviation Ra of the profile of the targeted surface, specifically the arithmetic mean of the absolute values ​​of the profile peaks and valleys (relative to the average line) of the surface within the sampling length Lr of the targeted surface. In actual measurement, the more measuring points there are, the more accurate Ra is. Alternatively, surface roughness may also refer to the maximum height Rz of the profile of the targeted surface, specifically the distance between the peak top line and the valley bottom line of the profile of the targeted surface. It is understood that when the roughness of different surface areas is involved, for example, when the first surface roughness, the second surface roughness, the third surface roughness, and the fourth surface roughness are involved, the same roughness measurement standard is used.

[0114] For example, a portion of the doped semiconductor layer exposed in the opening is further formed with a plurality of discontinuous protrusions 21 on a side facing away from the semiconductor substrate. The discontinuous protrusions 21 may include at least one of dot-shaped protrusions (such as the bright spots within the circle in FIG8-2 ) and linear protrusions (such as the white curve within the square frame in FIG8-2 ). The linear protrusions may be straight-line protrusions, curved-line protrusions, or unclosed loop-shaped protrusions.

[0115] The discontinuous raised portions 21 can be located at any position on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate. The discontinuous raised portions 21 also help increase the surface roughness of the doped semiconductor layer at the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, enhancing the bonding force between the electrode and the doped semiconductor layer, and strengthening the connection strength between the two. This reduces the risk of the electrode detaching from the doped semiconductor layer, thereby improving the structural reliability of the solar cell.

[0116] In embodiments of the present application, the number of discontinuous raised portions per unit area in the edge region of the opening may be greater than the number of discontinuous raised portions per unit area in the middle region of the opening; or the number of discontinuous raised portions per unit area in the edge region of the opening may be less than the number of discontinuous raised portions per unit area in the middle region of the opening. The openings herein may be circular, square, or elliptical, and the shape enclosed by the boundary of the corresponding middle region of the opening is the same as the shape enclosed by the boundary of the opening, and the distance from the boundary of the middle region to the boundary of the opening is equal or approximately equal. For example, when the opening is circular, the middle region is a circular or approximately circular region surrounding the center of the opening, and the distance from the boundary of the middle region to the outer boundary of the opening in a radial direction passing through the center of the opening is equal or approximately equal (i.e., equal within a tolerance range); the area within the opening excluding the middle region is the edge region of the opening. Approximately circular means that it may have some small deformation relative to the circle, such as a deformation within a tolerance range (e.g., within 5% or 10%). As shown in Figure 8-2, the areas enclosed by the large red circles in the figure are the middle region of the opening, and the remaining areas are the edge regions of the opening.

[0117] For example, when the doped semiconductor layer is a P-type doped semiconductor layer, as shown in FIG8-4 , the number of discontinuous raised portions per unit area at the edge region of the opening is greater than the number of discontinuous raised portions per unit area at the middle region of the opening. Generally, due to the low doping concentration of a P-type doped semiconductor layer and its high hole-poor electron-density properties, it is not conducive to forming an electrode on the P-type doped semiconductor layer. It is understandable that, when forming electrodes of the same thickness, it is more difficult to form an electrode on a P-type doped semiconductor layer than on an N-type doped semiconductor layer. Furthermore, for an opening, the difficulty of forming an electrode at the edge region of the opening is greater than that of forming an electrode in the middle region of the opening. Based on this, in some embodiments of the present application, the number of discontinuous raised portions per unit area at the edge region of the opening of the P-type doped semiconductor layer is greater than the number of discontinuous raised portions per unit area at the middle region of the opening. This can improve the fabrication of the electrode at the edge region of the opening, thereby ensuring the quality of the electrode formed at the edge region of the opening, making the quality of the electrodes formed at the edge region and the middle region of the opening more consistent, which is conducive to improving the carrier transport effect in the electrode.

[0118] Exemplarily, when the doped semiconductor layer is an N-type doped semiconductor layer, as shown in FIG8-3 , the number of discontinuous protrusions per unit area in the middle region of the opening is greater than the number of discontinuous protrusions per unit area in the edge region of the opening. Generally, since the doping concentration of the N-type doped semiconductor layer is relatively high and the N-type doped semiconductor layer has the property of having more electrons and fewer holes, it is advantageous to form an electrode on the N-type doped semiconductor layer. It is understandable that when forming electrodes of the same thickness, the difficulty of forming an electrode on the N-type doped semiconductor layer is less than the difficulty of forming an electrode on the P-type doped semiconductor layer. In addition, for an opening, since the difficulty of forming an electrode in the middle region of the opening is less than the difficulty of forming an electrode in the edge region of the opening, that is, the difficulty of forming an electrode in the middle region of the N-type doped semiconductor layer is less, the speed of forming the electrode in the middle region of the N-type doped semiconductor layer is faster. However, too fast an electrode production speed is not conducive to improving adhesion. Therefore, in some embodiments of the present application, by setting the number of discontinuous protrusions per unit area of ​​the N-type doped semiconductor layer in the middle region of the opening relative to the number of discontinuous protrusions per unit area of ​​the edge region of the opening, the specific surface area of ​​the middle region of the N-type doped semiconductor layer can be increased, which is beneficial to improving the bonding strength between the electrode in the middle region and the N-type doped semiconductor layer.

[0119] Exemplarily, the height of the discontinuous raised portion is greater than 0 μm and less than or equal to 0.5 μm. Considering that if the height of the discontinuous raised portion is too high, the discontinuous raised portion is easily broken, and the tension between the electrode and the doped semiconductor layer is reduced, the height of the discontinuous raised portion in this application is less than or equal to 0.5 μm.

[0120] Furthermore, considering that if the height of the discontinuous protrusion is too small, it will not contribute much to increasing the surface roughness of the doped semiconductor layer, therefore, in some examples, the height of the discontinuous protrusion is greater than or equal to 0.001 μm.

[0121] The height of the discontinuous protrusions may be, for example, 0.001 μm, 0.003 μm, 0.006 μm, 0.009 μm, 0.01 μm, 0.05 μm, 0.07 μm, 0.1 μm, 0.2 μm, 0.3 μm or 0.5 μm.

[0122] The height range of the discontinuous protrusions in the present application is beneficial to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, and enhancing the connection strength between the two. In addition, it avoids the problem of reduced tension between the electrode and the doped semiconductor layer due to excessive height.

[0123] For the back-contact cells of Figures 4 to 7, since the materials, doping concentrations, and conductivity of the P-type doped semiconductor layer and the N-type doped semiconductor layer are different, the contact resistance and adhesion between the P-type doped semiconductor layer and the first electrode, and between the N-type doped semiconductor layer and the second electrode are also different. However, it is currently difficult to ensure that the contact resistance and adhesion between the P-type doped semiconductor layer and the first electrode, and between the N-type doped semiconductor layer and the second electrode meet the requirements, and therefore it is difficult to achieve a good match between the P region and the N region in terms of electrical properties and tensile strength.

[0124] The embodiments of the present application provide solutions to the above problems. Referring to Figures 8-2 to 8-10, in the back-contact solar cell of this embodiment, the dielectric layer includes multiple first openings and multiple second openings, the first openings exposing a portion of the first doped semiconductor layer, and the second openings exposing a portion of the second doped semiconductor layer, wherein: the area of ​​the first doped semiconductor layer exposed to the first openings has a first surface roughness, and the area of ​​the second doped semiconductor layer exposed to the second openings has a second surface roughness, and the first surface roughness and the second surface roughness are different.

[0125] Taking the first surface roughness as an example, the first surface roughness of the area of ​​the first doped semiconductor layer exposed to the first opening affects the contact area between the first electrode and the first doped semiconductor layer formed in the area of ​​the first opening, thereby affecting the contact resistance between the first electrode and the first doped semiconductor layer, the bonding force between the first electrode and the first doped semiconductor layer, and the film formation quality of the first electrode. The contact resistance between the first electrode and the first doped semiconductor layer and the bonding force between the first electrode and the first doped semiconductor layer in turn affect the number of first openings. Therefore, the first surface roughness can be controlled to adjust the contact resistance and bonding force between the first electrode and the first doped semiconductor layer, the film formation quality of the first electrode, and the number of first openings.

[0126] With the above technical solution, the region of the first doped semiconductor layer exposed by the first opening has a first surface roughness. This first surface roughness can increase the contact area between the first electrode and the first doped semiconductor layer, thereby increasing the bonding strength between the first electrode and the first doped semiconductor layer and reducing the contact resistance between the first electrode and the second doped semiconductor layer. The region of the second doped semiconductor layer exposed by the second opening has a second surface roughness. This second surface roughness has the same technical effect as the first surface roughness and is not further described here. In addition, the first surface roughness of the region of the first doped semiconductor layer exposed to the first opening is different from the second surface roughness of the region of the second doped semiconductor layer exposed to the second opening. Therefore, by regulating the first surface roughness and the second surface roughness, the film quality of the first electrode and the second electrode, the contact resistance and bonding force between the first electrode and the first doped semiconductor layer, and between the second electrode and the second doped semiconductor layer, the number of the first opening and the second opening, etc. can be adjusted to reduce the mismatch in the film quality of the first electrode and the second electrode, the contact resistance and bonding force between the first electrode and the first doped semiconductor layer, and between the second electrode and the second doped semiconductor layer, and the number of the first opening and the second opening caused by the different materials, doping concentrations, and conductivity of the first doped semiconductor layer and the second doped semiconductor layer. This helps ensure that the contact resistance and bonding force between the first electrode and the first doped semiconductor layer, and between the second electrode and the second doped semiconductor layer, and the number of the first opening and the second opening meet the design requirements of the solar cell, and the film quality of the first electrode and the second electrode also meets the solar cell design, thereby improving the structural stability of the solar cell. In addition, during the solar cell manufacturing process, the P region and N region of the solar cell can be effectively identified based on the different surface roughness. In addition, compared with directly using a high-temperature sintering process to form electrodes, the present application can form electrodes at the openings using a low-temperature metallization process, which can reduce the cost of the metallization process.

[0127] Exemplarily, the first surface roughness is greater than the second surface roughness. For example, FIG8-5 shows the surface of the first doped semiconductor layer in the region exposed to the first opening, which has the first surface roughness. FIG8-6 shows the surface of the second doped semiconductor layer in the region exposed to the second opening, which has the second surface roughness. By comparing FIG8-5 and FIG8-6 , it can be seen that the first surface roughness is greater than the second surface roughness.

[0128] In the above technical solution, the first surface roughness is the surface roughness of the region of the first doped semiconductor layer exposed to the first opening, that is, the surface roughness of the region of the N-type doped semiconductor layer exposed to the first opening. In the embodiments of the present application, by relatively increasing the first surface roughness, the contact area between the N-type doped semiconductor layer and the electrode can be relatively increased, the contact resistance between the N-type doped semiconductor layer and the electrode can be reduced, and the bonding strength between the N-type doped semiconductor layer and the electrode can be improved. In some examples, because the contact resistance between the N-type doped semiconductor layer and the electrode is low and the bonding strength between the N-type doped semiconductor layer and the electrode is high, the number of first openings corresponding to the N region of the N-type doped semiconductor layer can be reduced while satisfying the bonding strength and contact resistance requirements. In other words, the number of first openings is less than the number of second openings. This reduction in the number of first openings can improve the efficiency of forming the first openings in the dielectric layer and reduce damage to the N-type doped semiconductor layer caused by laser die cutting, which can help ensure the passivation effect of the N region.

[0129] In some embodiments, the first surface roughness is smaller than the second surface roughness. For example, FIG8-7 shows the surface of the first doped semiconductor layer in the area exposed to the first opening, and the surface has the first surface roughness. FIG8-8 shows the surface of the second doped semiconductor layer in the area exposed to the second opening, and the surface has the second surface roughness. By comparing FIG8-7 and FIG8-8, it can be seen that the first surface roughness is smaller than the second surface roughness.

[0130] The second surface roughness is the surface roughness of the area of ​​the second doped semiconductor layer (i.e., the P-type doped semiconductor layer in this embodiment) exposed to the second opening. Since the electrical conductivity of the P-type doped semiconductor layer is greater than the electrical conductivity of the N-type doped semiconductor layer, that is, the electrical conductivity of the P-type doped semiconductor layer is higher, the contact resistance between the P-type doped semiconductor layer and the second electrode is relatively large. In the embodiment of the present application, by relatively increasing the second surface roughness corresponding to the P-type doped semiconductor layer, the contact area between the P-type doped semiconductor layer and the second electrode can be relatively increased, and the contact resistance between the P-type doped semiconductor layer and the second electrode can be reduced, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. Furthermore, the bonding force between the P-type doped semiconductor layer and the electrode can be enhanced, further enhancing the connection strength between the two, reducing the risk of the electrode falling off from the P-type doped semiconductor layer, and improving the structural reliability of the solar cell.

[0131] It should be noted that the first surface roughness and the second surface roughness can be controlled by controlling laser parameters such as laser energy, laser spot size, laser spot overlap rate, laser irradiation area, laser energy at different positions, etc., or by controlling the composition, concentration, time, etc. of the etching solution.

[0132] Exemplarily, a region of the first doped semiconductor layer covered by the dielectric layer has a third surface roughness; and the first surface roughness is greater than the third surface roughness.

[0133] The embodiments of the present application employ the above-described technical solution to relatively increase the surface roughness of the portion of the first doped semiconductor layer exposed in the opening. This can relatively increase the contact area between the first doped semiconductor layer and the first electrode, thereby reducing the contact resistance between the first electrode and the first doped semiconductor layer. Furthermore, it increases the bonding force between the first electrode and the first doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the first electrode detaching from the first doped semiconductor layer, and improving the structural reliability of the solar cell. Furthermore, by setting the third surface roughness of the region of the first doped semiconductor layer covered by the dielectric layer to be relatively low, it can ensure good film quality of the dielectric layer formed on the first doped semiconductor layer, thereby ensuring that the dielectric layer has a good passivation effect on the first doped semiconductor layer.

[0134] Exemplarily, the area of ​​the second doped semiconductor layer covered by the dielectric layer has a fourth surface roughness, and the second surface roughness is greater than the fourth surface roughness. This technical effect can refer to the technical effect corresponding to the first surface roughness being greater than the third surface roughness.

[0135] Exemplarily, a region of the first doped semiconductor layer covered by the dielectric layer has a third surface roughness, a region of the second doped semiconductor layer covered by the dielectric layer has a fourth surface roughness, and the third surface roughness is smaller than the fourth surface roughness.

[0136] The third surface roughness is the surface roughness of the region of the first doped semiconductor layer (i.e., the N-type doped semiconductor layer in this embodiment) covered by the dielectric layer, and the fourth surface roughness is the surface roughness of the region of the second doped semiconductor layer (i.e., the P-type doped semiconductor layer in this embodiment) covered by the dielectric layer. It is understood that the doping concentration of the P-type doped semiconductor layer is generally lower than that of the N-type doped semiconductor layer, i.e., the second doped semiconductor layer has a lower doping concentration than the first doped semiconductor layer. Therefore, the conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer. When the third and fourth surface roughnesses are the same, the contact resistance between the P-type doped semiconductor layer and the second electrode is greater than the contact resistance between the N-type doped semiconductor layer and the first electrode. To ensure that the contact resistances of the P and N regions are the same or similar, thereby achieving good photoelectric conversion efficiency for the solar cell, the fourth surface roughness is made greater than the third surface roughness. This increases the contact area between the second doped semiconductor layer and the second electrode, thereby reducing the contact resistance between the P-type doped semiconductor layer and the second electrode.

[0137] Exemplary embodiments of achieving a difference between the first surface roughness and the second surface roughness include: forming a plurality of first holes 15-1 in the region of the first doped semiconductor layer exposed to the first opening, forming a plurality of second holes 15-2 in the region of the second doped semiconductor layer exposed to the second opening, forming a circle of annular protrusions at the edges of the first holes 15-1 and the edges of the second holes 15-2, and having an average height of the annular protrusions 16-1 of the first holes being different from the average height of the annular protrusions 16-2 of the second holes. As shown in FIG8-3 , the circular (or quasi-circular) region surrounded by the bright circle represents the first holes 15-1, and the bright circle represents the circle of annular protrusions 16-1 formed at the edges of the first holes 15-1; and the circular (or quasi-circular) region surrounded by the bright circle represents the second holes 15-2, and the bright circle represents the circle of annular protrusions 16-2 formed at the edges of the second holes 15-2.

[0138] The features of the first hole 15 - 1 , the second hole 15 - 2 , the annular protrusion 16 - 1 of the first hole, and the annular protrusion 16 - 2 of the second hole are the same as those described in the above embodiment and will not be repeated here.

[0139] It should be noted that in the embodiment of the present application, the first hole 15-1 does not penetrate the first doped semiconductor layer 12-1 and is a blind hole. Similarly, the second hole 15-2 does not penetrate the second doped semiconductor layer 12-2 and is a blind hole.

[0140] The embodiment of the present application adopts the above-mentioned technical solution, and the surface roughness of the opening area (including the area of ​​the first opening and the area of ​​the second opening) can be adjusted by using the holes and the annular protrusions, so that the area of ​​the doped semiconductor layer exposed in the opening on the side away from the semiconductor substrate forms an uneven surface feature, which is beneficial to increase the surface roughness and specific surface area. Based on this, since the electrodes (including the first electrode and the second electrode) of the solar cell provided by the present application are formed on the doped semiconductor layer with an uneven surface, the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, which is beneficial to increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. Further, the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, which is beneficial to reduce the contact resistance between the electrode and the doped semiconductor layer, and improve the photoelectric conversion efficiency of the solar cell. Moreover, the different average heights of the annular protrusions result in different surface roughnesses in the area of ​​the first opening and the area of ​​the second opening. Therefore, the first surface roughness and the second surface roughness can be controlled by adjusting the average height of the annular protrusions to achieve the technical effect of the difference between the first surface roughness and the second surface roughness. Please refer to the above and will not repeat them here.

[0141] For example, the average height of the annular protrusions can be measured using the following method: the same number of annular protrusions are selected at the same or approximately the same position in the first opening region and the second opening region, and the average height of the annular protrusions is calculated to obtain the average height of the annular protrusions of the first hole and the annular protrusions of the second hole. In this regard, for example, when the distance between a position in the first opening region and the center of the first opening region is equal to the distance between a position in the second opening region and the center of the second opening region, the position in the first opening region and the position in the second opening region constitute the same position in the first opening region and the second opening region, respectively; when the difference between the distance between a position in the first opening region and the center of the first opening region and the distance between a position in the second opening region and the center of the second opening region is less than a distance value or a tolerance, the position in the first opening region and the position in the second opening region constitute approximately the same position in the first opening region and the second opening region, respectively.

[0142] Illustratively, the average height of the annular protrusion 16 - 1 of the first hole is greater than the average height of the annular protrusion 16 - 2 of the second hole.

[0143] By adopting the above technical solution, the average height of the annular raised portion 16-1 of the first hole is relatively increased, which can relatively increase the surface roughness of the area of ​​the N-type doped semiconductor layer exposed to the first opening corresponding to the first hole. This can relatively increase the contact area between the N-type doped semiconductor layer and the first electrode, reduce the contact resistance between the N-type doped semiconductor layer and the first electrode, and improve the bonding strength between the N-type doped semiconductor layer and the first electrode. In some examples, because the contact resistance between the N-type doped semiconductor layer and the first electrode is low and the bonding strength between the N-type doped semiconductor layer and the first electrode is high, the number of first openings corresponding to the N region of the N-type doped semiconductor layer can be reduced while maintaining the bonding strength and contact resistance. In other words, the number of first openings is smaller than the number of second openings. This reduction in the number of first openings can reduce damage to the N-type doped semiconductor layer caused by laser die cutting, which can help ensure the passivation effect of the N region.

[0144] Illustratively, the average height of the annular protrusion 16 - 2 of the second hole is greater than the average height of the annular protrusion 16 - 1 of the first hole.

[0145] Using the above technical solution, the average height of the annular raised portion 16-2 of the second hole is greater than the average height of the annular raised portion 16-1 of the first hole. Therefore, the second surface roughness of the region of the P-type doped semiconductor layer exposed to the second opening corresponding to the second hole is greater than the first surface roughness of the region of the N-type doped semiconductor layer exposed to the first opening corresponding to the first hole. Because the electrical conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer, that is, the P-type doped semiconductor layer has a higher electrical conductivity, the contact resistance between the P-type doped semiconductor layer and the second electrode is greater. In the embodiments of the present application, by relatively increasing the second surface roughness corresponding to the P-type doped semiconductor layer, the contact area between the P-type doped semiconductor layer and the second electrode is relatively increased, thereby reducing the contact resistance between the P-type doped semiconductor layer and the second electrode, which is beneficial for improving the photoelectric conversion efficiency of the solar cell. Furthermore, the bonding force between the P-type doped semiconductor layer and the electrode is enhanced, further strengthening the connection strength between the two, reducing the risk of the electrode detaching from the P-type doped semiconductor layer, and improving the structural reliability of the solar cell.

[0146] Exemplarily, a plurality of first holes 15-1 are formed in the region of the first doped semiconductor layer exposed to the first opening 14-1, and a plurality of second holes 15-2 are formed in the region of the second doped semiconductor layer exposed to the second opening 14-2; wherein the number of second holes 15-2 per unit area located in the middle region of the second opening 14-2 is greater than the number of first holes 15-1 per unit area located in the middle region of the first opening 14-1.

[0147] For example, as shown in Figures 8-3 and 8-4, the areas enclosed by large red circles in both figures are the middle areas of the first opening 14-1 and the middle areas of the second opening 14-2, respectively, with the remaining areas being the edges of the openings. As can be seen from both figures, the number of second holes 15-2 per unit area in the middle area of ​​the second opening 14-2 is greater than the number of first holes 15-1 per unit area in the middle area of ​​the first opening 14-1.

[0148] Because the conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer, the contact resistance between the P-type doped semiconductor layer and the second electrode is relatively large. Furthermore, when the electrode contacts the doped semiconductor layer at the opening, the main point of tension is concentrated in the middle region of the opening. The middle region of the second opening has a large number of holes per unit area, which helps increase the roughness of the middle region of the second opening, thereby increasing the contact area between the second electrode and the second doped semiconductor layer in the middle region of the second opening, reducing the contact resistance between the P-type doped semiconductor layer and the second electrode, and improving the photoelectric conversion efficiency of the solar cell. Furthermore, this can enhance the bonding force between the second electrode and the second doped semiconductor layer, strengthen the connection strength between the two, reduce the risk of the electrode falling off the P-type doped semiconductor layer, and improve the structural reliability of the solar cell.

[0149] It is understandable that in different embodiments, for example, under different laser conditions, the number of first holes per unit area in the middle region of the first opening may be greater than the number of second holes per unit area in the middle region of the second opening.

[0150] Exemplarily, a plurality of first holes 15-1 are formed in the region of the first doped semiconductor layer exposed to the first opening 14-1, and a plurality of second holes 15-2 are formed in the region of the second doped semiconductor layer exposed to the second opening 14-2; wherein the average radial maximum dimension of the holes located in the central region of the second opening 14-2 is greater than the average radial maximum dimension of the holes located in the central region of the first opening 14-1. Exemplarily, the average radial maximum dimension can be measured using the following method: the same number of first holes and second holes are selected at the same or nearly the same locations in the regions of the first holes and the second holes, respectively, and the average of their radial maximum dimensions is calculated to obtain the average radial maximum dimension of the first holes and the second holes.

[0151] Still referring to FIG. 8-3 and FIG. 8-4 , it can be seen that the average radial maximum size of the holes in the middle region of the second opening 14 - 2 is larger than the average radial maximum size of the holes in the middle region of the first opening 14 - 1 .

[0152] Because the conductivity of the P-type doped semiconductor layer is greater than that of the N-type doped semiconductor layer, that is, the conductivity of the P-type doped semiconductor layer is higher, the contact resistance between the P-type doped semiconductor layer and the second electrode is relatively large. In the embodiment of the present application, by increasing the average radial maximum dimension of the holes in the middle region of the second opening corresponding to the P-type doped semiconductor layer, the corresponding second surface roughness is relatively increased, which can relatively increase the contact area between the P-type doped semiconductor layer and the second electrode, reduce the contact resistance between the P-type doped semiconductor layer and the second electrode, and is beneficial to improving the photoelectric conversion efficiency of the solar cell. Furthermore, the bonding force between the P-type doped semiconductor layer and the electrode can be enhanced, further strengthening the connection strength between the two, reducing the risk of the electrode falling off the P-type doped semiconductor layer, and improving the structural reliability of the solar cell.

[0153] It is understandable that in different embodiments, for example, under different laser conditions, the average radial maximum size of the holes in the middle area of ​​the first opening may be larger than the average radial maximum size of the holes in the middle area of ​​the second opening.

[0154] For example, the doping concentration of the first doped semiconductor layer located at the first opening 14-1 on the side away from the semiconductor substrate is greater than the doping concentration on the side closer to the semiconductor substrate. And / or, the doping concentration of the second doped semiconductor layer located at the second opening 14-2 on the side away from the semiconductor substrate is greater than the doping concentration on the side closer to the semiconductor substrate. The effect of this example refers to the effect of the doping concentration of the doped semiconductor layer located at the opening on the side away from the semiconductor substrate being greater than the doping concentration on the side closer to the semiconductor substrate, and will not be repeated here.

[0155] For example, referring to Figures 8-9 and 8-10, the difference between the doping concentration of the first doped semiconductor layer located at the first opening 14-1 on the side away from the semiconductor substrate and the doping concentration on the side closer to the semiconductor substrate is a first difference; the difference between the doping concentration of the second doped semiconductor layer located at the second opening 14-2 on the side away from the semiconductor substrate and the doping concentration on the side closer to the semiconductor substrate is a second difference; the first difference is greater than the second difference. The abscissa in Figures 8-9 represents the depth of the first doped semiconductor layer along the direction from the surface of the first doped semiconductor layer close to the first electrode to the surface of the first doped semiconductor layer close to the semiconductor substrate, and the ordinate represents the doping concentration of the first doped semiconductor layer. The abscissa in Figures 8-10 represents the depth of the second doped semiconductor layer along the direction from the surface of the second doped semiconductor layer close to the second electrode to the surface of the second doped semiconductor layer close to the semiconductor substrate, and the ordinate represents the doping concentration of the second doped semiconductor layer. By comparing Figures 8-9 and 8-10, it can be seen that the first difference between the doping concentration of the N-type doped semiconductor layer on the side away from the semiconductor substrate and the doping concentration on the side closer to the semiconductor substrate is greater.

[0156] The above technical solution, due to the large first difference, is beneficial for increasing the transmission speed of electrons in the first doped semiconductor layer, that is, facilitating the rapid transmission of electrons from the first doped semiconductor layer to the first electrode. This allows for a suitable reduction in the number of first openings, which in turn reduces damage to the first doped semiconductor layer. Furthermore, the large first difference means that the doping concentration of the first doped semiconductor layer located at the first opening, distal from the semiconductor substrate, increases more than the doping concentration of the first doped semiconductor layer located proximal to the semiconductor substrate. This reduces the contact resistance between the first electrode and the first doped semiconductor layer, thereby reducing the thickness of the first doped semiconductor layer. This not only saves costs but also improves the manufacturing efficiency of the solar cell.

[0157] It is understandable that in different embodiments, for example, under different laser conditions, the second difference may be greater than the first difference.

[0158] Illustratively, a portion of the first doped semiconductor layer exposed in the first opening 14-1 is formed with a plurality of discontinuous raised portions 21 on a side facing away from the semiconductor substrate; and / or a portion of the second doped semiconductor layer exposed in the second opening 14-2 is formed with a plurality of discontinuous raised portions 21 on a side facing away from the semiconductor substrate. The characteristics and effects of the discontinuous raised portions in this embodiment are the same as those described in the above embodiment and are not further described here.

[0159] Exemplarily, the number of discontinuous protrusions per unit area of ​​the edge region of the second opening 14 - 2 is greater than the number of discontinuous protrusions per unit area of ​​the edge region of the first opening 14 - 1 .

[0160] Using the above technical solution, it is generally not conducive to forming a second electrode on the P-type doped semiconductor layer because the doping concentration of the P-type doped semiconductor layer corresponding to the second opening 14-2 is low and the P-type doped semiconductor layer has the property of more holes and fewer electrons. It is understandable that when forming electrodes of the same thickness, the difficulty of forming the second electrode on the P-type doped semiconductor layer is greater than the difficulty of forming the first electrode on the N-type doped semiconductor layer corresponding to the first opening 14-1. In addition, for a single opening, the difficulty of forming an electrode in the edge region of the opening is greater than the difficulty of forming an electrode in the middle region of the opening. Based on this, in some embodiments of the present application, the number of discontinuous raised portions per unit area of ​​the P-type doped semiconductor layer located at the edge region of the second opening 14-2 is increased relative to the number of discontinuous raised portions per unit area of ​​the N-type doped semiconductor layer located at the edge region of the first opening 14-1. This can improve the fabrication effect of the electrode in the edge region of the second opening 14-2, thereby ensuring the quality of the electrode formed in the edge region of the second opening, making the quality of the electrodes formed in the edge region and the middle region of the second opening 14-2 more consistent, which is conducive to improving the carrier transmission effect in the second electrode.

[0161] It is understandable that in different embodiments, for example, under different laser conditions, the number of discontinuous protrusions per unit area of ​​the edge region of the first opening 14 - 1 is greater than the number of discontinuous protrusions per unit area of ​​the edge region of the second opening 14 - 2 .

[0162] Exemplarily, the number of discontinuous protrusions per unit area in the middle region of the first opening 14 - 1 is greater than the number of discontinuous protrusions per unit area in the middle region of the second opening 14 - 2 .

[0163] With the above technical solution, since the doping concentration of the N-type doped semiconductor layer corresponding to the first opening 14-1 is relatively high and the N-type doped semiconductor layer has the property of more electrons and fewer holes, it is advantageous to form an electrode on the N-type doped semiconductor layer. It can be understood that when forming electrodes of the same thickness, the difficulty of forming an electrode in the N-type doped semiconductor layer is less than the difficulty of forming an electrode in the P-type doped semiconductor layer corresponding to the second opening 14-2. In addition, for an opening, since the difficulty of forming an electrode in the middle region of the opening is less than the difficulty of forming an electrode in the edge region of the opening, that is, the difficulty of forming an electrode in the middle region of the N-type doped semiconductor layer is less, the speed of forming the electrode in the middle region of the N-type doped semiconductor layer is faster. However, too fast an electrode production speed is not conducive to improving adhesion. Therefore, in some embodiments of the present application, by setting the number of discontinuous protrusions per unit area of ​​the N-type doped semiconductor layer located in the middle region of the first opening relative to the number of discontinuous protrusions per unit area located in the middle region of the second opening, the specific surface area of ​​the middle region of the N-type doped semiconductor layer can be increased, thereby facilitating improving the bonding strength between the electrode in the middle region and the N-type doped semiconductor layer.

[0164] It is understandable that in different embodiments, for example, under different laser conditions, the number of discontinuous protrusions per unit area in the middle region of the second opening 14 - 2 is greater than the number of discontinuous protrusions per unit area in the middle region of the first opening 14 - 1 .

[0165] For the convenience of description, the doped semiconductor layer in the following embodiments of the present application may include a doped semiconductor layer, or may include at least one of the first doped semiconductor layer 12-1 and the second doped semiconductor layer 12-2; the opening in the following embodiments of the present application may include a type of opening, or may include at least one of the first opening 14-1 and the second opening 14-2; the hole in the following embodiments of the present application may include a type of hole, or may include at least one of the first hole 15-1 and the second hole 15-2; the annular protrusion in the following embodiments of the present application may include a type of annular protrusion, or may include at least one of the annular protrusion 16-1 of the first hole and the annular protrusion 16-2 of the second hole.

[0166] 1 and 2 , a groove 18 is formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate, and a plurality of holes are formed on a surface of the groove 18 away from the semiconductor substrate.

[0167] It is understandable that the greater the depth of the groove 18, the smaller the thickness of the portion of the doped semiconductor layer exposed in the opening. When the solar cell is in operation, the doped semiconductor layer can effectively shunt and collect photogenerated carriers of opposite conductivity types. The thickness of the doped semiconductor layer will affect the magnitude of its own shunting effect on photogenerated carriers. Based on this, the depth of the groove 18 and the minimum thickness of the doped semiconductor layer below the groove 18 can be determined according to the requirements for the carrier shunting ability of the doped semiconductor layer below the groove 18 in the actual application scenario.

[0168] As shown in Figure 3, the doped semiconductor layer has a first thickness d1 at the openings and a second thickness d2 at the non-openings, where the first thickness d1 is less than the second thickness d2. The thickness of the doped semiconductor layer at the openings is less than the thickness at the non-openings, which reduces the distance carriers travel from the semiconductor substrate to the electrode and lowers the longitudinal transmission resistance. In particular, for non-sintered electrodes, the thickness of the doped semiconductor layer can be made smaller, thereby reducing the longitudinal transmission resistance, ensuring that the doped semiconductor layer has a high carrier shunting capability, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0169] The specific morphology of the groove 18 can be determined according to the actual manufacturing process. For example, the side of the groove 18 can be a plane perpendicular to the surface of the semiconductor substrate; or, it can be a plane inclined to the surface of the semiconductor substrate; or, the side of the groove 18 can also be an arc-shaped surface that is concave on both sides. With such a configuration, compared with the side of the groove 18 being a plane, when the side of the groove 18 is an arc-shaped surface that is concave on both sides, the side of the groove 18 has a larger surface area, which can further increase the contact area between the electrode and the doped semiconductor layer, further reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the contact performance of the electrode.

[0170] For example, the longitudinal cross-section of groove 18 can be bowl-shaped. In this case, the sides of groove 18 are concave on both sides, which can increase the surface area of ​​the sides of groove 18, further reducing the risk of the electrode detaching from the doped semiconductor layer and improving the contact performance of the electrode. In addition, when the longitudinal cross-section of groove 18 is bowl-shaped, the morphology of groove 18 is relatively regular, preventing the occurrence of undesirable problems such as gaps during the process of filling groove 18 with conductive material used to manufacture the electrode, thereby ensuring a high yield of the solar cell.

[0171] Exemplarily, the doped semiconductor layer has a first thickness at the opening, and for the unexposed portion of the doped semiconductor layer that is not exposed at the opening: it includes a first unexposed portion at the opening edge of the dielectric layer and a remaining unexposed portion other than the first unexposed portion, the first unexposed portion has a third thickness, and the remaining unexposed portion has a fourth thickness, wherein the fourth thickness>the third thickness>the first thickness.

[0172] For example, along the thickness direction of the semiconductor substrate, the first thickness range of the doped semiconductor layer at the opening can be greater than or equal to 20 nm. For example, the first thickness of the doped semiconductor layer at the opening can be 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, or 150 nm. In this case, the minimum thickness of the portion of the doped semiconductor layer located below the opening is within the above range, which can prevent the portion of the doped semiconductor layer exposed in the opening from having a smaller thickness after forming a surface with holes, thereby ensuring that the doped semiconductor layer has a higher carrier shunting ability, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0173] Exemplarily, the number of holes per unit area in the middle region of the opening is greater than the number of holes per unit area in the edge region of the opening. Exemplarily, as shown in FIG8-2 , the number of holes 15 per unit area in the middle region of the opening is greater than the number of holes 15 per unit area in the edge region of the opening, i.e., the holes 15 in the middle region of the opening are denser than the holes 15 in the edge region.

[0174] Exemplarily, the middle region occupies 70% to 80% of the area of ​​the opening. Exemplarily, the middle region occupies 70%, 71%, 72%, 72.5%, 73%, 74%, 75%, 75.5%, 76%, 77%, 78%, 79%, 80% of the area of ​​the opening.

[0175] It is understandable that when the metal material of the electrode contacts the doped semiconductor layer at the opening, the main force point of the tension is concentrated in the middle area of ​​the opening. The number of holes in the middle area is relatively large compared to the number of holes in the edge area. The large number of holes in the middle area is conducive to increasing the contact area between the electrode and the doped semiconductor layer in the middle area. Therefore, the proportion of the middle area to the area of ​​the opening directly affects the stability of the electrode structure. At the same time, due to the large number of holes in the middle area, the recombination in the middle area will be serious. Therefore, if the middle area is too large, it will cause serious recombination at the dielectric layer corresponding to the opening, reducing the photoelectric conversion efficiency; if the middle area is too small, it will not play a role in effectively increasing the bonding force between the electrode and the doped semiconductor layer. Therefore, the above-mentioned proportion range of the middle area can not only effectively increase the contact area between the electrode and the doped semiconductor layer, thereby enhancing the bonding force between the electrode and the doped semiconductor layer, and further enhance the connection strength between the two, but also will not cause excessive recombination.

[0176] Exemplarily, the average radial maximum dimension of the holes located in the middle region of the opening is greater than the average radial maximum dimension of the holes located in the edge region of the opening. Exemplarily, the radial maximum dimension of the holes within the same area or the radial maximum dimension of the same number of holes can be measured in the middle region and the edge region respectively, and their average values ​​can be calculated to obtain the average radial maximum dimension of the holes in the middle region and the edge region. Since the main force points of the tension when the metal material of the electrode contacts the doped semiconductor layer at the opening are concentrated in the middle region of the opening, the larger average radial maximum dimension of the holes in the middle region is conducive to more metal deposition in the holes, thereby increasing the contact area between the electrode and the doped semiconductor layer, thereby enhancing the bonding force between the electrode and the doped semiconductor layer, further enhancing the connection strength between the two, reducing the risk of the electrode falling off the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0177] By adopting the above technical solution, when the metal material of the electrode contacts the doped semiconductor layer at the opening, the main force point of the tension is concentrated in the middle area of ​​the opening, and the number of holes per unit area in the middle area of ​​the present application is relatively large, which is beneficial to increase the roughness of the middle area of ​​the opening, and further beneficial to increase the contact area between the electrode and the doped semiconductor layer in the middle area of ​​the opening, thereby enhancing the bonding force between the electrode and the doped semiconductor layer, further enhancing the connection strength between the two, reducing the risk of the electrode falling off the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0178] For example, at least two holes 15 are in contact with each other. Thus, when an electrode is formed on the doped semiconductor layer, the conductive material used to manufacture the electrode formed in the two or more holes in contact with each other is electrically connected together. This can increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell.

[0179] Exemplarily, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer exposed in the opening away from the semiconductor substrate.

[0180] With the above technical solution, after the dielectric layer is opened, it is necessary to use an etching solution to remove the residue. Since amorphous silicon has good corrosion resistance, amorphous silicon is distributed on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. In this way, the amorphous silicon can protect the doped polycrystalline silicon layer below it, preventing the doped polycrystalline silicon layer below the amorphous silicon from being severely damaged by the etching solution, thereby causing serious recombination. In addition, amorphous silicon has a good passivation effect, which is beneficial to reducing the recombination caused by direct contact between the doped polycrystalline silicon layer and the electrode.

[0181] Optionally, when the doped semiconductor layer is a doped polycrystalline silicon layer, the portion of the doped semiconductor layer exposed in the opening on a side facing away from the semiconductor substrate may further include at least one of microcrystalline silicon and nanocrystalline silicon. The beneficial effects of microcrystalline silicon and / or nanocrystalline silicon are similar to those of amorphous silicon, and reference may be made to the above description, which will not be further elaborated here.

[0182] Exemplarily, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at the edge of the opening of the dielectric layer, below the dielectric layer, and disposed on a side of the doped polysilicon layer away from the semiconductor substrate.

[0183] With the above technical solution, after the dielectric layer is opened, it is necessary to use an etching liquid to remove the residue. When the etching liquid is used to remove the residue, the edge of the opening of the dielectric layer and the portion located below the dielectric layer will also be side-etched. In this case, since amorphous silicon has good corrosion resistance, amorphous silicon is distributed at the edge of the opening of the dielectric layer and below the dielectric layer, on the side of the doped polysilicon layer facing away from the semiconductor substrate. In this way, the amorphous silicon can protect the doped polysilicon layer below it, preventing the doped polysilicon layer below the amorphous silicon layer from being severely damaged by the etching liquid, thereby causing serious recombination. In addition, amorphous silicon has a good passivation effect, which is beneficial to reducing the recombination loss caused by direct contact between the doped polysilicon layer and the electrode.

[0184] Exemplarily, the length of the amorphous silicon distributed along a direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than 0 μm and less than or equal to 6 μm. Here, the length of the amorphous silicon distributed is calculated as the length from the edge of the opening of the dielectric layer, along a direction parallel to the semiconductor substrate and away from the edge of the opening, to the farthest amorphous silicon. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate.

[0185] Based on the role of amorphous silicon described above, it can be seen that if the length range of the amorphous silicon is too large, since the lateral transmission resistance of amorphous silicon is larger than that of polycrystalline silicon, it is not conducive to the lateral transmission of carriers, which will reduce the photoelectric conversion efficiency of the solar cell. In addition, if the length range of the amorphous silicon is large, a large amount of heat is required when forming the opening in the dielectric layer. The large amount of heat will cause excessive damage to the doped semiconductor layer when forming the opening in the dielectric layer, resulting in poor passivation effect of the doped semiconductor layer. Therefore, in this application, the length of the amorphous silicon distributed from the edge of the opening in the dielectric layer along the direction parallel to the semiconductor substrate is less than or equal to 6μm.

[0186] Furthermore, if the length range of the distributed amorphous silicon is too small, it will not be able to effectively prevent corrosion when the side erosion is severe, and the passivation effect will not be obvious. Therefore, in some examples, the length of the distributed amorphous silicon is greater than or equal to 0.001 μm from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate.

[0187] The length of the amorphous silicon distribution may be, for example, 0.001 μm, 0.007 μm, 0.01 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm, 5 μm or 6 μm.

[0188] Exemplarily, along the thickness direction of the semiconductor substrate, the depth of the amorphous silicon ranges from greater than 0 nm to less than or equal to 350 nm.

[0189] In some embodiments, the depth of the amorphous silicon at the location where the portion of the doped semiconductor layer exposed at the opening facing away from the semiconductor substrate and where a protrusion (e.g., a ring-shaped protrusion or a discontinuous protrusion) is distributed is greater than the depth of the amorphous silicon at the location without the protrusion. Exemplarily, the depth of the amorphous silicon at the location where the portion of the doped semiconductor layer exposed at the opening facing away from the semiconductor substrate and where the protrusion is distributed is greater than 0 nm and less than or equal to 350 nm, while the depth of the amorphous silicon at the location without the protrusion is greater than 0 nm and less than or equal to 50 nm. Since the protrusion is formed by melting and resolidifying the material of the doped semiconductor layer in most cases, when the doped semiconductor layer is a doped polycrystalline silicon layer, the material of the protrusion is mainly amorphous silicon, and therefore the depth of the amorphous silicon at the protrusion is greater than the depth of the amorphous silicon at the non-protrusion.

[0190] In the above technical solution, considering that if the depth of amorphous silicon is too large, it will lead to a large carrier transmission resistance, thereby affecting the electrical performance of the solar cell, the depth of amorphous silicon is less than or equal to 350nm.

[0191] Furthermore, considering that if the depth range of amorphous silicon is too small, it cannot protect the underlying doped semiconductor layer and prevent the underlying doped semiconductor layer from being damaged by the corrosive liquid, and cannot effectively passivate the surface of the doped polysilicon, therefore, in some examples, the depth of amorphous silicon is greater than or equal to 0.001 nm.

[0192] The depth of the amorphous silicon along the thickness direction of the semiconductor substrate may be, for example, 0.001 nm, 0.005 nm, 0.009 nm, 0.01 nm, 0.05 nm, 0.1 nm, 0.8 nm, 1 nm, 6 nm, 10 nm, 50 nm, 100 nm, 200 nm or 350 nm.

[0193] 8-11 , pores 22 are formed at the edge of the opening of the dielectric layer 13 and between the dielectric layer 13 and the underlying doped semiconductor layer 12. The size and number of the pores 22 are not limited.

[0194] Typically, hydrogen is formed in the dielectric layer during its formation. For example, when the dielectric layer's material includes aluminum oxide, excess hydrogen is produced during the deposition of aluminum oxide due to the presence of water in the reaction. Another example is when depositing silicon nitride, residual nitrogen-hydrogen bonds are present. At high temperatures, these bonds break and recombine to produce hydrogen. Because the dielectric layer contains hydrogen, heat can cause hydrogen to escape from the dielectric layer during laser opening. This hydrogen escape can cause film cracking in areas outside the opening, damaging the dielectric layer and the doped semiconductor layer, thereby affecting the passivation performance of the solar cell.

[0195] In this embodiment, the pores 22 can provide space for hydrogen to escape during the laser mold opening process, thereby alleviating or avoiding the explosion of the dielectric layer in the non-opening area caused by the laser mold opening, and is conducive to accurately controlling the size of the opening area, and reducing the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, thereby effectively ensuring the passivation effect of the solar cell.

[0196] Exemplarily, the length of the pores 22 distributed from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 5 μm. Exemplarily, the length of the pores 22 distributed is calculated as the length from the edge of the opening of the dielectric layer, in a direction parallel to the semiconductor substrate and away from the edge of the opening, to the farthest pore. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate. Considering that if the length of the pores 22 is too large, for example, 10 μm, 20 μm or 30 μm or more, the dielectric layer is prone to cracking and falling off, resulting in affecting the passivation effect of the solar cell, thereby increasing the recombination loss of the doped semiconductor layer, the embodiment of the present application has a length of pores distributed from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate of less than or equal to 5 μm.

[0197] Furthermore, if the length of the distributed pores 22 is too small, hydrogen will escape during the laser mold opening process, and insufficient space will be provided for hydrogen escape, and the dielectric layer in the non-opening area will still be at risk of film explosion. Therefore, in some examples, the length of the distributed pores is greater than or equal to 0.01 μm starting from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate.

[0198] The length of the pores distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate may be, for example, 0.01 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm or 5 μm.

[0199] The above-mentioned length range of distributed pores provided in the present application can provide a reasonable space for the escape of hydrogen in the dielectric layer during the laser mold opening process, which can effectively alleviate or avoid the film explosion of the dielectric layer in the non-opening area caused by laser mold opening, which is conducive to accurately controlling the size of the opening area and reducing the damage caused by laser mold opening to the doped semiconductor layer in the non-opening area. It can also prevent the dielectric layer from being broken and falling off due to the excessive length of the distributed pores, which is conducive to avoiding the breakage and falling off of the dielectric layer affecting the passivation effect of the solar cell, thereby reducing the damage caused by laser mold opening and ensuring the passivation effect of the solar cell.

[0200] For example, from the edge of the opening of the dielectric layer 13 along a direction parallel to the semiconductor substrate layer, the length of the amorphous silicon is greater than the length of the pores 22. After the dielectric layer is molded, an etching solution is needed to remove the residue. During the process of removing the residue with the etching solution, the etching solution is more likely to remain in the pores and is not easy to flow out. In order to prevent the etching solution from corroding the doped polysilicon in the pores and damaging the doped polysilicon, in some embodiments of the present application, amorphous silicon is formed at the edge of the opening of the dielectric layer and below the dielectric layer on the side of the doped polysilicon layer facing away from the semiconductor substrate, and the length of the amorphous silicon is greater than the length of the pores.

[0201] Illustratively, the pores 22 include at least one metal material in the electrode.

[0202] The present application adopts the above-mentioned solution, and the pores 22 include at least one metal material in the electrode, which can increase the contact area between the electrode and the doped semiconductor layer. In this way, the contact resistance between the electrode and the doped semiconductor layer can be reduced, and the bonding force between the electrode and the doped semiconductor layer can be increased, thereby reducing the risk of the electrode detaching from the doped semiconductor layer and improving the structural reliability of the solar cell.

[0203] Exemplarily, the metal material includes one or more of nickel, copper, silver or tin.

[0204] The present application adopts the above-mentioned solution, and these metal materials are filled into the pores, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance between the electrode and the doped semiconductor layer, and increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, these metals can also block deep energy level impurities or other metals from diffusing into the doped semiconductor layer and the semiconductor substrate, thereby reducing the recombination of the doped semiconductor layer and the semiconductor substrate, and reducing the recombination loss.

[0205] For example, the portion of the dielectric layer near the opening warps away from the doped semiconductor layer. As indicated by the arrows in Figures 8-13, because the portion of the dielectric layer near the opening warps away from the doped semiconductor layer, a space is formed between the dielectric layer and the underlying doped semiconductor layer near the opening. This further provides space for hydrogen generated in the dielectric layer under the action of the laser during the laser mold opening process to escape, thereby alleviating or avoiding film explosion, reducing damage caused by laser mold opening, and preventing the dielectric layer from cracking and falling off, which could affect the passivation effect of the solar cell, thereby ensuring the passivation effect of the solar cell.

[0206] Exemplarily, the angle range of the warping of the portion of the dielectric layer near the opening in the direction away from the doped semiconductor layer is greater than 0° and less than or equal to 20°. The angle is the angle α shown in Figure 4. Exemplarily, the angle is the angle formed by the surface of the portion of the dielectric layer near the opening facing the doped semiconductor layer relative to the first surface of the semiconductor substrate, one side of the angle corresponds to the first surface of the semiconductor substrate and is parallel to the direction of the first surface of the semiconductor substrate, and the other side corresponds to the surface of the portion of the dielectric layer near the opening facing the doped semiconductor layer. Considering that if the angle of the warping of the portion of the dielectric layer near the opening in the direction away from the doped semiconductor layer is too large, for example, 30°, 40° or other larger angles, the dielectric layer is likely to crack and fall off, affecting the passivation effect of the solar cell and causing recombination loss of the doped semiconductor layer, the angle of the warping of the portion of the dielectric layer near the opening in the direction away from the doped semiconductor layer in the embodiment of the present application is less than or equal to 20°.

[0207] Furthermore, considering that if the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is too small, it will not be conducive to providing space for the escape of hydrogen during the laser mold opening process, and will cause the dielectric layer in the non-opening area of ​​the laser mold opening to have the risk of film explosion, therefore, in some examples, the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is greater than or equal to 0.001°.

[0208] The angle at which the portion of the dielectric layer near the opening is warped away from the doped semiconductor layer may be, for example, 0.001°, 0.005°, 0.01°, 0.05°, 0.09°, 1°, 6°, 9°, 10°, 12°, 15°, 18° or 20°.

[0209] The angle range in which the portion of the dielectric layer close to the opening provided in the embodiment of the present application is warped in a direction away from the doped semiconductor layer can provide a reasonable space for hydrogen in the dielectric layer to escape during the laser mold opening process, can alleviate or avoid the dielectric layer explosion in the non-opening area caused by the laser mold opening, and can reduce the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, and can prevent the dielectric layer from cracking and falling off due to excessive warping angles. Therefore, the above-mentioned angle range can ensure the passivation effect of the solar cell, reduce the damage caused by the laser mold opening, and avoid the rupture of the dielectric layer affecting the passivation effect of the solar cell.

[0210] For example, as shown in FIG8-12, a pit 23 is formed in the edge area of ​​the opening. FIG8-12 is a partial enlarged schematic diagram of point A in FIG8-3. The maximum radial dimension of the pit 23 is much smaller than the maximum radial dimension of the hole, and there is no annular protrusion around the pit 23 (as shown in the figure, there is no white bright circle around the pit 23). The pits 23 are mainly distributed in the edge area of ​​the opening. The pits are beneficial to increasing the surface roughness and specific surface area of ​​the edge area of ​​the opening, increasing the bonding force between the electrode and the doped semiconductor layer, strengthening the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0211] Exemplarily, when the doped semiconductor layer includes an N-type doped semiconductor layer, the pits 23 are distributed in edge regions of openings of the N-type doped semiconductor layer.

[0212] Generally, since the doping concentration of the N-type doped semiconductor layer is relatively high and the N-type doped semiconductor layer has the property of having more electrons and fewer holes, it is advantageous to form an electrode on the N-type doped semiconductor layer. It is understandable that when forming electrodes of the same thickness, the difficulty of forming an electrode on the N-type doped semiconductor layer is less than the difficulty of forming an electrode on the P-type doped semiconductor layer. That is, the speed of forming an electrode on the N-type doped semiconductor layer is relatively high, which will lead to reduced adhesion between the electrode and the N-type doped semiconductor layer. In addition, for an opening, since it is more difficult to form an electrode in the edge region of the opening than in the middle region of the opening, in some embodiments of the present application, since the pits 23 are distributed in the edge region of the opening of the N-type doped semiconductor layer, the specific surface area of ​​the edge region of the opening of the N-type doped semiconductor layer can be increased, the difficulty of forming the electrode in the edge region can be reduced, and the quality of the electrode formed in the edge region of the opening can be ensured. The contact area between the electrode and the N-type doped semiconductor layer located in the edge region of the opening can be increased, the bonding force between the electrode and the N-type doped semiconductor layer located in the edge region of the opening can be improved, and the contact resistance between the electrode and the N-type doped semiconductor layer located in the edge region of the opening can be reduced.

[0213] For example, referring to FIG8-2 , the dielectric layer 13 has a crack 24 formed near the edge of the opening. When forming an electrode at a position corresponding to the opening in the dielectric layer, since the dielectric layer has a crack 24 formed near the edge of the opening, the material forming the electrode can also be filled into the crack 24 and electrically connected to the doped semiconductor layer through the crack 24, thereby further enhancing the bonding strength between the electrode and the doped semiconductor layer. In addition, when the dielectric layer is opened, the crack formed at the edge of the opening in the dielectric layer is conducive to the escape of hydrogen, reducing the risk of film explosion, facilitating the precise control of the size of the opening in the dielectric layer, and avoiding damage to the doped semiconductor layer below the non-opening area, which may lead to severe recombination.

[0214] For example, as shown in Figures 8-13, silicon oxide is formed on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. In one embodiment, the thickness of the silicon oxide formed on the annular protrusion is relatively thick. Furthermore, the silicon oxide distribution in the peripheral area of ​​the annular protrusion (for the hole, the side away from the hole) is relatively concentrated, and the silicon oxide in the peripheral area of ​​the annular protrusion is thicker than the silicon oxide in the hole 15. It is understood that after the dielectric layer is opened, it is necessary to use an etching solution to remove the residue. When using the etching solution to remove the residue, since the silicon oxide is located above the doped semiconductor layer, the etching solution preferentially reacts with the silicon oxide, which can reduce the etching solution's corrosion of the next layer, i.e., the doped semiconductor layer, thereby reducing mold opening damage. In addition, silicon oxide has a good passivation effect. Silicon oxide can passivate the surface of the doped semiconductor layer, which is beneficial to reduce the recombination loss caused by direct contact between the doped semiconductor layer and the electrode.

[0215] It should be noted that in some examples, the silicon oxide formed on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate needs to be removed. Because the portion of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate has multiple holes formed thereon, the holes can increase the contact area between the electrode and the doped semiconductor layer, improve bonding strength, and reduce contact resistance. Therefore, in other examples, the silicon oxide formed on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate may not be removed.

[0216] For example, when the dielectric layer is made of aluminum oxide, the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate includes aluminum. Since aluminum is a metallic element, if there is residual aluminum on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate, the contact resistance between the electrode and the doped semiconductor layer can be reduced, which is more conducive to carrier shunting, reduces the carrier recombination rate, and further improves the photoelectric conversion efficiency of the solar cell.

[0217] For example, the portion of the doped semiconductor layer exposed in the opening has a through hole penetrating the doped semiconductor layer. Here, the size of the through hole penetrating the doped semiconductor layer can be nanometer-scale.

[0218] In some examples, a through hole penetrating the doped semiconductor layer is formed within a hole. When the portion of the doped semiconductor layer exposed in the opening includes a through hole penetrating the doped semiconductor layer, in some examples, when forming an electrode, the material forming the electrode can pass through the through hole and directly contact the semiconductor substrate. This allows a small amount of carriers generated by the semiconductor substrate to be directly transferred to the electrode, thereby reducing resistance, improving carrier shunting capability, and further increasing the photoelectric conversion rate of the solar cell.

[0219] In this embodiment, the electrode 17 can be a single-layer structure, such as shown in Figures 1, 2, 4 and 5; it can also be a stacked multi-layer structure, such as shown in Figures 9-1 and 9-2, where the electrode includes a stacked two-layer structure, namely a stacked conductive contact layer 17-2 and a connecting electrode 17-1.

[0220] For the back-contact solar cells shown in Figures 4-7 , the electrodes include a first electrode 17A and a second electrode 17B. The first electrode 17A and the second electrode 17B are disposed on a side of the dielectric layer 13 away from the semiconductor substrate 11. The first electrode 17A is electrically connected to the first doped semiconductor layer 12-1 through a first opening 14-1, and the second electrode 17B is electrically connected to the second doped semiconductor layer 12-2 through a second opening 14-2. Electrical connection, as used herein, may also be referred to as electrical coupling or electrical contact. At least one of the first electrode 17A and the second electrode 17B includes a stacked conductive contact layer 17-2 and a connecting electrode 17-1.

[0221] For the convenience of description, the electrodes in the following embodiments of the present application may include one electrode, or may include at least one of the first electrode 17A and the second electrode 17B, and the characteristics of at least one of the first electrode 17A and the second electrode 17B are the same as the characteristics of the electrodes described below.

[0222] The conductive contact layer 17 - 2 is located on a side of the electrode close to the doped semiconductor layer 12 , and the connecting electrode 17 - 1 is electrically connected to the doped semiconductor layer 12 through the conductive contact layer 17 - 2 .

[0223] When the electrode is a single-layer structure, the electrode can be formed by screen printing, chemical plating, electroplating, deposition, etching, etc. When the electrode comprises a stacked multi-layer structure, each film layer can be formed by electroplating, chemical plating, screen printing, deposition, etching, etc.

[0224] The electrode material can be a metal material such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc.; it can also be a metal oxide, including various types of TCO, such as ITO, AZO, IWO, etc.; it can also be a metal nitride, such as TiN, etc.; it can also be a metal carbide, such as TiC, etc.; it can also be a metal sulfide, etc., as well as other conductive connecting materials such as graphene, etc., or various combinations of the above materials. The material of the conductive contact layer 17-2 and the connecting electrode 17-1 can also be any of the above electrode materials or a suitable combination thereof.

[0225] It should be noted that if the electrode includes a conductive contact layer 17-2 and a connecting electrode 17-1, the material of the conductive contact layer 17-2 and the material of the connecting electrode 17-1 may be the same or different. The material and thickness of the conductive contact layer 17-2 can be determined according to the conductivity type of the doped semiconductor layer and the actual application scenario, and are not specifically limited here. In one possible implementation, the conductive contact layer 17-2 is formed by electroplating or chemical plating, and the material may be, for example, one or more of Ag, Ni, and Sn. The connecting electrode 17-1 is formed by silk screen printing, and the material may be, for example, silver paste, copper paste, or silver-coated copper paste.

[0226] It is understood that when the electrode includes a multi-layer structure, since the bottommost conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer with an uneven surface, it is beneficial to increase the bonding force between the conductive contact layer 17-2 and the doped semiconductor layer, reduce the risk of the conductive contact layer 17-2 detaching from the doped semiconductor layer, that is, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. Here, when the conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer with an uneven surface, the surface of the conductive contact layer 17-2 on the side facing away from the semiconductor substrate can be flat or uneven. When the surface of the conductive contact layer 17-2 on the side facing away from the semiconductor substrate also has uneven surface features, when forming the connecting electrode 17-1, it is beneficial to increase the contact area between the conductive contact layer 17-2 and the connecting electrode 17-1, improve the bonding force between the conductive contact layer 17-2 and the connecting electrode 17-1, that is, further increase the bonding force between the electrode and the doped semiconductor layer, and further reduce the risk of the electrode detaching from the doped semiconductor layer. When the electrode is a single-layer structure, the electrode is formed on the surface of the uneven doped semiconductor layer, which is beneficial to increase the bonding force between the electrode and the doped semiconductor layer, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell.

[0227] An embodiment of the present application further provides a photovoltaic module, comprising a plurality of cell strings, wherein the plurality of cell strings can be connected together in series and / or in parallel. Each cell string comprises a plurality of solar cells and a plurality of interconnecting members, wherein the interconnecting members are used to connect the plurality of solar cells in series. It is understood that the interconnecting members are electrically connected to the electrodes of the plurality of solar cells, thereby connecting the plurality of solar cells in series. Here, the solar cell includes the solar cell of any of the above embodiments.

[0228] In addition, the above-mentioned interconnection member may be, for example, a soldering tape, a metal wire, a conductive tape, etc.

[0229] In the technology of forming electrodes using a low-temperature metallization process, a prerequisite for the smooth progress of low-temperature metallization is to ensure good contact between the electrode material and the surface of the doped semiconductor layer. If the contact is poor, low-temperature metallization will be difficult to carry out, or even impossible to carry out. However, using the existing electrode manufacturing method, after openings are opened in the dielectric layer through processes such as laser etching, the surface of the doped semiconductor layer needs to be pretreated before the electrode is formed to improve the contact performance between the electrode and the doped semiconductor layer. However, after the above pretreatment, the surface of the doped semiconductor layer exposed in the opening is relatively flat, which reduces the bonding force between the electrode and the doped semiconductor layer, resulting in a higher risk of the electrode detaching from the doped semiconductor layer, reducing the structural reliability of the solar cell.

[0230] To solve the above problems, the present invention provides a method for manufacturing a solar cell. The following describes the manufacturing process based on the cross-sectional views of the operations shown in Figures 10 to 15. Specifically, the method for manufacturing a solar cell includes the following steps:

[0231] First, a semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other. The conductivity type and surface morphology of the semiconductor substrate can be referred to above and will not be described in detail here.

[0232] In actual applications, when the first surface of the semiconductor substrate included in the solar cell faces the light and is a textured surface, the semiconductor substrate can be cleaned to remove impurities on the surface. Then, the first surface of the semiconductor substrate is textured using a texturing solution such as an alkaline solution to improve the semiconductor substrate's absorption of light.

[0233] Next, a doped semiconductor layer is formed on the first surface and / or the second surface. The material, conductivity type, formation location, and thickness of the doped semiconductor layer can be found in the previous text. The specific formation process of the doped semiconductor layer can be determined based on the formation location of the doped semiconductor layer on the semiconductor substrate.

[0234] For example, when the solar cell being manufactured is a double-sided contact cell, an intrinsic semiconductor layer can be formed on the first and / or second surfaces using a process such as chemical vapor deposition. Next, as shown in FIG10 , the intrinsic semiconductor layer is doped using a process such as diffusion or ion implantation to form a doped semiconductor layer.

[0235] For example, when the solar cell being manufactured is a back-contact cell, a deposition and doping process can be used to form a full-layer doped semiconductor layer on the first surface and / or the second surface. Subsequently, at least a portion of the doped semiconductor layer can be selectively removed using a process such as laser etching.

[0236] Next, as shown in Figure 11, a dielectric layer 13 is formed on the side of the doped semiconductor layer 12 facing away from the semiconductor substrate 11. Specifically, the dielectric layer 13 can be formed by chemical vapor deposition or physical vapor deposition. The material and thickness of the dielectric layer 13 can be referred to above.

[0237] Next, as shown in FIG. 11 and FIG. 12 , a penetrating opening 14 is formed on the dielectric layer 13 , so that at least a portion of the doped semiconductor layer 12 is exposed from the opening 14 .

[0238] The embodiments of the present invention do not specifically limit the method for forming the opening. For example, the opening can be formed using a laser etching process and / or a wet etching process. When the opening is formed using a laser etching process and a wet etching process, the opening can be first formed using the laser etching process, and then processed using the wet etching process. Alternatively, the opening can be formed using a process such as wet etching or dry etching under the masking effect of a corresponding mask layer.

[0239] It is worth noting that the laser etching process has a high etching precision. Therefore, when using the laser etching process to form an opening in the dielectric layer, the formation precision of the opening can be improved, thereby improving the formation precision of the electrode and improving the yield of the manufactured solar cell. In addition, as shown in Figure 11, the specific etching depth corresponding to the formation of the opening 14 can be equal to the thickness of the dielectric layer 13. In this case, the dielectric layer 13 is just etched through, reducing the damage caused by the etching process to the portion of the doped semiconductor layer 12 exposed in the opening 14. Alternatively, as shown in Figure 12, the etching depth can be slightly greater than the thickness of the dielectric layer 13. In this case, the portion of the doped semiconductor layer 12 exposed in the opening 14 is also etched to a certain depth to ensure that the dielectric layer 13 is etched through, thereby ensuring that the electrode can pass through the dielectric layer 13 and electrically connect to the doped semiconductor layer 12. At the same time, there is no need to strictly control the etching precision to require the etching depth to be equal to the thickness of the dielectric layer 13, thereby reducing the etching difficulty. Among them, when the specific etching depth corresponding to the formation of the opening 14 is slightly greater than the thickness of the dielectric layer 13, silicon residues are likely to remain on the surface of the portion of the doped semiconductor layer 12 exposed in the opening 14.

[0240] Next, as shown in FIG13 , a plurality of holes are formed on the side of the doped semiconductor layer 12 exposed in the opening 14, facing away from the semiconductor substrate 11. It will be appreciated that the opening and the holes can be formed in the same process step or in different process steps, for example, by forming the opening first and then the holes.

[0241] Exemplarily, a groove 18 is formed on a side of the portion of the doped semiconductor layer 12 exposed in the opening 14 away from the semiconductor substrate 11 , and a plurality of holes are formed on a surface of the groove 18 .

[0242] In some other examples, a hole is directly formed on the side of the portion of the doped semiconductor layer 12 exposed in the opening 14 facing away from the semiconductor substrate 11 , without including the groove 18 .

[0243] Exemplarily, a wet etching process can be used to form a groove on the side of the doped semiconductor layer exposed in the opening that is away from the semiconductor substrate, and to form a plurality of holes on the surface of the groove. Specifically, the etching solution can contain ammonium bifluoride and / or ammonium fluoride, so that the silicon residue remaining on the semiconductor substrate after the opening is opened, and optionally, the oxide formed on the doped semiconductor layer exposed in the opening after etching can be removed by the etching solution, thereby ensuring good contact performance between the electrode subsequently formed on the groove and the doped semiconductor layer. Moreover, the etching solution corrodes the part of the doped semiconductor layer exposed in the opening, forming a groove with holes on the surface. In addition, in actual application, the material of the dielectric layer usually includes silicon nitride. Compared with hydrogen fluoride solution, the acidity of ammonium bifluoride solution and ammonium fluoride solution is moderate. Specifically, when the etching solution contains ammonium bifluoride and / or ammonium fluoride, the etching solution can dissolve the above-mentioned oxides and silicon residues, and form grooves with holes on the surface of the doped semiconductor layer without causing a significant impact on the dielectric layer including silicon nitride, thereby preventing the etching solution from excessively corroding the dielectric layer during the groove formation process, ensuring that the dielectric layer has a good passivation effect, and at the same time ensuring that the openings and electrodes have high forming accuracy.

[0244] In actual application, the concentration of the above-mentioned etching solution and the specific process conditions of wet etching can be determined according to the type of etching solution, the size of the groove to be formed, and the size and number of holes arranged on the groove surface, and are not specifically limited here.

[0245] Exemplarily, when the etching solution contains ammonium bifluoride and / or ammonium fluoride, the concentration of fluoride ions in the etching solution can be greater than or equal to 2 g / L and less than or equal to 13 g / L. For example, the concentration of fluoride ions in the etching solution can be 2 g / L, 5 g / L, 7 g / L, 10 g / L or 12 g / L. In this case, the etching solution mainly removes oxides and silicon residues and forms grooves by reacting fluoride ions with silicon ions in the oxide, or by reacting fluoride ions with silicon atoms to form silicon tetrafluoride. Based on this, the concentration of fluoride ions within the above range can prevent the etching solution from having a poor etching effect on the above-mentioned silicon residues and oxides due to a low concentration of fluoride ions, thereby ensuring good contact performance between the electrode and the doped semiconductor layer; at the same time, it can also prevent the etching solution from etching grooves and holes at a low rate, which is conducive to improving manufacturing efficiency. In addition, it can also prevent the high concentration of fluorine ions from causing the formation rate of grooves and holes to be fast and making it difficult to control the end time of etching, thereby ensuring that the morphology of the grooves and holes meets the working requirements; at the same time, it can also prevent the etching solution from having a large impact on the dielectric layer during the formation of grooves and holes, thereby ensuring that the dielectric layer has a good passivation effect and a high opening forming accuracy.

[0246] Specifically, when the etching solution contains ammonium bifluoride and / or ammonium fluoride, the concentration of ammonium bifluoride and / or ammonium fluoride in the etching solution can be determined based on the concentration of fluoride ions in the etching solution. For example, when the etching solution contains ammonium bifluoride but does not contain ammonium fluoride, the concentration of ammonium bifluoride in the etching solution can be greater than or equal to 5 g / L and less than or equal to 20 g / L.

[0247] Exemplarily, the etching time corresponding to the above-mentioned wet etching process can be greater than or equal to 10s and less than or equal to 60s. For example, the above-mentioned etching time can be 10s, 20s, 30s, 40s, 50s or 60s, etc. In this case, within a certain range, the etching time corresponding to the wet etching process is proportional to the size of the grooves and holes formed. Therefore, when the etching time is within the above-mentioned range, it can prevent the grooves from having a lower surface roughness due to the shorter etching time, resulting in a smaller groove formation depth and a smaller hole diameter, thereby ensuring that the contact area between the electrode and the portion of the doped semiconductor layer corresponding to the groove is larger. In addition, it can also prevent the thickness of the portion of the doped semiconductor layer remaining below the groove from being smaller due to the longer etching time, thereby ensuring that the doped semiconductor layer has good carrier shunting ability, thereby ensuring that the solar cell has good working performance.

[0248] For example, the process temperature corresponding to the wet etching process may be greater than or equal to 15° C. and less than or equal to 30° C. For example, the process temperature may be 15° C., 18° C., 20° C., 22° C., 24° C., 26° C., 28° C., or 30° C. The beneficial effects in this case are similar to the beneficial effects of the wet etching process having an etching time greater than or equal to 10 seconds and less than or equal to 60 seconds, and are not further described here.

[0249] Furthermore, in actual applications, the etching solution may contain additives to minimize the etching rate of the dielectric layer during the groove formation process, further improving the passivation effect of the dielectric layer on the doped semiconductor layer and further improving the forming accuracy of the opening and electrode. For example, the etching solution described above may contain additives.

[0250] The types of the above-mentioned additives and their concentrations in the etching solution can be determined according to the type of etching solution and the actual application scenario, as long as they can hinder the etching solution from corroding the dielectric layer.

[0251] Exemplarily, the additive may include at least one of 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, and sodium acetate. For example, the additive may be only 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, or sodium acetate. Another example: the additive may include any two of 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, and sodium acetate. Another example: the additive may include any three of 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, and sodium acetate. Another example: the additive may include 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, and sodium acetate. In this case, 3-ethylbutoxypropylamine, aniline acid, sodium benzoate, and sodium acetate have good solubility and dispersibility in the etching solution and easily form steric hindrance on the surface of the dielectric layer, hindering the contact between ammonium bifluoride and / or ammonium fluoride and the dielectric layer. As a result, the etching solution has an extremely low corrosion rate on the dielectric layer during the groove formation process, further improving the passivation effect of the dielectric layer on the doped semiconductor layer and further improving the formation accuracy of the opening and electrode.

[0252] Exemplarily, in the above-mentioned etching solution, the concentration of the additive can be greater than or equal to 0.5 ml / L and less than or equal to 5 ml / L. For example, the concentration of the additive can be 0.5 ml / L, 1 ml / L, 2 ml / L, 3 ml / L, 4 ml / L or 5 ml / L, etc. In this case, the concentration of the additive in the etching solution is within the above-mentioned range, which can prevent the steric hindrance formed by the additive on the surface of the dielectric layer due to the low concentration of the additive, thereby ensuring that the etching efficiency of the dielectric layer is low. In addition, it can also prevent the etching solution from corroding silicon residues and oxides due to a high concentration of the additive, and from affecting the formation of grooves and holes, thereby ensuring that the electrode and the doped semiconductor layer have a high connection strength and contact performance.

[0253] Secondly, when the electrodes are subsequently formed using an electroplating process, the etching solution may contain a surfactant to reduce the surface tension of the electroplating pretreatment solution, thereby enhancing its wettability in the small pores formed on the surface of the grooves. This facilitates filling the pores with the metal material used to form the electrodes, ensuring a large contact area between the electrodes and the doped semiconductor layer. For example, the etching solution may contain a surfactant.

[0254] The type of the above-mentioned surfactant and the concentration of the surfactant in the etching solution can be determined according to the type of etching solution and the actual application scenario, as long as the surface tension of the electroplating pretreatment solution can be reduced.

[0255] Exemplarily, the surfactant may include at least one of perfluorotriethylamine, perfluorohexyl sulfonyl ammonium and perfluorohexyl sulfonyl fluoride. For example, the surfactant may be perfluorotriethylamine, perfluorohexyl sulfonyl ammonium or perfluorohexyl sulfonyl fluoride. For another example, the surfactant may include any two of perfluorotriethylamine, perfluorohexyl sulfonyl ammonium and perfluorohexyl sulfonyl fluoride. For another example, the surfactant may include perfluorotriethylamine, perfluorohexyl sulfonyl ammonium and perfluorohexyl sulfonyl fluoride. In this case, the above-mentioned perfluorotriethylamine, perfluorohexyl sulfonyl ammonium and perfluorohexyl sulfonyl fluoride all have good wetting properties, which can ensure that the electroplating pretreatment solution has strong wettability to the holes on the groove surface.

[0256] Exemplarily, in the above-mentioned etching solution, the concentration of the surfactant can be greater than or equal to 0.01 ml / L and less than or equal to 0.2 ml / L. For example, the concentration of the surfactant can be 0.01 ml / L, 0.04 ml / L, 0.08 ml / L, 0.12 ml / L, 0.16 ml / L or 0.2 ml / L, etc. In this case, the concentration of the surfactant is within the above-mentioned range, which can prevent the electrode material from not filling or not completely filling the holes during electroplating due to the poor wettability of the electroplating pretreatment liquid to the holes on the groove surface due to the low concentration of the surfactant, ensuring that there is no gap between the electrode and the doped semiconductor layer, and ensuring that there is a large contact area between the motor and the doped semiconductor layer. In addition, it can also prevent the high concentration of the surfactant from preventing some surfactant molecules from being unable to contact water, thereby improving the utilization rate of the surfactant and reducing the loss of the surfactant.

[0257] Then, as shown in FIG. 14 , an electrode 17 is formed in the opening, and the electrode 17 is electrically connected to the doped semiconductor layer 12 .

[0258] In actual application, the electrode can be formed in the opening by electroplating or physical vapor deposition, and the electrode is electrically connected to the doped semiconductor layer. The material of the electrode can be referred to above and will not be described here.

[0259] Where the electrode further includes a conductive contact layer, a process such as deposition and etching, electroplating, chemical plating, or screen printing can be used to form the conductive contact layer on at least a portion of the surface of the opening. The material and thickness of the conductive contact layer can be found in the previous section and will not be further described here. Then, as shown in FIG15 , a connecting electrode 17-1 can be formed on the conductive contact layer 17-2 using the aforementioned method.

[0260] The beneficial effects of the method for manufacturing a solar cell according to the embodiment of the present invention can be found in the analysis of the beneficial effects of various implementations of the solar cell in the foregoing text, and will not be elaborated here.

[0261] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0262] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A solar cell comprising: a semiconductor substrate having a first side and a second side opposite to each other; a doped semiconductor layer, disposed on the first surface of the semiconductor substrate; a dielectric layer, disposed on a side of the doped semiconductor layer facing away from the semiconductor substrate; The dielectric layer includes a plurality of openings, wherein the openings expose a portion of the doped semiconductor layer; a plurality of holes are formed on a side of the doped semiconductor layer exposed in the openings away from the semiconductor substrate; The electrode is arranged on a side of the dielectric layer away from the semiconductor substrate, and the electrode passes through an opening on the dielectric layer and is electrically connected to the doped semiconductor layer.

2. The solar cell according to claim 1, wherein A ring-shaped protrusion is formed on the edge of the hole.

3. The solar cell according to claim 2, wherein The width of the annular protrusion is greater than 0 μm and less than or equal to 0.3 μm; and / or, The height of the annular protrusion is greater than 0 μm and less than or equal to 0.5 μm; and / or, The ratio of the maximum radial dimension of the hole to the width of the annular protrusion is less than or equal to 60.

4. The solar cell according to claim 1, wherein The hole is a hemispherical hole; And / or, the maximum radial size of the hole is nanometer-scale, or the maximum radial size of the hole is greater than 0 μm and less than or equal to 3 μm.

5. The solar cell according to claim 1, wherein A groove is formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate, and the plurality of holes are formed on a surface of the groove away from the semiconductor substrate.

6. The solar cell according to claim 1, wherein The number of holes per unit area in the middle region of the opening is greater than the number of holes per unit area in the edge region of the opening.

7. The solar cell according to claim 6, wherein The middle area accounts for 70% to 80% of the area of ​​the opening.

8. The solar cell according to claim 1, wherein A plurality of discontinuous protrusions are formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate.

9. The solar cell according to claim 8, wherein The doped semiconductor layer is a P-type doped semiconductor layer, and the number of discontinuous protrusions per unit area in the edge region of the opening is greater than the number of discontinuous protrusions per unit area in the middle region of the opening; or, The doped semiconductor layer is an N-type doped semiconductor layer, and the number of discontinuous protrusions per unit area in the middle region of the opening is greater than the number of discontinuous protrusions per unit area in the edge region of the opening.

10. The solar cell according to claim 8 or 9, wherein: The height of the discontinuous protrusion is greater than 0 μm and less than or equal to 0.5 μm.

11. The solar cell according to claim 1, wherein The portion of the doped semiconductor layer exposed in the opening has a fifth surface roughness on a side facing away from the semiconductor substrate, and the portion of the doped semiconductor layer not exposed in the opening has a sixth surface roughness on a side facing away from the semiconductor substrate, and the fifth surface roughness is greater than the sixth surface roughness.

12. The solar cell according to claim 1, wherein The doped semiconductor layer includes a first doped semiconductor layer and a second doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer are alternately arranged on the first surface of the semiconductor substrate; The first doped semiconductor layer is an N-type doped semiconductor layer, and the second doped semiconductor layer is a P-type doped semiconductor layer; The multiple openings include: multiple first openings and multiple second openings; wherein, the first openings expose a partial area of ​​the first doped semiconductor layer, and the second openings expose a partial area of ​​the second doped semiconductor layer; the area of ​​the first doped semiconductor layer exposed to the first opening has a first surface roughness, and the area of ​​the second doped semiconductor layer exposed to the second opening has a second surface roughness, and the first surface roughness and the second surface roughness are different.

13. The solar cell according to claim 12, wherein: The area of ​​the first doped semiconductor layer covered by the dielectric layer has a third surface roughness, and the area of ​​the second doped semiconductor layer covered by the dielectric layer has a fourth surface roughness; The third surface roughness is smaller than the fourth surface roughness.

14. The solar cell according to claim 12, wherein A plurality of first holes are formed in the area where the first doped semiconductor layer is exposed to the first opening, and a plurality of second holes are formed in the area where the second doped semiconductor layer is exposed to the second opening. A circle of annular protrusions is formed on the edges of the first holes and the edges of the second holes, and the average height of the annular protrusions of the first holes is different from the average height of the annular protrusions of the second holes.

15. The solar cell according to claim 12, wherein A plurality of first holes are formed in the area of ​​the first doped semiconductor layer exposed to the first opening, and a plurality of second holes are formed in the area of ​​the second doped semiconductor layer exposed to the second opening; wherein the number of second holes per unit area located in the middle area of ​​the second opening is greater than the number of first holes per unit area located in the middle area of ​​the first opening.

16. The solar cell according to claim 12, wherein A plurality of first holes are formed in the area of ​​the first doped semiconductor layer exposed to the first opening, and a plurality of second holes are formed in the area of ​​the second doped semiconductor layer exposed to the second opening; wherein the average radial maximum size of the holes located in the middle area of ​​the second opening is greater than the average radial maximum size of the holes located in the middle area of ​​the first opening.

17. The solar cell according to claim 1, wherein The doping concentration of the doped semiconductor layer located in the opening and away from the semiconductor substrate is greater than the doping concentration of the doped semiconductor layer located in the opening and close to the semiconductor substrate.

18. The solar cell according to claim 12, wherein A difference between a doping concentration of the first doped semiconductor layer located at the first opening and away from the semiconductor substrate and a doping concentration of the first doped semiconductor layer located at the first opening and close to the semiconductor substrate is a first difference; A difference between a doping concentration of the second doped semiconductor layer located at the second opening and away from the semiconductor substrate and a doping concentration of the second doped semiconductor layer located at the second opening and close to the semiconductor substrate is a second difference; The first difference is greater than the second difference.

19. The solar cell according to claim 12, wherein A portion of the first doped semiconductor layer exposed in the first opening is formed with a plurality of discontinuous protrusions on a side facing away from the semiconductor substrate; a portion of the second doped semiconductor layer exposed in the second opening is formed with a plurality of discontinuous protrusions on a side facing away from the semiconductor substrate; The number of discontinuous protrusions per unit area of ​​the edge region of the first opening is smaller than the number of discontinuous protrusions per unit area of ​​the edge region of the second opening; And / or, the number of discontinuous protrusions per unit area in the middle region of the first opening is greater than the number of discontinuous protrusions per unit area in the middle region of the second opening.

20. The solar cell according to claim 1, wherein The doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer exposed in the opening away from the semiconductor substrate.

21. The solar cell according to claim 1, wherein The doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at the edge of the opening of the dielectric layer, below the dielectric layer, and arranged on a side of the doped polysilicon layer away from the semiconductor substrate.

22. The solar cell according to claim 1, wherein A gap is formed at the edge of the opening of the dielectric layer and between the dielectric layer and the doped semiconductor layer below.

23. The solar cell according to claim 22, wherein The doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: an amorphous silicon layer located at an edge of the opening of the dielectric layer, below the dielectric layer, and on a side of the doped polysilicon layer away from the semiconductor substrate; Starting from the edge of the opening of the dielectric layer and along a direction parallel to the semiconductor base layer, a length where the amorphous silicon is distributed is greater than a length where the pores are distributed.

24. The solar cell according to claim 22, wherein The pores include at least one metal material in the electrode.

25. The solar cell according to claim 1 or 23, wherein A portion of the dielectric layer close to the opening is warped in a direction away from the doped semiconductor layer.

26. The solar cell according to claim 1, wherein A recess is formed in the edge area of ​​the opening.

27. The solar cell according to claim 26, wherein The doped semiconductor layer is an N-type doped semiconductor layer, and the pits are distributed in the edge region of the opening of the N-type doped semiconductor layer.

28. The solar cell according to claim 1, wherein The dielectric layer has a crack formed at an edge close to the opening.

29. The solar cell according to claim 1, wherein Silicon oxide is formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate.

30. The solar cell according to claim 1, wherein The dielectric layer includes aluminum oxide, and the portion of the doped semiconductor layer exposed in the opening and facing away from the semiconductor substrate includes aluminum.

31. The solar cell according to claim 1, wherein A portion of the doped semiconductor layer exposed in the opening has a through hole penetrating the doped semiconductor layer.

32. A photovoltaic module comprising a plurality of cell strings, wherein the cell strings comprise a plurality of solar cells and a plurality of interconnectors, wherein the interconnectors are used to connect the plurality of solar cells in series; in, The solar cell is the solar cell according to any one of claims 1 to 31.

33. A method for manufacturing a solar cell, comprising: Providing a semiconductor substrate having a first surface and a second surface opposite to each other; forming a doped semiconductor layer on the first surface and / or the second surface; forming a dielectric layer on a side of the doped semiconductor layer facing away from the semiconductor substrate; forming a through opening on the dielectric layer so that at least a portion of the doped semiconductor layer is exposed from the opening, and forming a plurality of holes on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate; An electrode is formed in the opening, and the electrode is electrically connected to the doped semiconductor layer.

34. The method for manufacturing a solar cell according to claim 33, wherein: The opening is formed by a laser etching process.

35. The method for manufacturing a solar cell according to claim 33 or 34, wherein: A laser etching process and / or a wet etching process is used to form a plurality of holes on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate, wherein the etching solution of the wet etching process contains ammonium bifluoride and / or ammonium fluoride.

36. The method for manufacturing a solar cell according to claim 35, wherein: The etching solution contains additives; the additives include at least one of 3-ethylbutoxypropylamine, aniline acid, sodium benzoate and sodium acetate; and / or, The etching solution contains a surfactant; the surfactant includes at least one of perfluorotriethylamine, perfluorohexyl sulfonyl ammonium and perfluorohexyl sulfonyl fluoride; and / or, In the etching solution, the concentration of fluoride ions is greater than or equal to 2 g / L and less than or equal to 13 g / L; and / or, The etching time corresponding to the wet etching process is greater than or equal to 10s and less than or equal to 60s; and / or, The process temperature corresponding to the wet etching process is greater than or equal to 15° C. and less than or equal to 30° C.

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