Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device with which it is possible, in a reverse-conducting IGBT (RC-IGBT) in which an IGBT and a diode are internally provided in the same chip, to more effectively suppress hole injection in a diode part and improve recovery characteristics.　A semiconductor device according to the present invention has an IGBT and a diode in the same chip, the semiconductor device being characterized in that: the diode has a second trench that is provided between a first-conductivity-type third body layer and fourth body layer formed on a main surface of a semiconductor substrate, a first electrode that is formed on the third-body-layer-side side wall in the second trench with an insulating film interposed therebetween, and a second electrode that is formed on the fourth-body-layer-side side wall in the second trench with an insulating film interposed therebetween and is formed so as to be set apart from the first electrode with at least a second insulating film interposed therebetween; and an n layer having a higher concentration than the impurity concentration of the semiconductor substrate is provided below the third body layer and the fourth body layer.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device structure and a manufacturing method thereof, and in particular to a technique that is effective when applied to a reverse conducting IGBT (RC-IGBT) in which an IGBT and a diode are built in the same chip.

[0002] IGBTs (Insulated Gate Bipolar Transistors), which are capable of high-power, high-speed switching, are widely used in a wide range of applications, from industrial to consumer, and even automotive applications, including motor control inverters for electric vehicles and trains, and inverter circuits for induction cookware, washing machines, and air conditioners.

[0003] In many applications of IGBTs, there exists a mode in which a freewheeling current flows from the emitter to the collector. Conventionally, to accommodate this freewheeling operation, a freewheeling diode is connected in anti-parallel to the IGBT on a separate chip.

[0004] In recent years, reverse conducting IGBTs (RC-IGBTs), which combine an IGBT and a freewheel diode on a single chip, have become increasingly popular. A reverse conducting IGBT incorporates a freewheel diode into the IGBT chip, and the diode is connected in reverse parallel to the IGBT to perform freewheeling operation.

[0005] As background art in this technical field, for example, there is a technique such as that described in Patent Document 1. Patent Document 1 discloses "a semiconductor device capable of reducing the area of ​​the p-body layer in the diode portion of an RC-IGBT to suppress hole injection and improve recovery characteristics."

[0006] JP 2023-147422 A

[0007] Reverse conducting IGBTs (RC-IGBTs) have the advantage of being able to reduce chip size by sharing the termination area between the IGBT and diode, and reducing thermal resistance because losses generated in the IGBT area or diode area are dissipated throughout the entire chip.

[0008] On the other hand, since the IGBT and diode are fabricated on the same chip, simultaneous optimization of each chip is difficult, and controlling the lifetime of the diode is particularly difficult, making it difficult to reduce the diode's injection and recovery loss.

[0009] The above-mentioned Patent Document 1 proposes a structure in which an anode p-layer is provided between wide trench structures to reduce the area of ​​the anode region and reduce hole injection from the anode. However, there is room for improvement in order to further reduce hole injection into the diode.

[0010] Therefore, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that incorporates an IGBT and a diode on the same chip.

[0011] In order to achieve the above object, the present invention provides a semiconductor device having an IGBT and a diode within a single chip, the IGBT including: a first body layer and a second body layer of a first conductivity type formed on a main surface of a semiconductor substrate; a first trench provided between the first body layer and the second body layer; a first gate electrode formed on a sidewall of the first trench on a side facing the first body layer via a gate insulating film; and a second gate electrode formed on a sidewall of the first trench on a side facing the second body layer via a gate insulating film and spaced apart from the first gate electrode via at least a first insulating film; The diode includes a third body layer and a fourth body layer of a first conductivity type formed on a main surface of the semiconductor substrate, a second trench provided between the third body layer and the fourth body layer, a first electrode formed on a sidewall of the second trench on the side of the third body layer via an insulating film, and a second electrode formed on a sidewall of the second trench on the side of the fourth body layer via an insulating film and spaced apart from the first electrode via at least a second insulating film, and is characterized in that an n-layer having an impurity concentration higher than that of the semiconductor substrate is provided below the third body layer and the fourth body layer.

[0012] The present invention also provides a semiconductor device including the steps of: (a) forming a first trench in a first region of a main surface of a semiconductor substrate and forming a second trench in a second region; (b) sequentially depositing a gate insulating film and a gate electrode film in each of the first trench and the second trench, and forming a first gate electrode and a second gate electrode in the first trench by photolithography and dry etching, and forming a first electrode and a second electrode in the second trench; (c) forming a p-body layer by ion implantation of p-type impurities in the main surface of the semiconductor substrate excluding the first trench and the second trench; and (d) forming an n-layer by ion implantation of n-type impurities in the main surface of the semiconductor substrate excluding the first trench and the second trench, wherein the n-layer has an impurity concentration higher than that of the semiconductor substrate and is formed below the p-body layer.

[0013] According to the present invention, it is possible to realize a semiconductor device and a manufacturing method thereof that can more effectively suppress hole injection into the diode portion and improve recovery characteristics in a reverse conducting IGBT (RC-IGBT) that has an IGBT and a diode built into the same chip.

[0014] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0015] 4A is a diagram schematically showing a cross-sectional structure of a reverse conducting IGBT according to Example 1 of the present invention; FIG. 4B is a diagram schematically showing a cross-sectional structure of a reverse conducting IGBT according to Example 3 of the present invention; FIG. 4C is a diagram showing a manufacturing process following FIG. 4D; FIG. 4E is a diagram showing a manufacturing process following FIG. 4D; and FIG. 4E are diagrams schematically showing a cross-sectional structure of a reverse conducting IGBT according to Example 4 of the present invention.

[0016] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0017] First Embodiment A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

[0018] FIG. 1 is a diagram showing a schematic cross-sectional structure of a reverse conducting IGBT (RC-IGBT) according to this embodiment.

[0019] As shown in FIG. 1, a reverse conducting IGBT (RC-IGBT) 1 of this embodiment is configured by incorporating an IGBT section 3 and a diode section 4 in the same chip.

[0020] The reverse conducting IGBT 1 is － The semiconductor device has a plurality of wide trenches 5 formed in the main surface of a semiconductor substrate (silicon substrate) 2. Fig. 1 shows an example in which one trench 5 is formed in the region where the IGBT section 3 is formed, one trench 5 is also formed in the region where the diode section 4 is formed, and one trench 5 is also formed in the boundary region between the IGBT section 3 and the diode section 4.

[0021] Note that a "wide trench" means that the width W_DT of trench 5 in the cross section shown in FIG. 1 is larger than the width W_Dp of p body layer 12 (W_DT>W_Dp) described later, and is not necessarily limited to a specific length.

[0022] A gate insulating film 6 (gate oxide film) is formed inside each trench 5 so as to cover the bottom and side surfaces of the trench 5 .

[0023] In the region where the IGBT portion 3 is formed, two p body layers 12 are formed on the main surface of the semiconductor substrate 2, on either side of the trench 5, with the trench 5 sandwiched therebetween. Here, the p body layer 12 on the left side of the trench 5 is referred to as a "first body layer" of the first conductivity type (p type), and the p body layer 12 on the right side of the trench 5 is referred to as a "second body layer" of the first conductivity type (p type). Therefore, the trench 5 of the IGBT portion 3 is provided between the first body layer and the second body layer. The trench 5 of the IGBT portion 3 is referred to as a "first trench."

[0024] Inside trench 5 (first trench) of IGBT section 3, a polysilicon electrode (gate) 7 is formed on the left sidewall of trench 5 on the p body layer 12 (first body layer) side, with a gate insulating film 6 (gate oxide film) interposed therebetween. Also, a polysilicon electrode (gate) 7 is formed on the right sidewall of trench 5 on the p body layer 12 (second body layer) side, with a gate insulating film 6 (gate oxide film) interposed therebetween. Here, polysilicon electrode (gate) 7 formed on the left sidewall of trench 5 is called a "first gate electrode," and polysilicon electrode (gate) 7 formed on the right sidewall of trench 5 is called a "second gate electrode."

[0025] A polysilicon electrode 8 serving as the emitter of the IGBT section 3 is formed between a polysilicon electrode (gate) 7 (first gate electrode) formed on the left sidewall of the trench 5 and a polysilicon electrode (gate) 7 (second gate electrode) formed on the right sidewall of the trench 5.

[0026] An interlayer insulating film 15 is formed between the polysilicon electrode (gate) 7 (first gate electrode) formed on the left sidewall of the trench 5, the polysilicon electrode (gate) 7 (second gate electrode) formed on the right sidewall of the trench 5, and the polysilicon electrode (emitter) 8 so as to fill the inside of the trench 5 (first trench), thereby electrically insulating the electrodes from each other.

[0027] In the region where the diode portion 4 is formed, two p body layers 12 are formed on the main surface of the semiconductor substrate 2, on either side of the trench 5, with the trench 5 sandwiched therebetween. Here, the p body layer 12 on the left side of the trench 5 is referred to as a "third body layer" of the first conductivity type (p type), and the p body layer 12 on the right side of the trench 5 is referred to as a "fourth body layer" of the first conductivity type (p type). Therefore, the trench 5 of the diode portion 4 is provided between the first body layer and the second body layer. The trench 5 of the diode portion 4 is referred to as a "second trench."

[0028] Inside trench 5 (second trench) of diode section 4, a polysilicon electrode (gate or anode) 9 is formed on the left sidewall of trench 5 facing p body layer 12 (third body layer) with a gate insulating film 6 (gate oxide film) interposed therebetween. Also, a polysilicon electrode (gate or anode) 9 is formed on the right sidewall of trench 5 facing p body layer 12 (fourth body layer) with a gate insulating film 6 (gate oxide film) interposed therebetween. Here, polysilicon electrode (gate or anode) 9 formed on the left sidewall of trench 5 is referred to as a "first electrode," and polysilicon electrode (gate or anode) 9 formed on the right sidewall of trench 5 is referred to as a "second electrode."

[0029] A polysilicon electrode 10 serving as the anode of the diode section 4 is formed between a polysilicon electrode (gate or anode) 9 (first electrode) formed on the left sidewall of the trench 5 and a polysilicon electrode (gate or anode) 9 (second electrode) formed on the right sidewall of the trench 5.

[0030] An interlayer insulating film 15 is formed between the polysilicon electrode (gate or anode) 9 (first electrode) formed on the left sidewall of the trench 5, the polysilicon electrode (gate or anode) 9 (second electrode) formed on the right sidewall of the trench 5, and the polysilicon electrode (anode) 10 so as to fill the inside of the trench 5 (second trench), thereby electrically insulating the electrodes from each other.

[0031] The p body layer 12 (third body layer) on the left side of the trench 5 in the diode section 4 and the p body layer 12 (fourth body layer) on the right side of the trench 5 are provided with an impurity concentration (n － ) are provided with n-layers 11 each having a higher impurity concentration than the n-layers 11.

[0032] The p-body layer 12 (first body layer) on the left side of the trench 5 in the IGBT section 3 and the p-body layer 12 (second body layer) on the right side of the trench 5 are provided with an n-type impurity layer having a higher impurity concentration (n-) than the impurity concentration (n-) of the semiconductor substrate 2 and a higher impurity concentration than the n-layer 11 in the diode section 4. ＋ A layer 14 is provided respectively.

[0033] The main surface of the semiconductor substrate 2 is provided with an n-type IGBT section 3. ＋ An interlayer insulating film 15 is formed to cover the layer 14, the gate insulating film 6 (gate oxide film), and each electrode in the trench 5, and also to cover the p-body layer 12 of the diode portion 4, the gate insulating film 6 (gate oxide film), and each electrode in the trench 5.

[0034] In the interlayer insulating film 15 , contact holes 16 are formed that penetrate the interlayer insulating film 15 and reach the p-body layers 12 in the IGBT section 3 and the diode section 4 .

[0035] An emitter electrode and an anode electrode 18 are formed on the interlayer insulating film 15 so as to cover the interlayer insulating film 15. The emitter electrode and the anode electrode 18 serve as the emitter electrode of the IGBT section 3 and the anode electrode of the diode section 4. The emitter electrode and the anode electrode 18 are also embedded inside the contact holes 16, and serve as contacts 17 that connect the emitter electrode and the anode electrode 18 to each p body layer 12. In each p body layer 12 where the bottom of the contact hole 16 is located, a p ＋ A layer 13 is formed.

[0036] An n-buffer layer 20 is formed on the back surface side of the semiconductor substrate 2. A p-layer 21 is further formed outside the n-buffer layer 20 in the IGBT section 3, and an n-layer 22 is further formed outside the n-buffer layer 20 in the diode section 4. ＋ The p-layer 21 and the n-layer 22 are formed. ＋ A collector electrode and a cathode electrode 23 are formed on the outer side of the layer 22. The collector electrode and the cathode electrode 23 serve as the collector electrode of the IGBT section 3 and the cathode electrode of the diode section 4, respectively.

[0037] As described above, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment is a semiconductor device having the IGBT section 3 and the diode section 4 within the same chip. The IGBT section 3 includes a first body layer (p body layer) and a second body layer (p body layer) of a first conductivity type (p type) formed on the main surface of the semiconductor substrate 2, a first trench 5 provided between the first body layer and the second body layer, a first gate electrode 7 formed on a sidewall of the first trench 5 facing the first body layer via a gate insulating film 6, and a second gate electrode 7 formed on a sidewall of the first trench 5 facing the second body layer via the gate insulating film 6 and spaced apart from the first gate electrode 7 via at least a first insulating film (interlayer insulating film 15). The diode section 4 has a third body layer (p body layer) and a fourth body layer (p body layer) of a first conductivity type (p type) formed on the main surface of the semiconductor substrate 2, a second trench 5 provided between the third body layer and the fourth body layer, a first electrode 9 formed on a sidewall of the second trench 5 on the third body layer side with an insulating film (gate insulating film 6) interposed therebetween, and a second electrode 9 formed on a sidewall of the second trench 5 on the fourth body layer side with the insulating film (gate insulating film 6) interposed therebetween and spaced from the first electrode 9 with at least a second insulating film (interlayer insulating film 15) interposed therebetween, and an n layer 11 having an impurity concentration higher than that of the semiconductor substrate 2 is provided below the third body layer and the fourth body layer.

[0038] By providing the n-type injection suppression layer 11 under the p-body layer 12 of the diode section 4, hole injection can be further reduced compared to the prior art (for example, Patent Document 1).

[0039] In order to ensure the effect of reducing hole injection, it is desirable to provide n layer 11 on the entire lower surface of p body layer 12 .

[0040] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

[0041] FIG. 2 is a diagram showing a schematic cross-sectional structure of a reverse conducting IGBT (RC-IGBT) of this embodiment, which corresponds to a modification of the first embodiment (FIG. 1).

[0042] 2, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment differs from the first embodiment (FIG. 1) in that, in addition to providing an n layer 11 below the p body layer 12 of the diode portion 4, an n layer 11 is also provided below the p body layer 12 of the IGBT portion 3. The other configurations are the same as those of the first embodiment (FIG. 1).

[0043] That is, an n-layer 11 having a higher impurity concentration than that of semiconductor substrate 2 is also provided below the first body layer (p-body layer) and the second body layer (p-body layer).

[0044] By providing an n-type injection suppression layer 11 similar to that in the diode section 4 also on the IGBT section 3 side, it becomes a carrier accumulation layer, and the on-voltage of the IGBT can be reduced.

[0045] Third Embodiment A semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to FIGS.

[0046] FIG. 3 is a diagram showing a schematic cross-sectional structure of a reverse conducting IGBT (RC-IGBT) of this embodiment, which corresponds to a modification of the second embodiment (FIG. 2).

[0047] 3, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment differs from the second embodiment (FIG. 2) in that n layer 11 is provided under p body layer 12 of IGBT portion 3 and diode portion 4, and in that only the portion of n layer 11 directly below contact 17 is highly doped. The other configurations are the same as those of the second embodiment (FIG. 2).

[0048] That is, the emitter electrode 18 of the IGBT section 3 and the first body layer (p body layer 12, p ＋ layer 13) and the second body layer (p body layer 12, p ＋ a first contact 17 and a second contact 17 respectively connecting the anode electrode 18 of the diode section 4 and the third body layer (p body layer 12, p ＋ layer 13) and the fourth body layer (p body layer 12, p ＋The first contact 17, the second contact 17, the third contact 17, and the fourth contact 17 are connected to the n-layer 11, respectively. An n' layer 24 having a higher concentration than the n-layer 11 is provided below each of the first contact 17, the second contact 17, the third contact 17, and the fourth contact 17.

[0049] By providing n-type injection suppression layers 11 under the p-body layers 12 of the IGBT section 3 and the diode section 4 and further increasing the concentration of the n-layer of only the portion of the n-type injection suppression layer 11 directly under the contact 17, it is possible to lower the on-voltage of the IGBT in the IGBT section 3 and also improve the RBSOA tolerance (avalanche tolerance: reverse bias safe operation area) by causing avalanche to occur directly under the contact layer. Furthermore, by increasing the concentration of the n-type injection suppression layer 11 in the diode section 4, hole injection is further suppressed.

[0050] 4A to 4F, the main manufacturing process of the reverse conducting IGBT (RC-IGBT) 1 of FIG. 3 will be described.

[0051] Note that the reverse conducting IGBTs (RC-IGBTs) 1 of Example 1 (FIG. 1), Example 2 (FIG. 2), and Example 4 (FIG. 5) described later can also be fabricated using a manufacturing method similar to that of this example, and in this specification, the manufacturing method will be described using the structure of FIG. 3 as a representative example.

[0052] First, as shown in FIG. － A plurality of wide trenches 5 are formed in the main surface of a mold semiconductor substrate (silicon substrate) 2. At this time, the trenches 5 are formed in the region where the IGBT section 3 is to be formed, the region where the diode section 4 is to be formed, and the boundary region between the IGBT section 3 and the diode section 4.

[0053] 4B , a gate insulating film 6 and polysilicon films 7 to 10 are sequentially formed in each of the trenches 5 (first trench) of the IGBT section 3, the trench 5 (second trench) of the diode section 4, and the trench 5 in the boundary region between the IGBT section 3 and the diode section 4. Then, by photolithography and dry etching, a first gate electrode 7 and a second gate electrode 7 are formed in the trench 5 of the IGBT section 3, and a first electrode 9 and a second electrode 9 are formed in the trench 5 of the diode section 4. At this time, an electrode 8 serving as an emitter is formed in the trench 5 of the IGBT section 3, an electrode 10 serving as an anode is formed in the trench 5 of the diode section 4, and each electrode is also formed in the trench 5 in the boundary region between the IGBT section 3 and the diode section 4.

[0054] Next, as shown in FIG. 4C , a mask is formed to cover each trench 5 and each gate insulating film 6, and p-type impurity ions are implanted into the main surface of the semiconductor substrate 2 excluding each trench 5 and each gate insulating film 6 to form a p-body layer 12.

[0055] Furthermore, an n-layer 11 is formed on the main surface of the semiconductor substrate 2 excluding the trenches 5 and the gate insulating films 6 by ion implantation of n-type impurities.

[0056] Next, as shown in FIG. 4D , a mask is formed to cover the diode portion 4, each trench 5, and each gate insulating film 6, and n-type impurity ions are implanted into the main surface of the semiconductor substrate 2 except for the diode portion 4, thereby forming n-type impurity ions on the p-body layer 12 of the IGBT portion 3. ＋ Layer 14 is formed.

[0057] Next, as shown in FIG. 4E, an interlayer insulating film 15 is formed on the main surface of the semiconductor substrate 2, and a hole is formed by photolithography and dry etching through the interlayer insulating film 15 to form an n-type semiconductor layer. ＋ Contact holes 16 are formed to expose p-body layer 12 including layer 14. At this time, contact holes 16 are also formed on electrodes 8 and 10.

[0058] Next, as shown in FIG. 4F, p-type impurity ions are implanted through the contact hole 16 to form p-type impurity ions at the bottom of the contact hole 16. ＋ Layer 13 is formed.

[0059] Furthermore, an n′ layer 24 is formed below the contact hole 16 by ion implantation of an n-type impurity having a higher concentration than the n layer 11 through the contact hole 16 .

[0060] Although not shown, thereafter, an emitter electrode and an anode electrode 18, which are front surface electrodes, an n-buffer layer 20 on the rear surface, a p-layer 21, and a collector electrode and a cathode electrode 23, which are rear surface electrodes, are formed, thereby completing the structure of the reverse conducting IGBT (RC-IGBT) 1 in FIG. 3.

[0061] A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG.

[0062] FIG. 5 is a diagram showing a schematic cross-sectional structure of a reverse conducting IGBT (RC-IGBT) of this embodiment, which corresponds to a modification of the third embodiment (FIG. 3).

[0063] As shown in Fig. 5, the reverse conducting IGBT (RC-IGBT) 1 of this embodiment differs from Example 3 (Fig. 3) in that the n-layer only directly below the contact 17 of the IGBT section 3 is highly doped, and the n-layer directly below the contact 17 of the diode section 4 is not highly doped. The rest of the configuration is the same as Example 3 (Fig. 3).

[0064] That is, the semiconductor device has a first contact 17 and a second contact 17 that connect the emitter electrode 18 of the IGBT section 3 to the first body layer (p body layer 12, p+ layer 13) and the second body layer (p body layer 12, p+ layer 13), respectively, and a third contact 17 and a fourth contact 17 that connect the anode electrode 18 of the diode section 4 to the third body layer (p body layer 12, p+ layer 13) and the fourth body layer (p body layer 12, p+ layer 13), respectively, and an n' layer 24 having a higher concentration than the n layer 11 is provided below each of the first contact 17 and the second contact 17, and no n' layer 24 is provided below each of the third contact 17 and the fourth contact 17.

[0065] By providing n-type injection suppression layers 11 under the p-body layers 12 of the IGBT section 3 and the diode section 4 and further increasing the concentration of the n-type injection suppression layers 11 only in the portion directly under the contact 17 of the IGBT section 3, it is possible to lower the on-voltage of the IGBT in the IGBT section 3 and also improve the RBSOA tolerance (avalanche tolerance: reverse bias safe operation area) by causing avalanche to occur directly under the contact layer. Furthermore, by increasing the concentration of the n-type injection suppression layers 11 in the diode section 4, hole injection is further suppressed.

[0066] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0067] REFERENCE SIGNS LIST 1... reverse conducting IGBT (RC-IGBT) 2... semiconductor substrate (silicon substrate) 3... IGBT section 4... diode section 5... (wide) trench 6... gate insulating film (gate oxide film) 7... polysilicon electrode (gate) 8... polysilicon electrode (emitter) 9... polysilicon electrode (gate or anode) 10... polysilicon electrode (anode) 11... n layer (injection suppression layer) 12... p body layer 13... p ＋ Layer 14...n ＋ Layer 15: Interlayer insulating film 16: Contact hole 17: Contact 18: Emitter electrode and anode electrode 19: n － Layer 20...n buffer layer 21...p layer 22...n ＋ Layer 23...collector electrode and cathode electrode 24...n' layer.

Claims

1. A semiconductor device having an IGBT and a diode on the same chip, wherein the IGBT comprises: a first body layer and a second body layer of a first conductivity type formed on a main surface of a semiconductor substrate; a first trench provided between the first body layer and the second body layer; a first gate electrode formed on a sidewall of the first trench on the side of the first body layer via a gate insulating film; and a second gate electrode formed on a sidewall of the first trench on the side of the second body layer via a gate insulating film and spaced apart from the first gate electrode via at least a first insulating film; and the diode comprises: a third body layer and a fourth body layer of a first conductivity type formed on the main surface of the semiconductor substrate; a second trench provided between the third body layer and the fourth body layer; a first electrode formed on a sidewall of the second trench on the side of the third body layer via an insulating film; a second electrode formed on a sidewall of the second trench on the side of the fourth body layer via an insulating film and spaced apart from the first electrode via at least a second insulating film; and an n-layer having an impurity concentration higher than that of the semiconductor substrate is provided below the third body layer and the fourth body layer.

2. A semiconductor device according to claim 1, characterized in that an n-layer having a higher impurity concentration than the semiconductor substrate is provided below the first body layer and the second body layer.

3. A semiconductor device according to claim 2, comprising: a first contact and a second contact connecting the emitter electrode of the IGBT to the first body layer and the second body layer, respectively; and a third contact and a fourth contact connecting the anode electrode of the diode to the third body layer and the fourth body layer, respectively; wherein an n' layer having a higher concentration than the n layer is provided below each of the first contact, the second contact, the third contact and the fourth contact.

4. A semiconductor device according to claim 2, comprising: a first contact and a second contact connecting the emitter electrode of the IGBT to the first body layer and the second body layer, respectively; and a third contact and a fourth contact connecting the anode electrode of the diode to the third body layer and the fourth body layer, respectively; wherein an n' layer having a higher concentration than the n layer is provided directly below each of the first contact and the second contact; and wherein the n' layer is not provided directly below each of the third contact and the fourth contact.

5. A semiconductor device according to claim 1, wherein the n-layer is provided on the entire lower surface of the third body layer and the fourth body layer.

6. A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a first trench in a first region of a main surface of a semiconductor substrate, and forming a second trench in a second region; (b) sequentially depositing a gate insulating film and a gate electrode film in each of the first trench and the second trench, and forming a first gate electrode and a second gate electrode in the first trench by photolithography and dry etching, and forming a first electrode and a second electrode in the second trench; (c) forming a p-body layer by ion implantation of p-type impurities in the main surface of the semiconductor substrate excluding the first trench and the second trench; and (d) forming an n-layer by ion implantation of n-type impurities in the main surface of the semiconductor substrate excluding the first trench and the second trench, wherein the n-layer has an impurity concentration higher than that of the semiconductor substrate and is formed below the p-body layer.

7. A method for manufacturing a semiconductor device according to claim 6, wherein an IGBT is formed in the first region, and a diode is formed in the second region.

8. A method for manufacturing a semiconductor device according to claim 7, further comprising, prior to step (d), a step (e) of forming a mask on the first region, wherein the n-layer is formed in the second region excluding the second trench, and is not formed in the first region.

9. A method for manufacturing a semiconductor device according to claim 7, comprising, after step (d), the steps of: (f) forming an interlayer insulating film on a main surface of the semiconductor substrate and forming a contact hole that penetrates the interlayer insulating film by photolithography and dry etching to expose the p-body layer; and (g) forming an n' layer below the contact hole by ion implantation of n-type impurities through the contact hole at a concentration higher than that of the n layer.

10. A method for manufacturing a semiconductor device according to claim 9, further comprising the step of (h) forming a mask on the second region before step (g), wherein the n' layer is formed below the contact hole in the first region, but is not formed below the contact hole in the second region.

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