Imaging device and method for manufacturing same

Abstract

An imaging device according to the present invention includes: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a plan view. The first wiring layer includes first wiring in the peripheral region. The second wiring layer includes second wiring in the peripheral region. The first through electrode electrically connects the first wiring and the second wiring in the peripheral region. One or more layers including a photoelectric conversion layer are located on the first layer in the pixel region.

Description

Imaging device and manufacturing method thereof

[0001] The present disclosure relates to an imaging device and a manufacturing method thereof.

[0002] In an imaging device in which a plurality of semiconductor substrates are stacked, electrical connections are sometimes made using through electrodes. Patent Document 1 describes an example of such an imaging device.

[0003] JP 2023-057137 A

[0004] The present disclosure provides a technique suitable for suppressing scattering of the material of the through electrode.

[0005] the first wiring layer includes a first wiring layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels includes a pixel electrode, a counter electrode located above the pixel electrode, and one or more layers including a photoelectric conversion layer located between the pixel electrode and the counter electrode, the first wiring layer includes a first wiring layer in the peripheral region, and the second wiring layer includes a second wiring layer in the peripheral region, the first through electrode electrically connecting the first wiring and the second wiring in the peripheral region, and the one or more layers are located on the first layer in the pixel region.

[0006] From another perspective, the present disclosure provides a method for manufacturing an imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, the method comprising: bonding the second wiring layer of the second substrate to a support substrate; scraping the second semiconductor layer of the second substrate; bonding the second semiconductor layer of the second substrate to the first wiring layer of the first substrate; removing the support substrate; forming a first through electrode in the peripheral region that penetrates the second wiring layer and the second semiconductor layer; forming a first portion on the first through electrode; and forming a plurality of pixel electrodes in the pixel region.

[0007] The technology according to the present disclosure is suitable for suppressing scattering of the material of the through electrode.

[0008] FIG. 1 is a plan view of an imaging device according to embodiment 1. FIG. 2 is a cross-sectional view of the imaging device according to embodiment 1. FIG. 3 is a diagram illustrating protection of a first through electrode in embodiment 1. FIG. 4A is a diagram illustrating a method for manufacturing an imaging device according to embodiment 1. FIG. 4B is a diagram illustrating a method for manufacturing an imaging device according to embodiment 1. FIG. 4C is a diagram illustrating a method for manufacturing an imaging device according to embodiment 1. FIG. 4D is a diagram illustrating a method for manufacturing an imaging device according to embodiment 1. FIG. 5 is a cross-sectional view of an imaging device according to embodiment 2. FIG. 6 is a diagram illustrating protection of a first through electrode in embodiment 2. FIG. 7 is a cross-sectional view of an imaging device according to a reference embodiment. FIG. 8 is a diagram illustrating exposure of a first through electrode to dry etching in the reference embodiment. FIG. 9 is a cross-sectional view of an imaging device according to embodiment 3. FIG. 10 is a cross-sectional view of an imaging device according to embodiment 4. FIG. 11A is a diagram illustrating a manufacturing method applicable to embodiments 1 and 2. FIG. 11B is a diagram illustrating a manufacturing method applicable to embodiments 1 and 2. FIG. 11C is a diagram illustrating a manufacturing method applicable to embodiments 1 and 2. FIG. 11D is a diagram illustrating a manufacturing method applicable to embodiments 1 and 2. FIG. 11E is an explanatory diagram of a manufacturing method applicable to embodiments 1 and 2. FIG. 11F is an explanatory diagram of a manufacturing method applicable to embodiments 1 and 2. FIG. 11G is an explanatory diagram of a manufacturing method applicable to embodiments 1 and 2. FIG. 12A is an explanatory diagram of a manufacturing method applicable to embodiments 3 and 4. FIG. 12B is an explanatory diagram of a manufacturing method applicable to embodiments 3 and 4. FIG. 12C is an explanatory diagram of a manufacturing method applicable to embodiments 3 and 4. FIG. 13 is a cross-sectional view of an imaging device according to embodiment 5. FIG. 14 is a cross-sectional view of an imaging device according to embodiment 6. FIG. 15 is a schematic diagram of a configuration example of a camera system according to embodiment 7.

[0009] (Findings that form the basis of the present disclosure) In recent years, there has been a demand for higher resolution in the market for imaging devices, and the pixels of imaging devices have been made smaller. Furthermore, there has also been a demand for a smaller planar area of ​​the semiconductor substrate in the imaging device, and stacked imaging devices in which multiple semiconductor substrates are stacked have been developed.

[0010] In a stacked-type imaging device, electrical connection across the semiconductor substrate is possible by having through electrodes penetrate the semiconductor substrate. The through electrodes can include TSVs (Through-Silicon Vias).

[0011] During the manufacture of an imaging device, the material of the through electrode may scatter. For example, the material of the through electrode may scatter when dry etching a photoelectric conversion layer. If the material scatters, it may adhere to a dry etching chamber and contaminate the dry etching chamber. Therefore, the present inventors have investigated a technique suitable for suppressing the scattering of the material of the through electrode.

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component positions and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Various aspects described in the embodiments can be combined with each other unless a contradiction occurs. Furthermore, the components in the following embodiments are merely illustrative. In each drawing, components having substantially the same function are designated by the same reference numerals, and redundant explanations may be omitted or simplified.

[0013] Furthermore, the various elements shown in the drawings are merely shown schematically to facilitate understanding of the present disclosure, and the dimensional ratios and appearances may differ from those of the actual objects.

[0014] In the embodiments, terms such as "upper" and "lower" are used merely to specify the relative positions of components and are not intended to limit the orientation of the imaging device when in use. In the embodiments, "height" refers to a position in the up-down direction. In the embodiments, "planar view" refers to a view from the thickness direction of the substrate on which the first through-electrodes are provided. In the embodiments, "in-plane direction" refers to a direction perpendicular to the thickness direction of the substrate on which the first through-electrodes are provided.

[0015] In the embodiments, the expression "element B is located on element A" may be used. This expression may mean that at least a part of element B overlaps with, is above, and is in contact with at least a part of element A when viewed from above.

[0016] In the embodiments, the expression "element B is located above element A" may be used. This expression may mean that at least a part of element B overlaps with, is above, and is separated from at least a part of element A when viewed from above.

[0017] In the embodiments, a "via" includes a conductor disposed within a hole. A "trench" refers to a groove. A "substrate" may also be referred to as a "wafer." Unless otherwise specified, the terms "connection" and "electrically connected" may be read interchangeably.

[0018] 1 is a plan view of an imaging device 1A according to embodiment 1. The imaging device 1A includes a pixel region R1 and a peripheral region R2. The pixel region R1 includes a plurality of pixels 50. The peripheral region R2 is located outside the pixel region R1 in a plan view.

[0019] 1, a plurality of pixels 50 are arranged in a row direction and a column direction. A pixel array is formed by the plurality of pixels 50 in a pixel region R1. The pixel region R1 is rectangular. The row direction and the column direction refer to the directions in which the rows and the columns extend, respectively.

[0020] 1, the center of each pixel 50 is located on a lattice point of a square lattice. However, for example, multiple pixels 50 may be positioned so that the center of each pixel 50 is located on a lattice point of a triangular lattice, a hexagonal lattice, or the like. For example, the pixels 50 may be arranged one-dimensionally, in which case the imaging device 1A can be used as a line sensor.

[0021] 2 is a cross-sectional view of the image pickup device 1A according to embodiment 1. The image pickup device 1A is a front side illumination (FSI) type.

[0022] The imaging device 1A includes a substrate 400, a substrate 500, an insulating film 100, an insulating film 200, a control electrode 321, a plurality of pixel electrodes 311, a photoelectric conversion layer 312, a counter electrode 313, an insulating film 314, a light-shielding film 331, a protective film 332, a color filter 341, a microlens 342 and a first through electrode 10.

[0023] 2 , insulating films 100 and 200 cover first through-electrodes 10 from above. This configuration can prevent the scattering of the material of the through-electrodes from first through-electrodes 10 when processing photoelectric conversion layer 312, counter electrode 313, and insulating film 314. Specifically, as will be described later, in the manufacture of imaging device 1A, photoelectric conversion layer 312, counter electrode 313, and insulating film 314 are patterned by etching. During this patterning, insulating films 100 and 200 prevent the scattering of the material of the through-electrodes from first through-electrodes 10.

[0024] 2 , the light-shielding film 331 covers the first through-hole electrode 10 from above. This configuration can further prevent the scattering of the material of the through-hole electrode from the first through-hole electrode 10. Specifically, as described below, in the manufacture of the imaging device 1A, the light-shielding film 331 is formed so as to cover the photoelectric conversion layer 312, the counter electrode 313, the insulating film 314, the insulating film 100, and the insulating film 200 from above. The as-deposited light-shielding film 331, which is in a state immediately after deposition, has unnecessary portions removed by etching, and is patterned into the light-shielding film 331 extending over the range shown in FIG. 2 . During this patterning, the light-shielding film 331 remaining in the finished imaging device 1A, together with the insulating film 100 and the insulating film 200, prevents the scattering of the material of the through-hole electrode from the first through-hole electrode 10.

[0025] The substrate 400 includes a semiconductor substrate 410 and a wiring layer 450. The wiring layer 450 is located on the semiconductor substrate 410. The wiring layer 450 includes a plurality of wirings 460. The plurality of wirings 460 includes a wiring 465. The wiring 465 is located in the peripheral region R2.

[0026] The semiconductor substrate 410 includes a surface 410a and a surface 410b. The surface 410a is the surface of the semiconductor substrate 410 on the wiring layer 450 side. The surface 410a is closer to the wiring layer 450 than the surface 410b. The surface 410b is the surface of the semiconductor substrate 410 opposite to the wiring layer 450.

[0027] The substrate 500 is located on the substrate 400. The substrate 500 includes a semiconductor substrate 510, an interconnect layer 550, and a transistor 570. The interconnect layer 550 is located on the semiconductor substrate 510. The interconnect layer 550 includes a plurality of interconnects 560. The plurality of interconnects 560 includes an interconnect 565. The interconnect 565 is located in the peripheral region R2. The transistor 570 includes a source 570s, a drain 570d, and a gate 570g. The transistor 570 is connected to the pixel electrode 311.

[0028] In a plan view, in the pixel region R1, a plurality of pixels 50 are arranged on the substrate 500. Each of the plurality of pixels 50 includes a pixel electrode 311, a photoelectric conversion layer 312, and a counter electrode 313. The counter electrode 313 is located above the pixel electrode 311. The photoelectric conversion layer 312 is located between the pixel electrode 311 and the counter electrode 313.

[0029] The semiconductor substrate 510 includes a surface 510a and a surface 510b. The surface 510a is the surface of the semiconductor substrate 510 on the wiring layer 550 side. The surface 510a is closer to the wiring layer 550 than the surface 510b. The surface 510b is the surface of the semiconductor substrate 510 opposite to the wiring layer 550.

[0030] The source 570s and drain 570d of the transistor 570 are located on the surface 510a. The gate 570g is located in the wiring layer 550. The gate 570g is located above the source 570s and drain 570d. With this configuration, it is easier to connect the pixel electrode 311 and the gate 570g of the transistor 570 with short wiring than in a configuration in which the source 570s and drain 570d are located on the surface 510b.

[0031] The insulating film 100 is located on the wiring layer 550. The insulating film 200 is located on the insulating film 100. The control electrode 321 and the plurality of pixel electrodes 311 are located in the same layer as the insulating film 200. The insulating film 200, the control electrode 321, and the plurality of pixel electrodes 311 are located at the same height.

[0032] The photoelectric conversion layer 312 is typically a photoelectric conversion film. The photoelectric conversion layer 312 is located on the insulating film 200 in the pixel region R1 and the plurality of pixel electrodes 311. The counter electrode 313 is located on the photoelectric conversion layer 312. The insulating film 314 is located on the counter electrode 313.

[0033] The light-shielding film 331 is located on the insulating film 200, the control electrode 321, and the insulating film 314. The protective film 332 is located on the insulating film 200, the light-shielding film 331, and the insulating film 314. The color filter 341 is located on the protective film 332. The microlens 342 is located on the color filter 341.

[0034] The first through electrode 10 is located in the peripheral region R2 and penetrates the wiring layer 550 and the semiconductor substrate 510. In the peripheral region R2, the first through electrode 10 electrically connects the wiring 465 and the wiring 565. In a plan view, the top surface 10a of the first through electrode 10 has a portion that does not overlap with the photoelectric conversion layer 312. Specifically, in a plan view, the entire top surface 10a of the first through electrode 10 does not overlap with the photoelectric conversion layer 312.

[0035] The first through electrode 10 includes a via 11, a via 12, and a pad 13. The vias 11 and 12 are connected to the pad 13. The via 11 extends downward to a deeper position than the via 12. The via 11 passes through the wiring layer 550 and the semiconductor substrate 510, and is connected to the upper surface 465a of the wiring 465. The via 12 is connected to the wiring 565. The pad 13 is flat. The pad 13 is provided with a top surface 10a.

[0036] The wiring 565 is located closer to the semiconductor substrate 510 than the top surface 10a, that is, on the lower side in the example shown in Fig. 2. The via 12 is connected to the top surface 565a of the wiring 565.

[0037] 2 , the insulating film 100 is located on the first through electrode 10. The first through electrode 10 can be protected by the insulating film 100. Specifically, the insulating film 100 is located on the top surface 10a of the first through electrode 10.

[0038] The light-shielding film 331 has light-shielding properties and electrical conductivity. The light-shielding film 331 shields one or some of the pixels 50 from light. The light-shielded pixels 50 operate as optical black pixels. The light-shielding film 331 also electrically connects the control electrode 321 and the counter electrode 313.

[0039] The photoelectric conversion layer 312 generates signal charges. Specifically, signal charges are generated by irradiating the photoelectric conversion layer 312 with light and are collected by the pixel electrode 311. When holes are used as signal charges, a control voltage is applied to the counter electrode 313 via the control electrode 321 and the light-shielding film 331 so that the pixel electrode 311 has a lower potential than the counter electrode 313. When electrons are used as signal charges, a control voltage is applied to the counter electrode 313 via the control electrode 321 and the light-shielding film 331 so that the pixel electrode 311 has a higher potential than the counter electrode 313.

[0040] In this embodiment, the transistor 570 is an amplifying transistor. The transistor 570 generates and outputs a signal corresponding to the amount of signal charge generated by the photoelectric conversion layer 312.

[0041] In this embodiment, the semiconductor substrate 410 and the semiconductor substrate 510 include silicon.

[0042] In the wiring layer 450, a plurality of wirings 460 are located in an insulator. The insulator includes, for example, an oxide. The oxide is, for example, silicon oxide. The plurality of wirings 460 are conductors, for example, including a metal.

[0043] In the wiring layer 550, a plurality of wirings 560 are located in an insulator. The insulator includes, for example, an oxide. The oxide is, for example, silicon oxide. The plurality of wirings 560 are conductors, for example, including a metal.

[0044] In this embodiment, the insulating film 100 and the insulating film 200 include at least one selected from the group consisting of silicon oxide and silicon nitride.

[0045] In this embodiment, the pixel electrode 311 may include at least one selected from the group consisting of a metal and a metal compound. Examples of metals include copper, titanium, tantalum, and aluminum. Examples of metal compounds include metal nitrides. Examples of metal nitrides include titanium nitride and tantalum nitride. The pixel electrode 311 may also include polysilicon doped with impurities to provide conductivity.

[0046] The materials exemplified as the materials of the pixel electrode 311 can be used as the material of the control electrode 321. The material of the control electrode 321 may be the same as the material of the pixel electrode 311. In the imaging device 1A, the number of control electrodes 321 may be one or more. Note that in the embodiment, "the same material" means that the types of elements contained in the material are the same. In the embodiment, the materials are considered to be the same whether the composition ratios of the elements contained in the materials are the same or different.

[0047] In this embodiment, the photoelectric conversion layer 312 includes an organic material. The organic material may be an organic semiconductor. The photoelectric conversion layer 312 may include one or more organic semiconductor layers. The organic semiconductor layers may be made of an organic p-type semiconductor or an organic n-type semiconductor.

[0048] At least one layer selected from the group consisting of an electron transport layer, a hole transport layer, an electron blocking layer, and a hole blocking layer may be provided adjacent to the photoelectric conversion layer 312. The electron transport layer transports electrons. The hole transport layer transports holes. The electron blocking layer blocks electrons. The hole blocking layer blocks holes.

[0049] The photoelectric conversion layer 312 has a lower surface 312 a and a side surface 312 b. The angle θ between the lower surface 312 a and the side surface 312 b (see part (b) in FIG. 3 ) is, for example, 70° to 90°, and may be 80° to 90°. An angle θ in this range can be formed, for example, when the photoelectric conversion layer 312 is patterned by dry etching.

[0050] An oxide may be provided on the side surface 312b of the photoelectric conversion layer 312. The oxide can be obtained, for example, when the photoelectric conversion layer 312 is patterned by dry etching using oxygen as an etching gas. Specifically, an oxide can be formed on the side surface 312b by oxidizing a portion of the photoelectric conversion layer 312 with oxygen. Furthermore, during dry etching, oxygen may come into contact with a structure surrounding the photoelectric conversion layer 312 to form an oxide, which may then be scattered from the structure toward the photoelectric conversion layer 312 and adhere to the photoelectric conversion layer 312, resulting in the formation of an oxide on the side surface 312b.

[0051] In this embodiment, the counter electrode 313 is transparent to the light to be detected. The counter electrode 313 is a conductive semiconductor. For example, the counter electrode 313 includes indium tin oxide (ITO). The counter electrode 313 may also be a transparent conductive semiconductor including other materials.

[0052] In this embodiment, the insulating film 314 includes at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, an organic polymer material, and an inorganic polymer material. The insulating film 314 may be transparent to light of a wavelength to be detected by the imaging device 1A. The insulating film 314 may have a single-layer structure or a multilayer structure. The insulating film 314 may include a passivation film.

[0053] In this embodiment, the light-shielding film 331 includes at least one selected from the group consisting of metals and metal compounds. In one specific example, the light-shielding film 331 includes at least one selected from the group consisting of titanium, titanium nitride, aluminum, silicon, copper-doped aluminum, copper, and tungsten. The light-shielding film 331 may include an alloy including at least two of the materials listed in the above specific example.

[0054] The protective film 332 has insulating properties. The protective film 332 includes, for example, at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, an organic polymer material, and an inorganic polymer material. The protective film 332 may be transparent to light of a wavelength to be detected by the imaging device 1A. The material contained in the protective film 332 and the material contained in the insulating film 314 may be the same or different. The protective film 332 may have a single-layer structure or a multilayer structure.

[0055] In this embodiment, the first through-electrode 10 includes at least one via, and more specifically, at least one TSV. In the example of FIG. 1, the via 11 is more specifically a TSV.

[0056] The first through-hole electrode 10 may contain a metal. The first through-hole electrode 10 contains, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum. In this embodiment, the first through-hole electrode 10 contains copper as a main component. The inclusion of copper in the first through-hole electrode 10 is advantageous from the viewpoint of suppressing glare on the pixel 50 due to light reflection. Here, the main component refers to the component that is contained in the largest amount by mass. In one example, the main component is a component that accounts for more than 50 mass%. In one specific example, the main component is a component that accounts for more than 80 mass%.

[0057] The manufacturing method of the imaging device 1A according to this embodiment is outlined below: (1) Bonding the substrate 500 and the support substrate 810 (2) Thinning the semiconductor substrate 510 of the substrate 500 (3) Depositing a bonding film 488 on the thinned semiconductor substrate 510, and bonding the substrate 400 (4) Forming the first through electrode 10 in the bonding structure of (3) above (5) Depositing the insulating film 100 on the first through electrode 10 (6) Depositing the photoelectric conversion layer 312, the counter electrode 313, and the insulating film 314 (7) Patterning the photoelectric conversion layer 312 by dry etching

[0058] 3A and 3B are diagrams illustrating protection of the first through electrode 10 in embodiment 1. Specifically, part (a) of Fig. 3 shows the structure before the dry etching of (7) above, and part (b) of Fig. 3 shows the structure after the dry etching of (7) above.

[0059] In the structure before dry etching shown in part (a) of Figure 3, the first through electrode 10 is located below the pixel electrode 311. Furthermore, the first through electrode 10 is covered with the insulating film 100 and the insulating film 200. This makes it possible to protect the first through electrode 10 from the dry etching for patterning the photoelectric conversion layer 312 by the insulating film 100 and the insulating film 200 on the first through electrode 10 and to suppress scattering of the material of the first through electrode 10.

[0060] The thickness of the insulating film 100 may be 30 nm or more. For example, the thickness of the insulating film 100 is 30 nm or more and 1000 nm or less, and in a specific example, 50 nm or more and 700 nm or less. The thickness of the insulating film 200 is typically the same as that of the pixel electrode 311, and for example, is 50 nm or more and 1000 nm or less, and in one numerical example, is 150 nm. For example, the total thickness of the insulating film 100 and the insulating film 200 is 150 nm or more and 1500 nm or less, and in one numerical example, is 200 nm.

[0061] 4A to 4D are explanatory views of a manufacturing method of the imaging device 1A according to embodiment 1. In Fig. 4A to 4D, the description will begin with the formation of the first through electrode 10 in (4) above. Note that in Fig. 4A to 4D, the structure below the wiring layer 550 is omitted.

[0062] 4A , a trench 13h is formed in the wiring layer 550. Next, in the process of part [2], a hole 12h is formed in the wiring layer 550. Next, in the process of part [3], a hole 11h is formed in the wiring layer 550 and the semiconductor substrate 510.

[0063] 4A, an electrode material is filled into the holes 11h, 12h, and 13h. As a result, a via 11 is formed in the hole 11h, a via 12 is formed in the hole 12h, and a pad 13 is formed in the trench 13h. Thus, the first through electrode 10 is formed. Subsequently, the top surface 10a of the pad 13 and the upper surface of the wiring layer 550 are smoothed by CMP (Chemical Mechanical Polishing).

[0064] 4B, the insulating film 100 is formed on the wiring layer 550 and the first through-electrode 10. Next, in the process of part [6], an electrode film 671 is formed on the insulating film 100.

[0065] 4B , a part of the electrode film 671 is etched to form the control electrode 321 and the plurality of pixel electrodes 311. This processing exposes a part of the insulating film 100. Subsequently, the insulating film 200 is formed on the insulating film 100, the control electrode 321, and the plurality of pixel electrodes 311.

[0066] 4C, the insulating film 200 is removed from the control electrode 321 and the plurality of pixel electrodes 311. This removal is performed by CMP.

[0067] 4C , a photoelectric conversion layer 312 is formed on the control electrode 321, the plurality of pixel electrodes 311, and the insulating film 200. Subsequently, a counter electrode 313 is formed on the photoelectric conversion layer 312. Subsequently, an insulating film 314 is formed on the counter electrode 313.

[0068] Next, in the process of part

[10] of Figure 4C, dry etching is used to remove the insulating film 314, the counter electrode 313 and the photoelectric conversion layer 312 in the portions that overlap the first through electrode 10 and the control electrode 321 in a planar view.

[0069] Specifically, the process of part

[10] in Figure 4C includes first dry etching and second dry etching, in this order. The first dry etching removes portions of the insulating film 314 and the counter electrode 313 that are located above the first through-hole electrode 10 and the control electrode 321 in a planar view. The second dry etching is dry etching that uses the insulating film 314 as a mask. The second dry etching removes portions of the photoelectric conversion layer 312 that are located above the first through-hole electrode 10 and on the control electrode 321 in a planar view.

[0070] In this embodiment, the photoelectric conversion layer 312 contains an organic substance. The etching gas for the second dry etching contains oxygen. The organic substance reacts with the oxygen in the etching gas to generate carbon oxide, thereby progressing the second dry etching.

[0071] 4D , a light-shielding film 331 is formed by deposition and etching on the insulating film 200, the control electrode 321, and the insulating film 314. Next, in the process of part

[12] , a protective film 332 is formed on the insulating film 200 and the light-shielding film 331.

[0072] The formation of the light-shielding film 331 in the process shown in part

[11] of FIG. 4D will be specifically described. In this process, the light-shielding film 331 is formed so as to cover the photoelectric conversion layer 312, the counter electrode 313, the insulating film 314, the insulating film 100, and the insulating film 200 from above. Next, a mask (not shown) is formed so as to cover the first through electrode 10 and the formed as-deposited light-shielding film 331 from above. Next, using the mask, portions of the as-deposited light-shielding film 331 not covered by the mask are removed by dry etching. As a result, unnecessary portions of the as-deposited light-shielding film 331 are removed, and the as-deposited light-shielding film 331 is patterned to extend over the area shown in part

[11] of FIG. 4D . The unnecessary portions may be, for example, pad openings.

[0073] During patterning of the light-shielding film 331, the light-shielding film 331 remaining in the finished imaging device 1A, together with the insulating film 100 and the insulating film 200, suppresses scattering of the material of the through electrode from the first through electrode 10. Specifically, although the amount of etching gas for the dry etching is limited, it can reach the overlapping region that overlaps with the first through electrode 10 in a planar view below the mask. Therefore, although the extent of the effect of the dry etching is limited, it may also extend to the overlapping region. In this regard, the insulating film 100, the insulating film 200, and the light-shielding film 331 remaining in the finished imaging device 1A protect the first through electrode 10 from dry etching in the overlapping region. This suppresses scattering of the material of the through electrode from the first through electrode 10.

[0074] In the first embodiment, a configuration is adopted in which the light-shielding film 331 overlaps with at least a portion of the first through electrode 10 in a plan view in the completed imaging device 1A. With this configuration, the above-described scattering suppression effect of the light-shielding film 331 can be exerted. Specifically, in the completed imaging device 1A, the light-shielding film 331 overlaps with at least a portion of the pad 13 in a plan view. More specifically, in the completed imaging device 1A, the light-shielding film 331 overlaps with the entire top surface 10a of the pad 13 in a plan view. Even more specifically, in the completed imaging device 1A, the light-shielding film 331 extends over the entire in-plane direction in a plan view so as to protrude from the outer edge of the top surface 10a of the pad 13.

[0075] 4D, a color filter 341 is formed on the light-shielding film 331. Subsequently, a microlens 342 is formed on the color filter 341.

[0076] Other embodiments will be described below. In the following, elements common to the embodiment already described and the embodiment to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applicable unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0077] 5 is a cross-sectional view of an imaging device 1B according to embodiment 2. The imaging device 1B includes a protective electrode 351.

[0078] The protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 are located in the same layer as the insulating film 200. The insulating film 200, the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 are located on the first through-electrodes 10 and the wiring layer 550. The insulating film 200, the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 are located at the same height.

[0079] The protective film 332 is located on the protective electrode 351 , the insulating film 200 and the insulating film 314 .

[0080] 5 , the protecting electrode 351 is located on the first through-hole electrode 10. The first through-hole electrode 10 can be protected by the protecting electrode 351. Specifically, the protecting electrode 351 is located on the top surface 10a of the first through-hole electrode 10.

[0081] In the second embodiment, the protecting electrode 351 may include at least one selected from the group consisting of a metal and a metal compound. Examples of the metal include titanium, tantalum, and aluminum. Examples of the metal compound include a metal nitride. Examples of the metal nitride include titanium nitride and tantalum nitride. The protecting electrode 351 may include polysilicon doped with impurities to provide conductivity. The material of the protecting electrode 351 may be the same as the material of the pixel electrode 311.

[0082] In the second embodiment, the insulating film 100 is not formed on the first through electrode 10 in the above-described (5) described in the first embodiment. Instead, in the second embodiment, a protective electrode 351 is formed on the first through electrode 10.

[0083] 6A and 6B are diagrams illustrating protection of the first through electrode 10 in embodiment 2. Specifically, part (a) of Fig. 6 shows the structure before the dry etching of (7) above, and part (b) of Fig. 6 shows the structure after the dry etching of (7) above.

[0084] In the structure before dry etching shown in part (a) of Fig. 6 , the first through electrode 10 is located below the protective electrode 351. This means that the protective electrode 351 on the first through electrode 10 protects the first through electrode 10 from dry etching for patterning the photoelectric conversion layer 312, and makes it possible to suppress scattering of the material of the first through electrode 10.

[0085] The thickness of the shielding electrode 351 may be 30 nm or more. For example, the thickness of the shielding electrode 351 is 30 nm or more and 1000 nm or less, and in one specific example, the thickness is 50 nm or more and 700 nm or less.

[0086] In the manufacturing method of the image pickup device 1B according to the second embodiment, the insulating film 100 is not formed in the portion [5] of FIG. 4B described in the first embodiment.

[0087] In the manufacturing method of the imaging device 1B according to the second embodiment, the step of part [7] in FIG. 4B described in the first embodiment is modified. That is, the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 are formed by etching a portion of the electrode film 671. This processing exposes a portion of the wiring layer 550. Subsequently, the insulating film 200 is formed on the wiring layer 550, the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311.

[0088] In the manufacturing method of the imaging device 1B according to the second embodiment, the steps of parts [8] and [9] in FIG. 4C described in the first embodiment are modified. That is, the insulating film 200 on the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 is removed. This removal is performed by CMP. Thereafter, the photoelectric conversion layer 312 is formed on the protective electrode 351, the control electrode 321, the plurality of pixel electrodes 311, and the insulating film 200.

[0089] In the first and second embodiments, for example, a logic circuit is provided on the substrate 400. A plurality of pixels 50 are provided on the substrate 500. The plurality of pixels 50 are controlled by the logic circuit.

[0090] 7 is a cross-sectional view of an imaging device 1X according to a reference embodiment. In the imaging device 1X, the pads 13 of the first through electrodes 10 are located at the same height as the pixel electrodes 311. In the reference embodiment, neither the insulating film 100 nor the protective electrode 351 is formed on the first through electrodes 10.

[0091] 8 is a diagram illustrating exposure of the first through electrode 10 to dry etching in the reference embodiment. Specifically, part (a) of FIG. 8 shows the structure before the dry etching of (7) above. Part (b) of FIG. 8 shows the structure after the dry etching of (7) above.

[0092] In the structure before dry etching shown in part (a) of Figure 8, the pad 13 of the first through-hole electrode 10 is located at the same height as the pixel electrode 311. In the dry etching for patterning the photoelectric conversion layer 312, the pad 13 of the first through-hole electrode 10 is exposed to the dry etching. This exposure may cause the material of the first through-hole electrode 10 to scatter. In part (b) of Figure 8, reference numeral 640 schematically represents the state in which the material of the first through-hole electrode 10 has scattered.

[0093] In contrast, as described above, according to embodiment 1 or embodiment 2, the insulating film 100 or the protective electrode 351 can protect the first through electrode 10 from dry etching for patterning the photoelectric conversion layer 312.

[0094] 9 is a cross-sectional view of an imaging device 1C according to embodiment 3. The imaging device 1C includes a substrate 600 and a second through electrode 20. In the imaging device 1C, an insulating film 100 is located on a first through electrode 10, similar to the imaging device 1A according to embodiment 1.

[0095] Substrate 600 is located on substrate 400. Substrate 500 is located on substrate 600.

[0096] The substrate 600 includes a wiring layer 650, a semiconductor substrate 610, an insulating film 670, and a bonding film 683. The semiconductor substrate 610 is located on the wiring layer 650. The insulating film 670 is located on the semiconductor substrate 610. The bonding film 683 is located on the insulating film 670. The wiring layer 650 includes a plurality of wirings 660. The plurality of wirings 660 includes a wiring 665. The wiring 665 is located in the peripheral region R2.

[0097] The semiconductor substrate 610 includes a surface 610a and a surface 610b. The surface 610a is the surface of the semiconductor substrate 610 on the wiring layer 650 side. The surface 610a is closer to the wiring layer 650 than the surface 610b. The surface 610b is the surface of the semiconductor substrate 610 opposite to the wiring layer 650.

[0098] The second through electrode 20 is located in the peripheral region R2 and penetrates the semiconductor substrate 610 and the wiring layer 650. In the peripheral region R2, the second through electrode 20 electrically connects the wiring 465 and the wiring 665. The second through electrode 20 is electrically connected to the first through electrode 10.

[0099] The second through electrode 20 includes a via 21, a via 22, and a pad 23. The vias 21 and 22 are connected to the pad 23. The via 21 extends downward to a deeper position than the via 22. The via 21 penetrates the semiconductor substrate 610 and the wiring layer 650, and is connected to the wiring 465. The via 22 penetrates the semiconductor substrate 610, and is connected to the wiring 665. The pad 23 is flat. The top surface 20a of the second through electrode 20 is provided on the pad 23.

[0100] In this embodiment, the semiconductor substrate 610 comprises silicon.

[0101] In the wiring layer 650, a plurality of wirings 660 are located in an insulator. The insulator includes, for example, an oxide. The oxide is, for example, silicon oxide. The plurality of wirings 660 are conductors, for example, including a metal.

[0102] In this embodiment, the second through-electrode 20 includes at least one via, specifically at least one TSV. In the example of Fig. 9, the via 21 is specifically a TSV.

[0103] The second through electrode 20 may be made of any of the materials exemplified as the material of the first through electrode 10. The material of the second through electrode 20 may be the same as the material of the first through electrode 10.

[0104] 10 is a cross-sectional view of an imaging device 1D according to embodiment 4. Like the imaging device 1C according to embodiment 3, the imaging device 1D includes a substrate 600 and a second through electrode 20. In the imaging device 1D, like the imaging device 1B according to embodiment 2, a protective electrode 351 is located on the first through electrode 10.

[0105] In the third and fourth embodiments, for example, a logic circuit is provided on a substrate 400. A plurality of pixels 50 are provided on a substrate 500. A memory is provided on a substrate 600. The plurality of pixels 50 are controlled by the logic circuit. Outputs from the plurality of pixels 50 are recorded in the memory. The memory is, for example, a dynamic random access memory (DRAM).

[0106] (Manufacturing Method Applicable to Embodiments 1 and 2) Figures 11A to 11G are explanatory views of a manufacturing method applicable to Embodiments 1 and 2. In Figures 11A to 11G, steps <1> to <9> and steps <11> to <20> are common to Embodiments 1 and 2. Step <10> differs between Embodiments 1 and 2. In Figures 11D to 11G, the structure of Embodiment 1 is depicted on the left side, and the structure of Embodiment 2 is depicted on the right side. Unless there is a particular contradiction, the description of Figures 11A to 11G and the description of Figures 4A to 4D can be combined.

[0107] 11A, a semiconductor substrate 510, a support substrate 810, and a semiconductor substrate 410 are prepared. Next, in the process of part <2>, a wiring layer 550 is formed on the semiconductor substrate 510, and a wiring layer 450 is formed on the semiconductor substrate 410.

[0108] 11A , a bonding film 581 is formed on the wiring layer 550. This forms the wiring layer 550 including the bonding film 581. A bonding film 588 is formed on the support substrate 810. A bonding film 482 is formed on the wiring layer 450. This forms the wiring layer 450 including the bonding film 482.

[0109] The bonding film 482 contains, for example, an oxide. In this regard, the bonding films 488, 581, 583, 588, 682, and 683 also contain, for example, an oxide, similar to the bonding film 482.

[0110] 11A , the bonding film 581 and the bonding film 588 are bonded together. This forms a layered structure in which the support substrate 810, the wiring layer 550, and the semiconductor substrate 510 are layered in this order. In this layered structure, the bonding film 588 and the bonding film 581 are included in the wiring layer 550.

[0111] 11B, the semiconductor substrate 510 is thinned by grinding it. In the process of part <6>, a bonding film 488 is formed on the semiconductor substrate 510.

[0112] 11B , the bonding film 488 and the bonding film 482 are bonded together. This forms a layered structure in which the semiconductor substrate 410, the wiring layer 450, the semiconductor substrate 510, the wiring layer 550, and the support substrate 810 are stacked in this order. In this layered structure, the bonding film 482 and the bonding film 488 are included in the wiring layer 450.

[0113] 11C, the support substrate 810 is removed from the laminated structure obtained in the step of part <7> of FIG. 11B. In a first example, this removal is performed by CMP or wet etching. In a second example, this removal is performed by peeling the support substrate 810 from the bonding film 588.

[0114] Next, in the step of part <9> in Fig. 11C, the first through electrode 10 is formed. This step can correspond to, for example, the steps of part [1] to part [4] in Fig. 4A.

[0115] In the first embodiment, following the step of part <9> in Fig. 11C , in the step of part <10-1> in Fig. 11C , an insulating film 100 is formed on the wiring layer 550 and the first through-electrode 10. Then, a control electrode 321, a plurality of pixel electrodes 311, and an insulating film 200 are formed on the insulating film 100. Then, a passivation film 910 is formed on the control electrode 321, a plurality of pixel electrodes 311, and an insulating film 200. The formation of the control electrode 321, a plurality of pixel electrodes 311, and an insulating film 200 corresponds to, for example, the steps of part [6] in Fig. 4B to part [8] in Fig. 4C .

[0116] 11C , in the step of part <10-2>, a protective electrode 351, a control electrode 321, a plurality of pixel electrodes 311, and an insulating film 200 are formed on the wiring layer 550 and the first through-hole electrode 10. Subsequently, a passivation film 910 is formed on the protective electrode 351, the control electrode 321, the plurality of pixel electrodes 311, and the insulating film 200.

[0117] Following the process of part <10-1> or part <10-2> in Figure 11C, in the process of part <11> in Figure 11D, a hole 920 is formed from the passivation film 910 side so as to expose the wiring 465. The hole 920 is a hole for inserting a pad for PCM (Process Control Monitor) testing. Next, in the process of part <12>, a PCM test and a simple test are performed on the structure obtained in the process of part <11>.

[0118] 11D, the holes 920 are backfilled with a filler material 930. During this backfilling, the filler material 930 is filled into the holes 920 and deposited on the passivation film 910.

[0119] Next, in the step of part <14> in FIG. 11E , the filler 930 on the passivation film 910 and the passivation film 910 are removed. This removal is performed by CMP. As a result, in the first embodiment, the control electrode 321 and the plurality of pixel electrodes 311 are exposed. In the second embodiment, the protective electrode 351, the control electrode 321, and the plurality of pixel electrodes 311 are exposed.

[0120] Next, in the step of portion <15> of FIG. 11E , in the first embodiment, a photoelectric conversion layer 312 is formed on the control electrode 321, the plurality of pixel electrodes 311, and the insulating film 200. In the second embodiment, a photoelectric conversion layer 312 is formed on the protective electrode 351, the control electrode 321, the plurality of pixel electrodes 311, and the insulating film 200. Subsequently, a counter electrode 313 is formed on the photoelectric conversion layer 312. Subsequently, an insulating film 314 is formed on the counter electrode 313. The insulating film 314 includes a passivation film. The step of portion <15> of FIG. 11E can correspond to, for example, the step of portion [9] of FIG. 4C . Note that in FIGS. 11E and 11F , the counter electrode 313 and the insulating film 314 are depicted collectively as a single layer.

[0121] 11E , dry etching is performed to remove, from the insulating film 314, the counter electrode 313, and the photoelectric conversion layer 312, portions that overlap with the first through-hole electrode 10 and portions that overlap with the control electrode 321 in plan view. The process of portion <16> in Fig. 11E can correspond to, for example, the process of portion

[10] in Fig. 4C .

[0122] 11F, a light-shielding film 331 is formed on the insulating film 200, the control electrode 321, and the insulating film 314. This step may correspond to, for example, the step of part

[11] in FIG. 4D.

[0123] 11F, a protective film 332 is formed on the insulating film 200 and the light-shielding film 331. Subsequently, a part of the protective film 332 and the filler material 930 in the hole 920 are removed so as to expose the wiring 465. The formation of the protective film 332 corresponds to, for example, the step of part

[12] in FIG.

[0124] Next, in the step of part <19> of FIG. 11F, a PCM inspection is performed on the structure obtained in the step of part <18>.

[0125] Next, in the step of part <20> in Fig. 11G, a color filter 341 is formed on the light-shielding film 331. Subsequently, a microlens 342 is formed on the color filter 341. The step of part <20> in Fig. 11G corresponds to, for example, the step of part

[13] in Fig. 4D.

[0126] 12A to 12C are explanatory views of a manufacturing method applicable to embodiments 3 and 4. In FIGS. 12A to 12C, steps 1 to 10 are common to embodiments 3 and 4.

[0127] 12A , a semiconductor substrate 510, a support substrate 810, a semiconductor substrate 410, and a semiconductor substrate 610 are prepared. Next, in a process of part <<2>>, a wiring layer 550 is formed on the semiconductor substrate 510, a wiring layer 450 is formed on the semiconductor substrate 410, and a wiring layer 650 is formed on the semiconductor substrate 610.

[0128] 12A , a bonding film 581 is formed on the wiring layer 550. As a result, the wiring layer 550 including the bonding film 581 is formed. A bonding film 588 is formed on the supporting substrate 810. A bonding film 482 is formed on the wiring layer 450. As a result, the wiring layer 450 including the bonding film 482 is formed. A bonding film 682 is formed on the wiring layer 650. As a result, the wiring layer 650 including the bonding film 682 is formed.

[0129] 12A , the bonding film 581 and the bonding film 588 are bonded together. This forms a layered structure in which the support substrate 810, the wiring layer 550, and the semiconductor substrate 510 are layered in this order. In this layered structure, the bonding film 588 and the bonding film 581 are included in the wiring layer 550.

[0130] 12A , the bonding film 482 and the bonding film 682 are bonded together. As a result, a layered structure is formed in which the semiconductor substrate 410, the wiring layer 450, the wiring layer 650, and the semiconductor substrate 610 are stacked in this order. The bonding film 482 in this layered structure is included in the wiring layer 450. The bonding film 682 in this layered structure is included in the wiring layer 650.

[0131] 12B, the semiconductor substrate 510 is thinned by grinding, and the semiconductor substrate 610 is thinned by grinding.

[0132] Next, in the process of part <<6>> in FIG. 12B , the second through electrode 20 is formed. Specifically, an insulating film 670 is formed on the semiconductor substrate 610. Next, a trench is formed in the insulating film 670. Next, two holes are formed in the semiconductor substrate 610 and the wiring layer 650. Next, an electrode material is buried in the two holes and the trench. As a result, vias 21 and 22 are formed in the two holes, and a pad 23 is formed in the trench. In this way, the second through electrode 20 is formed.

[0133] 12B, a bonding film 583 is formed on the semiconductor substrate 510. The bonding film 683 is formed on the insulating film 670 and the second through-electrode 20.

[0134] 12C , the bonding film 583 and the bonding film 683 are bonded. As a result, a layered structure is formed in which the semiconductor substrate 410, the wiring layer 450, the wiring layer 650, the semiconductor substrate 610, the insulating film 670, the bonding film 683, the bonding film 583, the semiconductor substrate 510, the wiring layer 550, and the support substrate 810 are stacked in this order. The bonding film 683 in this layered structure is included in the substrate 600. The bonding film 583 in this layered structure is included in the substrate 500.

[0135] 12C, the support substrate 810 is removed from the layered structure obtained in the step of the part <<8>>. In a first example, this removal is performed by CMP or wet etching. In a second example, this removal is performed by peeling the support substrate 810 from the bonding film 588.

[0136] Next, in the process of part <<10>> in FIG. 12C , the first through electrode 10 is formed. Specifically, a trench is formed in the bonding film 588. Next, two holes are formed: one that penetrates the wiring layer 550 and the semiconductor substrate 510, and the other that exists in the wiring layer 550. Next, an electrode material is buried in the two holes and the trench. As a result, vias 11 and 12 are formed in the two holes, and a pad 13 is formed in the trench. In this way, the first through electrode 10 is formed.

[0137] Thereafter, steps similar to those in the portion <10-1> or portion <10-2> of FIG. 11C are carried out, and steps similar to those in the portions <11> to <20> of FIGS. 11D to 11G are carried out.

[0138] Various modifications can be applied to the above-described first to fourth embodiments.

[0139] For example, the imaging device may be a back side illumination (BSI) type. The semiconductor substrate 510 may be located on the wiring layer 550. Both the via 11 and the via 12 in the first through electrode 10 may penetrate the semiconductor substrate 510.

[0140] As can be understood from the above description, in embodiments 1 to 4, the imaging devices 1A to 1D include a first substrate, a second substrate, and a first through-electrode 10. The first substrate includes a first semiconductor layer and a first wiring layer. The second substrate is located on the first substrate. The second substrate includes a second semiconductor layer and a second wiring layer. The first through-electrode penetrates the second wiring layer and the second semiconductor layer. In the pixel region R1, a plurality of pixels 50 are arranged on the second substrate in a planar view.

[0141] In the first and second embodiments, the first substrate corresponds to the substrate 400, the first semiconductor layer corresponds to the semiconductor substrate 410, the first wiring layer corresponds to the wiring layer 450, the second substrate corresponds to the substrate 500, the second semiconductor layer corresponds to the semiconductor substrate 510, and the second wiring layer corresponds to the wiring layer 550. In the third and fourth embodiments, the first substrate corresponds to the substrate 600, the first semiconductor layer corresponds to the semiconductor substrate 610, the first wiring layer corresponds to the wiring layer 650, the second substrate corresponds to the substrate 500, the second semiconductor layer corresponds to the semiconductor substrate 510, and the second wiring layer corresponds to the wiring layer 550.

[0142] In the first to fourth embodiments, each of the plurality of pixels 50 includes one or more layers including a photoelectric conversion layer 312. The one or more layers are located between the pixel electrode 311 and the counter electrode 313.

[0143] In one example, the one or more layers are photoelectric conversion layer 312. In another example, the one or more layers include, in addition to photoelectric conversion layer 312, at least one layer selected from the group consisting of an electron transport layer, a hole transport layer, an electron blocking layer, and a hole blocking layer.

[0144] The second substrate includes a first layer located on the first through-electrode 10. The one or more layers are located on the first layer in the pixel region R1. With this configuration, the first through-electrode 10 can be protected by the first layer from dry etching for patterning the photoelectric conversion layer 312. This makes it possible to suppress scattering of the material of the first through-electrode 10.

[0145] The first layer may be a single layer at the same height or a combination of multiple layers at the same height. In embodiments 1 and 3, the first layer is an insulating film 100. In embodiments 2 and 4, the first layer includes an insulating film 200, a protection electrode 351, a control electrode 321, and a pixel electrode 311.

[0146] Suppressing scattering of the material of the first through electrode 10 can bring about various advantages. For example, this can suppress contamination of the dry etching chamber. Furthermore, for example, this can easily prevent the first through electrode 10 from being scraped off, resulting in a decrease in its conductivity.

[0147] The first layer has a first portion including a first material. The first portion is located on the first through electrode 10. The first through electrode 10 includes a second material. The first portion may be a part of or the entire first layer.

[0148] In the first and third embodiments, the first portion is the insulating film 100. In the second and fourth embodiments, the first portion is the protective electrode 351.

[0149] In the first and third embodiments, the first material is an insulating material. The imaging devices 1A and 1C according to this configuration are easy to manufacture. The insulating material includes, for example, at least one selected from the group consisting of silicon oxide and silicon nitride.

[0150] Here, "silicon oxide" refers to a compound containing silicon (Si) and oxygen (O). "Silicon oxide" may further contain carbon (C), nitrogen (N), or both. Specific examples of "silicon oxide" include silicon dioxide (SiO2), silicon oxycarbide (SiOC), and silicon oxynitride (SiON). Silicon dioxide (SiO2) may be obtained based on tetraethoxysilane (TEOS). Although each of these materials has its own unique composition and properties, they are collectively referred to as "silicon oxide" in this specification.

[0151] Furthermore, "silicon nitride" is a compound containing silicon (Si) and nitrogen (N). "Silicon nitride" may further contain carbon (C). Specific examples of "silicon nitride" include silicon nitride (SiN, Si3N4), silicon oxynitride (SiON), and silicon carbonitride (SiCN). Although each of these materials has its own unique composition and properties, they are collectively referred to as "silicon nitride" in this specification.

[0152] The explanations regarding "silicon oxide" and "silicon nitride" can also be applied to the above explanations regarding the materials of the insulating film 100 and the insulating film 200.

[0153] In the first and third embodiments, the pixel electrode 311 is located between the first layer and the one or more layers in the pixel region R1.

[0154] In the second and fourth embodiments, the pixel electrode 311 may contain the first material. This configuration allows the first portion and the pixel electrode 311 to be formed in the same process.

[0155] In the second and fourth embodiments, the first material may include at least one selected from the group consisting of a metal and a metal compound. Examples of the metal include titanium, tantalum, and aluminum. Examples of the metal compound include a metal nitride. Examples of the metal nitride include titanium nitride and tantalum nitride. The first material may include polysilicon doped with impurities to provide conductivity.

[0156] The second material may include a metal, for example, at least one selected from the group consisting of copper, aluminum, tungsten, and tantalum.

[0157] The thickness of the first layer may be 30 nm or more. When the first layer is thick, the first layer is likely to protect the first through electrode 10 from dry etching. The thickness of the first layer is, for example, 30 nm or more and 1000 nm or less, and in a specific example, 50 nm or more and 700 nm or less.

[0158] The first wiring layer may be located on the first semiconductor layer, and the first semiconductor layer may be located on the first wiring layer. The second wiring layer may be located on the second semiconductor layer, and the second semiconductor layer may be located on the second wiring layer.

[0159] As can be understood from the above description, the insulating film 200 and the light-shielding film 331 can also protect the first through-electrodes 10 and suppress scattering of the material of the first through-electrodes 10 .

[0160] In embodiments 3 and 4, the imaging devices 1C and 1D include a third substrate and a second through electrode 20. The third substrate includes a third semiconductor layer and a third wiring layer. The first substrate is located on the third substrate. The third wiring layer includes a third wiring in the peripheral region R2. In embodiments 3 and 4, the third substrate corresponds to the substrate 400, the third semiconductor layer corresponds to the semiconductor substrate 410, the third wiring layer corresponds to the wiring layer 450, and the third wiring corresponds to the wiring 465.

[0161] The second through electrode 20 penetrates the first wiring layer and the first semiconductor layer. The second through electrode 20 is electrically connected to the first through electrode 10. The second through electrode 20 electrically connects the first wiring and the third wiring in the peripheral region R2.

[0162] In the first to fourth embodiments, substrate structures for the imaging devices 1A to 1D are disclosed. The substrate structure includes a first substrate, a second substrate, a first through-electrode 10, and a first layer. The substrate structure includes a first region and a second region. In a plan view, a plurality of pixel electrodes 311 are arranged in the first region. In a plan view, the second region is located outside the first region. The first wiring layer includes first wiring in the second region. The second wiring layer includes second wiring in the second region. The first through-electrode 10 electrically connects the first wiring and the second wiring in the second region. The first layer is located on the first through-electrode 10. The height from the bottom surface of the first substrate to the top surface of the first through-electrode 10 is lower than the height from the bottom surface of the first substrate to the bottom surfaces of the plurality of pixel electrodes 311. With this configuration, the first through-electrode 10 can be protected by the first layer when a structure including a photoelectric conversion layer 312 is formed on the substrate structure. This makes it possible to prevent the material of the first through electrode 10 from scattering during the manufacturing of the imaging devices 1A to 1D. The reason for this will be explained below.

[0163] Consider manufacturing imaging devices 1A to 1D using the substrate structure. Specifically, consider forming a photoelectric conversion layer 312 so as to overlap with the first through-hole electrode 10 and the plurality of pixel electrodes 311 in a planar view, and then performing dry etching so that the photoelectric conversion layer 312 overlapping with the first through-hole electrode 10 in a planar view is removed and the photoelectric conversion layer 312 overlapping with the plurality of pixel electrodes 311 in a planar view remains. In this case, the first layer protects the first through-hole electrode 10 from dry etching and can suppress scattering of the material of the first through-hole electrode 10.

[0164] In this configuration, the substrate structure may include portions of the imaging devices 1A to 1D that are the same height as the pixel electrodes 311 and portions that are lower in height than the pixel electrodes 311. The first region may correspond to the pixel region R1. The second region may correspond to the peripheral region R2.

[0165] In embodiments 1 to 4, the manufacturing method of the imaging devices 1A to 1D includes the following steps: a step of preparing a first substrate, a second substrate, and a support substrate 810; a step of bonding the second wiring layer of the second substrate to the support substrate 810; a step of thinning the second semiconductor layer of the second substrate by grinding it down; a step of bonding the ground-down second semiconductor layer of the second substrate to the first wiring layer of the first substrate; a step of removing the support substrate 810 from the second substrate; a step of forming a first through electrode 10 that penetrates the second wiring layer and the second semiconductor layer in the peripheral region R2; a step of forming a first portion on the first through electrode 10; and a step of forming a plurality of pixel electrodes 311 in the pixel region.

[0166] In such a manufacturing method, the first portion can protect the first through-hole electrode 10 in a process after the formation of the first portion. Therefore, scattering of the material of the first through-hole electrode 10 during the manufacturing of the imaging devices 1A to 1D can be suppressed. Specifically, consider forming the photoelectric conversion layer 312 so as to overlap the first through-hole electrode 10 and the plurality of pixel electrodes 311 in a planar view, and then performing dry etching so that the photoelectric conversion layer 312 overlapping the first through-hole electrode 10 in a planar view is removed and the photoelectric conversion layer 312 overlapping the plurality of pixel electrodes 311 in a planar view remains. In this case, the first portion protects the first through-hole electrode 10 from dry etching, and scattering of the material of the first through-hole electrode 10 can be suppressed.

[0167] In embodiments 1 to 4, the manufacturing method of the imaging devices 1A to 1D includes the following steps: forming the one or more layers on a plurality of pixel electrodes 311; and removing the one or more layers above the first through electrode 10 by dry etching.

[0168] According to this manufacturing method, the first through electrode 10 can be protected from dry etching by the first portion, thereby suppressing scattering of the material of the first through electrode 10. Here, as described above, the one or more layers include the photoelectric conversion layer 312.

[0169] In the first and third embodiments, the manufacturing method of the imaging devices 1A and 1C includes the following steps: forming a first layer including a first portion on the first through electrode 10, and forming a plurality of pixel electrodes 311 on the first layer. In this configuration, the first layer is, for example, an insulating film 100.

[0170] The manufacturing methods of the imaging devices 1B and 1D of the second and fourth embodiments include a step of forming a first layer including a first portion and a plurality of pixel electrodes 311 on the first through electrode 10. In this configuration, the first portion is, for example, a protective electrode 351.

[0171] Fifth Embodiment FIG. 13 is a cross-sectional view of an imaging device 1E according to a fifth embodiment. The imaging device 1E is a backside illumination (BSI) type. In the imaging device 1A of FIG. 2, a semiconductor substrate 510 is disposed between the wiring 460 included in the substrate 400 and the wiring 560 included in the substrate 500, and the wiring 460 and the wiring 560 do not face each other. In contrast, in the imaging device 1E of FIG. 13, a semiconductor substrate is not disposed between the wiring 460 included in the substrate 400 and the wiring 560 included in the substrate 500, and the wiring 460 and the wiring 560 face each other. In the imaging device 1A of FIG. 2, photoelectric conversion is performed in the photoelectric conversion layer 312. In contrast, in the imaging device 1E of FIG. 13, photoelectric conversion is performed in the semiconductor substrate 510.

[0172] The substrate 400 includes a semiconductor substrate 410 and a wiring layer 450. The wiring layer 450 is located on the semiconductor substrate 410. The wiring layer 450 includes a plurality of wirings 460. The plurality of wirings 460 includes a wiring 465. The wiring 465 is located in the peripheral region R2.

[0173] The substrate 500 is located on the substrate 400. The substrate 500 includes a semiconductor substrate 510, a wiring layer 550, a transistor 570, a transistor 575, a photoelectric conversion unit 578, and a charge accumulation region 579. The transistor 570, the transistor 575, the photoelectric conversion unit 578, and the charge accumulation region 579 are provided on the semiconductor substrate 510. The semiconductor substrate 510 is located on the wiring layer 550. The wiring layer 550 includes a plurality of wirings 560. The plurality of wirings 560 includes a wiring 565 and a wiring 566. In the example of FIG. 13 , the wiring 565 is located in the peripheral region R2. However, the wiring 565 may be located in the pixel region R1. At least a portion of the wiring 566 is located in the pixel region R1.

[0174] The transistor 570 includes a source 570s, a drain 570d, and a gate 570g. In this embodiment, the transistor 570 is an amplifying transistor.

[0175] The transistor 575 includes a source, a drain, and a gate 575g. One of the source and the drain of the transistor 575 is connected to a photoelectric conversion unit 578. The other of the source and the drain of the transistor 575 forms a charge accumulation region 579. In this embodiment, the photoelectric conversion unit 578 is a photodiode provided on the semiconductor substrate 510. The transistor 575 is a transfer transistor.

[0176] The first through electrode 10 includes vias 11, 12, 14, and a pad 13. The vias 11, 12, and 14 are connected to the pad 13. The via 11 extends downward to a deeper position than the vias 12 and 14. The via 11 penetrates the semiconductor substrate 510 and the wiring layer 550, and is connected to the wiring 465. The via 12 penetrates the semiconductor substrate 510, and is connected to the wiring 565. The via 14 penetrates the semiconductor substrate 510, and is connected to the wiring 566. The pad 13 is flat. The pad 13 has a top surface 10a.

[0177] A via 11 is disposed in a hole provided in the wiring layer 550 and the semiconductor substrate 510. A via 12 is disposed in a hole provided in the semiconductor substrate 510. A via 14 is disposed in a hole provided in the semiconductor substrate 510.

[0178] 13 , the via 11 is connected to an upper surface 465a of the wiring 465. The via 12 is connected to an upper surface 565a of the wiring 565. The via 14 is connected to an upper surface 566a of the wiring 566.

[0179] The wiring 566 is electrically connected to the charge storage region 579 and the gate 570g.

[0180] Signal charges are generated when light is irradiated onto the photoelectric conversion unit 578. The transistor 575 transfers the signal charges from the photoelectric conversion unit 578 to the charge accumulation region 579. The transistor 570 generates and outputs a signal according to the amount of signal charges accumulated in the charge accumulation region 579.

[0181] 13 , the insulating film 100 is located on the first through electrode 10. Specifically, the insulating film 100 is located on the uppermost surface 10a of the first through electrode 10. The insulating film 200 is located on the insulating film 100.

[0182] The light-shielding film 331 is located on the insulating film 200. The protective film 332 is located on the light-shielding film 331. The color filter 341 is located on the protective film 332. The microlens 342 is located on the color filter 341.

[0183] The light-shielding film 331 shields one or some of the pixels 50 from light. The light-shielded pixels 50 operate as optical black pixels.

[0184] In the present embodiment, a configuration is adopted in which the light-shielding film 331 overlaps at least a portion of the first through-hole electrode 10 in a plan view in the finished imaging device 1E. With this configuration, when the light-shielding film 331 is patterned by etching, the light-shielding film 331 remaining in the finished imaging device 1E, together with the insulating film 100 and the insulating film 200, can suppress scattering of the material of the through-hole electrode from the first through-hole electrode 10. Specifically, in the finished imaging device 1E, the light-shielding film 331 overlaps at least a portion of the pad 13 in a plan view. More specifically, in the finished imaging device 1E, the light-shielding film 331 overlaps the entire top surface 10a of the pad 13 in a plan view. Even more specifically, in the finished imaging device 1E, the light-shielding film 331 extends over the entire in-plane direction in a plan view so as to protrude from the outer edge of the top surface 10a of the pad 13.

[0185] As can be understood from the above description, in embodiment 5, the imaging device 1E includes a first substrate, a second substrate, and a first through-electrode 10. The first substrate includes a first semiconductor layer and a first wiring layer. The second substrate is located on the first substrate. The second substrate includes a second semiconductor layer and a second wiring layer. The first through-electrode penetrates the second wiring layer and the second semiconductor layer. In the pixel region R1, a plurality of pixels 50 are arranged on the second substrate in a planar view.

[0186] In embodiment 5, the first substrate corresponds to substrate 400, the first semiconductor layer corresponds to semiconductor substrate 410, the first wiring layer corresponds to wiring layer 450, the second substrate corresponds to substrate 500, the second semiconductor layer corresponds to semiconductor substrate 510, and the second wiring layer corresponds to wiring layer 550.

[0187] In the fifth embodiment, each of the plurality of pixels 50 includes a photoelectric conversion unit 578 provided in the second semiconductor layer.

[0188] The imaging device 1E includes a first layer located on the first through-hole electrode 10. According to this configuration, when the light-shielding film 331 is patterned by etching, the first layer can protect the first through-hole electrode 10 and suppress scattering of the material of the first through-hole electrode 10. In the fifth embodiment, the first layer is an insulating film 100.

[0189] The first layer has a first portion including a first material. The first portion is located on the first through electrode 10. The first through electrode 10 includes a second material. The first portion may be a part of or the entire first layer. In the fifth embodiment, the first portion is an insulating film 100.

[0190] In the fifth embodiment, the first material is an insulating material, for example, the insulating material includes at least one selected from the group consisting of silicon oxide and silicon nitride.

[0191] As can be understood from the above description, the insulating film 200 and the light-shielding film 331 can also protect the first through-electrodes 10 and suppress scattering of the material of the first through-electrodes 10 .

[0192] Sixth Embodiment Fig. 14 is a cross-sectional view of an imaging device 1F according to a sixth embodiment. The imaging device 1F is a back side illumination (BSI) type, similar to the imaging device 1E of Fig. 13. The imaging device 1F of Fig. 14 has a photoelectric conversion layer 312 located above the semiconductor substrate 510, similar to the imaging device 1A of Fig. 2. Photoelectric conversion is performed in the photoelectric conversion layer 312.

[0193] The substrate 500 includes a transistor 570, a transistor 571, and a charge storage region 573. The transistor 570, the transistor 571, and the charge storage region 573 are provided on a semiconductor substrate 510. In this embodiment, the transistor 570 is an amplification transistor. The transistor 571 is a reset transistor. The transistor 571 includes a source, a drain, and a gate 571g. One of the source and the drain of the transistor 570 forms the charge storage region 573.

[0194] The plurality of wirings 560 include a wiring 565 and a wiring 567. A via 15 is disposed in a hole provided in the semiconductor substrate 510. The pixel electrode 311, the gate 570g, and the charge accumulation region 573 are electrically connected by the via 15 and the wiring 567.

[0195] Signal charges are generated when the photoelectric conversion layer 312 is irradiated with light. The generated signal charges are collected by the pixel electrode 311 and sent from the pixel electrode 311 to the charge accumulation region 573 through the via 15 and the wiring 567. The transistor 570 generates and outputs a signal corresponding to the amount of signal charge accumulated in the charge accumulation region 573. The transistor 571 can reset the signal charge and potential in the charge accumulation region 573.

[0196] A hole 590 is provided facing the upper surface 465a of the wiring 465. A pad (not shown) is provided inside the hole 590. An external terminal can be electrically connected to the wiring 465, the first through electrode 10, the control electrode 321, the light-shielding film 331, the counter electrode 313, etc. via the pad.

[0197] Seventh Embodiment A camera system 1000 according to this embodiment will be described with reference to FIG.

[0198] 15 schematically illustrates an example configuration of a camera system 1000 according to this embodiment. The camera system 1000 includes a lens optical system 1100, an imaging device 1200, a system controller 1300, and a camera signal processing circuit 1400. The camera system 1000 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0199] The lens optical system 1100 may include a lens group including, for example, an autofocus lens and a zoom lens, and an aperture. The lens optical system 1100 focuses light onto the imaging plane of the imaging device 1200. The imaging devices 1A to 1F according to the first to sixth embodiments described above can be widely used as the imaging device 1200.

[0200] The system controller 1300 controls the entire camera system 1000. The system controller 1300 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0201] The camera signal processing circuit 1400 has a function of processing an output signal from the image capture device 1200. The camera signal processing circuit 1400 receives output data from the image capture device 1200 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The image capture device 1200 and the camera signal processing circuit 1400 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 1200 as a part thereof. The camera signal processing circuit 1400 is, for example, a DSP (Digital Signal Processor).

[0202] (Additional Note) The present disclosure discloses the following techniques.

[0203] and a peripheral region located outside the pixel region in a plan view. (Technology 1) An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a plan view. In the pixel region, the plurality of pixels are arranged on the second substrate, and each of the plurality of pixels includes: a pixel electrode; a counter electrode located above the pixel electrode; and one or more layers including a photoelectric conversion layer located between the pixel electrode and the counter electrode. The first wiring layer includes first wiring in the peripheral region, and the second wiring layer includes second wiring in the peripheral region. The first through electrode electrically connects the first wiring and the second wiring in the peripheral region. The one or more layers are located on the first layer in the pixel region.

[0204] (Technology 2) The imaging device according to Technology 1, wherein the first layer has a first portion including an insulating material, and the first portion is located on the first through-electrode.

[0205] (Technology 3) The imaging device according to Technology 2, wherein the pixel electrode is located between the first layer and the one or more layers in the pixel region.

[0206] (Technology 4) The imaging device according to Technology 1, wherein the first layer has a first portion including a first material, the pixel electrode includes the first material, and the first portion is located on the first through-electrode.

[0207] (Technology 5) The imaging device according to any one of Technologies 1 to 4, wherein the first layer has a thickness of 30 nm or more.

[0208] (Technology 6) The imaging device according to any one of Techniques 1 to 5, wherein the first wiring layer is located on the first semiconductor layer.

[0209] (Technology 7) The imaging device according to any one of Techniques 1 to 6, wherein the second wiring layer is located on the second semiconductor layer.

[0210] (Technology 8) The imaging device according to Technology 7, wherein the second substrate further includes a transistor including a source and a drain and connected to the pixel electrode, the second semiconductor layer includes a first surface and a second surface closer to the second wiring layer than the first surface, and the source and the drain are located on the second surface.

[0211] (Technology 9) The imaging device according to Technology 7 or 8, wherein the second wiring is closer to the second semiconductor layer than a top surface of the first through electrode, the first through electrode includes a first via, and the first via is connected to a top surface of the second wiring.

[0212] (Technology 10) The imaging device according to Technology 9, wherein the first through electrode further includes a second via, and the second via penetrates the second wiring layer and the second semiconductor layer and is connected to an upper surface of the first wiring.

[0213] (Technology 11) An imaging device described in any one of Technologies 1 to 10, further comprising: a third substrate including a third semiconductor layer and a third wiring layer; and a second through electrode that penetrates the first wiring layer and the first semiconductor layer and is electrically connected to the first through electrode, wherein the first substrate is located on the third substrate, the third wiring layer includes a third wiring in the peripheral region, and the second through electrode electrically connects the first wiring and the third wiring in the peripheral region.

[0214] (Technology 12) The imaging device according to any one of Techniques 1 to 11, wherein, in the plan view, a top surface of the first through electrode includes a portion that does not overlap with the photoelectric conversion layer.

[0215] (Technology 13) A method for manufacturing an imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, the method comprising: bonding the second wiring layer of the second substrate to a support substrate; scraping the second semiconductor layer of the second substrate; bonding the second semiconductor layer of the second substrate to the first wiring layer of the first substrate; removing the support substrate; forming a first through electrode in the peripheral region that penetrates the second wiring layer and the second semiconductor layer; forming a first portion on the first through electrode; and forming a plurality of pixel electrodes in the pixel region.

[0216] (Technology 14) The manufacturing method according to Technology 13, wherein forming the first portion includes forming a first layer including the first portion on the first through electrode, and forming the plurality of pixel electrodes includes forming the plurality of pixel electrodes on the first layer.

[0217] (Technology 15) The manufacturing method according to Technology 13, wherein forming the first portion and forming the plurality of pixel electrodes includes forming a first layer including the first portion and the plurality of pixel electrodes on the first through electrode.

[0218] (Technology 16) The manufacturing method according to any one of Techniques 13 to 15, further comprising: forming one or more layers including a photoelectric conversion layer on the plurality of pixel electrodes; and removing the one or more layers above the first through electrode by dry etching.

[0219] (Technology 17) An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels includes a photoelectric conversion unit provided in the second semiconductor layer, the first wiring layer includes a first wiring in the peripheral region, and the second wiring layer includes a second wiring in the peripheral region, the first through electrode electrically connecting the first wiring and the second wiring in the peripheral region, and the first layer includes a first portion including an insulating material, and the first portion is located on the first through electrode.

[0220] (Technology 18) An imaging device described in Technology 17, wherein the second semiconductor layer is located on the second wiring layer, the first through electrode includes a first via and a second via, the first via penetrates the second semiconductor layer and is connected to an upper surface of the second wiring, and the second via penetrates the second wiring layer and the second semiconductor layer and is connected to an upper surface of the first wiring.

[0221] (Technology 19) An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a light-shielding film; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels performs photoelectric conversion, the first wiring layer includes first wiring in the peripheral region, the second wiring layer includes second wiring in the peripheral region, and the first through electrode electrically connects the first wiring and the second wiring in the peripheral region, and the light-shielding film overlaps at least a portion of the first through electrode in a planar view.

[0222] (Technology 20) A substrate structure for an imaging device, comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixel electrodes; a first region; and a second region located outside the pixel region in a planar view, wherein the plurality of pixel electrodes are arranged in the first region, the first wiring layer includes a first wiring in the second region, the second wiring layer includes a second wiring in the second region, the first through electrode electrically connects the first wiring and the second wiring in the second region, and a height from a bottom surface of the first substrate to an upper surface of the first through electrode is lower than a height from the bottom surface of the first substrate to bottom surfaces of the plurality of pixel electrodes.

[0223] The imaging device according to the present disclosure can be employed, for example, for mobile applications.

[0224] 1A, 1B, 1C, 1D, 1E, 1F, 1X Imaging device 10 First through electrode 20 Second through electrode 10a, 20a Top surface 11, 12, 14, 15, 21, 22 Via 11h, 12h Hole 13, 23 Pad 13h Trench 50 Pixel 100, 200, 314, 670 Insulating film 311 Pixel electrode 312 Photoelectric conversion layer 312a Lower surface 312b Side surface 313 Counter electrode 321 Control electrode 331 Light-shielding film 332 Protective film 341 Color filter 342 Microlens 351 Protective electrode 400, 500, 600 Substrate 410, 510, 610 Semiconductor substrate 410a, 410b, 510a, 510b, 610a, 610b Surface 450, 550, 650 Wiring layer 460, 465, 560, 565, 566, 567, 660, 665 Wiring 482, 488, 581, 583, 588, 682, 683 Bonding film 465a, 565a, 566a Upper surface 570, 571, 575 Transistor 570d Drain 570g, 571g, 575g Gate 570s Source 578 Photoelectric conversion unit 573, 579 Charge storage region 671 Electrode film 810 Support substrate 910 Passivation film 590, 920 Hole 930 Filler 1000 Camera system 1100 Lens optical system 1200 Imaging device 1300 System controller 1400 Camera signal processing circuit R1 Pixel area R2 Peripheral area

Claims

1. An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a plan view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels includes a pixel electrode, a counter electrode located above the pixel electrode, and one or more layers including a photoelectric conversion layer located between the pixel electrode and the counter electrode, the first wiring layer including a first wiring in the peripheral region, the second wiring layer including a second wiring in the peripheral region, the first through electrode electrically connecting the first wiring and the second wiring in the peripheral region, and the one or more layers are located on the first layer in the pixel region.

2. The imaging device according to claim 1, wherein the first layer includes a first portion including an insulating material, and the first portion is located on the first through electrode.

3. The imaging device according to claim 2, wherein the pixel electrode is located between the first layer and the one or more layers in the pixel region.

4. The imaging device according to claim 1, wherein the first layer includes a first portion containing a first material, the pixel electrode includes the first material, and the first portion is located on the first through electrode.

5. The imaging device according to claim 1, wherein the first layer has a thickness of 30 nm or more.

6. The imaging device according to claim 1, wherein the first wiring layer is located on the first semiconductor layer.

7. The imaging device according to claim 1, wherein the second wiring layer is located on the second semiconductor layer.

8. The imaging device described in claim 7, wherein the second substrate further includes a transistor including a source and a drain and connected to the pixel electrode, the second semiconductor layer includes a first surface and a second surface closer to the second wiring layer than the first surface, and the source and the drain are located on the second surface.

9. An imaging device as described in claim 7, wherein the second wiring is closer to the second semiconductor layer than the top surface of the first through electrode, the first through electrode includes a first via, and the first via is connected to the top surface of the second wiring.

10. The imaging device described in claim 9, wherein the first through electrode further includes a second via, and the second via penetrates the second wiring layer and the second semiconductor layer and is connected to the upper surface of the first wiring.

11. The imaging device of claim 1, further comprising: a third substrate including a third semiconductor layer and a third wiring layer; and a second through electrode that penetrates the first wiring layer and the first semiconductor layer and is electrically connected to the first through electrode, wherein the first substrate is located on the third substrate, the third wiring layer includes a third wiring in the peripheral region, and the second through electrode electrically connects the first wiring and the third wiring in the peripheral region.

12. An imaging device according to any one of claims 1 to 11, wherein, in the plan view, the top surface of the first through electrode includes a portion that does not overlap with the photoelectric conversion layer.

13. A method for manufacturing an imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, the method comprising: bonding the second wiring layer of the second substrate to a support substrate; scraping the second semiconductor layer of the second substrate; bonding the second semiconductor layer of the second substrate to the first wiring layer of the first substrate; removing the support substrate; forming a first through electrode in the peripheral region that penetrates the second wiring layer and the second semiconductor layer; forming a first portion on the first through electrode; and forming a plurality of pixel electrodes in the pixel region.

14. The manufacturing method described in claim 13, wherein forming the first portion includes forming a first layer including the first portion on the first through electrode, and forming the plurality of pixel electrodes includes forming the plurality of pixel electrodes on the first layer.

15. The manufacturing method according to claim 13, wherein forming the first portion and forming the plurality of pixel electrodes includes forming a first layer including the first portion and the plurality of pixel electrodes on the first through electrode.

16. The manufacturing method according to any one of claims 13 to 15, further comprising: forming one or more layers including a photoelectric conversion layer on the plurality of pixel electrodes; and removing the one or more layers above the first through electrode by dry etching.

17. An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a first layer located on the first through electrode; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a plan view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels includes a photoelectric conversion unit provided in the second semiconductor layer, the first wiring layer includes a first wiring in the peripheral region, and the second wiring layer includes a second wiring in the peripheral region, the first through electrode electrically connecting the first wiring and the second wiring in the peripheral region, and the first layer includes a first portion including an insulating material, and the first portion is located on the first through electrode.

18. The imaging device described in claim 17, wherein the second semiconductor layer is located on the second wiring layer, the first through electrode includes a first via and a second via, the first via penetrates the second semiconductor layer and is connected to an upper surface of the second wiring, and the second via penetrates the second wiring layer and the second semiconductor layer and is connected to an upper surface of the first wiring.

19. An imaging device comprising: a first substrate including a first semiconductor layer and a first wiring layer; a second substrate located on the first substrate and including a second semiconductor layer and a second wiring layer; a first through electrode penetrating the second wiring layer and the second semiconductor layer; a light-shielding film; a plurality of pixels; a pixel region; and a peripheral region located outside the pixel region in a planar view, wherein the plurality of pixels are arranged on the second substrate in the pixel region, and each of the plurality of pixels performs photoelectric conversion; the first wiring layer includes first wiring in the peripheral region; the second wiring layer includes second wiring in the peripheral region; the first through electrode electrically connects the first wiring and the second wiring in the peripheral region; and the light-shielding film overlaps at least a portion of the first through electrode in a planar view.

Images