Power supply circuit, wireless communication system and chip

Abstract

Provided are a power supply circuit, a wireless communication system and a chip, relating to the technical field of communication devices, and capable of providing various power supply voltages for radio frequency PAs. The power supply circuit comprises: a switching amplification circuit, a linear amplification circuit, a control circuit and an inductor. The control circuit comprises a mode detection circuit, a mode selection circuit and a hysteresis comparison circuit; the mode detection circuit is coupled to a first end of the inductor; the mode selection circuit is coupled to the switching amplification circuit; the hysteresis comparison circuit is coupled to the first end of the inductor and a second end of the inductor; and the mode detection circuit and the hysteresis comparison circuit are further coupled to the mode selection circuit.

Description

Power supply circuit, wireless communication system and chip

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 5, 2024, with application number 202410168666.1 and application name “Power supply circuit, wireless communication system and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of communication equipment, and in particular to a power supply circuit, a wireless communication system, and a chip. Background Art

[0003] As mobile wireless communication technology has gradually transitioned from the traditional voice-centric era to the fourth generation mobile communication technology (4G) of mobile broadband and the networked 5G era, electronic devices with mobile or wireless communication capabilities have become increasingly common, providing wireless communication services to users. With increasing user demand for mobile wireless communication technology, higher communication speeds, and the need for anytime, anywhere access to wireless communication networks, these demands have led to the rapid development of mobile wireless communication technology. Electronic devices must support various communication modes and standards, from 4G Long Term Evolution (LTE) to 5G New Radio (NR), and from early wireless fidelity (Wi-Fi) to today's Wi-Fi 6. Communication bandwidths are increasing, from the 1.4MHz bandwidth of 4G LTE to the 100MHz and even 200MHz bandwidths of 5G NR. Furthermore, broadband Wi-Fi and millimeter wave communication systems offer even wider signal bandwidths. In these electronic devices, processing radio frequency (RF) signals is a common practice. For example, before a radio frequency signal is transmitted, the transmitter needs to use a radio frequency power amplifier (RFPA) to increase the output power of the radio frequency signal (eg, to maintain sufficient energy per bit).

[0004] With the increase in the number of frequency bands and the need to support more advanced wireless communication features such as uplink carrier aggregation (CA) and uplink multiple-input multiple-output (MIMO), several uplink transmitters are required to operate simultaneously. At the same time, to improve cellular system coverage and compensate for the loss between the PA output and the antenna, the output power of the RFPA must become increasingly higher. Therefore, the transmitter of current electronic devices is a transmitter system that coexists with multiple wireless communication systems such as Wi-Fi, cellular, and satellite communications. The actual power of the RFPA used in different wireless communication systems varies. To save power, it is necessary to provide the RFPA with multiple power supply voltages.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a power supply circuit, a wireless communication system, and a chip, which can provide a plurality of power supply voltages for a PA.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect, a power supply circuit includes: a switching amplifier circuit, a linear amplifier circuit, a control circuit, and an inductor. Structurally, the control circuit is coupled to the switching amplifier circuit; the linear amplifier circuit is coupled to the first end of the inductor, and the switching amplifier circuit is coupled to the second end of the inductor. The first end of the inductor is coupled to a power amplifier; the linear amplifier circuit is also coupled to a processing circuit. The control circuit includes a mode detection circuit, a mode selection circuit, and a hysteresis comparator circuit. The mode detection circuit is coupled to the first end of the inductor, the mode selection circuit is coupled to the switching amplifier circuit, and the hysteresis comparator circuit is coupled to the first and second ends of the inductor. The mode detection circuit and the hysteresis comparator circuit are also coupled to the mode selection circuit. Functionally, the linear amplifier circuit is configured to output a first power supply signal based on a first envelope signal output by the processing circuit. Typically, the first envelope signal can be an envelope signal of a transmission signal of the processing circuit. The hysteresis comparison circuit is configured to output a first control signal to the mode selection circuit in response to the voltages at the first and second ends of the inductor. The mode detection circuit is configured to output a mode selection signal to the mode selection circuit in response to the voltage at the first end of the inductor. The mode selection circuit is configured to output a plurality of switching control signals to the switching amplifier circuit in response to the mode selection signal and the first control signal. The switching amplifier circuit is configured to output a first power supply voltage or a second power supply voltage in a first mode in response to the plurality of switching control signals, wherein the second power supply voltage is greater than the first power supply voltage. The switching amplifier circuit is also configured to output a first power supply voltage or a third power supply voltage in a second mode in response to the plurality of switching control signals, wherein the third power supply voltage is greater than the second power supply voltage. The switching amplifier circuit is configured to output a second power supply voltage or a third power supply voltage in a third mode in response to the plurality of switching control signals.Based on the above scheme, the mode detection circuit can generate a mode selection signal based on the voltage at the first end of the inductor, that is, the voltage output by the power supply circuit to the power amplifier. When the mode selection signal enables different modes (for example, the first mode is a buck mode, the second mode is a buck-boost mode, and the third mode is a boost mode, etc.), the mode selection circuit can generate a switch control signal for each switch in the switching amplifier circuit SA based on the corresponding mode selection signal and a first control signal having a duty cycle. The switching amplifier circuit SA can generate two different supply voltages in response to the multiple switch control signals in each mode. In this way, the switching amplifier circuit SA can generate multiple different output voltages when operating in multiple modes. Finally, the voltage Vsw output by the switching amplifier circuit SA is converted from a rectangular wave to a triangular wave through filtering by the inductor L1, and is used together with the first power supply signal output by the LA to power the PA, thereby providing multiple supply voltages to the PA. Compared with directly using the power supply voltage to power the PA or conventional two-voltage power supply, since the power supply circuit provided in the embodiment of the present application can provide multiple supply voltages, it can better adapt to the actual power of wireless communication systems in different frequency bands, thereby saving power consumption.

[0009] In one possible implementation, the power supply circuit further includes: a coupling capacitor coupled between the linear amplifier circuit and the first end of the inductor; a hysteresis comparator circuit coupled to the linear amplifier circuit and the processing circuit; a hysteresis comparator circuit further configured to receive a bias voltage representing a voltage difference across the coupling capacitor; and a hysteresis comparator circuit configured to output a first control signal to the mode selection circuit in response to the voltages at the first and second ends of the inductor, a first power supply signal, and the bias voltage. In the above embodiment, the switching amplifier circuit SA and the linear amplifier circuit LA are directly coupled via the inductor L1. This architecture is commonly referred to in the industry as a direct current (DC) coupling architecture. To ensure optimal ETM performance (including high bandwidth and power efficiency), an alternating current (AC) coupling architecture is crucial. Compared to a DC coupling architecture, an AC coupling architecture can reduce the supply voltage required by the linear amplifier circuit LA, thereby lowering the power supply requirements of the linear amplifier circuit and improving the overall bandwidth and efficiency of the ETM. Therefore, most advanced and practical ETMs are based on an AC coupling architecture. In order to implement the power supply circuit through the AC coupling architecture, a coupling capacitor Cac may be introduced between the linear amplifier circuit LA and the switching amplifier circuit SA.

[0010] In one possible implementation, in a first mode, the output voltage at the first end of the inductor is within a first voltage range; in a second mode, the output voltage at the first end of the inductor is within a second voltage range; and in a third mode, the output voltage at the first end of the inductor is within a third voltage range. The first voltage range overlaps with the second voltage range, and the maximum voltage of the first voltage range is within the second voltage range, while the minimum voltage of the second voltage range is within the first voltage range. The second voltage range overlaps with the third voltage range, and the maximum voltage of the second voltage range is within the third voltage range, while the minimum voltage of the third voltage range is within the second voltage range. Thus, there is significant overlap between the voltage ranges of the first end of the inductor in the first mode and the second mode, and between the second mode and the third mode, ensuring that the linear amplifier circuit can always maintain output voltage switching at any position within the interval formed by the first voltage range, the second voltage range, and the third voltage range, thereby ensuring normal output of the output voltage at the first end of the inductor.

[0011] In a possible implementation, the first mode includes a buck mode, the second mode includes a buck-boost mode, and the third mode includes a boost mode.

[0012] In one possible implementation, the mode selection circuit is further configured to perform timing control on multiple switch control signals; the switching amplifier circuit is configured to, in response to the multiple switch control signals, first switch the first supply voltage to the second supply voltage, then switch the second supply voltage to the third supply voltage, in the second mode; and first switch the third supply voltage to the second supply voltage, then switch the second supply voltage to the first supply voltage. This reduces the overhead of switching device selection and stress in the switching amplifier circuit caused by excessive voltage difference changes caused by directly switching the first supply voltage to the third supply voltage, or by switching the third supply voltage to the first supply voltage, in the second mode.

[0013] In one possible implementation, a mode detection circuit includes: a voltage divider circuit, a first comparator, a second comparator and an output circuit; the voltage divider circuit is coupled to the first end of the inductor; the voltage divider circuit is also coupled to the positive end of the first comparator and the positive end of the second comparator; the voltage divider circuit is configured to output a first divided voltage to the positive end of the first comparator and the positive end of the second comparator, and the first divided voltage is less than the voltage of the first end of the inductor; the reverse end of the first comparator is coupled to the first reference level end, the first comparator is configured to receive a first reference level inputted from the first reference level end, and output a first comparison result based on the first reference level and the first divided voltage; the reverse end of the second comparator is coupled to the second reference level end, the second comparator is configured to receive a second reference level inputted from the second reference level end, and output a second comparison result based on the second reference level and the first divided voltage; wherein the first reference level and the second reference level are not equal; the output circuit is used to output a mode selection signal to the mode selection circuit based on the first comparison result and the second comparison result. Here, the relationship between the first reference level Vref1, the second reference level Vref2, and the first divided voltage VFB3 and the corresponding mode of the mode selection signal are described as follows: when VFB3 < Vref1 < Vref2, the first comparison result and the second comparison result are both logic "0", and the mode selection signal output by the output circuit enables the first mode; when Vref1 < VFB3 < Vref2, the first comparison result is logic "1" and the second comparison result is logic "0", and the mode selection signal output by the output circuit enables the second mode; when Vref1 < Vref2 < VFB3, the first comparison result is logic "1" and the second comparison result is logic "1", and the mode selection signal output by the output circuit enables the third mode. Of course, according to this method, more comparators can be provided to generate more comparison results, thereby achieving output control of four or more levels in more modes.

[0014] In one possible implementation, the power supply circuit further includes: a common-mode rejection circuit and a current conversion circuit; the hysteresis comparison circuit includes: a hysteresis comparator; a common-mode rejection circuit coupled to the first end of the inductor; the common-mode rejection circuit is further coupled to the current conversion circuit and is configured to perform common-mode rejection processing on the voltage at the first end of the inductor to generate a common-mode rejection voltage, and output the common-mode rejection voltage to the current conversion circuit; the current conversion circuit is further coupled to the positive terminal of the hysteresis comparator and is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output it to the positive terminal of the hysteresis comparator; the negative terminal of the hysteresis comparator is further coupled to the first end of the inductor and the second end of the inductor via a current sensor. In this solution, the function of the hysteresis comparison circuit is primarily implemented by the hysteresis comparator, and the input signal for the hysteresis comparator is constructed via the common-mode rejection circuit, the current conversion circuit, and the current sensor.

[0015] In one possible implementation, the power supply circuit further includes: a common-mode rejection circuit and a current conversion circuit; the hysteresis comparison circuit includes: a hysteresis comparator; a common-mode rejection circuit coupled to the linear amplification circuit, the first end of the inductor, and the processing circuit; the common-mode rejection circuit is further coupled to the current conversion circuit and configured to perform common-mode rejection processing on the first power supply signal, the voltage at the first end of the inductor, and the bias voltage to generate a common-mode rejection voltage, and output the common-mode rejection voltage to the current conversion circuit; the current conversion circuit is further coupled to the positive terminal of the hysteresis comparator and configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output it to the positive terminal of the hysteresis comparator; the negative terminal of the hysteresis comparator is further coupled to the first end of the inductor and the second end of the inductor via a current sensor. In this solution, the function of the hysteresis comparison circuit is primarily implemented by the hysteresis comparator, and the input signal for the hysteresis comparator is constructed via the common-mode rejection circuit, the current conversion circuit, and the current sensor.

[0016] In one possible implementation, the control circuit further includes a filter circuit coupled to the inverting terminal of the hysteresis comparator. The filter circuit is mainly used to filter out interference components of the signal input to the inverting terminal of the hysteresis comparator to achieve hardware matching between the input signal and the control circuit.

[0017] In one possible implementation, the power supply circuit further includes: a common-mode suppression circuit and a current conversion circuit; the hysteresis comparison circuit includes: a first comparator, a second comparator, and a latch; the common-mode suppression circuit is coupled to the first end of the inductor; the common-mode suppression circuit is also coupled to the current conversion circuit, and the common-mode suppression circuit is configured to perform common-mode suppression processing on the voltage at the first end of the inductor to generate a common-mode suppression voltage, and output the common-mode suppression voltage to the current conversion circuit; the current conversion circuit is also coupled to the positive end of the first comparator and the positive end of the second comparator, and is configured to convert the common-mode suppression voltage into a first feedback voltage in the current domain, and output it to the positive end of the first comparator and the positive end of the second comparator; the output end of the first comparator is coupled to the first input end of the latch, and the output end of the second comparator is coupled to the second input end of the latch; the output end of the latch is coupled to the mode selection circuit; the reverse end of the first comparator and the reverse end of the second comparator are also coupled to the first end of the inductor and the second end of the inductor through the current sensor. In this solution, the function of the hysteresis comparator circuit is mainly realized by two comparators and a latch, and input signals for the two comparators are constructed by a common-mode suppression circuit, a current conversion circuit, and a current sensor.

[0018] In one possible implementation, the power supply circuit further includes: a common-mode rejection circuit and a current conversion circuit; the hysteresis comparison circuit includes: a first comparator, a second comparator, and a latch; the common-mode rejection circuit is coupled to the linear amplification circuit, the first end of the inductor, and the processing circuit; the common-mode rejection circuit is further coupled to the current conversion circuit, and the common-mode rejection circuit is configured to perform common-mode rejection processing on the first power supply signal, the voltage at the first end of the inductor, and the bias voltage to generate a common-mode rejection voltage, and output the common-mode rejection voltage to the current conversion circuit; the current conversion circuit is further coupled to the positive end of the first comparator and the positive end of the second comparator, and is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain, and output the voltage to the positive end of the first comparator and the positive end of the second comparator; the output end of the first comparator is coupled to the first input end of the latch, and the output end of the second comparator is coupled to the second input end of the latch; the output end of the latch is coupled to the mode selection circuit; the inverse end of the first comparator and the inverse end of the second comparator are further coupled to the first end of the inductor and the second end of the inductor via current sensors. In this solution, the function of the hysteresis comparator circuit is mainly realized by two comparators and a latch, and input signals for the two comparators are constructed by a common-mode suppression circuit, a current conversion circuit, and a current sensor.

[0019] In one possible implementation, the control circuit further includes a first filter circuit and a second filter circuit; the first filter circuit is coupled to the inverting terminal of the first comparator; and the second filter circuit is coupled to the inverting terminal of the second comparator. The first filter circuit and the second filter circuit are primarily used to filter out interference components of the signal input to the hysteresis comparator, thereby achieving hardware matching between the input signal and the control circuit.

[0020] In one possible implementation, the control circuit further includes: a first filter circuit and a second filter circuit; the first filter circuit and the second filter circuit are coupled in series to the inverting terminal of the first comparator; and the second filter circuit is coupled to the inverting terminal of the second comparator. The first filter circuit and the second filter circuit are primarily used to filter out interference components of the signal input to the hysteresis comparator, thereby achieving hardware matching between the input signal and the control circuit.

[0021] In a second aspect, a wireless communication system is provided, comprising: a processing circuit, a power amplifier and a power supply circuit provided by the first aspect and its possible implementation; the power supply circuit is coupled to the processing circuit and the power amplifier, and the processing circuit is also coupled to the power amplifier.

[0022] According to a third aspect, a chip is provided, comprising a substrate and a power supply circuit provided by the first aspect and possible implementations thereof, which is arranged on the substrate.

[0023] In a fourth aspect, an electronic device is provided, comprising a printed circuit board (PCB) and a power supply circuit or a wireless communication system as described above, which is arranged on the PCB.

[0024] It should be understood that the second to fourth aspects of the present application are consistent with the technical solutions of the first aspect of the present application, and the beneficial effects achieved by each aspect and the corresponding possible implementation methods are similar, which will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0026] FIG1 is a top view of an electronic device provided in an embodiment of the present application;

[0027] FIG2 is a bottom view of an electronic device provided in an embodiment of the present application;

[0028] FIG3 is a schematic diagram of the internal structure of an electronic device with its back cover opened according to an embodiment of the present application;

[0029] FIG4 is a schematic structural diagram of a wireless communication system provided in an embodiment of the present application;

[0030] FIG5 is a schematic diagram of the structure of a processing circuit provided in an embodiment of the present application;

[0031] FIG6 is a schematic diagram of curves of a transmission signal and an envelope signal in an embodiment of the present application;

[0032] FIG7 is a schematic structural diagram of a wireless communication system provided by another embodiment of the present application;

[0033] FIG8 is a schematic structural diagram of a power supply circuit provided in an embodiment of the present application;

[0034] FIG9 is a schematic structural diagram of a control circuit provided in an embodiment of the present application;

[0035] FIG10 is a timing diagram of node signals of a power supply circuit provided in an embodiment of the present application;

[0036] FIG11 is a schematic structural diagram of a wireless communication system provided by yet another embodiment of the present application;

[0037] FIG12 is a schematic structural diagram of a power supply circuit provided by another embodiment of the present application;

[0038] FIG13 is a schematic diagram of an output voltage of a power supply circuit provided in an embodiment of the present application;

[0039] FIG14 is a schematic structural diagram of a power supply circuit provided in yet another embodiment of the present application;

[0040] FIG15 is a schematic structural diagram of a power supply circuit provided in yet another embodiment of the present application;

[0041] FIG16 is a schematic structural diagram of a control circuit provided by another embodiment of the present application;

[0042] FIG17 is a schematic structural diagram of a filter circuit provided in an embodiment of the present application;

[0043] FIG18 is a schematic structural diagram of a filter circuit provided by another embodiment of the present application;

[0044] FIG19 is a schematic structural diagram of a filter circuit provided in yet another embodiment of the present application;

[0045] FIG20 is a schematic structural diagram of a current sensor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present application in conjunction with the accompanying drawings. In the following description, reference is made to the accompanying drawings that form a part of this application and illustrate specific aspects of the embodiments of the present application or specific aspects in which the embodiments of the present application can be used. It should be understood that the embodiments of the present application can be used in other aspects and can include structural or logical changes not depicted in the accompanying drawings.

[0047] In this application, unless otherwise clearly specified or limited, the term "coupling" may refer to a method of electrical connection for signal transmission. "Coupling" may be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0048] A linear amplifier (LA), also known as a linear power amplifier, is an amplifier whose output signal amplitude is proportional to the input signal amplitude. Typical linear amplifiers include class B power amplifiers (class B) and class AB power amplifiers (class AB).

[0049] A switching amplifier (SA), also known as a switching power amplifier or switching-type power amplifier, offers higher efficiency than an LA, typically exceeding 90% and even reaching 100% under ideal conditions. Typical switching amplifiers include Class D power amplifiers.

[0050] A hysteresis comparator circuit is characterized by controlling its output by comparing it with two unequal thresholds (constituting a hysteresis window, Vhyst) when the input signal gradually increases or decreases. Specifically, when the input signal gradually increases and falls within the hysteresis window, Vhyst, the output maintains its previous state until the input signal exceeds the larger threshold, at which point the output state changes. When the input signal gradually decreases and falls within the hysteresis window, Vhyst, the output maintains its previous state until the input signal falls below the smaller threshold, at which point the output state changes. Thus, its transfer characteristic has the shape of a "hysteresis" curve. Typical components of a hysteresis comparator circuit include a hysteresis comparator, also known as a Schmitt trigger or hysteresis comparator.

[0051] Embodiments of the present application provide a wireless communication system that can be applied to electronic devices such as mobile phones, tablet computers, personal computers (PCs), personal digital assistants (PDAs), smart watches, netbooks, wearable electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, in-vehicle devices, smart cars, smart speakers, robots, smart glasses, and the like.

[0052] Figures 1 to 3 are schematic diagrams of the structure of an electronic device 100 in an embodiment of the present application, wherein Figure 1 is a top view of the electronic device 100 in an embodiment of the present application, Figure 2 is a bottom view of the electronic device 100 in an embodiment of the present application, and Figure 3 is a schematic diagram of the internal structure of the electronic device 100 in an embodiment of the present application after the back cover is opened. Figure 3 shows a specific configuration of various internal components of the electronic device. The dotted arrow in Figure 3 indicates the direction in which the back cover is opened. It is understandable that the structure of the electronic device 100 shown in Figures 1 to 3 does not constitute a specific limitation on the electronic device 100 described in the embodiment of the present application. In some possible implementations, relative to Figures 1 to 3, the electronic device 100 may also include more or fewer components, a combination of certain components, certain split components, the arrangement of different components, etc., and the embodiment of the present application does not make specific limitations on this.

[0053] 1 and 2 , the electronic device 100 may include a housing 100A. The housing 100A may include a front cover 101, a rear cover 102, and a frame 103. The front cover 101 and the rear cover 102 are arranged opposite to each other. The frame 103 surrounds the front cover 101 and the rear cover 102 and assembles the front cover 101 and the rear cover 102 together.

[0054] The front cover 101 may be a glass cover plate, and the display 194 is disposed below the front cover 101. Structures corresponding to input / output components may be disposed around the periphery of the housing 100A. For example, an opening 105A corresponding to a front camera and / or an opening 106 corresponding to a receiver may be disposed at the top of the front cover 101; a button 190 may be disposed on one side of the frame 103; an opening 107 corresponding to a microphone, an opening 108 corresponding to a speaker, and an opening 109 corresponding to a USB port may be disposed at the bottom of the frame 103; and an opening 105B corresponding to a rear camera may be disposed at the top of the rear cover 102. Of course, other structures may be disposed around the housing 100A, and this is not specifically limited in the embodiments of the present application.

[0055] Furthermore, a cavity may be formed inside the housing 100A, and the aforementioned internal components may be housed within the cavity. For example, as shown in FIG3 , the internal components may be housed within the cavity 104. In practical applications, the internal components may include a printed circuit board (PCB) 110, a battery 142 for powering the internal components, a speaker 170A for converting an audio signal into a sound signal, a receiver 170B for converting an audio signal into a sound signal, a microphone 170C for converting a sound signal into an audio signal, a USB interface 130, a camera 193A, a camera 193B, and a motor 191 for generating a vibration prompt. The PCB 110 may include a processing circuit 111, a power supply circuit 112, a power management integrated circuit (PMIC) 113, a control circuit 114, a SIM card interface 115, and a front-end module (FEM) circuit 116. The FEM circuit 116 may include at least one power amplifier (PA), a switch 1161, an antenna circuit 1162, etc. The power supply circuit 112 may include at least one voltage modulation circuit 151. For example, the voltage modulation circuit 151 may be an envelope tracking modulator (ETM) or an average power tracking (APT) modulator. FIG2 uses the ETM as an example for illustration. The PMIC 113 provides a battery voltage VBatt to the at least one ETM. The at least one ETM may be used to power at least one power amplifier, with one ETM configured for each power amplifier.

[0056] It should be noted that filters, low-noise amplifiers, audio codecs, internal memories, sensors, inductors, capacitors, etc. may also be provided on the PCB 110. Here, in order to clearly illustrate the embodiment of the present application, filters, low-noise amplifiers, audio codecs, internal memories, sensors, inductors, and capacitors are not shown in FIG3 . Furthermore, since the components on the PCB 110 are arranged closely to fit all the components within a limited space, the embodiment of the present application does not specifically limit the arrangement of the components on the PCB 110. For example, the internal components may be provided on one side of the PCB 110 (such as the side facing the rear cover 102); or, the internal components may be provided on both sides of the PCB 110 (such as on the side facing the rear cover 102 and on the side facing the front cover 101), and the embodiment of the present application does not specifically limit this.

[0057] For example, referring to FIG3 , the at least one power amplifier may include: power amplifier PA 162A, power amplifier PA 162B, power amplifier PA 162C, and power amplifier PA 162D. Different power amplifiers may support the same or different frequency bands and be used to amplify radio frequency signals of the same or different frequency bands and the same or different bandwidth ranges. Assume that power amplifier PA 162A may be used to amplify radio frequency signals meeting bandwidth range (wideband) A, power amplifier PA 162B may be used to amplify radio frequency signals meeting bandwidth range B, power amplifier PA 162C may be used to amplify radio frequency signals meeting bandwidth range C, and power amplifier PA 162D may be used to amplify radio frequency signals meeting bandwidth range D, where one or more of A, B, C, and D may be the same or different. Accordingly, at least one envelope tracking modulator may include: envelope tracking modulator ETM 151A, envelope tracking modulator ETM 151B, envelope tracking modulator ETM 151C and envelope tracking modulator ETM 151D, different envelope tracking modulators may support the same or different bandwidth ranges, envelope tracking modulator ETM 151A may power power amplifier PA 162A, envelope tracking modulator ETM 151B may power power amplifier PA 162B, envelope tracking modulator ETM 151C may power power amplifier PA 162C and envelope tracking modulator ETM 151D may power power amplifier PA 162D.

[0058] Specifically, as shown in Figure 4, a structural diagram of a wireless communication system provided in an embodiment of the present application is provided. The wireless communication system can be used in the electronic device 100 shown in Figures 1 to 3 to transmit a radio frequency signal. The wireless communication system may include a processing circuit 40, a power amplifier PA41, a power amplifier PA42, an envelope tracking modulator ETM 41, and an envelope tracking modulator ETM 42. Here, the processing circuit 40 may adopt part or all of the processing circuit 111 shown in Figures 1 to 3. When the wireless communication system transmits a radio frequency signal, the processing circuit 40 may generate a first radio frequency signal TX41 based on the data to be sent on a channel. For example, the baseband circuit in the processing circuit 40 generates a baseband signal (BS, which may be, for example, an in-phase quadrature (IQ) signal) and inputs it to the radio frequency circuit in the processing circuit 40. The radio frequency circuit modulates the baseband signal BS to generate a first radio frequency signal TX41. The first radio frequency signal TX41 is a radio frequency signal.

[0059] Furthermore, the processing circuit 40 may also provide the first envelope signal ET_DAC 41 to the envelope tracking modulators ETM 41 and ETM 42. FIG6 is a schematic diagram of the first RF signal TX41 and the first envelope signal ET_DAC 41 in an embodiment of the present application. Referring to FIG6 , curve 601 represents the waveform of an RF signal (e.g., the first RF signal TX41), and curve 602 is a curve formed by connecting the highest amplitude points of the first RF signal TX41 at different frequencies. Curve 602 can be referred to as the envelope signal of curve 601 (first envelope signal ET_DAC 41). The amplitude of the first envelope signal ET_DAC 41 varies with the amplitude of the first RF signal TX41.

[0060] The envelope tracking modulator ETM 41 is configured to supply power to the power amplifier PA 41 based on the first envelope signal ET_DAC 41. When the first RF signal TX41 satisfies a bandwidth range A (e.g., the first RF signal TX41 satisfies a bandwidth range of a mid-frequency band of a 4G network), the power amplifier PA 41 is configured to amplify the output power of the first RF signal TX41 based on the power supply voltage Vpa 41 output by the envelope tracking modulator ETM 41 and output a first amplified output signal RF_out 41.

[0061] The envelope tracking modulator ETM 42 is configured to supply power to the power amplifier PA 42 based on the first envelope signal ET_DAC 41. When the first RF signal TX 41 meets the bandwidth range B (e.g., the first RF signal TX 41 meets the bandwidth range specified by the frequency bands n41, n77, n78, and n79 in the 5G network), the power amplifier PA 42 is configured to amplify the output power of the first RF signal TX 41 based on the power supply voltage Vpa 42 output by the envelope tracking modulator ETM 42 and output a second amplified output signal RF_out 42. FIG. 4 shows only two ETMs, but it is understood that more or fewer ETMs may be included.

[0062] In some possible implementations, referring to FIG4 , since the wireless communication system can support dual-channel or multi-channel transmission of technologies such as multiple-in multipleout (MIMO), the wireless communication system can provide two or more channels of RF signals, namely TX41 and TX42. When the RF signals of the two channels meet different bandwidth ranges, the system indicators of the wireless communication system will be very different, and the requirements for the envelope tracking modulator will also be very different. Therefore, for different RF signals, multiple envelope tracking modulators need to be set for different bandwidth ranges. For example, referring to FIG4 , the first RF signal TX41 corresponds to the envelope tracking modulator ETM 41, and the second RF signal TX2 corresponds to the envelope tracking modulator ETM 42. The above-mentioned wireless communication system requires a total of two envelope tracking modulators to power power amplifiers of different operating frequency bands under different bandwidth ranges.

[0063] In some possible implementations, the processing circuit 111 shown in FIG3 above may include at least one baseband circuit and at least one radio frequency (RF) circuit, one baseband circuit may correspond to one RF circuit, and the baseband circuit and its corresponding RF circuit may modulate the signal according to one or more communication technologies. For example, the first baseband circuit and the first RF circuit may modulate the signal according to 5G technology, the second baseband circuit and the second RF circuit may frequency modulate the signal according to 4G technology, the third baseband circuit and the third RF circuit may modulate the signal according to WI-FI technology, the fourth baseband circuit and the fourth RF circuit may modulate the signal according to Bluetooth technology, etc. Alternatively, the first baseband circuit and the first RF circuit may also modulate the signal according to 4G technology and 5G technology at the same time, the second baseband circuit and the second RF circuit may also modulate the signal according to Wi-Fi technology, etc. Of course, in some possible implementations, one baseband circuit may also correspond to multiple RF circuits to improve integration. In practical applications, the above-mentioned RF circuit may be implemented using a radio frequency integrated circuit (RFIC).

[0064] In practical applications, FIG5 is a schematic diagram of the structure of the processing circuit 40 in an embodiment of the present application. As shown in FIG5 , the processing circuit 40 may include: a baseband circuit 401 and a radio frequency circuit 402, wherein the baseband circuit 401 may include a baseband encoder 4011 and a baseband processor 4012. The baseband encoder 4011 encodes the received signal source and outputs a baseband signal Bs (e.g., the first transmit signal in the embodiment of the present application) after encoding. The baseband encoder 4011 may also determine the envelope of the baseband signal Bs, for example, by calculating the amplitude of the baseband signal Bs and averaging multiple amplitudes. The baseband encoder 4011 may output an envelope signal ET_DAC (e.g., a first envelope signal ET_DAC41) containing the envelope information of the baseband signal Bs. The baseband processor 4012 may be a central processing unit (CPU) or a microcontroller unit (MCU), etc. The baseband processor 4012 may have processing and control functions to generate power amplifier enable signals, such as the enable signal PA41_EN for the power amplifier PA41 and / or the enable signal PA42_EN for the power amplifier PA42. The RF circuit 402 is configured to receive the baseband signal Bs from the baseband circuit 401 and process the baseband signal Bs to generate a first RF signal TX41. For example, the RF circuit 402 may perform processing such as analog conversion, filtering, and upconversion to obtain the first RF signal TX41. In some possible implementations, the first envelope signal ET_DAC41 may also be generated by the RF circuit 402.

[0065] It should be noted that the one or more communication technologies mentioned above may be understood as one or more mobile communication technologies, such as global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), and emerging wireless communication technologies (also known as fifth-generation mobile communication technologies, English: 5th generation mobile networks or 5th generation wireless systems, 5th-Generation, 5th-Generation New Radio, abbreviated as 5G, 5G technology, or 5G NR). Wireless communication technologies may include wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared technology (IR), etc.

[0066] Of course, the processing circuit 111 may also include an application circuit, wherein the application circuit may include one or more processors. For example, the application circuit may include circuits such as, but not limited to, one or more single-core or multi-core processors. The (one or more) processors may include a combination of general-purpose processors and special-purpose processors (e.g., a graphics processor, an application processor, etc.), such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a neural-network processing unit (NPU), a video codec, a digital signal processor (DSP), etc. These processors may be coupled to or may include memory / storage, and may be configured to execute instructions stored in the memory / storage to enable various applications or systems to run on the electronic device 100.

[0067] In some possible implementations, the baseband circuit and the radio frequency circuit may be integrated with other components of the processing circuit 111 into a single device; alternatively, the baseband circuit and the radio frequency circuit may each be a separate device independent of the processing circuit 111. In some embodiments, a baseband circuit and a radio frequency circuit may be integrated into a single device, which is provided separately from the processing circuit 111.

[0068] In specific applications, the baseband circuitry may include circuitry such as, but not limited to, a core processor. The baseband circuitry (multi-core or more single-core) may include one or more baseband processors or control logic that generate baseband signals for the transmit path of the RF circuitry. The baseband circuitry may be coupled to an application circuit interface to generate and process baseband signals and control the operation of the RF circuitry.

[0069] In some possible implementations, the baseband circuitry may include a third generation (3G) baseband processor, a fourth generation (4G) baseband processor, a fifth generation (5G) baseband processor, or other future baseband processors. The baseband circuitry may handle various wireless control functions for the radio frequency circuitry to communicate with one or more wireless networks.

[0070] In other embodiments, some or all of the functions of the baseband processor may be included in a module stored in the memory and may be executed via a central processing unit (CPU). Wireless control functions may include but are not limited to signal modulation / demodulation, encoding / decoding, radio frequency shifting, etc.

[0071] In practical applications, the modulation / demodulation function of the baseband circuit may include fast Fourier transform (FFT), precoding, constellation mapping / demapping and other functions; the encoding / decoding function of the baseband circuit may include convolution, tail-biting convolution, turbo, Viterbi or low-density parity check (LDPC) encoder / decoder and other functions; of course, the implementation methods of the above-mentioned modulation / demodulation and encoder / decoder functions are not limited to these examples, and other suitable functions may be included in other implementation methods.

[0072] In some embodiments, the baseband circuitry may also include one or more audio digital signal processors (DSPs). The audio DSP(s) may include elements for compression / decompression and echo cancellation, and may include other suitable processing elements in other embodiments.

[0073] In some embodiments, the components of the baseband circuit can be appropriately combined in a single chip machine or a single chipset, and can also be arranged on the same PCB. In addition, some or all components of the baseband circuit and application circuit can be arranged on a system on chip (SOC).

[0074] With the development of wireless communication technology, baseband circuits can support one or more wireless communication technologies. Therefore, baseband circuits can support communication with the evolved universal mobile telecommunications system terrestrial radio access network (E-UTRAN) or other wireless metropolitan area networks (WMAN), wireless local area networks (WLAN), wireless personal area network communication technologies (WPAN), etc. Baseband circuits configured to support multiple wireless communication protocols can be called multi-mode baseband circuits.

[0075] It should be noted that as the functions of the electronic device 100 become increasingly comprehensive, the number of its internal components will also increase. Therefore, the cavity 104 may also include sensors such as a pressure sensor, a gyroscope sensor, an air pressure sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc.

[0076] With the development of communication technology, mobile wireless communication technology has gradually transitioned from the traditional voice-centric era to the fourth generation mobile communication technology (4G) era of mobile broadband and the networked 5G era. Electronic devices with mobile or wireless communication functions have become increasingly common, providing wireless communication services to users. With the increasing demand for mobile wireless communication technology, users are demanding higher communication speeds and the ability to access wireless communication networks anytime and anywhere. These demands have led to the rapid development of mobile wireless communication technology. Electronic devices are required to support various communication modes and standards, from 4G Long Term Evolution (LTE) to 5G New Radio (NR), and from early wireless fidelity (Wi-Fi) to today's Wi-Fi 6. Communication bandwidths are becoming increasingly wider, from the 1.4MHz bandwidth of 4G LTE to the 100MHz and even 200MHz bandwidth of 5G NR. In addition, broadband Wi-Fi and millimeter wave communication systems have even wider signal bandwidths. In these electronic devices, processing radio frequency (RF) signals is a common practice. For example, before transmitting a radio frequency signal, a power amplifier (PA) is required to increase the output power of the radio frequency signal (e.g., to maintain sufficient energy per bit). With the increase in the number of frequency bands and the support of more advanced wireless communication features such as uplink carrier aggregation (CA) and uplink multiple-input multiple-output (MIMO), multiple uplink transmitters are required to operate simultaneously. Furthermore, to improve cellular system coverage and compensate for the loss between the PA output and the antenna, the PA output power is required to be increasingly higher. Therefore, the transmitters of current electronic devices are transmitter systems that coexist with multiple wireless communication systems, such as Wi-Fi, cellular, and satellite communications. The actual power consumption of the PA varies depending on the wireless communication system. The service life of electronic devices is closely related to battery capacity and system efficiency. Given the current situation where battery capacity cannot be further expanded and the power consumption of other components of electronic devices is increasing, improving the transmission efficiency of the radio frequency component, especially the radio frequency PA system, which accounts for a large proportion of power consumption, is very important for extending the service life of the terminal. Therefore, to save power, it is necessary to provide the PA with multiple supply voltages.

[0077] To provide multiple power supply voltages for a power amplifier (PA), an embodiment of the present application provides a wireless communication system, as shown in FIG7 , including: a processing circuit 501, a switching amplifier circuit SA, a linear amplifier circuit LA, a control circuit HC, an inductor L1, and a power amplifier PA1; the control circuit HC is coupled to the switching amplifier circuit SA, for example, the switching amplifier circuit SA includes an output terminal SA out and an input terminal, and the control circuit HC is coupled to the output terminal SA out and the input terminal of the switching amplifier circuit SA; the linear amplifier circuit LA is coupled to a first terminal of the inductor L1, for example, the output terminal LA out of the linear amplifier circuit LA; the switching amplifier circuit SA is coupled to a second terminal of the inductor L1, for example, the output terminal SA out of the switching amplifier circuit SA is coupled to the second terminal of the inductor L1; the first terminal of the inductor L1 is used to couple to the power amplifier PA1; the linear amplifier circuit LA is also used to couple to the processing circuit 501, and the exemplary linear amplifier circuit LA is coupled to the processing circuit 501 via the input terminal; the linear amplifier circuit LA, the switching amplifier circuit SA, the control circuit HC, and the inductor L1 constitute an ETM 502 serving as a power supply circuit for the power amplifier PA1, and the first terminal of the inductor L1 serves as the output terminal ETM out of the ETM 502.

[0078] As shown in Figures 8 and 9 , the control circuit HC includes a mode detection circuit CI1, a mode selection circuit CI2, and a hysteresis comparator circuit CMP1. The mode detection circuit CI1 is coupled to the first end of the inductor L1 (i.e., ETM out), the mode selection circuit CI2 is coupled to the input end of the switching amplifier circuit SA, and the hysteresis comparator circuit CMP1 is coupled to the first end of the inductor L1 (i.e., ETM out) and the second end of the inductor L1 (SA out). The mode detection circuit CI1 and the hysteresis comparator circuit CMP1 are also coupled to the mode selection circuit CI2. Typically, as shown in Figure 8 , the power supply circuit also includes a common-mode rejection circuit CMR and a current conversion circuit SE2. The hysteresis comparator circuit CMP1 can be a hysteresis comparator. The common-mode rejection circuit CMR is coupled to the first terminal of the inductor L1. The common-mode rejection circuit CMR is also coupled to the input terminal of the current conversion circuit SE2. The common-mode rejection circuit CMR is configured to perform common-mode rejection processing on the voltage at the first terminal of the inductor L1 to generate a common-mode rejection voltage, which is then output to the current conversion circuit SE2. The output terminal of the current conversion circuit SE2 is coupled to the positive terminal (+) of the hysteresis comparator CMP1. The current conversion circuit SE2 is configured to convert the common-mode rejection voltage into a first feedback voltage VFB1 in the current domain, which is then output to the positive terminal (+) of the hysteresis comparator CMP1. The negative terminal (-) of the hysteresis comparator CMP1 is also coupled to the first terminal and the second terminal of the inductor L1 via the current sensor SE1. The current sensor SE1 detects the current in the inductor L1 and outputs a second feedback voltage VFB2 to the negative terminal (-) of the hysteresis comparator CMP1. In some examples, the current sensor SE1 and the current conversion circuit SE2 may both use an operational transconductance amplifier (OTA or gm for short).

[0079] Based on the above structure, the linear amplifier circuit LA is configured to output a first power supply signal based on the first envelope signal ET_DAC 41 output by the processing circuit 501; wherein, the hysteresis comparison circuit CMP1 is configured to output a first control signal Vsw-ctrl to the mode selection circuit CI2 in response to the voltages at the first and second ends of the inductor L1; wherein, when the hysteresis comparison circuit adopts a hysteresis comparator, the hysteresis comparator mainly generates the first control signal Vsw-ctrl based on the first feedback voltage VFB1 and the second feedback voltage VFB2; the output mode detection circuit CI1 is configured to output a mode selection signal to the mode selection circuit CI2 in response to the voltage at the first end of the inductor L1; the mode selection circuit CI2 is configured to output a mode selection signal in response to the mode selection signal and the first The control signal Vsw-ctrl outputs multiple switching control signals to the switching amplifier circuit SA; the switching amplifier circuit SA is configured to output a first power supply voltage or a second power supply voltage in a first mode in response to the multiple switching control signals, where the second power supply voltage is greater than the first power supply voltage; the switching amplifier circuit SA is further configured to output a first power supply voltage or a third power supply voltage in a second mode in response to the multiple switching control signals, where the third power supply voltage is greater than the second power supply voltage; the switching amplifier circuit SA is configured to output a second power supply voltage or a third power supply voltage in a third mode in response to the multiple switching control signals. Among them, the first envelope signal ET_DAC 41 can be the envelope signal of the transmission signal BS1 of the processing circuit 501. In Figure 8, the first envelope signal ET_DAC 41 can be represented as a pair of alternating signals (including the input negative voltage Vin-Neg, the input positive voltage Vin-pos) and a DC bias input voltage Vin-DC. To match the input impedance of the linear amplifier circuit LA, the input negative voltage Vin-Neg, the input positive voltage Vin-pos, and the DC bias input voltage Vin-DC are respectively input into the linear amplifier circuit LA through a resistor. In addition, in Figure 8, the input end of the linear amplifier circuit LA connected to the input positive voltage Vin-pos is also coupled to the first end of the inductor L1 (i.e., ETM out) through a feedback loop to achieve feedback control.

[0080] As shown in FIG10 , the first mode is a buck mode, the second mode is a buck-boost mode, and the third mode is a boost mode. Based on the switching amplifier circuit SA shown in FIG9 and FIG10 (a), when the mode selection signals are respectively enable signals for enabling different modes (for example, EN-buck enables the buck mode, EN-BB enables the buck-boost mode, and EN-boost enables the boost mode), the mode selection circuit can generate a switch control signal for each switch in the switching amplifier circuit SA based on the corresponding enable signal and the first control signal Vsw-ctrl having a duty cycle. As shown in FIG9 , the provided switching amplifier circuit SA includes a drive circuit DR and a switched capacitor SC circuit; the switched capacitor SC circuit includes five switches M1-M5 and a flying capacitor Cf. Switches M1-M4 are connected in series between a power supply (for providing a battery voltage Vbatt) and ground GND. Switches M5 and M4 are connected in series between a power supply (for providing a battery voltage Vbatt) and ground GND. A flying capacitor Cf is connected between the connection point between switches M5 and M4 and the connection point between switches M1 and M2. The connection point between switches M2 and M3 serves as an output terminal SA out for providing a voltage Vsw to the second terminal of the inductor. A drive circuit DR is connected to the control terminals of switches M1-M5 and is configured to generate a drive level based on the switch control signals of each switch to control the conduction or cutoff of each switch. In one example, in conjunction with (b) in FIG10 , in the first mode, the output voltage Vsw=Vbatt or 0V can be achieved by controlling the conduction or cutoff of M1 and M2; in another example, in conjunction with (b) in FIG10 , in the second mode, the output voltage Vsw=0V can be achieved by controlling the conduction of M1 and M4, and charging the flying capacitor Cf, and then by controlling the conduction of M2 and M5, the flying capacitor Cf is connected in series with the power supply to achieve the output voltage Vsw=2×Vbatt; in another example, in conjunction with (b) in FIG10 , in the third mode, the output voltage Vsw=Vbatt can be achieved by controlling the conduction of M1, M2 and M4, and charging the flying capacitor Cf, and then by controlling the conduction of M2 and M5, the flying capacitor Cf is connected in series with the power supply to achieve the output voltage Vsw=2×Vbatt. In this way, based on the structure shown in FIG9 , the first supply voltage can be 0V, the second supply voltage is Vbatt, and the third supply voltage is 2×Vbatt.In addition, in the buck-boost mode, in order to reduce the overhead on switch selection and switch stress caused by the excessive change in the voltage difference between the switch before and after switching when Vsw switches between 0V and 2×Vbatt, the mode selection circuit is also configured to perform timing control on multiple switch control signals; the switch amplifier circuit SA is configured to, in response to the multiple switch control signals, first switch the first supply voltage to the second supply voltage in the second mode, and then switch the second supply voltage to the third supply voltage; and, switch the third supply voltage to the second supply voltage, and then switch the second supply voltage to the first supply voltage. For example, based on (c) in Figure 10, when the voltage Vsw is switched from 0V to 2×Vbat, the output voltage Vsw=0V can be achieved by controlling the conduction of M1 and M4, and the flying capacitor Cf can be charged. Then, the output voltage Vsw=Vbatt can be achieved by controlling the conduction of M1 and M2. Finally, the output voltage Vsw=2×Vbatt can be achieved by controlling the conduction of M2 and M5 and connecting the flying capacitor Cf in series with the power supply. When the voltage Vsw is switched from 2×Vbat to 0V, the output voltage Vsw=2×Vbatt can be achieved by controlling the conduction of M2 and M5 and connecting the flying capacitor Cf in series with the power supply. Then, the output voltage Vsw=Vbatt can be achieved by controlling the conduction of M1 and M2. Finally, the output voltage Vsw=0V can be achieved by controlling the conduction of M1 and M4, and the flying capacitor Cf can be charged.

[0081] Based on the above structure, the control circuit HC provided is suitable for an ETM with a three-level switch. The voltage Vsw output by the switch amplifier circuit SA can be 0, Vbatt, or 2xVbatt. The switch amplifier circuit SA has three operating modes:

[0082] Buck mode: Vsw switches between 0 and Vbatt;

[0083] Buck-boost mode: Vsw switches between 0, Vbatt and 2xVbatt;

[0084] Boost mode: Vsw switches between Vbatt and 2xVbatt.

[0085] It should be noted that the embodiments of the present application are not limited to the structure of the switching amplifier circuit SA shown in FIG. 9 . In some examples, the switching amplifier circuit SA can also be implemented using other structures. For example, it can include more flying capacitors Cf and switches, or it can also include an inductor. Furthermore, the switching amplifier circuit SA can provide more modes. For example, in other modes, the SA can output a third supply voltage or a fourth supply voltage under the control of multiple switch control signals, where the fourth supply voltage is greater than the third supply voltage. This means that the switching amplifier circuit SA can be extended to ETM applications with four or more voltage levels.

[0086] In this way, the voltage Vsw is converted from a rectangular wave to a triangular wave after filtering by the inductor L1 and is used to power the PA together with the first power supply signal output by the LA, thereby providing a variety of power supply voltages to the PA. Compared with directly using the power supply voltage to power the PA or the conventional two-voltage power supply, since the power supply circuit provided in the embodiment of the present application can provide a variety of power supply voltages, it can better adapt to the actual power of wireless communication systems in different frequency bands, thereby saving power consumption.

[0087] 9 , the mode detection circuit CI1 includes a voltage divider circuit CI11 , a first comparator CMP2 , a second comparator CMP3 , and an output circuit CI12 .

[0088] The voltage divider circuit CI11 is coupled to the first end of the inductor L1 (i.e., ETM out); the voltage divider circuit CI11 is also coupled to the positive end (+) of the first comparator CMP2 and the positive end (+) of the second comparator CMP3; the voltage divider circuit CI11 is configured to output a first divided voltage VFB3 to the positive end (+) of the first comparator CMP2 and the positive end (+) of the second comparator CMP3, and the first divided voltage VFB3 is less than the voltage of the first end of the inductor L1; the negative end (-) of the first comparator CMP2 is coupled to the first reference level end, and the first comparator CMP2 is configured to receive the first reference level Vref1 inputted by the first reference level end, based on The first reference level Vref1 and the first divided voltage VFB3 output a first comparison result; the reverse terminal (-) of the second comparator CMP3 is coupled to the second reference level terminal, and the second comparator CMP3 is configured to receive the second reference level Vref2 inputted at the second reference level terminal, and output a second comparison result based on the second reference level Vref1 and the first divided voltage VFB3; wherein the first reference level Vref1 and the second reference level Vref2 are not equal; the output circuit CI12 is used to output a mode selection signal to the mode selection circuit C12 based on the first comparison result and the second comparison result. The relationship between the first reference level Vref1, the second reference level Vref2, and the first divided voltage VFB3, and the mode enable signal corresponding to the mode selection signal, is described as follows: When VFB3 < Vref1 < Vref2, the first comparison result and the second comparison result are both logic "0," and the output circuit CI12 outputs EN-buck; when Vref1 < VFB3 < Vref2, the first comparison result is logic "1" and the second comparison result is logic "0," and the output circuit CI12 outputs EN-BB; when Vref1 < Vref2 < VFB3, the first comparison result is logic "1" and the second comparison result is logic "1," and the output circuit CI12 outputs EN-boost. Of course, this approach can also be used to implement output control in four or more levels in more modes by providing more comparators to generate more comparison results.

[0089] In the above scheme, the switching amplifier circuit SA and the linear amplifier circuit LA are directly coupled via inductor L1. This architecture is generally referred to in the industry as a direct current (DC) coupling architecture. It is worth noting that to ensure optimal ETM performance (including high bandwidth and power efficiency), an alternating current (AC) coupling architecture is crucial. Compared to a DC coupling architecture, an AC coupling architecture can reduce the supply voltage required by the linear amplifier circuit LA (i.e., the LA power supplies Vdd-LA and Vss-LA in FIG8 ), thereby reducing the power supply requirements of the linear amplifier circuit and improving the overall bandwidth and efficiency of the ETM. Therefore, most advanced and practical ETMs are based on an AC coupling architecture. As shown in FIG11 , in the ETM502 ( FIG11 ) implemented in an AC coupling architecture, a coupling capacitor Cac is introduced between the linear amplifier circuit LA and the switching amplifier circuit SA. Specifically, as shown in FIG11 , a coupling capacitor Cac is coupled between the output terminal LAout of the linear amplifier circuit LA and the first terminal of the inductor L1. Due to the introduction of the coupling capacitor Cac, the hysteresis comparator circuit also needs to refer to a bias voltage Cap DC in, which represents the voltage difference across the coupling capacitor, when performing hysteresis control. In conjunction with FIG9 , the hysteresis comparator circuit CMP1 is also coupled to the output terminal LAout of the linear amplifier circuit LA and the processing circuit 501. The hysteresis comparator circuit CMP1 is further configured to receive a bias voltage Cap DC in provided by the processing circuit 501. The bias voltage represents the voltage difference across the coupling capacitor. This bias voltage can be pre-configured in the processing circuit 501 by an engineer based on the capacitance value of the coupling capacitor Cac and is adjustable. The hysteresis comparator circuit CMP1 is specifically configured to output a first control signal to the mode selection circuit in response to the voltages across the first and second terminals of the inductor L1, the first power supply signal, and the bias voltage.

[0090] Specifically, as shown in Figure 12, the power supply circuit 502 also includes: a common-mode rejection circuit CMR, a current conversion circuit SE2; the hysteresis comparator CMP1 uses a hysteresis comparator; the common-mode rejection circuit CMR is coupled to the first end of the inductor L1, the output end LA out of the linear amplifier circuit LA, the first end of the inductor L1 and the processing circuit 501; the common-mode rejection circuit CMR is also coupled to the input end of the current conversion circuit SE2, and is configured to perform common-mode rejection processing on the first power supply signal, the voltage of the first end of the inductor L1 and the bias voltage Cap DC in to generate a common-mode rejection voltage, and output the common-mode rejection voltage to the current conversion circuit SE2; the output end of the current conversion circuit SE2 is coupled to the positive end (+) of the hysteresis comparator, and the current conversion circuit SE2 is configured to convert the common-mode rejection voltage into a first feedback voltage VFB1 in the current domain, and output it to the positive end (+) of the hysteresis comparator; the negative end (-) of the hysteresis comparator is also coupled to the first end of the inductor L1 and the second end of the inductor through the current sensor SE1.

[0091] In some examples, in the first mode, the output voltage of the first end of the inductor L1 is within a first voltage range, in the second mode, the output voltage of the first end of the inductor L1 is within a second voltage range, and in the third mode, the output voltage of the first end of the inductor L1 is within a third voltage range. The first voltage range overlaps with the second voltage range, and the maximum voltage of the first voltage range is within the second voltage range, and the minimum voltage of the second voltage range is within the first voltage range. The second voltage range overlaps with the third voltage range, and the maximum voltage of the second voltage range is within the third voltage range, and the minimum voltage of the third voltage range is within the second voltage range. As shown in Figure 13 , when the first mode is buck mode, the second mode is buck-boost mode, and the third mode is boost mode, the voltage at the output of the switching amplifier circuit SA at Vsw in buck-boost mode can range from 0V (ground GND) to a DC voltage of approximately 1.5×Vbatt. The DC voltage at the output of the switching amplifier circuit SA at Vsw in buck and boost modes significantly overlaps with the voltage range of the switching amplifier circuit SA at Vsw in buck-boost mode. As shown in Figure 13 , the solid line represents the actual DC output of the SA and its corresponding modes, while the dashed line represents the DC output voltage level that can be generated in each mode. The significant overlap between these modes ensures that the SA can consistently switch its output voltage within the solid line range. As shown in Figure 13 , the first reference level Vref1 and the second reference level Vref2 satisfy the following relationship: 2×Vref1<Vbatt<2×Vref2. This relationship depends primarily on the ratio of the first divided voltage VFB3 to the voltage of ETM out. As shown in FIG9 , the voltage divider circuit CI11 mainly includes a resistor R1 and a resistor R2 connected in series between ETM out and GND. The first divided voltage VFB3 is obtained from the connection point of the resistor R1 and the resistor R2. In order to maintain a stable output of the first divided voltage VFB3, the voltage divider circuit CI11 generally further includes a capacitor C1 connected in parallel with the resistor R2. When the ratio of the resistor R1 to the resistor R2 is 1:1, the ratio of the first divided voltage VFB3 to the voltage of ETM out is 1:2. Then, the first reference level Vref1 and the second reference level Vref2 satisfy the following relationship: 2×Vref1<Vbatt<2×Vref2. In other examples, when the ratio of the resistor R1 to the resistor R2 is 2:1, the ratio of the first divided voltage VFB3 to the voltage of ETM out is 1:3. Then, the first reference level Vref1 and the second reference level Vref2 satisfy the following relationship: 3×Vref1<Vbatt<3×Vref2.

[0092] In some examples, as shown in FIG9 , the hysteresis comparator CMP1 can be implemented by a hysteresis comparator. Referring to FIG8 , the hysteresis comparator has a fixed hysteresis band (i.e., a hysteresis window Vhyst). A current sensor SE1 and a filter circuit RC1 coupled to the negative terminal (-) of the hysteresis comparator are used to detect the current in the inductor L1. Based on the detection result, a second feedback voltage VFB2 is output to the negative terminal (-) of the hysteresis comparator. In this way, in the ETM, the output current of the switching amplifier circuit SA is monitored, and the hysteresis comparator compares the detected first feedback voltage VFB1 with VFB2±Vhyst to generate a control signal Vsw-ctrl for the switching amplifier circuit SA. Specifically, as shown in conjunction with FIG9 and FIG12 , the duty cycle of the control signal Vsw-ctrl of the switching amplifier circuit SA can be controlled by detecting the voltage difference Vac across the coupling capacitor Cac. Specifically, a hysteresis comparator is used to minimize the output power of the linear amplifier circuit LA (due to LA's relatively low efficiency) to control the duty cycle of Vsw-ctrl. Furthermore, referring to FIG12 , taking the voltage V_ETM out at the first end of the inductor L1, the voltage V_LA out at the output end of LA, and the voltage V_Cap DC in across the coupling capacitor Cac as examples, the relationship between the three satisfies: V_ETM out = V_LA out + V_Cap DC in. The duty cycle of Vsw-ctrl is controlled to ensure that the above equation holds true. VFB2 can be equivalent to the left-hand component of the equation, namely, V_ETM out, while VFB1 can be equivalent to the right-hand component, namely, V_LA out + V_Cap DC in. In ET mode, VFB1 and VFB2 in Figure 12 respectively detect the voltage at the first terminal of inductor L1 (which can be converted into the current flowing through inductor L1 by integrating the current through inductor L1 over time); and the voltage difference V_Cap DC in across coupling capacitor Cac. Based on the aforementioned operating principle, to maximize the output current of switching amplifier circuit SA while minimizing the output power of linear amplifier circuit LA, the voltage across coupling capacitor Cac can be used to determine whether LA is outputting power to load PA or absorbing power. For example, as shown in Figure 12: V_Cap DC in = (V_LAout) - (V_ETM out). If V_Cap DC in > 0, LA is outputting power to load PA. In this case, the output current of inductor L1 should be increased, that is, the duty cycle of Vsw-ctrl needs to be increased. Conversely, when V_Cap DC in < 0, LA is absorbing the output current of SA, indicating that the output current of SA is excessive, and the duty cycle of Vsw-ctrl needs to be reduced.As shown in FIG17 , filter circuit CR1 can be composed of a filter capacitor Cs1 and a filter resistor Rs1, wherein filter capacitor Cs1 and filter resistor Rs1 are connected in parallel between FB2 and ground GND. Filter circuit CR1 is primarily used to filter out interference components of the signal input to the negative terminal of the hysteresis comparator, thereby achieving hardware matching between the input signal and the control circuit. Similarly, a filter circuit can also be provided at the positive terminal (+) of the hysteresis comparator.

[0093] In combination with Figures 14 and 16, another method for constructing a hysteresis comparison circuit CMP1 and a hysteresis band (i.e., a hysteresis window) is shown. In this example, the power supply circuit 502 further includes: a common-mode suppression circuit CMR and a current conversion circuit SE2; the hysteresis comparison circuit CMP1 includes: a first comparator CMP11, a second comparator CMP12, and a latch SR; the common-mode suppression circuit CMR is coupled to the output terminal LAout of the linear amplifier circuit LA, the first end of the inductor L1, and the processing circuit 501; the common-mode suppression circuit CMR is also coupled to the input end of the current conversion circuit SE2, and the common-mode suppression circuit CMR is configured to suppress the first power supply signal, the voltage at the first end of the inductor L1, and the bias voltage Cap DC In performs common-mode rejection processing to generate a common-mode rejection voltage, which is then output to current conversion circuit SE2. The output of current conversion circuit SE2 is coupled to the positive terminal (+) of first comparator CMP11 and the positive terminal (+) of second comparator CMP12. Current conversion circuit SE2 is configured to convert the common-mode rejection voltage into a first feedback voltage VFB1 in the current domain, which is then output to the positive terminal (+) of first comparator CMP11 and the positive terminal (+) of second comparator CMP12. The negative terminal (-) of first comparator CMP11 and the negative terminal (-) of second comparator CMP12 are also coupled to the first and second terminals of inductor L1 via current sensor SE1. As shown in FIG14 , the power supply circuit further includes a first filter circuit RC1 and a second filter circuit RC2. The first filter circuit RC1 is coupled to the negative terminal (-) of first comparator CMP11, while the second filter circuit RC2 is coupled to the negative terminal of second comparator CMP12. In the architecture shown in Figure 14, two sense currents, Isens and Isens+Ihyst, are generated by current sensor SE1, with a small DC offset (Ihyst) introduced between them. The sense currents Isens and Isens+Ihyst flow into filter circuits RC1 and RC2, respectively, generating feedback voltages VFB2- and VFB2+. Both feedback voltages VFB2- and VFB2+ are proportional to the inductor current, but there is a slight offset voltage between them (caused by Ihyst). The feedback voltages VFB2- and VFB2+ serve as the upper and lower limits of the hysteresis band, respectively. This is equivalent to constructing VFB2 in the above example using the feedback voltages VFB2- and VFB2+, thereby controlling the duty cycle of Vsw-ctrl. Specifically, as shown in Figure 17, the first filter circuit CR1 can be composed of a filter capacitor Cs1 and a filter resistor Rs1, with the filter capacitor Cs1 and filter resistor Rs1 connected in parallel between FB2- and ground GND. The second filter circuit CR2 may be composed of a filter capacitor Cs2 and a filter resistor Rs2 , wherein the filter capacitor Cs2 and the filter resistor Rs2 are connected in parallel between FB2+ and the ground GND.The first filter circuit CR1 and the second filter circuit CR2 are mainly used to filter out interference components of the signal input to the hysteresis comparator to achieve hardware matching between the input signal and the control circuit. Similarly, a filter circuit can also be set between the current conversion circuit SE2 and the hysteresis comparator circuit CMP1.

[0094] In the solution shown in FIG14 , the requirements for precise matching between the two filter circuits and the sense currents Isens and Isens+Ihyst are very high. Any mismatch between these components may lead to significant changes in the switching frequency in the switching amplifier circuit SA and, in some cases, cause circuit failure. To address this problem, an alternative implementation scheme is proposed in FIG15 . In addition, it is understandable that the hysteresis comparison circuit CMP1 and the construction method of the hysteresis band (i.e., hysteresis window) provided in FIG14-FIG16 can also be applied to the ETM of the DC-coupled architecture, that is, the control circuit HC provided in FIG16 can also be applied to the power supply circuit provided in FIG8 . Since only the control circuit HC provided in FIG16 replaces the control circuit HC in FIG8 , its structure and connection relationship can refer to the description of the corresponding embodiments of FIG14 and FIG16 , and therefore will not be described in detail.

[0095] In FIG15 , the power supply circuit 502 further includes a first filter circuit RC1 and a second filter circuit RC2. The series connection of the first filter circuit RC1 and the second filter circuit RC2 is coupled to the negative terminal (-) of the first comparator CMP11. The second filter circuit RC2 is coupled to the negative terminal (-) of the second comparator CMP2. As shown in FIG18 , the first filter circuit CR1 can be composed of a filter capacitor Cs1 and a filter resistor Rs1, wherein the filter capacitor Cs1 and the filter resistor Rs1 are connected in parallel between VFB2+ and VFB2-. The second filter circuit CR2 can be composed of a filter capacitor Cs2 and a filter resistor Rs2, wherein the filter capacitor Cs2 and the filter resistor Rs2 are connected in parallel between VFB2- and ground GND. In addition, since the voltage division ratio of VFB2+ and VFB2- is mainly determined by the voltage division effect of resistors Rs1 and Rs2, the filter capacitors Cs1 and Cs2 can also be equivalent to a capacitor CS1. As shown in Figure 19, resistors Rs1 and Rs2 are connected in series between VFB2+ and GND, capacitor CS1 is connected in series between VFB2+ and GND, and the connection point of resistors Rs1 and Rs2 is connected to VFB2-. In this way, two sensing currents Isens are generated by the current sensor SE1. Since resistors Rs1 and Rs2 are connected in series, the value of resistor Rs1 is significantly smaller than that of resistor Rs2, resulting in a small voltage on resistor Rs1. The voltages at the two ends of resistor Rs1 serve as the upper and lower limits of the hysteresis band of the hysteresis comparator. Because resistors Rs1 and Rs2 are relatively matched and connected in series, this implementation relaxes the requirements for device matching.

[0096] Furthermore, as shown in FIG20 , if the current sensor SE1 is equivalent to one or more current sources, then in addition to providing the current source ISE1 for generating the sense current Isens, two variable current sources ICMP and ICMN can be added to the current sensor SE1 to increase the common-mode tuning range of the VFB2+ and VFB2- signals. The variable current source ICMP is connected between the power supply Vdd and VFB2+, and the variable current source ICMP is connected between the ground GND and VFB2+. In this way, by increasing the current output by the variable current source ICMP or decreasing the current of the variable current source ICMN, the common-mode component in VFB2+ and VFB2- can be increased. This common-mode component is the DC offset in VFB2+ and VFB2-. Specifically, adjusting the magnitude of this common-mode component adjusts the hysteresis band of the hysteresis comparator.

[0097] In addition, in some examples, a chip, a chip substrate, and the above-mentioned power supply circuit arranged on the substrate are also provided.

[0098] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0099] Although the present application has been described with reference to specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the scope of the present application. Accordingly, this specification and the drawings are merely illustrative of the present application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the scope of the present application. Thus, the present application is intended to include such modifications and variations as fall within the scope of the claims of the present application and their equivalents.

Claims

1. A power supply circuit, characterized in that: include: Switching amplifier circuit, linear amplifier circuit, control circuit and inductor; The control circuit is coupled to the switch amplifier circuit; The linear amplifier circuit is coupled to the first end of the inductor, and the switching amplifier circuit is coupled to the second end of the inductor. The first end of the inductor is used to couple to a power amplifier. The linear amplifier circuit is also used to couple to a processing circuit. The control circuit includes a mode detection circuit, a mode selection circuit and a hysteresis comparison circuit; The mode detection circuit is coupled to the first end of the inductor, the mode selection circuit is coupled to the switch amplifier circuit, the hysteresis comparison circuit is coupled to the first end of the inductor and the second end of the inductor, and the mode detection circuit and the hysteresis comparison circuit are further coupled to the mode selection circuit; The linear amplifying circuit is configured to output a first power supply signal based on the first envelope signal output by the processing circuit; The hysteresis comparison circuit is configured to output a first control signal to the mode selection circuit in response to voltages at the first terminal and the second terminal of the inductor; the mode detection circuit being configured to output a mode selection signal to the mode selection circuit in response to a voltage at the first terminal of the inductor; The mode selection circuit is configured to output a plurality of switch control signals to the switch amplifier circuit in response to the mode selection signal and the first control signal; The switching amplifier circuit is configured as follows: In response to the multiple switch control signals, the switch amplifier circuit outputs a first power supply voltage or a second power supply voltage in a first mode, wherein the second power supply voltage is greater than the first power supply voltage; In response to the plurality of switch control signals, the switch amplifier circuit outputs the first power supply voltage or the third power supply voltage in a second mode, wherein the third power supply voltage is greater than the second power supply voltage; and In response to the plurality of switch control signals, the switching amplifier circuit outputs the second power supply voltage or the third power supply voltage in a third mode.

2. The power supply circuit according to claim 1, characterized in that: The device further comprises: a coupling capacitor coupled between the linear amplifying circuit and the first end of the inductor; The hysteresis comparison circuit is further coupled to the linear amplification circuit and the processing circuit; The hysteresis comparison circuit is further configured to receive a bias voltage, wherein the bias voltage is configured to represent a voltage difference across the coupling capacitor; The hysteresis comparison circuit is configured to output a first control signal to the mode selection circuit in response to the voltages at the first and second ends of the inductor, including: the hysteresis comparison circuit is used to output the first control signal to the mode selection circuit in response to the voltages at the first and second ends of the inductor, the first power supply signal, and the bias voltage.

3. The power supply circuit according to claim 1 or 2, characterized in that: In the first mode, the output voltage of the first end of the inductor is within a first voltage range, in the second mode, the output voltage of the first end of the inductor is within a second voltage range, and in the third mode, the output voltage of the first end of the inductor is within a third voltage range; The first voltage range overlaps with the second voltage range, and a maximum voltage of the first voltage range is within the second voltage range, and a minimum voltage of the second voltage range is within the first voltage range; The second voltage range overlaps with the third voltage range, and a maximum voltage of the second voltage range is within the third voltage range, and a minimum voltage of the third voltage range is within the second voltage range.

4. The power supply circuit according to any one of claims 1 to 3, characterized in that: The first mode includes a buck mode, the second mode includes a buck-boost mode, and the third mode includes a boost mode.

5. The power supply circuit according to claim 4, characterized in that: The mode selection circuit is further configured to perform timing control on the plurality of switch control signals; The switching amplifier circuit is configured to, in response to the multiple switch control signals, first switch the first supply voltage to a second supply voltage and then switch the second supply voltage to a third supply voltage in the second mode; And, the third supply voltage is switched to the second supply voltage, and then the second supply voltage is switched to the first supply voltage.

6. The power supply circuit according to any one of claims 1 to 5, characterized in that: The mode detection circuit includes: a voltage divider circuit, a first comparator, a second comparator and an output circuit; The voltage divider circuit is coupled to the first end of the inductor; the voltage divider circuit is also coupled to the positive end of the first comparator and the positive end of the second comparator; the voltage divider circuit is configured to provide a positive voltage to the positive end of the first comparator and the positive end of the second comparator. The first end of the inductor outputs a first divided voltage, wherein the first divided voltage is less than the voltage at the first end of the inductor; The reverse terminal of the first comparator is coupled to the first reference level terminal, and the first comparator is configured to receive a first reference level input by the first reference level terminal, and output a first comparison result based on the first reference level and the first divided voltage; The reverse terminal of the second comparator is coupled to the second reference level terminal, and the second comparator is configured to receive a second reference level inputted at the second reference level terminal and output a second comparison result based on the second reference level and the first divided voltage; wherein the first reference level is not equal to the second reference level; The output circuit is configured to output the mode selection signal to the mode selection circuit based on the first comparison result and the second comparison result.

7. The power supply circuit according to any one of claims 1 to 6, characterized in that: The power supply circuit further includes: a common mode suppression circuit and a current conversion circuit; the hysteresis comparison circuit includes: a hysteresis comparator; The common-mode suppression circuit is coupled to the first end of the inductor; the common-mode suppression circuit is also coupled to the input end of the current conversion circuit, and is configured to perform common-mode suppression processing on the voltage at the first end of the inductor to generate a common-mode suppression voltage, and output the common-mode suppression voltage to the current conversion circuit; The output terminal of the current conversion circuit is coupled to the positive terminal of the hysteresis comparator, and the current conversion circuit is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output it to the positive terminal of the hysteresis comparator; The inverting terminal of the hysteresis comparator is further coupled to the first terminal of the inductor and the second terminal of the inductor through a current sensor.

8. The power supply circuit according to claim 2, wherein: The power supply circuit further includes: a common mode suppression circuit and a current conversion circuit; the hysteresis comparison circuit includes: a hysteresis comparator; The common-mode suppression circuit is coupled to the linear amplification circuit, the first end of the inductor, and the processing circuit; the common-mode suppression circuit is also coupled to the current conversion circuit and is configured to perform common-mode suppression processing on the first power supply signal, the voltage at the first end of the inductor, and the bias voltage to generate a common-mode suppression voltage, and output the common-mode suppression voltage to the current conversion circuit; The current conversion circuit is further coupled to the positive terminal of the hysteresis comparator, and the current conversion circuit is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output the first feedback voltage to the positive terminal of the hysteresis comparator; The inverting terminal of the hysteresis comparator is further coupled to the first terminal of the inductor and the second terminal of the inductor through a current sensor.

9. The power supply circuit according to claim 7 or 8, characterized in that: The control circuit further includes a filter circuit coupled to the reverse end of the hysteresis comparator.

10. The power supply circuit according to any one of claims 1 to 9, characterized in that: The power supply circuit further includes: a common mode suppression circuit and a current conversion circuit; the hysteresis comparison circuit includes: a first comparator, a second comparator and a latch; The common-mode suppression circuit is coupled to the first end of the inductor; the common-mode suppression circuit is also coupled to the current conversion circuit, and the common-mode suppression circuit is configured to perform common-mode suppression processing on the voltage at the first end of the inductor to generate a common-mode suppression voltage, and output the common-mode suppression voltage to the current conversion circuit; The current conversion circuit is coupled to the positive terminal of the first comparator and the positive terminal of the second comparator, and is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output it to the positive terminal of the first comparator and the positive terminal of the second comparator; The output terminal of the first comparator is coupled to the first input terminal of the latch, and the output terminal of the second comparator is coupled to the second input terminal of the latch; An output terminal of the latch is coupled to the mode selection circuit; The inverting end of the first comparator and the inverting end of the second comparator are further coupled to the first end of the inductor and the second end of the inductor through current sensors.

11. The power supply circuit according to claim 2, characterized in that: The power supply circuit further includes: a common mode suppression circuit and a current conversion circuit; the hysteresis comparison circuit includes: a first comparator, a second comparator and a latch; The common-mode suppression circuit is coupled to the output terminal of the linear amplification circuit, the first terminal of the inductor, and the processing circuit; the common-mode suppression circuit is also coupled to the current conversion circuit, and is configured to perform common-mode suppression processing on the first power supply signal, the voltage at the first terminal of the inductor, and the bias voltage to generate a common-mode suppression voltage, and output the common-mode suppression voltage to the current conversion circuit; The current conversion circuit is further coupled to the positive terminal of the first comparator and the positive terminal of the second comparator, and is configured to convert the common-mode rejection voltage into a first feedback voltage in the current domain and output it to the positive terminal of the first comparator and the positive terminal of the second comparator; The output terminal of the first comparator is coupled to the first input terminal of the latch, and the output terminal of the second comparator is coupled to the second input terminal of the latch; An output terminal of the latch is coupled to the mode selection circuit; The inverting end of the first comparator and the inverting end of the second comparator are further coupled to the first end of the inductor and the second end of the inductor through current sensors.

12. The power supply circuit according to claim 10 or 11, characterized in that: The control circuit further includes: a first filter circuit and a second filter circuit; the first filter circuit is coupled to the inverting end of the first comparator; and the second filter circuit is coupled to the inverting end of the second comparator.

13. The power supply circuit according to claim 10 or 11, characterized in that: The control circuit further includes: a first filtering circuit and a second filtering circuit; The series structure of the first filter circuit and the second filter circuit is coupled to the inverting end of the first comparator; the second filter circuit is coupled to the inverting end of the second comparator.

14. A wireless communication system, characterized in that: include: A processing circuit, a power amplifier, and a power supply circuit according to any one of claims 1 to 13; The power supply circuit is coupled to the processing circuit and the power amplifier, and the processing circuit is further coupled to the power amplifier.

15. A chip, characterized in that: The invention comprises a substrate, and a power supply circuit according to any one of claims 1 to 13 arranged on the substrate.

Images