Memory cell, memory, memory preparation method, chip, and electronic device

Abstract

The present application discloses a memory cell, a memory, a memory preparation method, a chip, and an electronic device. The memory cell comprises a first transistor and a second transistor which are arranged in a first direction parallel to a substrate; a first gate of the first transistor extends in a second direction perpendicular to the substrate, a second gate and a first semiconductor layer of the first transistor both extend in the first direction, the first gate surrounds the first semiconductor layer, and the first semiconductor layer surrounds the second gate; and a third gate of the second transistor extends in the second direction, and a second semiconductor layer of the second transistor is connected to the second gate.

Description

Storage unit, memory, memory manufacturing method, chip and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202410167340.7, application date February 6, 2024, and invention name “Memory unit, memory, memory preparation method, chip and electronic device”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] Embodiments of the present application relate to the field of semiconductor technology, and in particular to a storage unit, a memory, a method for preparing a memory, a chip, and an electronic device. Background Art

[0004] With the development of semiconductor technology, there are more and more types of memories, and dynamic random access memory (DRAM) is one of them. The memory includes multiple storage units.

[0005] In recent years, to overcome the problem that 1T1C (1Transistor 1Capacitor) structured memory cells require larger capacitors, making further scaling of memory cells more difficult, 2T0C structured memory cells have attracted much attention. However, the storage density of memories including 2T0C structured memory cells still needs to be improved.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a memory unit, a memory, a method for manufacturing a memory, a chip, and an electronic device, which can be used to improve the integration density and storage density of the memory. The technical solution is as follows:

[0008] On the one hand, an embodiment of the present application provides a memory cell, which includes a first transistor and a second transistor arranged along a first direction parallel to a substrate; the first gate of the first transistor extends along a second direction perpendicular to the substrate, the second gate of the first transistor and the first semiconductor layer both extend along the first direction, the first gate surrounds the first semiconductor layer, and the first semiconductor layer surrounds the second gate; the third gate of the second transistor extends along the second direction, and the second semiconductor layer of the second transistor is connected to the second gate.

[0009] On the other hand, an embodiment of the present application also provides a memory, which includes a plurality of memory cell layers stacked vertically on a substrate and a plurality of first bit lines, a plurality of second bit lines, a plurality of first word lines and a plurality of second word lines connected to the plurality of memory cell layers; the memory cell layer includes a plurality of memory cells arranged in an array; the memory cell is any of the memory cells described above.

[0010] On the other hand, an embodiment of the present application further provides a method for preparing a memory, the method being used to prepare the memory, the memory comprising a plurality of memory cell layers vertically stacked on a substrate, and a plurality of first bit lines, a plurality of second bit lines, a plurality of first word lines, and a plurality of second word lines connected to the plurality of memory cell layers; the memory cell layer comprising a plurality of memory cells arranged in an array, the memory cells comprising first transistors and second transistors arranged along a first direction parallel to the substrate; the method comprising:

[0011] Alternatingly preparing isolation layers and sacrificial layers on the substrate to obtain a stacked structure; etching the stacked structure along a second direction perpendicular to the substrate to form a first trench penetrating the stacked structure, and depositing a filling material in the first trench to obtain a first structure; forming the plurality of first bit lines and the plurality of second bit lines based on the first structure; forming a plurality of first transistors connected to the plurality of first transistors and a plurality of first word lines connected to the plurality of first transistors; forming a plurality of second transistors connected to the plurality of second bit lines and a plurality of second word lines connected to the plurality of second transistors;

[0012] The first gate of the first transistor extends along the second direction, the second gate of the first transistor and the first semiconductor layer both extend along the first direction, the first gate surrounds the first semiconductor layer, and the first semiconductor layer surrounds the second gate; the third gate of the second transistor extends along the second direction, and the second semiconductor layer of the second transistor is connected to the second gate.

[0013] On the other hand, an embodiment of the present application further provides a chip, which includes any of the memories described above.

[0014] On the other hand, an embodiment of the present application further provides an electronic device, which includes any of the memories described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] FIG1 is a logic circuit diagram of a memory cell provided in an embodiment of the present application;

[0017] FIG2 is a schematic structural diagram of a storage unit provided in an embodiment of the present application;

[0018] FIG3 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0019] FIG4 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0020] FIG5 is a flow chart of a method for preparing a memory provided in an embodiment of the present application;

[0021] FIG6 is a schematic diagram of a stacking structure provided in an embodiment of the present application;

[0022] FIG7 is a schematic diagram of a structure after forming a first trench according to an embodiment of the present application;

[0023] FIG8 is a schematic diagram of a first structure provided in an embodiment of the present application;

[0024] FIG9 is a schematic diagram of a structure after forming an etch stop layer according to an embodiment of the present application;

[0025] FIG10 is a schematic diagram of a structure after forming a third etched groove according to an embodiment of the present application;

[0026] FIG11 is a schematic diagram of a structure after forming a second bit line 300 according to an embodiment of the present application;

[0027] FIG12 is a schematic diagram of a structure after removing an etch stop layer provided in an embodiment of the present application;

[0028] FIG13 is a schematic diagram of a second structure provided in an embodiment of the present application;

[0029] FIG14 is a schematic diagram of a structure after forming a third trench according to an embodiment of the present application;

[0030] 15 is a schematic diagram of a structure after sequentially depositing a second insulating material and a second conductive material on the sidewalls of a third trench according to an embodiment of the present application;

[0031] FIG16 is a schematic diagram of a fifth structure provided in an embodiment of the present application;

[0032] FIG17 is a schematic diagram of a third structure provided in an embodiment of the present application;

[0033] FIG18 is a schematic diagram of a structure after depositing a fourth conductive material according to an embodiment of the present application;

[0034] FIG19 is a schematic diagram of a structure after depositing a fourth conductive material according to an embodiment of the present application;

[0035] FIG20 is a schematic diagram of a structure after forming a sixth trench according to an embodiment of the present application;

[0036] FIG21 is a schematic diagram of a sixth structure provided in an embodiment of the present application;

[0037] FIG22 is a schematic diagram of a structure after forming an eighth groove provided by an embodiment of the present application;

[0038] 23 is a schematic diagram of a structure after the third conductive material on the sidewall of a seventh trench is completely etched, provided by an embodiment of the present application;

[0039] FIG24 is a schematic diagram of a fourth structure provided in an embodiment of the present application;

[0040] FIG25 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0041] FIG26 is a schematic structural diagram of an electronic device provided in an embodiment of the present application.

[0042] The reference numerals in the figures represent respectively:

[0043] 100 - memory cell; 110 - first transistor; 120 - second transistor; 111 - first gate; 112 - second gate; 113 - first semiconductor layer; 121 - third gate; 122 - second semiconductor layer; 200 - first bit line; 300 - second bit line; 400 - first word line; 500 - second word line; 600 - connection line. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions and advantages of this application more clear, the following will further describe the embodiments of this application in detail with reference to the accompanying drawings. However, it should be understood that these descriptions are only exemplary and are not intended to limit the scope of this application.

[0045] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present application. These drawings are not drawn to scale, and for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0046] The terms used in the application are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used in the present application indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components. In the present application, unless otherwise clearly specified and limited, the terms "connected", "connected" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral whole; it can be a mechanical connection, an electrical connection or mutual communication; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. The term "layer" used in the present application refers to a portion of a material including an area with a thickness. The layer can extend horizontally, vertically and / or along a conical surface.

[0047] The terms "first", "second" and the like in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0048] The embodiments of the present application can be applied to a 2T scenario, where one transistor is a read transistor and the other is a write transistor. This application uses a 2T0C scenario as an example. Memory cells with a 2T0C (2 Transistor 0 Capacitor) structure are increasingly widely used. However, the integration density and storage density of memories including memory cells with a 2T0C structure still need to be improved.

[0049] A memory device includes multiple memory cells. Embodiments of the present application provide a novel 2T0C memory cell structure, which is more spatially advantageous for high-density memory cell design and more industrially feasible in terms of process, as well as a 3D memory device. The 2T0C memory cell includes two transistors, one of which is a read transistor and the other is a write transistor. Figure 1 shows a logic circuit diagram of the 2T0C memory cell provided by the present application.

[0050] As shown in Figure 1, the 2T0C memory cell includes a write transistor and a read transistor, wherein the read transistor is a dual-gate transistor. The first gate of the read transistor is used to connect to the read transistor word line, the second gate of the read transistor is connected to an electrode (source or drain) of the write transistor, and the second gate of the read transistor and the electrode connected thereto in the write transistor constitute a storage node (SN) for storing data. One of the source and drain electrodes of the read transistor is used to connect to the read transistor bit line. The write transistor has a gate and two electrodes (one of which is a source and the other is a drain), the gate of the write transistor is used to connect to the write transistor word line, one of the two electrodes of the write transistor is connected to the second gate of the read transistor, and the other electrode is used to connect to the write transistor bit line.

[0051] In one possible implementation, the write transistor or the read transistor may be an N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or a P-type MOSFET.

[0052] In the logic circuit diagram shown in Figure 1, a large voltage is applied to the gate of the write transistor through the write transistor word line, turning on the write transistor. When a "1" is to be written, a first voltage is applied to the write transistor bit line; when a "0" is to be written, a second voltage is applied to the write transistor bit line. There is a certain voltage difference between the first voltage and the second voltage.

[0053] To read a memory cell, a reference voltage is applied to the read transistor word line (a voltage that only allows the stored data to be read). If data "1" is stored in the second gate of the first transistor, the reference voltage can turn on the first transistor, and current flows between the read transistor bit line and the read transistor word line. However, if data "0" is stored in the second gate of the first transistor, the reference voltage keeps the first transistor off, and no current flows between the read transistor bit line and the read transistor word line. In other words, whether the read data is "1" or "0" can be determined by determining whether current flows between the read transistor bit line and the read transistor word line.

[0054] FIG2 shows a schematic structural diagram of a storage unit provided in an embodiment of the present application, wherein (1) in FIG2 shows a top view of a storage unit provided in an embodiment of the present application, and (2) in FIG2 shows a front view of a storage unit provided in an embodiment of the present application. In FIG2 , the first direction and the third direction are perpendicular to each other and are both parallel to the substrate, and the second direction is perpendicular to the substrate. It should be noted that the first direction, the second direction, and the third direction shown in FIG2 are only exemplary examples, and the embodiments of the present application are not limited thereto. In some embodiments, the first direction can also be referred to as a row direction in a plane parallel to the substrate, and the third direction can also be referred to as a column direction in a plane parallel to the substrate.

[0055] As shown in Figure 2, the memory cell 100 provided in an embodiment of the present application includes a first transistor 110 and a second transistor 120 located on a substrate and arranged in a first direction parallel to the substrate and connected to each other. The first transistor 110 is a read transistor, and the second transistor 120 is a write transistor. In other words, the memory cell 100 provided in an embodiment of the present application is a 2TOC memory cell. The data reading process of the 2TOC memory cell is non-destructive and does not require a large capacitor, which helps to improve the integration of the memory cell and reduce the processing conditions of the memory cell.

[0056] It should be noted that the first transistor 110 and the second transistor 120 are arranged along the first direction, which may mean that the arrangement direction from the first transistor 110 to the second transistor 120 is the first direction, or may mean that the arrangement direction from the second transistor 120 to the first transistor 110 is the first direction.

[0057] The first transistor 110 includes a first gate 111, a second gate 112, and a first semiconductor layer 113. The first gate 111 extends in a second direction perpendicular to the substrate, and the second gate 112 and the first semiconductor layer 113 both extend in the first direction. The first gate 111 surrounds the first semiconductor layer 113, and the first semiconductor layer 113 surrounds the second gate 112. The second transistor 120 includes a third gate 121 and a second semiconductor layer 122. The third gate 121 extends in the second direction, and the second semiconductor layer 122 is connected to the second gate 112 of the first transistor 110. In some embodiments, the first gate 111 can also be referred to as the external gate of the first transistor 110, and the second gate 112 can also be referred to as the internal gate of the first transistor 110.

[0058] The first transistor 110 is a vertical dual-gate transistor, which is easy to control. The first gate 111 of the first transistor 110 is used to connect to the first word line 400. By applying a voltage to the first gate 111 through the first word line 400, the conduction or shutdown of the first transistor 110 can be controlled. The first gate 111 extends along a second direction perpendicular to the substrate. The cross-sectional area of ​​the first gate 111 at different positions may be the same or different, which is related to the actual preparation process. Among them, the cross-section of the first gate 111 at any position refers to the plane obtained by cutting off the first gate 111 from any position using a plane parallel to the substrate. In some embodiments, the first word line 400 can also be referred to as a read transistor word line or a read word line.

[0059] The second transistor 120 is also a vertical transistor. The third gate 121 of the second transistor 120 is used to connect to the second word line 500. Applying a voltage to the third gate 121 through the second word line 500 can control the conduction or shutdown of the second transistor 120. The third gate 121 extends along a second direction perpendicular to the substrate. The cross-sectional area of ​​the third gate 121 at different locations can be the same or different, which is related to the actual manufacturing process. In some embodiments, the second word line 500 can also be referred to as a write transistor word line or a write word line.

[0060] In an exemplary embodiment, first semiconductor layer 113 is a cylindrical structure with an opening facing the first direction. The cylindrical structure includes an inner surface and an outer surface. The cylindrical structure is a hollow structure. The inner surface of the cylindrical structure is the surface that constitutes the hollow portion of the cylindrical structure, and the outer surface of the cylindrical structure is the surface of the cylindrical structure other than the inner surface. The first gate 111 surrounds the outer surface of the cylindrical structure parallel to the first direction, and the inner surface of the cylindrical structure surrounds the second gate 112.

[0061] For example, the surface of the outer surface of the cylindrical structure that is parallel to the first direction can also be referred to as the outer side surface of the cylindrical structure, and the surface of the outer surface of the cylindrical structure surrounded by the first gate 111 that is parallel to the first direction can also be referred to as the outer side surface of the cylindrical structure surrounded by the first gate 111. For example, the inner surface of the cylindrical structure includes a surface parallel to the first direction (which can be referred to as the inner side surface) and a surface perpendicular to the first direction (which can be referred to as the inner bottom surface), and the inner surface of the cylindrical structure surrounding the second gate 112 can also be referred to as the inner side surface and inner bottom surface of the cylindrical structure surrounding the second gate 112.

[0062] Exemplarily, the second gate 112 is a columnar structure, and the columnar second gate 112 extends from the opening of the first semiconductor layer 113 to the inner bottom surface of the first semiconductor layer 113 .

[0063] Illustratively, the second gate 112 includes, in addition to a portion surrounded by the first semiconductor layer 113, a portion not surrounded by the first semiconductor layer 113. The portion not surrounded by the first semiconductor layer 113 is used to connect to the second semiconductor layer 122 of the second transistor 120. This arrangement facilitates the connection of the second gate 112 to the second semiconductor layer 122 of the second transistor 120 while insulating the first semiconductor layer 113 from the second semiconductor layer 122.

[0064] Exemplarily, the first gate 111 has a ring-shaped longitudinal cross-section, wherein the longitudinal cross-section of the first gate 111 refers to a plane obtained by cutting the first gate 111 along a plane perpendicular to the first direction. Exemplarily, the longitudinal cross-section of the first gate 111 can be a circular ring, a square ring, an elliptical ring, etc.

[0065] Exemplarily, the dimension of the first gate 111 in the first direction is smaller than the dimension of the first semiconductor layer 113 in the first direction. That is, the first gate 111 surrounding the first semiconductor layer 113 means that the first gate 111 surrounds a portion of the first semiconductor layer 113. The region of the first semiconductor layer 113 surrounded by the first gate 111 is a channel region in the first semiconductor layer 113. In addition to the channel region, the first semiconductor layer 113 also includes a first electrode region and a second electrode region connected by the channel region, wherein the first electrode region is farther away from the second transistor 120 than the second electrode region.

[0066] The first gate 111 can control the channel region of the surrounded first semiconductor layer 113 to be turned on or off. When the channel region of the first semiconductor layer 113 is turned on, the first electrode region and the second electrode region of the first semiconductor layer 113 can be connected; when the channel region of the first semiconductor layer 113 is turned off, the first electrode region and the second electrode region of the first semiconductor layer 113 are not connected.

[0067] The channel region in the first semiconductor layer 113 is used to form a channel of the first transistor 110. In an exemplary embodiment, the channel of the first transistor 110 is a horizontal channel. In some embodiments, a horizontal channel can be understood as a channel having a length direction in a plane parallel to the substrate, where the channel length direction refers to the direction of the conductive path between the source and drain of the first transistor 110.

[0068] The horizontal channel described in the embodiment of the present application can be understood as a type of non-vertical channel. Generally or approximately, the channel extends in a plane parallel to the substrate, which can be understood as an embodiment in which the length direction of the channel or the carrier transmission direction is in a plane parallel to the substrate. The channel can be approximately parallel to the substrate, and the error can be within 10 degrees. In actual applications, it depends on the relative position between the effective source and drain. In some embodiments, the horizontal channel can be a planar channel or a ring channel, depending on factors such as the shape and relative position of the semiconductor layer, source, and drain.

[0069] One of the first electrode region and the second electrode region in the first semiconductor layer 113 is used to form the source of the first transistor 110, and the other electrode region is used to form the drain of the first transistor 110. The source and drain of the first transistor 110 can be interchanged in some cases. In practical applications, the source and drain of the first transistor 110 can be identified according to the direction of current.

[0070] The first electrode region is used to connect to the first bit line 200. In other words, the connection between the first semiconductor layer 113 and the first bit line 200 specifically refers to the connection between the first electrode region in the first semiconductor layer 113 and the first bit line 200. In some embodiments, the first bit line 200 can also be called a read transistor bit line or a read bit line.

[0071] The second electrode region is used to connect to a connection line 600, which is perpendicular to the substrate. Optionally, the connection line 600 is a planar structure perpendicular to the substrate. The connection line 600 is used to connect to the first semiconductor layer 113 (e.g., the second electrode region in the first semiconductor layer 113) of the memory cells 100 in each memory cell column stacked at the same position in multiple memory cell layers in the memory. In some embodiments, the connection line 600 can also be referred to as a GND (Ground).

[0072] In some embodiments, the channel region of the first semiconductor layer 113 has a different conductivity than the first and second electrode regions to which it is connected. For example, the channel region of the first semiconductor layer 113 is a metal oxide semiconductor, and the first and second electrode regions of the first semiconductor layer 113 have higher conductivity than the metal oxide semiconductor. In practical applications, this can be distinguished by conductivity testing. The main material of the channel region, the first electrode region, and the second electrode region of the first semiconductor layer 113 can be the same, and the region with higher conductivity can be achieved through doping. In some embodiments, the channel region of the first semiconductor layer 113 has the same conductivity as the first and second electrode regions to which it is connected. For example, the channel region, the first and second electrode regions of the first semiconductor layer 113 are all polycrystalline silicon or metal oxide semiconductors, and their conductivity can be close to that of a conductor or semiconductor. During preparation, the channel region, the first and second electrode regions of the first semiconductor layer 113 can be formed in a single process under the same process conditions. Therefore, in this embodiment, the boundaries between the channel region, the first and second electrode regions of the first semiconductor layer 113 are not particularly distinct.

[0073] In an exemplary embodiment, the first gate 111 and the first semiconductor layer 113 are insulated by a first insulating layer, and the first semiconductor layer 113 and the second gate 112 are insulated by a second insulating layer. That is, the first insulating layer is located between the first gate 111 and the first semiconductor layer 113, and the second insulating layer is located between the first semiconductor layer 113 and the second gate 112. The first gate 111 surrounds the first insulating layer, the first insulating layer surrounds the first semiconductor layer 113, the first semiconductor layer 113 surrounds the second insulating layer, and the second insulating layer surrounds the second gate 112.

[0074] Exemplarily, the first gate 111 and the first insulating layer are both circular structures with a longitudinal cross-section, and the first semiconductor layer 113 and the second insulating layer are both cylindrical structures with an opening facing the first direction. The circular structure with a longitudinal cross-section has an inner ring surface and an outer ring surface. The circular structure with a longitudinal cross-section is a hollow structure. The inner ring surface of the circular structure with a longitudinal cross-section refers to the surface of the hollow portion of the circular structure with a longitudinal cross-section, and the outer ring surface of the circular structure with a longitudinal cross-section refers to the surface of the circular structure with a longitudinal cross-section other than the inner ring surface. The cylindrical structure has an inner surface and an outer surface. The cylindrical structure is a hollow structure. The inner surface of the cylindrical structure refers to the surface of the hollow portion of the cylindrical structure, and the outer surface of the cylindrical structure refers to the surface of the cylindrical structure other than the inner surface. The inner surface of the cylindrical structure includes a surface parallel to the first direction (which can be called an inner side surface) and a surface perpendicular to the first direction (which can be called an inner bottom surface). The outer surface of the cylindrical structure includes a surface parallel to the first direction (which can be called an outer side surface) and a surface perpendicular to the first direction (which can be called an outer bottom surface).

[0075] The inner annular surface of the first gate 111 is aligned with the outer annular surface of the first insulating layer, the inner annular surface of the first insulating layer is aligned with the outer side surface of the first semiconductor layer 113, the inner side surface and inner bottom surface of the first semiconductor layer 113 are aligned with the outer side surface and outer bottom surface of the second insulating layer, respectively. The second gate 112 extends from the opening of the second insulating layer to the inner bottom surface of the second insulating layer, and the surface of the portion of the second gate 112 located within the cylindrical interior of the second insulating layer is aligned with the inner side surface and inner bottom surface of the second insulating layer. It should be noted that the alignment between surfaces in the embodiments of the present application refers to alignment without gaps.

[0076] Exemplarily, the dimension of the first insulating layer in the first direction is larger than the dimension of the first gate electrode 111 in the first direction, and smaller than the dimension of the first semiconductor layer 113 in the first direction. In this case, the first gate electrode 111 and the first semiconductor layer 113 can be insulated by the first insulating layer, while the first electrode region and the second electrode region of the first semiconductor layer 113 are exposed. The exposed first electrode region is used to connect to the first bit line 200, and the exposed second electrode region is used to connect to the connecting line 600.

[0077] The second insulating layer has a partial area not surrounded by the first semiconductor layer 113, and the second gate 112 has a partial area not surrounded by the second insulating layer. In this case, after the second gate 112 is insulated from the first semiconductor layer 113 by the second insulating layer, a partial area of ​​the second gate 112 can be exposed. This exposed partial area is used to connect to the second semiconductor layer 122 of the second transistor 120.

[0078] In an exemplary embodiment, the first semiconductor layer 113 is used to connect to the first bit line 200. For example, the first electrode region in the first semiconductor layer 113 is used to connect to the first bit line 200. The size of the first semiconductor layer 113 in the second direction is the same as the size of the first bit line 200 in the second direction. Exemplarily, the first semiconductor layer 113 and the first bit line 200 connected to the first semiconductor layer 113 are both located between two horizontal insulating layers, and the first semiconductor layer 113 and the first bit line 200 connected to the first semiconductor layer 113 extend from the lower surface of one of the horizontal insulating layers to the upper surface of the other horizontal insulating layer. The horizontal insulating layer refers to an insulating layer parallel to the substrate, the lower surface of the horizontal insulating layer refers to the surface of the horizontal insulating layer parallel to the substrate that is closer to the substrate, and the upper surface of the horizontal insulating layer refers to the surface of the horizontal insulating layer parallel to the substrate that is farther from the substrate.

[0079] That is, the first semiconductor layer 113 and the first bit line 200 connected to the first semiconductor layer 113 are located between the same two horizontal insulating layers, with their upper and lower surfaces parallel to the substrate respectively contacting the two horizontal insulating layers. This structure ensures that the first semiconductor layer 113 and the first bit line 200 connected to the first semiconductor layer 113 have the same thickness in a direction perpendicular to the substrate, ensuring a tight connection between the first semiconductor layer 113 and the first bit line 200 connected to the first semiconductor layer 113, and simplifies the fabrication process of the first semiconductor layer 113 and the first bit line 200.

[0080] Of course, in some embodiments, the size of the first semiconductor layer 113 in the second direction may also be different from the size of the first bit line 200 in the second direction, which is related to the actual manufacturing process.

[0081] The embodiment of the present application does not limit the relationship between the third gate 121 and the second semiconductor layer 122 , as long as the third gate 121 can control the channel region in the second semiconductor layer 122 .

[0082] In an exemplary embodiment, the relationship between the third gate 121 and the second semiconductor layer 122 can be: the third gate 121 surrounds the second semiconductor layer 122. In this structure, the portion of the second semiconductor layer 122 surrounded by the third gate 121 constitutes the channel region of the second semiconductor layer 122. Exemplarily, both the third gate 121 and the second semiconductor layer 122 have a surrounding structure with a circular longitudinal cross-section, and the inner surface of the third gate 121 surrounds the outer surface of the second semiconductor layer 122.

[0083] For example, when the third gate 121 surrounds the second semiconductor layer 122, the second semiconductor layer 122 is connected to the second gate 112 through the first conductive layer, and the second semiconductor layer 122 is also connected to the second bit line 300 through the second conductive layer; the first conductive layer and the second conductive layer are insulated by a third insulating layer (that is, the first conductive layer and the second conductive layer include a third insulating layer), and the second semiconductor layer 122 surrounds the third insulating layer. For example, the inner annular surface of the second semiconductor layer 122 is aligned with the surface of the third insulating layer parallel to the substrate. In some embodiments, the third insulating layer can also be referred to as a support structure, and the second bit line 300 can also be referred to as a write transistor bit line or a write bit line. Providing the third insulating layer as a support structure for preparing the second semiconductor layer 122 helps simplify the preparation process of the second semiconductor layer 122. In addition, the third insulating layer can electrically isolate the second gate 112 connected to the second semiconductor layer 122 from the second bit line 300 connected to the second semiconductor layer 122 to avoid short circuits.

[0084] Illustratively, the second semiconductor layer 122 is in direct contact with the first conductive layer, so that the second semiconductor layer 122 can be connected to the second gate 112 through the first conductive layer. Illustratively, the second semiconductor layer 122 surrounds the first conductive layer, for example, the inner annular surface of the second semiconductor layer 122 is aligned with the surface of the first conductive layer parallel to the substrate. Illustratively, the inner annular surface of the second semiconductor layer 122 can be aligned with the entire surface of the first conductive layer parallel to the substrate, or can be aligned with a portion of the surface of the first conductive layer parallel to the substrate that is close to the third insulating layer.

[0085] Illustratively, the second semiconductor layer 122 is in direct contact with the second conductive layer, so that the second semiconductor layer 122 can be connected to the second bit line 300 through the second conductive layer. Illustratively, the second semiconductor layer 122 surrounds the second conductive layer. For example, the inner annular surface of the second semiconductor layer 122 is aligned with the surface of the second conductive layer parallel to the substrate. Illustratively, the inner annular surface of the second semiconductor layer 122 can be aligned with the entire surface of the second conductive layer parallel to the substrate, or can be aligned with a portion of the surface of the second conductive layer parallel to the substrate that is close to the third insulating layer.

[0086] In an exemplary embodiment, the first conductive layer, the third insulating layer, the second conductive layer, and the second bit line 300 have the same dimensions in the second direction. For example, the first conductive layer, the third insulating layer, the second conductive layer, and the second bit line 300 are all located between two horizontal insulating layers, and the first conductive layer, the third insulating layer, the second conductive layer, and the second bit line 300 all extend from the bottom surface of one horizontal insulating layer to the top surface of the other horizontal insulating layer. In other words, the first conductive layer, the third insulating layer, the second conductive layer, and the second bit line 300 are located between the same two horizontal insulating layers, and their upper and lower surfaces, parallel to the substrate, contact the two horizontal insulating layers, respectively. This structure enables the second bit line 300 to be fabricated simultaneously with the fabrication of the first conductive layer, the third insulating layer, and the second conductive layer, thereby simplifying the fabrication process for the second bit line 300.

[0087] Exemplarily, when the first conductive layer and the first semiconductor layer 113 have the same size in the second direction, the first semiconductor layer 113 and the first bit line 200 have the same size in the second direction, and the first conductive layer, the third insulating layer, the second conductive layer, the second bit line 300 have the same size in the second direction, the first conductive layer, the third insulating layer, the second conductive layer, the second bit line 300, the first semiconductor layer 113, and the first bit line 200 have the same size in the second direction. For example, the first conductive layer, the third insulating layer, the second conductive layer, the second bit line 300, the first semiconductor layer 113, and the first bit line 200 are located between the same two horizontal insulating layers, and their respective upper and lower surfaces parallel to the substrate are in contact with the two horizontal insulating layers, respectively.

[0088] In an exemplary embodiment, the relationship between the third gate 121 and the second semiconductor layer 122 can also be: the second semiconductor layer 122 surrounds the third gate 121. In this structure, the portion of the second semiconductor layer 122 surrounding the third gate 121 is the channel region in the second semiconductor layer 122. Exemplarily, the third gate 121 is a columnar structure extending along the second direction, and the second semiconductor layer 122 is a surrounding structure with a circular cross-section, wherein the cross-section of the second semiconductor layer 122 is a plane obtained by cutting the second semiconductor layer 122 using a plane perpendicular to the second direction. The surrounding structure with a circular cross-section has an inner annular surface and an outer annular surface, and the inner annular surface of the second semiconductor layer 122 surrounds the side surface of the third gate 121. The side surface of the third gate 121 refers to the plane of the third gate 121 perpendicular to the substrate.

[0089] Illustratively, in addition to the channel region, the second semiconductor layer 122 also includes a third electrode region and a fourth electrode region connected via the channel region, wherein the fourth electrode region is farther away from the first transistor 110 than the third electrode region. One of the third and fourth electrode regions is used to form the source of the second transistor 120, and the other electrode region is used to form the drain of the second transistor 120. In some cases, the source and drain of the second transistor 120 can be interchanged. In practical applications, the source and drain of the second transistor 120 can be identified based on the direction of current.

[0090] The third electrode region is used to connect to the second gate 112. That is, the second semiconductor layer 122 and the second gate 112 refer to the third electrode region in the second semiconductor layer 122 being connected to the second gate 112. The fourth electrode region is used to connect to the second bit line 300. That is, the second semiconductor layer 122 and the second bit line 300 are connected to the fourth electrode region in the second semiconductor layer 122.

[0091] The channel region in the second semiconductor layer 122 is used to form a channel of the second transistor 120. In an exemplary embodiment, the channel of the second transistor 120 is a horizontal channel. In some embodiments, a horizontal channel can be understood as a channel having a length direction in a plane parallel to the substrate, where the channel length direction refers to the direction of the conductive path between the source and drain of the second transistor 120.

[0092] In some embodiments, the channel region of the second semiconductor layer 122 has a different conductivity than the third and fourth electrode regions to which it is connected. For example, the channel region of the second semiconductor layer 122 is a metal oxide semiconductor, and the third and fourth electrode regions of the second semiconductor layer 122 have higher conductivity than the metal oxide semiconductor. In practical applications, this can be distinguished by conductivity testing. The main material of the channel region, third electrode region, and fourth electrode region of the second semiconductor layer 122 can be the same, and the region with higher conductivity can be achieved through doping. In some embodiments, the channel region of the second semiconductor layer 122 has the same conductivity as the third and fourth electrode regions to which it is connected. For example, the channel region, third electrode region, and fourth electrode region of the second semiconductor layer 122 are all polycrystalline silicon or metal oxide semiconductors, and their conductivity can be close to that of a conductor or semiconductor. During fabrication, the channel region, third electrode, and fourth electrode regions of the second semiconductor layer 122 can be formed in a single process under the same process conditions. Therefore, in this embodiment, the boundaries between the channel region, third electrode region, and fourth electrode region of the second semiconductor layer 122 are not particularly distinct.

[0093] In an exemplary embodiment, the third gate 121 and the second semiconductor layer 122 are insulated by a fourth insulating layer (i.e., the fourth insulating layer is included between the third gate 121 and the second semiconductor layer 122). When the third gate 121 surrounds the second semiconductor layer 122, the third gate 121 surrounds the fourth insulating layer, and the fourth insulating layer surrounds the second semiconductor layer 122. Exemplarily, the fourth insulating layer has a surrounding structure with a ring-shaped longitudinal cross-section, and the inner annular surface of the third gate 121 is aligned with the outer annular surface of the fourth insulating layer, and the inner annular surface of the fourth insulating layer is aligned with the outer annular surface of the second semiconductor layer 122.

[0094] When the second semiconductor layer 122 surrounds the third gate 121, the second semiconductor layer 122 surrounds the fourth insulating layer, and the fourth insulating layer surrounds the third gate 121. Exemplarily, the fourth insulating layer is a surrounding structure with a ring-shaped cross-section. Optionally, the inner annular surface of the second semiconductor layer 122 is in contact with the outer annular surface of the fourth insulating layer, and the inner annular surface of the fourth insulating layer is in contact with the side surface of the third gate 121.

[0095] Embodiments of the present application provide a novel 2TOC memory cell structure. Two transistors in this 2TOC memory cell are arranged parallel to the substrate. This memory cell can be arranged not only in an array in a plane parallel to the substrate but also stacked perpendicular to the substrate, thereby forming a three-dimensional stacked memory. This facilitates improving the memory integration density, and thus the memory storage density. Furthermore, in this 2TOC memory cell, the first gate of the first transistor surrounds the first semiconductor layer, which in turn surrounds the second gate of the first transistor. This compact structure of the first transistor reduces the size of the memory cell, thereby improving the memory integration density and, therefore, the memory storage density.

[0096] The embodiment of the present application also provides a memory including a storage unit as shown in Figure 2. Figures 3 and 4 show schematic structural diagrams of the memory provided by the embodiment of the present application. The memory shown in Figures 3 and 4 is a three-dimensional memory with high integration density and storage density. Figure 3 shows a stereoscopic view of the memory provided by the embodiment of the present application, (1) in Figure 4 shows a top view of the memory provided by the embodiment of the present application, and (2) in Figure 4 shows a front view of the memory provided by the embodiment of the present application. In Figures 3 and 4, the first direction and the third direction are perpendicular to each other and are both parallel to the substrate, and the second direction is perpendicular to the substrate. It should be noted that the first direction, the second direction and the third direction shown in Figures 3 and 4 are only illustrative examples, and the embodiment of the present application is not limited to this.

[0097] 3 and 4 , the memory includes a plurality of memory cell layers stacked vertically on a substrate, and a plurality of first bit lines 200, a plurality of second bit lines 300, a plurality of first word lines 400, and a plurality of second word lines 500 connected to the plurality of memory cell layers. It should be noted that the structures shown in FIG3 and FIG4 are only partial structures of the memory. For example, FIG3 and FIG4 only show three memory cell layers of the memory, and the embodiments of the present application are not limited thereto.

[0098] The memory cell layer includes a plurality of memory cells 100 arranged in an array. That is, the memory cell layer is composed of a plurality of memory cell columns arranged at intervals in a first direction, or is composed of memory cell rows arranged at intervals in a third direction. It should be noted that Figures 3 and 4 illustrate only an example in which the memory cell layer includes one memory cell column, and the memory cell column includes three memory cells 100. The embodiments of the present application are not limited to this example.

[0099] The memory cell 100 includes a first transistor 110 and a second transistor 120 arranged along a first direction parallel to the substrate; the first gate 111 of the first transistor 110 extends along a second direction perpendicular to the substrate, the second gate 112 and the first semiconductor layer 113 of the first transistor 110 both extend along the first direction, the first gate 111 surrounds the first semiconductor layer 113, and the first semiconductor layer 113 surrounds the second gate 112; the third gate 121 of the second transistor 120 extends along the second direction, and the second semiconductor layer 122 of the second transistor 120 is connected to the second gate 112.

[0100] In an exemplary embodiment, the first semiconductor layer 113 of the storage unit 100 is a tubular structure with an opening facing the first direction, the tubular structure includes an inner surface and an outer surface, the inner surface of the tubular structure is the surface of the hollow part constituting the tubular structure, and the outer surface of the tubular structure is the surface of the tubular structure other than the inner surface; the first gate 111 of the storage unit 100 surrounds the surface of the outer surface of the tubular structure parallel to the first direction, and the inner surface of the tubular structure surrounds the second gate 112 of the storage unit 100.

[0101] In an exemplary embodiment, a first insulating layer is included between the first gate 111 of the memory cell 100 and the first semiconductor layer 113 of the memory cell 100, and a second insulating layer is included between the first semiconductor layer 113 of the memory cell 100 and the second gate 112 of the memory cell 100; the first gate 111 of the memory cell 100 surrounds the first insulating layer, the first insulating layer surrounds the first semiconductor layer 113 of the memory cell 100, the first semiconductor layer 113 of the memory cell 100 surrounds the second insulating layer, and the second insulating layer surrounds the second gate 112 of the memory cell 100.

[0102] In an exemplary embodiment, the third gate 121 of the memory cell 100 surrounds the second semiconductor layer 122 of the memory cell 100. In this case, the second semiconductor layer 122 of the memory cell 100 is connected to the second gate 112 of the memory cell 100 via the first conductive layer. The second semiconductor layer 122 of the memory cell 100 is also connected to the second bit line 300 via the second conductive layer. A third insulating layer is included between the first conductive layer and the second conductive layer, and the second semiconductor layer 122 of the memory cell 100 surrounds the third insulating layer.

[0103] In an exemplary embodiment, the second semiconductor layer 122 of the memory cell 100 surrounds the third gate 121 of the memory cell 100 .

[0104] The relevant introduction of the storage unit 100 is detailed in the embodiment shown in FIG2 , and will not be repeated here.

[0105] According to Figures 3 and 4, the first gates 111 of the multiple memory cells 100 in the memory cell column are isolated from each other in the third direction, such as by isolation through an insulating layer; the first semiconductor layers 113 of the multiple memory cells 100 in the memory cell column are isolated from each other in the third direction, such as by isolation through an insulating layer; the second gates 112 of the multiple memory cells 100 in the memory cell column are isolated from each other in the third direction, such as by isolation through an insulating layer; the third gates 121 of the multiple memory cells 100 in the memory cell column are isolated from each other in the third direction, such as by isolation through an insulating layer; the second semiconductor layers 122 of the multiple memory cells 100 in the memory cell column are isolated from each other in the third direction, such as by isolation through an insulating layer.

[0106] For example, the memory cells 100 stacked at the same position in multiple memory cell layers can constitute a memory cell string. The memory cells 100 stacked at the same position in multiple memory cell layers refer to the memory cells 100 in the multiple memory cell layers whose projections on the substrate overlap or approximately overlap. According to Figures 3 and 4, the second gates 112 of the multiple memory cells 100 in the memory cell string are isolated from each other in the second direction, such as by an insulating layer; the first semiconductor layers 113 of the multiple memory cells 100 in the memory cell string are isolated from each other in the second direction, such as by an insulating layer; and the second semiconductor layers 122 of the multiple memory cells 100 in the memory cell string are isolated from each other in the second direction, such as by an insulating layer.

[0107] Both the memory cell column and the memory cell string include a plurality of memory cells 100. The number of memory cells 100 included in the memory cell column and the number of memory cells 100 included in the memory cell string can be determined according to actual preparation requirements. For example, different memory cell columns include the same number of memory cells 100, and different memory cell strings include the same number of memory cells 100, so that the memory can be integrally formed through a relatively simplified process. It should be noted that the structure shown in Figures 3 and 4 only takes the example of a memory cell column including three memory cells 100 and a memory cell string including three memory cells 100, but the embodiments of the present application are not limited to this, that is, the memory cell column can also include two memory cells 100 or include more than three (such as 4, 8, 16) memory cells 100, and the memory cell string can also include two memory cells 100 or include more than three (such as 4, 5, 8, etc.) memory cells 100.

[0108] In an exemplary embodiment, a plurality of first bit lines 200 extend along a third direction perpendicular to the first and second directions; the first bit lines 200 are connected to the first semiconductor layer 113 of each memory cell 100 in a memory cell column in the memory cell layer.

[0109] For example, different first bit lines 200 are connected to the first semiconductor layers 113 of the memory cells 100 in different memory cell columns. That is, different memory cell columns do not share the same first bit line 200, so that the memory cells 100 in different memory cell columns can be conveniently controlled through different first bit lines 200. In some embodiments, without affecting data reading and writing, two memory cell columns adjacent in the first direction can share the same first bit line 200.

[0110] In the embodiment of the present application, the first bit line 200 is connected to the first semiconductor layer 113 of each memory cell 100 in a memory cell column, thereby simultaneously controlling the first semiconductor layer 113 of each memory cell 100 in a memory cell column through the first bit line 200. The first semiconductor layer 113 includes a first electrode region, a channel region, and a second electrode region. The connection of the first bit line 200 to the first semiconductor layer 113 of each memory cell 100 in a memory cell column means that the first bit line 200 is connected to the first electrode region of the first semiconductor layer 113 of each memory cell 100 in a memory cell column. That is, the first bit line 200 can simultaneously apply a voltage to the first electrode region of the first semiconductor layer 113 of each memory cell 100 in a memory cell column.

[0111] For example, the first bit line 200 is connected to the first semiconductor layer 113 of each memory cell 100 in a memory cell column, which may mean that the first bit line 200 is directly in contact with the first semiconductor layer 113 of each memory cell 100 in a memory cell column; it may also mean that the first bit line 200 is connected to the first semiconductor layer 113 of each memory cell 100 in a memory cell column through multiple third conductive layers, that is, the first bit line 200 is directly in contact with multiple third conductive layers, and each third conductive layer is directly in contact with the first semiconductor layer 113 of a memory cell 100 in a memory cell column.

[0112] For example, the areas of the longitudinal cross-sections of the first bit line 200 at different locations may be the same or different, depending on the actual manufacturing process. The longitudinal cross-section of the first bit line 200 at any location refers to a plane obtained by cutting the first bit line 200 at that location using a plane perpendicular to the third direction.

[0113] For example, the longitudinal cross-sectional area of ​​the first bit line 200 at the location where it connects to the first semiconductor layer 113 of the memory cell 100 is larger than the longitudinal cross-sectional area at other locations. In this case, the first bit line 200 is a columnar structure extending along the third direction and having a protrusion perpendicular to a side close to the first semiconductor layer 113. The protrusion of the columnar structure is the location where the first bit line 200 is used to connect to the first semiconductor layer 113 of each memory cell 100 in a memory cell column.

[0114] In an exemplary embodiment, the dimension of the first bit line 200 in the second direction is the same as the semiconductor dimension, which refers to the dimension in the second direction of the first semiconductor layer 113 of each memory cell 100 connected to the first bit line 200. Exemplarily, the first bit line 200 and the first semiconductor layer 113 of each memory cell 100 connected to the first bit line 200 are both located between two horizontal insulating layers, and the first bit line 200 and the first semiconductor layer 113 of each memory cell 100 connected to the first bit line 200 extend from the bottom surface of one horizontal insulating layer to the top surface of the other horizontal insulating layer. In other words, the first bit line 200 and the first semiconductor layer 113 of each memory cell 100 connected to the first bit line 200 are located between the same two horizontal insulating layers, and their respective upper and lower surfaces parallel to the substrate are in contact with the two horizontal insulating layers, respectively. This structure can ensure that the first bit line 200 and the first semiconductor layer 113 of each connected memory cell 100 have the same thickness in the direction perpendicular to the substrate, ensure the tight connection between the first bit line 200 and the first semiconductor layer 113, and simplify the preparation process of the first bit line 200 and the first semiconductor layer 113.

[0115] In an exemplary embodiment, a plurality of second bit lines 300 extend along the third direction, and the second bit lines 300 are connected to the second semiconductor layers 122 of the respective memory cells 100 in one memory cell column.

[0116] For example, different second bit lines 300 are connected to the second semiconductor layer 122 of the memory cells 100 in different memory cell columns. In other words, different memory cell columns do not share the same second bit line 300, so that the memory cells 100 in different memory cell columns can be conveniently controlled through different second bit lines 300. In some embodiments, without affecting data reading and writing, two memory cell columns adjacent in the first direction can share the same second bit line 300.

[0117] In the embodiment of the present application, the second bit line 300 is connected to the second semiconductor layer 122 of each memory cell 100 in a memory cell column, thereby simultaneously controlling the second semiconductor layer 122 of each memory cell 100 in a memory cell column through the second bit line 300. The second semiconductor layer 122 includes a third electrode region, a channel region, and a fourth electrode region. The connection of the second bit line 300 to the second semiconductor layer 122 of each memory cell 100 in a memory cell column means that the second bit line 300 is connected to the fourth electrode region of the second semiconductor layer 122 of each memory cell 100 in a memory cell column. That is, the second bit line 300 can simultaneously apply a voltage to the fourth electrode region of the second semiconductor layer 122 of each memory cell 100 in a memory cell column.

[0118] For example, the second bit line 300 is connected to the second semiconductor layer 122 of each memory cell 100 in a memory cell column, which may mean that the second bit line 300 is directly in contact with the second semiconductor layer 122 of each memory cell 100 in a memory cell column; it may also mean that the second bit line 300 is connected to the second semiconductor layer 122 of each memory cell 100 in a memory cell column through multiple fourth conductive layers, that is, the second bit line 300 is directly in contact with multiple fourth conductive layers, and each fourth conductive layer is directly in contact with the second semiconductor layer 122 of a memory cell 100 in a memory cell column.

[0119] For example, in the case where the second semiconductor layer 122 of the memory cell 100 surrounds the third gate 121 of the memory cell 100 and the second semiconductor layer 122 is connected to the second bit line 300 through the second conductive layer, the second conductive layer can be the same layer as the fourth conductive layer, or it can be a different layer from the fourth conductive layer but interconnected with the fourth conductive layer. This is not limited in the embodiments of the present application.

[0120] For example, the areas of the longitudinal cross-sections of the second bit line 300 at different locations may be the same or different, depending on the actual fabrication process. The longitudinal cross-section of the second bit line 300 at any location refers to a plane obtained by cutting the second bit line 300 at that location using a plane perpendicular to the third direction.

[0121] For example, the longitudinal cross-sectional area of ​​the second bit line 300 at the location where it connects to the second semiconductor layer 122 of the memory cell 100 is larger than the longitudinal cross-sectional area at other locations. In this case, the second bit line 300 is a columnar structure extending along the third direction and having a protrusion perpendicular to a side close to the second semiconductor layer 122. The protrusion of the columnar structure is the location where the second bit line 300 is used to connect to the second semiconductor layer 122 of each memory cell 100 in a memory cell column.

[0122] For example, in the case where the second semiconductor layer 122 of the memory cell 100 surrounds the third gate 121 of the memory cell 100, the second semiconductor layer 122 is connected to the second gate 112 and the second bit line 300 of the memory cell 100 through the first conductive layer and the second conductive layer respectively, and the first conductive layer and the second conductive layer are insulated by the third insulating layer, the second bit line 300 and the first conductive layer, the third insulating layer and the second conductive layer corresponding to the second semiconductor layer 122 connected to the second bit line 300 have the same size in the second direction.

[0123] Exemplarily, the second bit line 300 and the first conductive layer, third insulating layer, and second conductive layer corresponding to the second semiconductor layer 122 to which the second bit line 300 is connected are all located between two horizontal insulating layers. The second bit line 300 and the first conductive layer, third insulating layer, and second conductive layer corresponding to the second semiconductor layer 122 to which the second bit line 300 is connected extend from the bottom surface of one horizontal insulating layer to the top surface of the other horizontal insulating layer. In other words, the second bit line 300 and the first conductive layer, third insulating layer, and second conductive layer corresponding to the second semiconductor layer 122 to which the second bit line 300 is connected are located between the same two horizontal insulating layers, and their respective upper and lower surfaces parallel to the substrate are in contact with the two horizontal insulating layers. This structure enables the second bit line 300 to be fabricated simultaneously with the first conductive layer, third insulating layer, and second conductive layer corresponding to the second semiconductor layer 122, thereby simplifying the fabrication process for the second bit line 300.

[0124] In an exemplary embodiment, multiple first word lines 400 extend along the second direction; the first word lines 400 are connected to the first gates 111 of the memory cells 100 stacked at the same location in the multiple memory cell layers. The memory cells 100 stacked at the same location in the multiple memory cell layers refer to the memory cells 100 in the multiple memory cell layers whose projections on the substrate overlap or approximately overlap. For example, the memory cells 100 stacked at the same location in the multiple memory cell layers may constitute a memory cell string, and the first word lines 400 are connected to the first gates 111 of the memory cells 100 in a memory cell string.

[0125] For example, different first word lines 400 are connected to the first gates 111 of the memory cells 100 in different memory cell strings, that is, different memory cell strings do not share the first word line 400, so that the memory cells 100 in different memory cell strings can be conveniently controlled through different first word lines 400.

[0126] In an embodiment of the present application, the first word line 400 is connected to the first gate 111 of each stacked memory cell 100 (that is, each memory cell 100 in a memory cell string), so that the first gate 111 of each stacked memory cell 100 is controlled simultaneously through one first word line 400, that is, one first word line 400 can apply voltage to the first gate 111 of each stacked memory cell 100 at the same time.

[0127] In an exemplary embodiment, the first gate 111 of each memory cell 100 connected to the first word line 400 is a part of the first word line 400. This method can save materials for preparing the first word line 400, reduce the preparation cost of the first word line 400, and simplify the preparation process of the first word line 400.

[0128] In an exemplary embodiment, the first word line 400 includes the first gates 111 of each memory cell 100 to which it is connected and a first connection line for connecting the first gates 111 of each memory cell 100. For example, since the first gates 111 of the memory cells 100 are perpendicular to the substrate, the first connection line can also be perpendicular to the substrate to save material for preparing the first connection line. For example, the first connection line includes a plurality of spaced-apart connection sub-lines, each of which is used to connect the first gates 111 of two adjacent memory cells 100 in the second direction.

[0129] Exemplarily, the first gates 111 of the memory cells 100 connected to the first word line 400 overlap in a first projection plane on the substrate. The center of the first projection plane of the first gate 111 of the memory cells 100 overlaps with the center of the second projection plane of the first connecting line on the substrate. Exemplarily, the first connecting line includes multiple spaced connecting sub-lines, and the projection planes of the connecting sub-lines overlap on the substrate. The overlapping projection planes of the connecting sub-lines on the substrate serve as the second projection plane of the first connecting line on the substrate. The overlap of the center of the first projection plane with the center of the second projection plane indicates that the center of the first gate 111 of the memory cells 100 and the center of the first connecting line are located on the same straight line perpendicular to the substrate.

[0130] In some embodiments, the area of ​​the first projection plane can be equal to the area of ​​the second projection plane. That is, the cross-sectional area of ​​the first gate 111 of each memory cell 100 connected to the first word line 400 is equal to the cross-sectional area of ​​the first connecting line. In this case, the first word line 400 is a columnar structure perpendicular to the substrate and having the same cross-sectional area at all locations, such as a rectangular parallelepiped columnar structure. The cross-sectional area of ​​the first gate 111 refers to the plane obtained by cutting the first gate 111 along a plane parallel to the substrate; the cross-sectional area of ​​the first connecting line refers to the plane obtained by cutting the first connecting line along a plane parallel to the substrate.

[0131] In some embodiments, the area of ​​the first projection surface may also be larger than the area of ​​the second projection surface. That is, the cross-sectional area of ​​the first gate 111 of each memory cell 100 connected to the first word line 400 is larger than the cross-sectional area of ​​the first connecting line. In this case, the first word line 400 is a columnar structure perpendicular to the substrate and having protrusions on both sides perpendicular to the first direction. The protrusions of the columnar structure are located at the locations of the first gate 111 of each memory cell 100 connected to the first word line 400. Of course, in some embodiments, the area of ​​the first projection surface may also be smaller than the area of ​​the second projection surface, and this embodiment of the present application is not limited to this.

[0132] In an exemplary embodiment, a plurality of second word lines 500 extend along the second direction; the second word lines 500 are connected to the third gates 121 of the memory cells 100 stacked at the same position in the plurality of memory cell layers. In other words, the second word lines 500 are connected to the third gates 121 of the memory cells 100 in one memory cell string.

[0133] Exemplarily, different second word lines 500 are connected to the third gates 121 of the memory cells 100 in different memory cell strings, that is, different memory cell strings do not share the second word line 500, which facilitates the convenient control of the memory cells 100 in different memory cell strings through different second word lines 500.

[0134] In an embodiment of the present application, the second word line 500 is connected to the third gate 121 of each stacked memory cell 100 (that is, each memory cell 100 in a memory cell string), so that the third gate 121 of each stacked memory cell 100 is controlled simultaneously through a second word line 500, that is, a second word line 500 can apply voltage to the third gate 121 of each stacked memory cell 100 at the same time.

[0135] In an exemplary embodiment, the third gate 121 of each memory cell 100 connected to the second word line 500 is a part of the second word line 500. This method can save the preparation material of the second word line 500, reduce the preparation cost of the second word line 500, and simplify the preparation process of the second word line 500.

[0136] In an exemplary embodiment, the second word line 500 includes the third gates 121 of each memory cell 100 to which it is connected and a second connection line for connecting the third gates 121 of each memory cell 100. For example, since the third gates 121 of the memory cells 100 are perpendicular to the substrate, the second connection line can also be perpendicular to the substrate to save material for preparing the second connection line. For example, the second connection line includes a plurality of spaced-apart connection sub-lines, each of which is used to connect the third gates 121 of two memory cells 100 adjacent in the second direction.

[0137] Exemplarily, the third gates 121 of each memory cell 100 connected to the second word line 500 have their third projection planes on the substrate overlapped. The center of the third projection plane of each memory cell 100 on the substrate overlaps with the center of the fourth projection plane of the second connecting line on the substrate. Exemplarily, the second connecting line has multiple spaced connecting sub-lines, and the projection planes of each connecting sub-line on the substrate overlap. The overlapping projection planes of each connecting sub-line on the substrate serve as the fourth projection plane of the second connecting line on the substrate. The overlap of the center of the third projection plane with the center of the fourth projection plane indicates that the center of the third gate 121 of each memory cell 100 and the center of the second connecting line are located on the same straight line perpendicular to the substrate.

[0138] In some embodiments, the area of ​​the third projection plane can be equal to the area of ​​the fourth projection plane. That is, the cross-sectional area of ​​the third gate 121 of each memory cell 100 connected to the second word line 500 is equal to the cross-sectional area of ​​the second connecting line. In this case, the second word line 500 is a columnar structure perpendicular to the substrate with a uniform cross-sectional area at all locations, such as a rectangular columnar structure. The cross-sectional area of ​​the third gate 121 refers to the plane obtained by cutting the third gate 121 along a plane parallel to the substrate; the cross-sectional area of ​​the second connecting line refers to the plane obtained by cutting the second connecting line along a plane parallel to the substrate.

[0139] In some embodiments, the area of ​​the third projection plane may also be greater than the area of ​​the fourth projection plane. That is, the cross-sectional area of ​​the third gate 121 of each memory cell 100 connected to the second word line 500 is greater than the cross-sectional area of ​​the second connecting line. In this case, the second word line 500 is a columnar structure perpendicular to the substrate and having protrusions on both sides perpendicular to the first direction. The protrusions of the columnar structure are located at the locations of the third gate 121 of each memory cell 100 connected to the second word line 500. Of course, in some embodiments, the area of ​​the third projection plane may also be smaller than the area of ​​the fourth projection plane, and this embodiment of the present application is not limited to this.

[0140] For example, the first bit line 200 and the first word line 400 can be used during data reading, and thus the first bit line 200 can also be referred to as a read transistor bit line or read bit line (RBL for short), and the first word line 400 can also be referred to as a read transistor word line or read word line (RWL for short). The second bit line 300 and the second word line 500 can be used during data writing, and thus the second bit line 300 can also be referred to as a write transistor bit line or write bit line (WBL for short), and the second word line 500 can also be referred to as a write transistor word line or write word line (WWL for short).

[0141] In an exemplary embodiment, the memory further includes a plurality of connection lines 600 perpendicular to the substrate, the connection lines 600 being connected to the first semiconductor layer 113 of the memory cells 100 in respective memory cell columns stacked at the same location in the plurality of memory cell layers. The respective memory cell columns stacked at the same location in the plurality of memory cell layers refer to memory cell columns in the plurality of memory cell layers whose projections on the substrate overlap or approximately overlap, and the number of memory cells 100 in different memory cell columns is the same.

[0142] Exemplarily, connecting the connection line 600 to the first semiconductor layer 113 of the memory cells 100 in each memory cell column stacked at the same position in multiple memory cell layers means connecting the connection line 600 to the second electrode region in the first semiconductor layer 113 of the memory cells 100 in each memory cell column stacked at the same position in multiple memory cell layers. The connection line 600 can simultaneously apply a voltage to the second electrode region in the first semiconductor layer 113 of the memory cells 100 in each memory cell column stacked at the same position in multiple memory cell layers for easy control.

[0143] 3 and 4 , the second electrode region of the first semiconductor layer 113 of the memory cell 100 connected to the connecting line 600 penetrates the planar structure of the connecting line 600 along a first direction.

[0144] In an exemplary embodiment, the materials of the first gate 111, the second gate 112, the third gate 121, the first conductive layer, the second conductive layer, the first bit line 200, the second bit line 300, the first word line 400, and the second word line 500 are all conductive materials. For example, the conductive material may be an alloy composed of metal elements or an alloy composed of a combination of metal elements. Examples include tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide. For example, the materials of the first gate 111, the second gate 112, the third gate 121, the first conductive layer, the second conductive layer, the first bit line 200, the second bit line 300, the first word line 400, and the second word line 500 may be the same or different.

[0145] In an exemplary embodiment, the materials of the first semiconductor layer 113 and the second semiconductor layer 122 are semiconductor materials. The semiconductor material may be a single crystal semiconductor material, a polycrystalline semiconductor material, a microcrystalline semiconductor material, or an amorphous semiconductor material. For example, the semiconductor material may include, but is not limited to, single crystal silicon, polycrystalline silicon, germanium, silicon carbide, gallium arsenide, a metal oxide semiconductor, a nitride semiconductor, and the like. For example, the materials of the first semiconductor layer 113 and the second semiconductor layer 122 may be the same or different.

[0146] The band gap of a metal oxide semiconductor is greater than 2 eV. When a metal oxide semiconductor is used as the material of the semiconductor layer, a transistor with extremely low off-state current can be realized. In addition, in a transistor whose semiconductor layer is made of a metal oxide semiconductor, the insulation withstand voltage between the source and the drain is high, thereby providing a transistor with good reliability, and thus providing a memory with good reliability. It can also provide a transistor with a large output voltage and a high withstand voltage, and thus provide a memory with a large output voltage and a high withstand voltage. Exemplarily, the material of the first semiconductor layer 113 and / or the second semiconductor layer 122 is a metal oxide semiconductor, so that the first transistor 110 and / or the second transistor 120 is realized as a transistor with extremely low off-state current.

[0147] Exemplarily, the metal oxide semiconductor may include at least one of indium or zinc. Exemplarily, the metal oxide semiconductor may also include aluminum, gallium, yttrium, or tin. Exemplarily, the metal oxide semiconductor may also include one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Exemplarily, taking the metal oxide semiconductor including indium, element M, and zinc as an example, element M may be aluminum, gallium, yttrium, or tin, or may be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, or may be a combination of multiple of the above elements. Exemplarily, a metal oxide semiconductor including indium, gallium, and zinc may be referred to as indium gallium zinc oxide (IGZO). Exemplarily, if the material of the semiconductor layer of a transistor is IGZO, the transistor may be referred to as an IGZO MOSFET.

[0148] In an exemplary embodiment, the materials of the insulating layers (eg, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the horizontal insulating layer, etc.) are all insulating materials. It should be noted that the materials of different insulating layers can be the same or different.

[0149] By way of example, the insulating material may refer to insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides. By way of example, when miniaturization and high integration of transistors are carried out, problems such as leakage current may sometimes occur due to the thin filming of the gate insulating layer. Therefore, the insulating material used as the gate insulating layer may use a high-k (high dielectric constant) material. The high-k material can achieve low voltage operation of the transistor while maintaining the physical thickness. By way of example, the insulating material with a high dielectric constant may refer to gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

[0150] Embodiments of the present application provide a memory device having a novel 2TOC memory cell structure. Two transistors in this novel 2TOC memory cell are arranged parallel to a substrate. This memory cell can be arranged in an array in a plane parallel to the substrate and can also be stacked perpendicular to the substrate, thereby forming a three-dimensional stacked memory device. This improves the integration density and, consequently, the storage density of the memory device. Furthermore, in this novel 2TOC memory cell, the first gate of the first transistor surrounds the first semiconductor layer, which in turn surrounds the second gate of the first transistor. This compact structure of the first transistor reduces the size of the memory cell, thereby improving the integration density and, consequently, the storage density of the memory device.

[0151] The present application provides a method for preparing a memory device, which can be used to prepare the memory device shown in Figures 3 and 4 above. Parts that are identical or corresponding to the above embodiments will not be described in detail below. For example, the preparation method provided in this application is a method for preparing a memory device by integrated molding, that is, the memory device structure can be prepared at the same time, which is beneficial for reducing process costs and thermal budget.

[0152] As shown in Figure 5, the method for preparing the memory provided in the embodiment of the present application includes the following steps 501 to 505. Next, the method for preparing the memory provided in the embodiment of the present application is described in detail with reference to Figures 6 to 24. Among them, Figures 6 to 24 are structural schematic diagrams corresponding to some steps in the method for preparing the memory provided in the embodiment of the present application. In Figures 6 to 24, the first direction and the third direction are perpendicular to each other and are parallel to the substrate, and the second direction is perpendicular to the substrate. It should be noted that the first direction, the second direction and the third direction shown in Figures 6 to 24 are only illustrative examples, and the embodiments of the present application are not limited to this.

[0153] Step 501: Alternately prepare isolation layers and sacrificial layers on a substrate to obtain a stacked structure.

[0154] The substrate is a base plate used to support the memory, and one or more film layers can be formed on the substrate. The type of substrate can be an insulator substrate, a semiconductor substrate, a conductor substrate, etc. Among them, the insulator substrate can include a glass substrate, a quartz substrate, a sapphire substrate, a zirconium oxide substrate, a resin substrate, etc. The semiconductor substrate can include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The conductor substrate can include a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. In some embodiments, the substrate can also be a flexible substrate, such as a polyimide (PI) substrate, a polyethylene terephthalate (PET) substrate, or a surface-treated polymer soft film substrate. In some embodiments, the substrate can also be called a wafer.

[0155] By alternately depositing an isolation layer and a sacrificial layer on a substrate, that is, depositing a stack of isolation layers and sacrificial layers, a stacked structure can be obtained, and the memory is prepared by processing the stacked structure. The isolation layer is used to isolate different memory cells 100 in a memory cell string, and the sacrificial layer is used to provide a basis for subsequent etching and preparation. The isolation layer can be obtained by depositing an isolation material (such as an insulating material), and the sacrificial layer can be obtained by depositing a material having an etching selectivity ratio with the material of the isolation layer. For example, the material of the isolation layer is silicon oxide, and the material of the sacrificial layer is silicon nitride; for another example, the material of the isolation layer is silicon oxide, and the material of the sacrificial layer is polysilicon; for another example, the material of the isolation layer is silicon, and the material of the sacrificial layer is silicon germanium.

[0156] The embodiments of the present application do not limit the method of depositing the isolation layer and the method of depositing the sacrificial layer, and they can be deposited in the same manner or in different manners. For example, the method of depositing the material includes but is not limited to sputtering, evaporation, chemical vapor deposition, atomic layer deposition, etc.

[0157] For example, after alternately depositing the isolation layers and the sacrificial layers, a protective layer may be applied to the top surface (e.g., by coating or deposition). The protective layer is used to protect the alternately deposited isolation layers and sacrificial layers. For example, the protective layer is used to protect the isolation layers and sacrificial layers that do not need to be etched when etching the stacked structure. For another example, the protective layer is used to protect the isolation layers and sacrificial layers that do not need to be planarized when planarization processing (e.g., polishing) is required. For example, the protective layer may include one or more layers, and the protective layer may be an insulating film layer.

[0158] For example, the stacking structure is shown in FIG6 . (1) in FIG6 is a cross-sectional view obtained by cutting the stacking structure from any position of the stacking structure using a plane perpendicular to the third direction, and (2) in FIG6 is a cross-sectional view obtained by cutting the stacking structure from any position of the stacking structure using a plane perpendicular to the first direction. It should be noted that FIG6 only shows three isolation layers and two sacrificial layers stacked alternately, but the embodiments of the present application are not limited thereto, and more layers can be stacked as needed, for example, hundreds of isolation layers and hundreds of sacrificial layers can be stacked alternately.

[0159] Step 502: etching the stacked structure along a second direction perpendicular to the substrate to form a first trench penetrating the stacked structure, and depositing a filling material in the first trench to obtain a first structure.

[0160] The first trench penetrating the stacked structure can be understood as exposing the substrate at the bottom of the first trench. The size of the first trench in the second direction is the same as the size of the stacked structure in the second direction. Etching can be wet etching or dry etching. The size and shape of the first trench can be obtained by patterning the protective layer covering the stacked structure.

[0161] The first trench is required to isolate different memory cells 100 in a memory cell column. Exemplarily, there are multiple first trenches, spaced apart in the third direction. The dimension of the first trench in the first direction is smaller than the dimension of the stacked structure in the first direction. After the first trench is formed, both sides of the first trench perpendicular to the first direction have unetched stacked structures.

[0162] For example, the structure after the first groove is formed is shown in Figure 7. (1) in Figure 7 is a cross-sectional view obtained by cutting off the structure at a position where the first groove does not exist in the structure after the first groove is formed using a plane perpendicular to the third direction, and (2) in Figure 7 is a cross-sectional view obtained by cutting off the structure at a position where the first groove exists in the structure after the first groove is formed using a plane perpendicular to the third direction; (3) in Figure 7 is a cross-sectional view obtained by cutting off the structure at a position where the first groove exists in the structure after the first groove is formed using a plane perpendicular to the first direction. It should be noted that the embodiment of the present application is only described by taking the formation of three first grooves as an example, wherein the first and third first grooves arranged in the third direction are located at the boundary, and the second groove arranged in the third direction is located in the middle, but the embodiment of the present application is not limited to this.

[0163] After forming the first trench, a filler material is deposited in the first trench. The resulting structure after depositing the filler material is referred to as the first structure. The filler material is used to isolate different memory cells 100 in the memory cell column. Exemplarily, the filler material is an insulating material that has an etching selectivity ratio with the material of the stacked structure. For example, the filler material can be silicon nitride, aluminum oxide, polysilicon, etc. It should be noted that depositing the filler material in the first trench means completely filling the first trench with the filler material.

[0164] In an exemplary embodiment, depositing the filling material in the first trench may also refer to depositing a protective layer in the first trench and depositing the filling material in the first trench having the protective layer deposited thereon. The protective layer is configured to protect the filling material from being etched when etching the stacked structure. In other words, the material of the protective layer has an etching selectivity ratio with the material of the stacked structure.

[0165] For example, the first structure is shown in FIG8. (1) in FIG8 is a cross-sectional view obtained by cutting the first structure at a position where no filling material is present in the first structure using a plane perpendicular to the third direction, (2) in FIG8 is a cross-sectional view obtained by cutting the first structure at a position where the filling material is present in the first structure using a plane perpendicular to the third direction; and (3) in FIG8 is a cross-sectional view obtained by cutting the first structure at a position where the filling material is present in the first structure using a plane perpendicular to the first direction.

[0166] Step 503 : Based on the first structure, a plurality of first bit lines 200 and a plurality of second bit lines 300 are formed.

[0167] Multiple first bit lines 200 and multiple second bit lines 300 all extend along the third direction, multiple first bit lines 200 are arranged at intervals in the second direction, and multiple second bit lines 300 are arranged at intervals in the second direction. One first bit line 200 and one second bit line 300 constitute a bit line group, and one bit line group corresponds to one storage cell column.

[0168] In an exemplary embodiment, based on the first structure, the implementation process of forming a plurality of first bit lines 200 and a plurality of second bit lines 300 includes the following steps 503a to 503e:

[0169] Step 503a: Partially etch the sacrificial layer in the first structure from the first side of the first structure to obtain a first etched groove; and form an etch stop layer in the first etched groove.

[0170] The first side of the first structure refers to any side of the first structure perpendicular to the first direction. Partially etching the sacrificial layer in the first structure from the first side may refer to the portion of the sacrificial layer in the first structure that remains unetched after etching. The groove formed after partially etching the sacrificial layer in the first structure from the first side is referred to as a first etched groove.

[0171] For example, the longitudinal cross-section of the first etched groove is the same at all locations, that is, etching from the first side to the location where the sacrificial layer contacts the filling material (or the protective layer outside the filling material) stops. The longitudinal cross-section of the first etched groove at any location refers to a plane obtained by cutting the first etched groove at any location using a plane perpendicular to the third direction.

[0172] Exemplarily, the longitudinal cross-section of the position corresponding to the filling material in the first etched groove is smaller than the longitudinal cross-sections at other positions. In this case, after etching from the first side to the position in contact with the filling material (or the protective layer outside the filling material), the sacrificial layer continues to be partially etched.

[0173] After forming the first etch groove, an etch stop layer is formed in the first etch groove. The etch stop layer can be formed in the first etch groove by filling the first etch groove with a metal material (e.g., nickel, titanium, cobalt). The etch stop layer is used as a stop layer for subsequent etching and can also serve as a metal source for subsequent metal-induced crystallization.

[0174] For example, the structure after the etch stop layer is formed is shown in FIG9. (1) in FIG9 is a cross-sectional view obtained by cutting the structure at a position where no filling material exists in the structure after the etch stop layer is formed using a plane perpendicular to the third direction, (2) in FIG9 is a cross-sectional view obtained by cutting the structure at a position where the filling material exists in the structure after the etch stop layer is formed using a plane perpendicular to the third direction, and (3) in FIG9 is a cross-sectional view obtained by cutting the structure at a position where the filling material exists and no etch stop layer exists in the structure after the etch stop layer is formed using a plane perpendicular to the first direction.

[0175] Step 503b: etching the remaining sacrificial layer in the first structure from the second side of the first structure until the etching reaches the etch stop layer to obtain a second etched groove.

[0176] The first side and the second side are two sides of the first structure perpendicular to the first direction. In other words, the second side is the other side opposite the first side of the first structure. The remaining sacrificial layer in the first structure is completely etched away from the second side of the second structure. The resulting groove is called a second etched groove.

[0177] Step 503c: depositing a first semiconductor material, a first insulating material, and a first conductive material in sequence on the sidewalls of the second etched groove; and partially etching the first conductive material, the first insulating material, and the first semiconductor material in sequence to obtain a third etched groove.

[0178] The first semiconductor material may be any semiconductor material, such as single crystal silicon, polycrystalline silicon, germanium, silicon carbide, gallium arsenide, metal oxide semiconductors, nitride semiconductors, etc. The first insulating material may be any insulating material, such as insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides. The first conductive material may be any conductive material, such as tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, highly conductive semiconductors such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0179] For example, a first semiconductor material, a first insulating material, and a first conductive material are sequentially deposited on the sidewalls of the second etch groove by means of ALD (Atomic Layer Deposition). The embodiment of the present application does not limit the thickness of the first semiconductor material deposited on the sidewalls of the second etch groove, the thickness of the deposited first insulating material, and the thickness of the deposited first conductive material, and can be flexibly controlled according to actual needs. It should be noted that after the first semiconductor material, the first insulating material, and the first conductive material are sequentially deposited on the sidewalls of the second etch groove, there is no area in the second etch groove where no material is deposited.

[0180] After the first semiconductor material, the first insulating material and the first conductive material are deposited in sequence on the sidewalls of the second etched groove, the first conductive material, the first insulating material and the first semiconductor material are partially etched in sequence, that is, the first conductive material, the first insulating material and the first semiconductor material are etched back in sequence, for example, the etching back stops at the middle position, and the groove obtained when the etching is stopped is called the third etched groove.

[0181] For example, during the sequential partial etching of the first conductive material, the first insulating material, and the first semiconductor material, the first semiconductor material is overetched to a certain extent (i.e., the etching depth of the first semiconductor material in a direction parallel to the substrate is greater than the etching depth of the first conductive material and the first insulating material in a direction parallel to the substrate) to facilitate the subsequent formation of isolation. The unetched first semiconductor material is used to form the first semiconductor layer 113 of the first transistor 110, and the unetched first conductive material is used to form the second gate 112 of the first transistor 110. In other words, at this point, the first semiconductor layer 113 and the second gate 112 of the first transistor 110 have been formed.

[0182] For example, the structure after the third etching groove is formed is shown in Figure 10. (1) in Figure 10 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the third etching groove is formed using a plane perpendicular to the third direction, (2) in Figure 10 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the third etching groove is formed using a plane perpendicular to the third direction, (3) in Figure 10 is a cross-sectional view obtained by cutting off the structure at a position where the third etching groove is located in the structure after the third etching groove is formed using a plane perpendicular to the first direction, and (4) in Figure 10 is a cross-sectional view obtained by cutting off the structure at a position where the first conductive material exists in the structure after the third etching groove is formed using a plane perpendicular to the first direction.

[0183] Step 503d: A first conductive layer in contact with the unetched first conductive material and isolated from the unetched first semiconductor material, a third insulating layer in contact with the first conductive layer, a second conductive layer in contact with the third insulating layer, and a second bit line 300 extending along a third direction in contact with the second conductive layer are sequentially formed in the third etching groove.

[0184] Exemplarily, the process of forming a first conductive layer that contacts the unetched first conductive material and is isolated from the unetched first semiconductor material includes: growing an isolation material within a third etched trench, etching the isolation material (also referred to as etching back) to an extent that only some isolation material remains in the first semiconductor material, thereby forming a first basic trench, wherein the retained isolation material is used to separate the first semiconductor material from the first conductive material; growing a fifth conductive material within the first basic trench, etching the fifth conductive material to an extent that a certain length remains in a first direction, and using the layer formed by the retained fifth conductive material as the first conductive layer. The fifth conductive material can be the same as or different from the other conductive materials.

[0185] For example, the trench formed after etching the fifth conductive material is referred to as a second basic trench. The process of forming the third insulating layer in contact with the first conductive layer includes: growing a fourth insulating material within the second basic trench; etching the fourth insulating material to a certain length remaining in the first direction; and using the layer formed by the remaining fourth insulating material as the third insulating layer. The fourth insulating material can be the same as or different from the other insulating materials.

[0186] For example, the trench formed after etching the fourth insulating material is referred to as a third basic trench. The process of forming a second conductive layer in contact with the third insulating layer and a second bit line 300 extending in the third direction in contact with the second conductive layer includes: growing a sixth conductive material within the third basic trench; using the portion of the sixth conductive material separated by the filling material in the third direction as the second conductive layer; and using the remaining portion of the sixth conductive material other than the second conductive layer as the second bit line 300. The sixth conductive material can be the same as or different from the other conductive materials.

[0187] Illustratively, the above-mentioned method of generating the material may be to grow the material using an ALD growth process, and the above-mentioned etching may refer to wet etching.

[0188] For example, the structure after the second bit line 300 is formed is shown in FIG11. (1) in FIG11 is a cross-sectional view obtained by cutting the structure after the second bit line 300 is formed at a position where no filling material exists, using a plane perpendicular to the third direction; (2) in FIG11 is a cross-sectional view obtained by cutting the structure after the second bit line 300 is formed at a position where a filling material exists, using a plane perpendicular to the third direction; (3) in FIG11 is a cross-sectional view obtained by cutting the structure after the second bit line 300 is formed at a position where the third insulating layer is located, using a plane perpendicular to the first direction; and (4) in FIG11 is a cross-sectional view obtained by cutting the structure after the second bit line 300 is formed at a position where the first conductive material exists, using a plane perpendicular to the first direction.

[0189] Step 503e: forming a first bit line 200 extending along the third direction based on the etch stop layer.

[0190] For example, a method of forming the plurality of first bit lines 200 based on the etch stop layer may be to use the etch stop layer directly as the first bit line 200 .

[0191] For example, a method for forming the plurality of first bit lines 200 based on the etch stop layer may include removing the etch stop layer, depositing a seventh conductive material in the grooves formed after the etch stop layer is removed, and using the area where the seventh conductive material is deposited as the first bit line 200. The seventh conductive material may be the same as or different from the other conductive materials.

[0192] Illustratively, the etch stop layer is a metal material (eg, nickel, titanium, cobalt, etc.). Before removing the etch stop layer, the etch stop layer can be used to perform metal-induced crystallization on the first semiconductor material to convert the first semiconductor material into a single crystal material to improve mobility.

[0193] For example, after depositing the seventh conductive material, a metallization process may be performed on the current structure to reduce contact resistance, wherein the metallization process may be achieved by high-temperature annealing.

[0194] For example, the structure after the etch stop layer is removed is shown in Figure 12. (1) in Figure 12 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the etch stop layer is removed using a plane perpendicular to the third direction, (2) in Figure 12 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the etch stop layer is removed using a plane perpendicular to the third direction, (3) in Figure 12 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer exists in the structure after the etch stop layer is removed using a plane perpendicular to the first direction, and (4) in Figure 12 is a cross-sectional view obtained by cutting off the structure at a position where the first conductive material exists in the structure after the etch stop layer is removed using a plane perpendicular to the first direction.

[0195] The structure after forming the first bit line 200 and the second bit line 300 is referred to as the second structure. It should be noted that if a blank area exists after forming the first bit line 200 and the second bit line 300, the second structure refers to the structure obtained after depositing a filling material in the blank area.

[0196] For example, the second structure is shown in FIG13. (1) in FIG13 is a cross-sectional view obtained by cutting the second structure at a position where no filling material exists in the second structure using a plane perpendicular to the third direction, (2) in FIG13 is a cross-sectional view obtained by cutting the second structure at a position where the filling material exists in the second structure using a plane perpendicular to the third direction, (3) in FIG13 is a cross-sectional view obtained by cutting the second structure at a position where the third insulating layer is located in the second structure using a plane perpendicular to the first direction, and (4) in FIG13 is a cross-sectional view obtained by cutting the second structure at a position where the first conductive material exists in the second structure using a plane perpendicular to the first direction.

[0197] It should be noted that steps 503a to 503e are described from the perspective of one sacrificial layer. In an actual fabrication process, there are multiple sacrificial layers, each of which can form one first bit line 200 and one second bit line 300. That is, there are multiple first bit lines 200 and multiple second bit lines 300. The multiple first bit lines 200 are separated in the second direction by isolation layers, and the multiple second bit lines 300 are separated in the second direction by isolation layers.

[0198] It should be further noted that the above steps 503a to 503e are merely an exemplary implementation of forming the first bit line 200 and the second bit line 300, and the embodiments of the present application are not limited thereto. In some embodiments, the first bit line 200 and the second bit line 300 may also be formed by other methods. For example, the sacrificial layer in the first structure may be partially etched directly from the second side of the first structure to form a second etched groove. A third etched groove may be formed according to the above steps 503c and 503d, and the second bit line 300 may be formed in the third etched groove. Subsequently, the remaining sacrificial layer in the first structure may be etched away from the first side of the first structure, and a seventh conductive material may be deposited in the etched groove to form the first bit line 200.

[0199] Step 504 : forming a plurality of first transistors 110 connected to the plurality of first bit lines 200 and a plurality of first word lines 400 connected to the plurality of first transistors 110 .

[0200] The first transistor 110 includes a first gate 111, a second gate 112, and a first semiconductor layer 113. The first gate 111 of the first transistor 110 extends along the second direction, the second gate 112 and the first semiconductor layer 113 of the first transistor 110 both extend along the first direction, the first gate 111 of the first transistor 110 surrounds the first semiconductor layer 113 of the first transistor 110, and the first semiconductor layer 113 of the first transistor 110 surrounds the second gate 112 of the first transistor 110.

[0201] A plurality of first word lines 400 extend along the second direction, and the first word lines 400 are connected to the first transistors 110 (e.g., the first gates 111 of the first transistors 110) of the memory cells 100 stacked at the same position in the plurality of memory cell layers. The first bit line 200 is connected to the first transistors 110 (e.g., the first semiconductor layer 113 of the first transistors 110) in a memory cell column.

[0202] In an exemplary embodiment, the structure after forming the plurality of first bit lines 200 and the plurality of second bit lines 300 is referred to as a second structure, and the second structure includes a first transistor fabrication region. Based on this, the implementation process of forming the plurality of first transistors 110 connected to the plurality of first bit lines 200 and the plurality of first word lines 400 connected to the plurality of first transistors 110 includes the following steps 504a to 504d:

[0203] Step 504a: Etch the filling material in the first transistor preparation area along the second direction to form a second trench penetrating the second structure, and etch the isolation layer in the first transistor preparation area based on the second trench to obtain a third trench for exposing the first semiconductor material.

[0204] The first transistor fabrication area refers to an area used to fabricate the first transistor 110. There can be one or more first transistor fabrication areas, depending on actual fabrication requirements. One first transistor fabrication area is used to fabricate the first transistor 110 for multiple memory cell columns stacked at the same location on the substrate. The first transistor fabrication area is located between the multiple stacked first bit lines 200 and the multiple stacked second bit lines 300 corresponding to the multiple memory cell columns.

[0205] The first transistor fabrication region is perpendicular to the substrate and extends along the second direction. The first transistor fabrication region includes a filler material that extends through the first transistor fabrication region along the second direction, and a first semiconductor material that is in contact with the filler material and isolated by an isolation layer. A third trench exposing the first semiconductor material is formed by etching the filler material in the first transistor fabrication region along the second direction and etching the isolation layer in the first transistor fabrication region based on the second trench formed by the etching. The third trench exposing the first semiconductor material means that the third trench exposes the first semiconductor material in contact with the filler material and the first semiconductor material in contact with the isolation layer.

[0206] For example, the structure after the third trench is formed is shown in Figure 14. (1) in Figure 14 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the third trench is formed using a plane perpendicular to the third direction, (2) in Figure 14 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the third trench is formed using a plane perpendicular to the third direction, (3) in Figure 14 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the third trench is formed using a plane perpendicular to the first direction, and (4) in Figure 14 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation area is located in the structure after the third trench is formed using a plane perpendicular to the first direction.

[0207] Step 504b: depositing a second insulating material and a second conductive material in sequence on the sidewalls of the third trench.

[0208] For example, a second insulating material and a second conductive material are sequentially deposited on the sidewalls of the third trench by ALD. The second insulating material may be the same as or different from the other insulating materials. The second conductive material may be the same as or different from the other conductive materials.

[0209] After the second insulating material and the second conductive material are sequentially deposited on the sidewalls of the third trench, the second conductive materials are connected together in the second direction to form the first gate 111 of the first transistor 110 and the first word line 400 based on the second conductive materials.

[0210] For example, after depositing the second conductive material, there may be an area in the third trench where no material is deposited, or there may be no area in the third trench where no material is deposited, which depends on the actual preparation situation.

[0211] For example, the structure after the second insulating material and the second conductive material are sequentially deposited on the sidewall of the third trench is shown in FIG15. (1) in FIG15 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the second insulating material and the second conductive material are sequentially deposited on the sidewall of the third trench using a plane perpendicular to the third direction, (2) in FIG15 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the second insulating material and the second conductive material are sequentially deposited on the sidewall of the third trench using a plane perpendicular to the third direction, (3) in FIG15 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the second insulating material and the second conductive material are sequentially deposited on the sidewall of the third trench using a plane perpendicular to the first direction, and (4) in FIG15 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation area is located in the structure after the second insulating material and the second conductive material are sequentially deposited on the sidewall of the third trench using a plane perpendicular to the first direction.

[0212] For example, after sequentially depositing the second insulating material and the second conductive material on the sidewalls of the third trench, an area in the second trench where no material is deposited exists. Based on the area in the second trench where no material is deposited, the second conductive material and the second insulating material deposited at the bottom of the second trench can be etched to prevent connection between memory cells in different rows. Isolation material is then deposited in the etched structure to obtain a fifth structure. A row of memory cells refers to memory cells in a row of memory cells stacked at the same location in multiple memory cell layers.

[0213] For example, the fifth structure is shown in FIG16. (1) in FIG16 is a cross-sectional view obtained by cutting the fifth structure from a position where no filling material exists in the fifth structure using a plane perpendicular to the third direction, (2) in FIG16 is a cross-sectional view obtained by cutting the fifth structure from a position where a filling material exists in the fifth structure using a plane perpendicular to the third direction, (3) in FIG16 is a cross-sectional view obtained by cutting the fifth structure from a position where the third insulating layer is located in the fifth structure using a plane perpendicular to the first direction, and (4) in FIG16 is a cross-sectional view obtained by cutting the fifth structure from a position where the first transistor preparation region is located in the fifth structure using a plane perpendicular to the first direction.

[0214] Step 504c: Etching the filling material in contact with the second insulating material along the second direction to form a fourth trench penetrating the second structure.

[0215] The filling material in contact with the second insulating material may refer to the filling material in contact with the second insulating material on both sides of the second insulating material perpendicular to the first direction. Because the filling material in contact with the second insulating material is etched, the second insulating material is deposited on the sidewalls of the fourth trench formed after etching. In other words, the fourth trench can expose the second insulating material. Since the second insulating material is in contact with the second conductive material, it can be considered that the sidewalls of the fourth trench are sequentially arranged with the second insulating material and the second conductive material.

[0216] Step 504d: sequentially etching the second insulating material and the second conductive material on the sidewalls of the fourth trench, and depositing an isolation material in the etched trench to obtain a third structure.

[0217] After the second insulating material on the sidewall of the fourth trench is etched away, the second conductive material is exposed, and then the exposed second conductive material is etched away, thereby preventing the first gates 111 of different first transistors 110 in the memory cell column from being connected.

[0218] After etching away the second insulating material and the second conductive material from the sidewalls of the fourth trench, an isolation material is deposited in the trench. The resulting structure is referred to as a third structure. The first conductive material in the third structure is used to form the second gate electrode 112 of the first transistor 110. The first semiconductor material in the third structure is used to form the first semiconductor layer 113 of the first transistor 110, which is connected to the first bit line 200. The second conductive material in the third structure is used to form the first word line 400 connected to the first transistor 110 and extending in the second direction. The second conductive material in the third structure, which surrounds the first semiconductor layer 113, is used to form the first gate electrode 111 of the first transistor 110.

[0219] For example, the third structure is shown in FIG17. (1) in FIG17 is a cross-sectional view obtained by cutting the third structure from a position where no filling material exists in the third structure using a plane perpendicular to the third direction, (2) in FIG17 is a cross-sectional view obtained by cutting the third structure from a position where a filling material exists in the third structure using a plane perpendicular to the third direction, (3) in FIG17 is a cross-sectional view obtained by cutting the third structure from a position where the third insulating layer is located in the third structure using a plane perpendicular to the first direction, and (4) in FIG17 is a cross-sectional view obtained by cutting the third structure from a position where the first transistor preparation region is located in the third structure using a plane perpendicular to the first direction.

[0220] In an exemplary embodiment, the memory further includes a plurality of connection lines 600 perpendicular to the substrate, and the third structure includes a connection line preparation area. After forming the third structure, the memory preparation method further includes the following steps A and B:

[0221] Step A: etching the filling material in the connection line preparation area along the second direction to form a ninth trench penetrating the third structure, wherein the ninth trench is used to expose the first semiconductor material.

[0222] The connection line preparation area is used to prepare connection lines 600 perpendicular to the substrate. Exemplarily, the number of connection line preparation areas is one or more, which is related to actual preparation requirements. One connection line preparation area is used to prepare connection lines 600 connected to the first transistors 110 in multiple memory cell columns stacked at the same position on the substrate. The one connection line preparation area is located between the multiple stacked second bit lines 300 corresponding to the multiple memory cell columns and the first transistor preparation areas corresponding to the multiple memory cell columns. Exemplarily, the connection line preparation area is perpendicular to the second connection areas of the first transistors 110 in the multiple memory cell columns.

[0223] The connection line preparation region is perpendicular to the substrate and extends along the second direction. The connection line preparation region includes a filling material that penetrates the connection line preparation region along the second direction and a first semiconductor material that is in contact with the filling material and isolated by an isolation layer. The filling material in the connection line preparation region is etched along the second direction to form a ninth trench that exposes the first semiconductor material. The ninth trench exposing the first semiconductor material means that the ninth trench is exposed to the filling material and contacts the first semiconductor material.

[0224] Step B: Based on the ninth trench, a region to be filled is formed; a fourth conductive material is deposited in the region to be filled, where the fourth conductive material is used to form a connecting line 600 perpendicular to the substrate.

[0225] Illustratively, forming the to-be-filled region based on the ninth trench may refer to: using the region where the ninth trench is located as the to-be-filled region.

[0226] Illustratively, forming the area to be filled based on the ninth trench may also include etching the isolation layer in the connection line preparation area based on the ninth trench, and using the area where the resulting trench is located as the area to be filled. For example, the isolation layer in the connection line preparation area may be etched using a lateral wet etch to expose the first semiconductor material in contact with the isolation layer.

[0227] For example, ALD may be used to deposit the fourth conductive material in the region to be filled. After the fourth conductive material is deposited, a metallization process (eg, high-temperature annealing) may be performed to reduce contact resistance.

[0228] For example, in the case where the area where the ninth trench is located is used as the area to be filled, the structure after the fourth conductive material is deposited is shown in FIG18. (1) in FIG18 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the fourth conductive material is deposited using a plane perpendicular to the third direction, (2) in FIG18 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the fourth conductive material is deposited using a plane perpendicular to the third direction, (3) in FIG18 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction, (4) in FIG18 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation area is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction, and (5) in FIG18 is a cross-sectional view obtained by cutting off the structure at a position where the connection line preparation area is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction.

[0229] For example, for the case where the isolation layer in the connection line preparation area is etched based on the ninth groove, and the area where the groove is located after etching is used as the area to be filled, the structure after the fourth conductive material is deposited is shown in Figure 19. (1) in Figure 19 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the fourth conductive material is deposited using a plane perpendicular to the third direction, (2) in Figure 19 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the fourth conductive material is deposited using a plane perpendicular to the third direction, (3) in Figure 19 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction, (4) in Figure 19 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation area is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction, and (5) in Figure 19 is a cross-sectional view obtained by cutting off the structure at a position where the connection line preparation area is located in the structure after the fourth conductive material is deposited using a plane perpendicular to the first direction.

[0230] Step 505 : forming a plurality of second transistors 120 connected to the plurality of second bit lines 300 and a plurality of second word lines 500 connected to the plurality of second transistors 120 .

[0231] The third gate 121 of the second transistor 120 extends along the second direction, and the second semiconductor layer 122 of the second transistor 120 is connected to the second gate 112 .

[0232] A plurality of second word lines 500 extend along the second direction, and the second word lines 500 are connected to the second transistors 120 (e.g., the third gates 121 of the second transistors 120) of the memory cells 100 stacked at the same position in the plurality of memory cell layers. A second bit line 300 is connected to the second transistors 120 (e.g., the second semiconductor layers 122 of the second transistors 120) in a memory cell column.

[0233] In an exemplary embodiment, the third structure after forming the first transistor 110 and the first word line 400 includes a second transistor fabrication region. Based on this, the process of forming the plurality of second transistors 120 connected to the plurality of second bit lines 300 and the plurality of second word lines 500 connected to the plurality of second transistors 120 includes the following steps 505a to 505d:

[0234] Step 505a: Etch the filling material in the second transistor preparation area along the second direction to form a fifth trench penetrating the third structure, and etch the isolation layer in the second transistor preparation area based on the fifth trench to obtain a sixth trench, which is used to expose the third insulating layer.

[0235] The second transistor preparation area refers to an area used to prepare the second transistor 120. The number of second transistor preparation areas is one or more, which is related to the actual preparation requirements. One second transistor preparation area is used to prepare the second transistor 120 in multiple memory cell columns stacked at the same position on the substrate, and the one second transistor preparation area is located between the multiple stacked first bit lines 200 and the multiple stacked second bit lines 300 corresponding to the multiple memory cell columns. Exemplarily, the second transistor preparation area is an area of ​​the third insulating layer that runs through the third structure and is included in the multiple memory cell columns stacked at the same position.

[0236] The second transistor preparation region is perpendicular to the substrate and extends along the second direction. The second transistor preparation region includes a filling material that penetrates the second transistor preparation region along the second direction, and a third insulating layer that contacts the filling material and is isolated by the isolation layer. A sixth trench exposing the third insulating layer can be obtained by etching the filling material in the second transistor preparation region along the second direction and etching the isolation layer in the second transistor preparation region based on the fifth trench obtained by etching. The sixth trench exposing the third insulating layer means that the sixth trench exposes a surface of the third insulating layer that contacts the filling material and a surface that contacts the isolation layer.

[0237] For example, the structure after the sixth trench is formed is shown in Figure 20. (1) in Figure 20 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the sixth trench is formed using a plane perpendicular to the third direction, (2) in Figure 20 is a cross-sectional view obtained by cutting off the structure at a position where a filling material exists in the structure after the sixth trench is formed using a plane perpendicular to the third direction, (3) in Figure 20 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the sixth trench is formed using a plane perpendicular to the first direction, and (4) in Figure 20 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation region is located in the structure after the sixth trench is formed using a plane perpendicular to the first direction.

[0238] Step 505b: depositing a second semiconductor material, a third insulating material, and a third conductive material in sequence on the sidewalls of the sixth trench.

[0239] For example, a second semiconductor material, a third insulating material, and a third conductive material are sequentially deposited on the sidewalls of the sixth trench by ALD. The second semiconductor material may be the same as or different from the other semiconductor materials. The third insulating material may be the same as or different from the other insulating materials. The third conductive material may be the same as or different from the other conductive materials.

[0240] After the second semiconductor material, the third insulating material and the third conductive material are sequentially deposited on the sidewalls of the sixth trench, the third conductive materials are connected together in the second direction to form the third gate 121 of the second transistor 120 and the second word line 500 based on the third conductive material.

[0241] For example, after the third conductive material is deposited, there may be an area in the sixth trench where no material is deposited, or there may be no area in the sixth trench where no material is deposited, which depends on the actual preparation situation.

[0242] Illustratively, after the second semiconductor material, the third insulating material and the third conductive material are sequentially deposited on the sidewalls of the sixth trench, there is an area in the fifth trench where no material is deposited. Based on the area in the fifth trench where no material is deposited, the third conductive material, the third insulating material and the second semiconductor material deposited at the bottom of the fifth trench can be etched to prevent storage cells in different rows from being connected, and isolation material is deposited in the etched structure to obtain the sixth structure.

[0243] For example, the sixth structure is shown in FIG21. (1) in FIG21 is a cross-sectional view obtained by cutting the sixth structure from a position where no filling material exists in the sixth structure using a plane perpendicular to the third direction, (2) in FIG21 is a cross-sectional view obtained by cutting the sixth structure from a position where a filling material exists in the sixth structure using a plane perpendicular to the third direction, (3) in FIG21 is a cross-sectional view obtained by cutting the sixth structure from a position where the third insulating layer is located in the sixth structure using a plane perpendicular to the first direction, and (4) in FIG21 is a cross-sectional view obtained by cutting the sixth structure from a first transistor preparation region in the sixth structure using a plane perpendicular to the first direction.

[0244] Step 505c: etching the filling material in contact with the second semiconductor material along the second direction to form a seventh trench penetrating the third structure; etching the isolation layer in contact with the second semiconductor material based on the seventh trench to form an eighth trench.

[0245] The filling material in contact with the second semiconductor material refers to the filling material in contact with the second semiconductor material on both sides of the second semiconductor material perpendicular to the first direction. The isolation layer in contact with the second semiconductor material refers to the isolation layer in contact with the second semiconductor material on both sides of the second semiconductor material perpendicular to the first direction.

[0246] The eighth trench is obtained by further etching on the basis of the seventh trench, and therefore, the eighth trench includes the seventh trench. Since the eighth trench is obtained by etching the portion in contact with the second semiconductor material, the sidewalls of the eighth trench are deposited with the second semiconductor material, that is, the eighth trench can expose the second semiconductor material. Since the second semiconductor material is in contact with the third insulating material, and the third insulating material is in contact with the third conductive material, it can be considered that the sidewalls of the eighth trench are sequentially arranged with the second semiconductor material, the third insulating material and the third conductive material. It should be noted that the eighth trench includes the seventh trench, and the sidewalls of the seventh trench are also sequentially arranged with the second semiconductor material, the third insulating material and the third conductive material, and the thickness of the third conductive material arranged on the sidewalls of the seventh trench is less than the thickness of the third conductive material arranged on the sidewalls of other parts of the eighth trench except the seventh trench.

[0247] For example, the structure after the eighth trench is formed is shown in Figure 22. (1) in Figure 22 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the eighth trench is formed using a plane perpendicular to the third direction, (2) in Figure 22 is a cross-sectional view obtained by cutting off the structure at a position where a filling material exists in the structure after the eighth trench is formed using a plane perpendicular to the third direction, (3) in Figure 22 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the eighth trench is formed using a plane perpendicular to the first direction, and (4) in Figure 22 is a cross-sectional view obtained by cutting off the structure at a first transistor preparation region in the structure after the eighth trench is formed using a plane perpendicular to the first direction.

[0248] Step 505d: sequentially etch the second semiconductor material, the third insulating material, and the third conductive material on the sidewall of the eighth trench until the third conductive material on the sidewall of the seventh trench is completely etched, and deposit isolation material in the etched trench to obtain a fourth structure.

[0249] Since the thickness of the third conductive material arranged on the sidewall of the seventh trench is less than the thickness of the third conductive material arranged on the sidewall of other parts of the eighth trench except the seventh trench, after etching away the second semiconductor material and the third insulating material on the sidewall of the eighth trench, the third conductive material on the sidewall of the seventh trench will be etched away first, and the etching will be stopped after etching away the third conductive material on the sidewall of the seventh trench, thereby preventing the third gates 121 of different second transistors 120 in the memory cell column from being connected.

[0250] The process of sequentially etching the second semiconductor material, the third insulating material and the third conductive material on the sidewall of the eighth trench until the third conductive material on the sidewall of the seventh trench is completely etched can remove parasitic effects between storage cells.

[0251] After etching is stopped, an isolation material is deposited in the trench formed. The resulting structure is referred to as the fourth structure. The second semiconductor material in the fourth structure is used to form the second semiconductor layer 122 of the second transistor 120, which is connected to the second bit line 300. The third conductive material in the fourth structure is used to form the second word line 500, which is connected to the second transistor 120 and extends along the second direction. The portion of the third conductive material in the fourth structure that surrounds the second semiconductor layer 122 is used to form the third gate 121 of the second transistor 120.

[0252] For example, the structure after the third conductive material on the sidewall of the seventh trench is completely etched is shown in Figure 23. (1) in Figure 23 is a cross-sectional view obtained by cutting off the structure at a position where no filling material exists in the structure after the third conductive material on the sidewall of the seventh trench is completely etched using a plane perpendicular to the third direction, (2) in Figure 23 is a cross-sectional view obtained by cutting off the structure at a position where the filling material exists in the structure after the third conductive material on the sidewall of the seventh trench is completely etched using a plane perpendicular to the third direction, (3) in Figure 23 is a cross-sectional view obtained by cutting off the structure at a position where the third insulating layer is located in the structure after the third conductive material on the sidewall of the seventh trench is completely etched using a plane perpendicular to the first direction, and (4) in Figure 23 is a cross-sectional view obtained by cutting off the structure at a position where the first transistor preparation area is located in the structure after the third conductive material on the sidewall of the seventh trench is completely etched using a plane perpendicular to the first direction.

[0253] For example, the fourth structure is shown in Figure 24. (1) in Figure 24 is a cross-sectional view obtained by cutting the fourth structure from a position where no filling material exists in the fourth structure using a plane perpendicular to the third direction, (2) in Figure 24 is a cross-sectional view obtained by cutting the fourth structure from a position where a filling material exists in the fourth structure using a plane perpendicular to the third direction, (3) in Figure 24 is a cross-sectional view obtained by cutting the fourth structure from a position where the third insulating layer is located in the fourth structure using a plane perpendicular to the first direction, and (4) in Figure 24 is a cross-sectional view obtained by cutting the fourth structure from the first transistor preparation region in the fourth structure using a plane perpendicular to the first direction.

[0254] In an exemplary embodiment, after the fourth structure is formed, the fourth structure may be ground flat to expose the conductive material, thereby facilitating subsequent electrode extraction.

[0255] For example, after some of the above steps, for example, after the etching step, after the material deposition step, etc., a post-processing step of planarizing the current structure is also included to ensure that the top of the current structure is flat. The embodiment of the present application does not limit the post-processing method of planarization. For example, planarization can be achieved based on a CMP (Chemical Mechanical Polishing) process.

[0256] It should be noted that step 504 is a step for preparing the first transistor 110 and the first word line 400, and step 505 is a step for preparing the second transistor 120 and the second word line 500. The present embodiment of the application does not limit the order in which the steps of preparing the first transistor 110 and the first word line 400, and the steps of preparing the second transistor 120 and the second word line 500 are performed. In one implementation, after the first bit line 200 and the second bit line 300 are prepared based on steps 501 to 503, the first transistor 110 and the first word line 400 are first prepared based on step 504, and then the second transistor 120 and the second word line 500 are prepared based on step 505. In another implementation, after the first bit line 200 and the second bit line 300 are prepared based on steps 501 to 503, the second transistor 120 and the second word line 500 are first prepared based on step 505, and then the first transistor 110 and the first word line 400 are prepared based on step 504.

[0257] An embodiment of the present application also provides a chip, as shown in FIG25 , which includes the above-mentioned memory and can be integrated into any electronic device.

[0258] The present application also provides an electronic device, as shown in Figure 26, which includes the above-mentioned memory. The electronic device may include but is not limited to a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal.

[0259] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application. Industrial Applicability

[0260] The present application provides a novel 2T0C memory cell structure and a memory device having such a 2T0C memory cell. The two transistors in this 2T0C memory cell are arranged parallel to the substrate. This memory cell can be arranged in an array in a plane parallel to the substrate and can also be stacked perpendicular to the substrate, thereby forming a three-dimensional stacked memory. This improves the integration density and, consequently, the storage density of the memory. Furthermore, in this 2T0C memory cell, the first gate of the first transistor surrounds the first semiconductor layer, which in turn surrounds the second gate of the first transistor. This compact structure of the first transistor reduces the size of the memory cell, thereby improving the integration density and, consequently, the storage density of the memory.

Claims

1. A memory cell (100), comprising a first transistor (110) and a second transistor (120) arranged along a first direction parallel to a substrate; The first gate (111) of the first transistor (110) extends along a second direction perpendicular to the substrate, the second gate (112) of the first transistor (110) and the first semiconductor layer (113) both extend along the first direction, the first gate (111) surrounds the first semiconductor layer (113), and the first semiconductor layer (113) surrounds the second gate (112); The third gate (121) of the second transistor (120) extends along the second direction, and the second semiconductor layer (122) of the second transistor (120) is connected to the second gate (112).

2. The storage unit (100) according to claim 1, wherein The first semiconductor layer (113) is a cylindrical structure with an opening facing the first direction, the cylindrical structure comprising an inner surface and an outer surface, the inner surface being the surface constituting the hollow portion of the cylindrical structure, and the outer surface being the surface of the cylindrical structure excluding the inner surface; The first gate (111) surrounds a surface of the outer surface that is parallel to the first direction, and the inner surface surrounds the second gate (112).

3. The storage unit (100) according to claim 1, wherein A first insulating layer is included between the first gate (111) and the first semiconductor layer (113), and a second insulating layer is included between the first semiconductor layer (113) and the second gate (112); The first gate (111) surrounds the first insulating layer, the first insulating layer surrounds the first semiconductor layer (113), the first semiconductor layer (113) surrounds the second insulating layer, and the second insulating layer surrounds the second gate (112).

4. The storage unit (100) according to any one of claims 1 to 3, wherein: The first semiconductor layer (113) is used to connect to the first bit line (200), and the size of the first semiconductor layer (113) in the second direction is the same as the size of the first bit line (200) in the second direction.

5. The storage unit (100) according to any one of claims 1 to 4, wherein: The third gate (121) surrounds the second semiconductor layer (122).

6. The storage unit (100) according to claim 5, wherein The second semiconductor layer (122) is connected to the second gate (112) through a first conductive layer, and the second semiconductor layer (122) is also connected to a second bit line (300) through a second conductive layer; A third insulating layer is included between the first conductive layer and the second conductive layer, and the second semiconductor layer A layer (122) surrounds the third insulating layer.

7. The storage unit (100) according to any one of claims 1 to 4, wherein: The second semiconductor layer (122) surrounds the third gate (121).

8. A memory comprising a plurality of memory cell layers vertically stacked on a substrate and a plurality of first bit lines (200), a plurality of second bit lines (300), a plurality of first word lines (400), and a plurality of second word lines (500) connected to the plurality of memory cell layers; The memory cell layer comprises a plurality of memory cells (100) arranged in an array; the memory cells (100) are the memory cells according to any one of claims 1 to 7.

9. The memory according to claim 8, wherein The plurality of first bit lines (200) and the plurality of second bit lines (300) both extend along a third direction, the third direction being perpendicular to the first direction and the second direction; The first bit line (200) is connected to the first semiconductor layer (113) of each memory cell (100) in a memory cell column in the memory cell layer, and the second bit line (300) is connected to the second semiconductor layer (122) of each memory cell (100) in a memory cell column.

10. The memory according to claim 8 or 9, wherein: The plurality of first word lines (400) and the plurality of second word lines (500) both extend along the second direction; The first word line (400) is connected to the first gate (111) of each memory cell (100) stacked at the same position in the multiple memory cell layers, and the second word line (500) is connected to the third gate (121) of each memory cell (100) stacked at the same position in the multiple memory cell layers.

11. The memory according to claim 10, wherein The first gate (111) of each memory cell (100) connected to the first word line (400) is a part of the first word line (400).

12. The memory according to claim 10 or 11, wherein: The third gate (121) of each memory cell (100) connected to the second word line (500) is a part of the second word line (500).

13. The memory according to any one of claims 8 to 12, wherein: The memory further comprises a plurality of connection lines (600) perpendicular to the substrate, wherein the connection lines (600) are connected to the first semiconductor layers (113) of the memory cells (100) in each memory cell column stacked at the same position in the plurality of memory cell layers.

14. The memory according to any one of claims 8 to 13, wherein: The memory is applied in a chip.

15. The memory according to any one of claims 8 to 13, wherein: The memory is used in electronic equipment.

16. A method for preparing a memory, the method being used for preparing the memory, the memory comprising a plurality of memory cell layers vertically stacked on a substrate and a plurality of first bit lines (200), a plurality of second bit lines (300), a plurality of first word lines (400), and a plurality of second word lines (500) connected to the plurality of memory cell layers; the memory cell layers comprising a plurality of memory cells (100) arranged in an array, the memory cells (100) comprising a first transistor (110) and a second transistor (120) arranged along a first direction parallel to the substrate; the method comprising: Alternatingly preparing isolation layers and sacrificial layers on the substrate to obtain a stacked structure; Etching the stacked structure along a second direction perpendicular to the substrate to form a first trench penetrating the stacked structure, and depositing a filling material in the first trench to obtain a first structure; Based on the first structure, forming the plurality of first bit lines (200) and the plurality of second bit lines (300); forming a plurality of first transistors (110) connected to the plurality of first bit lines (200) and a plurality of first word lines (400) connected to the plurality of first transistors (110); forming a plurality of second transistors (120) connected to the plurality of second bit lines (300) and a plurality of second word lines (500) connected to the plurality of second transistors (120); The first gate (111) of the first transistor (110) extends along the second direction, the second gate (112) and the first semiconductor layer (113) of the first transistor (110) both extend along the first direction, the first gate (111) surrounds the first semiconductor layer (113), and the first semiconductor layer (113) surrounds the second gate (112); the third gate (121) of the second transistor (120) extends along the second direction, and the second semiconductor layer (122) of the second transistor (120) is connected to the second gate (112).

17. The preparation method according to claim 16, wherein The forming of the plurality of first bit lines (200) and the plurality of second bit lines (300) based on the first structure comprises: Partially etching the sacrificial layer in the first structure from a first side of the first structure to obtain a first etched groove; forming an etch stop layer in the first etched groove; Etching the remaining sacrificial layer in the first structure from the second side of the first structure until the etching reaches the etch stop layer to obtain a second etch groove; the first side and the second side are two sides of the first structure perpendicular to the first direction; Depositing a first semiconductor material, a first insulating material, and a first conductive material in sequence on the sidewalls of the second etched groove; and partially etching the first conductive material, the first insulating material, and the first semiconductor material in sequence to obtain a third etched groove; A first conductive layer in contact with the unetched first conductive material and isolated from the unetched first semiconductor material, a third insulating layer in contact with the first conductive layer, a second conductive layer in contact with the third insulating layer, and a second bit line (300) in contact with the second conductive layer and extending in a third direction are sequentially formed in the third etched groove, wherein the third direction is perpendicular to the first direction and the second direction; A first bit line (200) extending along the third direction is formed based on the etch stop layer.

18. The preparation method according to claim 16 or 17, wherein The second structure after forming the plurality of first bit lines (200) and the plurality of second bit lines (300) includes a first transistor preparation area; the forming of the plurality of first transistors (110) connected to the plurality of first bit lines (200) and the plurality of first word lines (400) connected to the plurality of first transistors (110) includes: Etching the filling material in the first transistor fabrication area along the second direction to form a second trench penetrating the second structure, etching the isolation layer in the first transistor fabrication area based on the second trench to form a third trench, the third trench being used to expose the first semiconductor material; and sequentially depositing a second insulating material and a second conductive material on sidewalls of the third trench; Etching the filling material in contact with the second insulating material along the second direction to form a fourth trench penetrating the second structure; sequentially etching the second insulating material and the second conductive material on sidewalls of the fourth trench, and depositing an isolation material in the etched trench to obtain a third structure; The first conductive material in the third structure is used to form the second gate (112) of the first transistor (110); the first semiconductor material in the third structure is used to form the first semiconductor layer (113) of the first transistor (110); the first semiconductor layer (113) is connected to the first bit line (200); the second conductive material in the third structure is used to form a first word line (400) connected to the first transistor (110) and extending along the second direction; the second conductive material in the third structure surrounding the first semiconductor layer (113) is used to form the first gate (111) of the first transistor (110).

19. The preparation method according to claim 18, wherein The third structure includes a second transistor preparation area; the forming of a plurality of second transistors (120) connected to the plurality of second bit lines (300) and a plurality of second word lines (500) connected to the plurality of second transistors (120) comprises: Etching the filling material in the second transistor fabrication area along the second direction to form a fifth trench penetrating the third structure, etching the isolation layer in the second transistor fabrication area based on the fifth trench to form a sixth trench, wherein the sixth trench is used to expose the third insulating layer; and sequentially depositing a second semiconductor material, a third insulating material, and a third conductive material on sidewalls of the sixth trench; The filling material in contact with the second semiconductor material is etched along the second direction to form a seventh trench penetrating the third structure; etching the isolation layer in contact with the second semiconductor material based on the seventh trench to form an eighth trench; sequentially etching the second semiconductor material, the third insulating material, and the third conductive material on the sidewalls of the eighth trench until the third conductive material on the sidewalls of the seventh trench is completely etched, and depositing the isolation material in the etched trench to obtain a fourth structure; The second semiconductor material in the fourth structure is used to form a second semiconductor layer (122) of the second transistor (120), and the second semiconductor layer (122) is connected to the second bit line (300); the third conductive material in the fourth structure is used to form a second word line (500) connected to the second transistor (120) and extending along the second direction, and the third conductive material in the fourth structure surrounding the second semiconductor layer (122) is used to form a third gate (121) of the second transistor (120).

20. The preparation method according to claim 18, wherein The memory further comprises a plurality of connection lines (600) perpendicular to the substrate, the third structure comprises a connection line preparation area, and the method further comprises: Etching the filling material in the connection line preparation area along the second direction to form a ninth trench penetrating the third structure, wherein the ninth trench is used to expose the first semiconductor material; Based on the ninth trench, a region to be filled is formed; a fourth conductive material is deposited in the region to be filled, and the fourth conductive material is used to form the connecting line (600).

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