Voltage control and regulation circuit for low-cost and fast response to voltage sag

Abstract

The present invention relates to the technical field of basic electronic circuits, and particularly solves the problems of excessive impact on system performance and poor flexibility of on-chip solutions for coping with voltage sags. Disclosed is a voltage control and regulation circuit for low-cost and fast response to a voltage sag. The circuit comprises: a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit, and a performance-aware voltage controller. The voltage is regulated in real time by means of a fully-closed-loop and double-loop architecture, thereby greatly reducing the performance cost during the regulation; the voltage loop controller and the current loop controller are jointly used, and different control parameters are used to respectively fit frequency regulation amounts corresponding to the voltage and the current, thereby implementing a flexible double-closed-loop control strategy; the clock gating circuit is used to process the frequency regulation amounts, and the working frequency of a controlled object can be quickly controlled by means of clock enabling; the performance-aware voltage controller and the clock gating circuit are jointly used, so as to achieve the objective of simply and efficiently countering voltage sags.

Description

Low-cost voltage control and regulation circuit with fast response to voltage drop Technical Field

[0001] The present invention belongs to the technical field of basic electronic circuits, and in particular relates to an on-chip voltage control and regulation circuit capable of quickly responding to a sudden voltage drop at a low cost. Background Art

[0002] The rapid development of integrated circuits has forced processors to handle increasingly complex and diverse tasks. Dramatic load fluctuations pose challenges to the stability of power supply networks. Load variations directly lead to variations in supply current, which in turn causes voltage sags. This means insufficient timing margins or even failure to meet minimum requirements, leading to calculation errors. Voltage sags can generally be divided into three stages. The first-order voltage sag is the most difficult to monitor. Its frequency and amplitude depend on package inductance and on-chip capacitance, with frequencies ranging from tens to hundreds of megahertz and amplitudes from tens to hundreds of millivolts. When a voltage sag occurs, various methods, such as low-dropout (LDO) and DC-DC converters, are needed to regulate the voltage back to avoid system errors.

[0003] Conventional voltage sag control and regulation systems often require multiple cycles to recover their frequency to avoid introducing new voltage sags. However, this entire process requires a recovery time of several microseconds, which severely impacts chip performance for loads experiencing frequent voltage sags. Designing different frequency recovery strategies based on the severity of voltage sags, however, incurs additional hardware costs due to such fine-grained division, increasing design complexity and reducing system flexibility. Therefore, a voltage control and regulation circuit with a low-cost, fast response to voltage sags is needed to rapidly address voltage sags while minimizing performance losses.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to address the shortcomings of the above-mentioned background technology and the main design challenges, and to provide a low-cost voltage control and regulation circuit that can quickly respond to voltage drops. The invention achieves the purpose of quickly responding to voltage drops according to the frequency adjustment amount corresponding to the voltage and current through a fully closed-loop, dual-loop circuit architecture, thereby solving the problem that the on-chip voltage drop response solution has too great an impact on system performance and poor flexibility.

[0006] The present invention adopts the following technical solutions to achieve the above-mentioned purpose:

[0007] A voltage control and regulation circuit with low cost and rapid response to voltage drops acts on a controlled object consisting of a chip circuit and an off-chip power supply chip that supplies power to the chip. The voltage control and regulation circuit includes: a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit, and a performance-aware voltage controller. The voltage monitoring unit is used to monitor and generate a voltage code value of the controlled object in the current clock cycle, with the output code value having a delay of 1-2 cycles. The current prediction unit is used to monitor the current code value of the current clock cycle and predict the current code value of the controlled object in the future clock cycles. The voltage loop controller is used to generate a frequency control variable controlled by the input voltage based on the voltage code value and the current code value of the current clock cycle. The current loop controller is used to generate a frequency control variable controlled by the input current based on the current code value in the future clock cycle. The clock gating circuit is used to receive the frequency control variable controlled by the input voltage and the frequency control variable controlled by the input current, and generate a clock enable signal and a global clock signal. The global clock signal is used to adaptively adjust the clock frequency of the chip circuit. The performance-aware voltage controller is used to receive the clock enable signal output by the clock gating circuit and generate a voltage regulation instruction for adaptively adjusting the output voltage of the off-chip power supply chip.

[0008] As a further optimization scheme for the voltage control and regulation circuit that can quickly respond to voltage drops at a low cost, the voltage loop controller processes the voltage code value and the current code value of the current clock cycle as follows to generate a frequency control amount controlled by the input voltage: the voltage code value of the current clock cycle is low-pass filtered to obtain the current voltage value, the current voltage value is subtracted from the static voltage value to obtain the delayed voltage drop S1, the current voltage drop F1 is predicted based on the delayed voltage drop S1 and the current code value of the current clock cycle, and the frequency control amount Vcf controlled by the voltage is calculated based on the delayed voltage drop S1, the current voltage drop F1, the target voltage drop T1, the proportional term coefficient a1 and the differential term coefficient b1 of the voltage loop controller, Vcf = (F1-T1)*a1+(F1-S1)*b1.

[0009] As a further optimization scheme for the voltage control and regulation circuit that can quickly respond to voltage drops at a low cost, the current loop controller processes the current code value of the future clock cycle as follows to generate a frequency control quantity controlled by the input current: the current code value of the current clock cycle is obtained based on the current code value of the future clock cycle, the current code value of the future clock cycle and the current code value of the current clock cycle are averaged and filtered to obtain the filtered predicted current value F2, the current code value of the current clock cycle is exponentially weighted and filtered to obtain the filtered current value S2, and the frequency control quantity Icf controlled by the current is calculated by combining the filtered predicted current value F2, the filtered current current value S2, the target current value T2, the proportional term coefficient a2 and the differential term coefficient b2 of the current loop controller, Icf = (F2-T2)*a2+(F2-S2)*b2.

[0010] As a further optimization solution for a voltage control and regulation circuit that quickly responds to voltage drops at a low cost, a clock gating circuit includes: an adder, a modulator, and a gated clock unit; one input end of the adder receives a frequency control amount controlled by the input voltage, the other input end of the adder receives a frequency control amount controlled by the input current, and the adder outputs a total frequency control amount; the input end of the modulator is connected to the output end of the adder, and the modulator outputs a clock enable signal; the input end of the gated clock unit is connected to the output end of the modulator, and the gated clock unit outputs a global clock signal.

[0011] As a further optimization solution for the voltage control and regulation circuit that can quickly respond to voltage drops at a low cost, the performance-aware voltage controller includes: a cycle timer, a clock gating monitor, and a voltage judgment logic; the cycle timer is used to periodically output a full count pulse according to the configuration parameters; the clock gating monitor receives the clock enable signal and the full count pulse, records the number of times the clock enable signal is invalid within a monitoring cycle, and periodically clears the count value of the number of times the clock enable signal is invalid under the action of the full count pulse; the voltage judgment logic receives the count value of the number of times the clock enable signal is invalid output by the clock gating monitor, compares the voltage rise threshold with the count value of the number of times the clock enable signal is invalid when the full count pulse is valid, and then outputs a voltage rise instruction; when the full count pulse is valid, compares the voltage callback threshold with the count value of the number of times the clock enable signal is invalid, and then outputs a voltage drop instruction.

[0012] As a further optimization solution for the voltage control and regulation circuit that can quickly respond to voltage drops at a low cost, the current prediction unit uses a machine learning algorithm to train and screen the flip weights of the system's key signals. It then multiplies and accumulates the flip monitoring results of the system's key signals to output the predicted current code value in the future clock cycle.

[0013] As a further optimization solution for the voltage control and regulation circuit that can quickly respond to voltage drops at a low cost, a 4th-order low-pass filter implemented by a four-stage pipeline is used to perform low-pass filtering on the voltage code value of the current clock cycle.

[0014] As a further optimization solution for the voltage control and regulation circuit that responds quickly to voltage drops at a low cost, the current code value of the current clock cycle is obtained based on the current code value of the future clock cycle through a first-level register.

[0015] As a further optimization solution for the voltage control and regulation circuit that can quickly respond to a voltage drop at a low cost, the modulator is a delta-sigma modulator.

[0016] The low-cost, fast-response voltage sag voltage control and regulation circuit proposed in the present invention has the following advantages over existing voltage sag control and regulation schemes:

[0017] (1) A fully closed-loop, dual-loop architecture is used to adjust voltage in real time. The voltage and current information are combined to achieve a predictive effect, which greatly reduces the performance cost during the adjustment period.

[0018] (2) The voltage loop controller and the current loop controller are used together, and different control parameters are used to fit the frequency adjustment amount corresponding to the voltage and current, realizing a flexible dual closed-loop control strategy.

[0019] (3) The frequency control that integrates the voltage monitoring quantity, current monitoring quantity and prediction quantity is processed through the clock gating circuit to obtain a global clock signal that can quickly control the controlled object. The performance-aware voltage controller and the clock gating circuit are used together to avoid frequent adjustments through gate counting, and the clock enable signal is converted into an adjustment of the voltage of the controlled object, thereby achieving the invention purpose of simply and efficiently combating voltage drops. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a block diagram of a low-cost, fast-response voltage sag controller and its regulating circuit according to the present invention.

[0021] FIG2 is a block diagram of the voltage loop controller of the present invention.

[0022] FIG3 is a block diagram of a low-pass filter in the voltage loop controller of the present invention.

[0023] FIG4 is a block diagram of the current loop controller of the present invention.

[0024] FIG5 is a block diagram of a clock gating circuit according to the present invention.

[0025] FIG6 is a block diagram of a performance-aware voltage controller according to the present invention.

[0026] FIG7 is a waveform diagram of various signals during the process of controlling and regulating voltage by the circuit proposed in the present invention. DETAILED DESCRIPTION

[0027] In order to better understand the purpose, structure and function of the present invention, the prediction circuit for zero-response period voltage sag monitoring of the present invention is further described in detail below with reference to the accompanying drawings.

[0028] As shown in Figure 1, the controller and regulation circuit for the controlled object, which provides a low-cost, fast response to voltage drops, includes a voltage monitoring unit, a current prediction unit, a voltage loop controller, a current loop controller, a clock gating circuit, and a performance-aware voltage controller. The overall circuit architecture is a fully closed-loop system. The controlled object, voltage monitoring unit, voltage loop controller, clock gating circuit, and performance-aware voltage controller form one loop, while the controlled object, current monitoring unit, current loop controller, clock gating circuit, and performance-aware voltage controller form another loop. The controlled object consists of the chip circuit and an off-chip power supply chip that provides it with power.

[0029] In this embodiment, a controlled object consisting of a SoC circuit and an off-chip power supply chip supplying power to the SoC is taken as an example to exemplify the voltage control and regulation circuit proposed in the present invention.

[0030] The voltage monitoring unit is used to monitor and generate the voltage code value of the current clock cycle of the controlled object, and the output code value has a delay of 1-2 cycles; the current prediction unit is used to monitor the current code value of the current clock cycle and predict the current code value of the controlled object in the future clock cycle; the voltage loop controller is used to generate a frequency control amount controlled by the input voltage based on the voltage code value of the current clock cycle and the current code value of the current clock cycle; the current loop controller is used to generate a frequency control amount controlled by the input current based on the current code value of the future clock cycle; the clock gating circuit is used to receive the frequency control amount controlled by the input voltage and the frequency control amount controlled by the input current and generate a fast-response clock enable signal and a global clock signal, and the global clock signal is used to adaptively adjust the clock frequency of the SoC circuit; the performance-aware voltage controller is used to receive the clock enable signal output by the clock gating circuit and generate a voltage adjustment instruction for adaptively adjusting the output voltage of the off-chip power chip.

[0031] The voltage monitoring unit is a circuit module that monitors the voltage of the object under test. The current prediction unit, trained using a machine learning algorithm to filter the flip weights of key system signals, multiplies and accumulates the flip monitoring results of key system signals and outputs a prediction of the current code value for the next clock cycle. This effectively predicts the current of the controlled object and also outputs the monitoring result of the current code value for the current cycle.

[0032] As shown in Figure 2, the voltage loop controller first sets the target voltage drop, proportional term coefficient, and differential term coefficient as needed, denoted as T1, a1, and b1 respectively. After receiving the voltage code value of the current clock cycle output by the voltage monitoring unit, it filters out high-frequency noise through a low-pass filter to ensure system stability and outputs the corresponding current voltage value. The actual delayed voltage drop S1 is obtained by subtracting the current voltage value from the static voltage value. The delayed voltage drop S1 passes through the voltage prediction unit to obtain the current voltage drop F1 without delay. The delayed voltage drop S1 is combined with the current voltage drop F1, the target voltage drop T1, the proportional term coefficient a1, and the differential term coefficient b1 to calculate the voltage-controlled frequency control variable Vcf.

[0033] The acquisition of the frequency control quantity controlled by voltage includes the following steps:

[0034] Step 101: Read the voltage code value of the current clock cycle output by the voltage monitoring unit. If the voltage code value of the current clock cycle output changes, go to step 102; otherwise, go to step 101.

[0035] Step 102: After the voltage code value of the current clock cycle output by the voltage monitoring unit passes through a low-pass filter, it is subtracted from the static voltage value to complete data preprocessing to obtain a delayed voltage drop. The delayed voltage drop data is recorded as S1. The so-called delayed voltage drop is the code value obtained after the current voltage drop code value passes through the register. Then, the process proceeds to step 103.

[0036] Step 103: The delayed voltage drop data S1 and the current code value of the current clock cycle are used by the voltage prediction unit to obtain the current voltage drop. The current voltage drop data is recorded as F1, and the process proceeds to step 104;

[0037] Step 104: Calculate the frequency control variable Vcf controlled by voltage = (F1-T1)*a1+(F1-S1)*b1.

[0038] As shown in Figure 3, the low-pass filter in the voltage loop controller uses a four-stage pipeline to implement a fourth-order low-pass filter. By adjusting the positions of the input, output, and filter coefficient weights, the critical path length is reduced to one level of multiplication and addition. By adjusting the filter coefficients, the filter timing converges to 2 GHz.

[0039] As shown in Figure 4, the current loop controller will first set the target current value, proportional term coefficient and differential term coefficient as needed, denoted as T2, a2, and b2 respectively. After receiving the current code value of the future clock cycle output by the current prediction unit, the current code value of the current clock cycle is obtained through the first-level register. The two are filtered out of high-frequency noise through an average filter to ensure system stability and output the corresponding filtered predicted current value F2. In addition, the current code value of the current clock cycle is passed through an exponential weighted filter to obtain the filtered current value S2. The filtered predicted current value F2 is combined with the filtered current current value S2 and the target current value T2, the proportional term coefficient a2 and the differential term coefficient b2 to obtain the frequency control amount Icf controlled by current through calculation.

[0040] The acquisition of the frequency control quantity controlled by current includes the following steps:

[0041] Step 201: Read the current code value of the future clock cycle output by the current prediction unit. If the current code value of the future clock cycle output changes, go to step 202; otherwise, go to step 201.

[0042] Step 202: Pass the current code value of the future clock cycle output by the current prediction unit through the first-level register to obtain the current code value of the current clock cycle, and then proceed to step 203;

[0043] Step 203: Apply an average filter to the current code value of the future clock cycle and the current code value of the current clock cycle to obtain a filtered predicted current value. The data of the filtered predicted current value is recorded as F2, and the process proceeds to step 204;

[0044] Step 204: The current code value of the current clock cycle is passed through an exponentially weighted average filter to obtain a filtered current current value. The filtered current current value data is recorded as S2, and the process proceeds to step 205;

[0045] Step 205: Calculate the frequency control variable Icf controlled by current = (F2-T2)*a2+(F2-S2)*b2.

[0046] As shown in Figure 5, the clock gating circuit combines the voltage-controlled frequency control variable and the current-controlled frequency control variable to generate a clock gating signal. When the frequency control variable is too large, the clock gating signal is disabled. To implement this clock gating circuit, the voltage-controlled frequency control variable and the current-controlled frequency control variable are added together to obtain a total frequency control variable. This total frequency control variable is passed through a delta-sigma modulator to generate a clock gating signal, also known as a clock enable signal. This gated clock signal is then output through a clock gating unit, serving as the global clock signal for the controlled object. The delta-sigma modulator includes a difference calculation step, an integration step, and a binarization step. The difference calculation step calculates the output error of the feedback signal. The integration step integrates the error, and then passes it through a binary quantizer to output a single-bit signal. Through continuous feedback adjustment, the error integral value is kept within a certain range, achieving the effect of the output signal tracking the input signal. This clock gating circuit can complete regulation within a single cycle, offering the advantage of fast response.

[0047] As shown in Figure 6, the performance-aware voltage controller receives the clock enable signal generated by the clock gating circuit, counts the clock gating ratio, and thus detects the performance degradation caused by gating adjustment. This information is then used to guide the off-chip power supply chip to adjust the supply voltage. First, the cycle timer periodically outputs a full count pulse according to the configuration parameters. Then, the clock gating monitor uses the full count pulse signal to periodically reset itself. During a monitoring cycle, it records the number of invalid clock enable signals from the clock gating circuit and outputs a cumulative value. Finally, when the full count pulse is valid, the voltage judgment logic compares the voltage rise threshold and voltage callback threshold with the cumulative number of invalid clock enable signal times, and outputs a voltage increase command and a voltage decrease command. The off-chip power supply chip adjusts the output voltage based on these two signals, thus achieving performance-aware voltage regulation.

[0048] As shown in Figure 7, current excitation begins at 10 ns, causing voltage changes. Because the current loop controller uses predicted dynamic current information, it can generate a current-controlled frequency control variable before the voltage drops. Subsequently, because the predicted dynamic current is always the amplitude of the step current, the current-controlled frequency control variable remains high. At 10 ns, the voltage loop controller senses that the voltage is rapidly dropping based on data from the voltage monitoring unit and outputs a large voltage-controlled frequency control variable. Subsequently, as the voltage stabilizes, the voltage-controlled frequency control variable gradually decreases. The clock gating circuit determines whether to perform clock gating based on the current-controlled frequency control variable and the voltage-controlled frequency control variable. At 10 ns, because both the voltage-controlled frequency control variable and the current-controlled frequency control variable are relatively large, the clock enable signal is pulled low. Subsequently, at 12 ns, the gated clock signal no longer outputs a rising edge, causing the dynamic current to return to zero. The clock enable signal is not reactivated until the voltage returns to a higher level. After multiple adjustments, the voltage gradually stabilizes, and the gated clock signal returns to its normal frequency.

[0049] It will be understood that the present invention is described by way of some embodiments, and that those skilled in the art may make various changes or equivalent substitutions to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A voltage control and regulation circuit that responds quickly to a sudden voltage drop at a low cost, acting on a controlled object consisting of a chip circuit and an off-chip power supply chip that supplies power to the chip, characterized in that: The voltage control and regulation circuit includes: The voltage monitoring unit is used to monitor and generate the voltage code value of the current clock cycle of the controlled object. The output code value has a delay of 1-2 cycles; A current prediction unit, used to monitor the current code value of the current clock cycle and predict the current code value of the controlled object in the future clock cycles; A voltage loop controller, configured to generate a frequency control variable controlled by an input voltage according to a voltage code value and a current code value of a current clock cycle; A current loop controller, configured to generate a frequency control variable controlled by an input current according to a current code value in a future clock cycle; a clock gating circuit, configured to receive a frequency control value controlled by an input voltage and a frequency control value controlled by an input current, and generate a clock enable signal and a global clock signal, wherein the global clock signal is used to adaptively adjust the clock frequency of the chip circuit; and The performance-aware voltage controller is used to receive a clock enable signal output by a clock gating circuit and generate a voltage regulation instruction for adaptively regulating the output voltage of an off-chip power supply chip.

2. The low-cost, fast-response voltage drop voltage control and regulation circuit according to claim 1, characterized in that: The voltage loop controller processes the voltage code value of the current clock cycle and the current code value of the current clock cycle as follows to generate a frequency control amount controlled by the input voltage: low-pass filtering is performed on the voltage code value of the current clock cycle to obtain the current voltage value, the current voltage value is subtracted from the static voltage value to obtain the delayed voltage drop S1, the current voltage drop F1 is predicted based on the delayed voltage drop S1 and the current code value of the current clock cycle, and the frequency control amount Vcf controlled by the voltage is calculated based on the delayed voltage drop S1, the current voltage drop F1, the target voltage drop T1, the proportional term coefficient a1 and the differential term coefficient b1 of the voltage loop controller, Vcf = (F1-T1)*a1+(F1-S1)*b1.

3. The low-cost, fast-response voltage drop voltage control and regulation circuit according to claim 1, characterized in that: The current loop controller processes the current code value of the future clock cycle as follows to generate a frequency control amount controlled by the input current: obtain the current code value of the current clock cycle based on the current code value of the future clock cycle, perform average filtering on the current code value of the future clock cycle and the current code value of the current clock cycle to obtain the filtered predicted current value F2, perform exponential weighted filtering on the current code value of the current clock cycle to obtain the filtered current value S2, and combine the filtered predicted current value F2, the filtered current current value S2, the target current value T2, the proportional term coefficient a2 and the differential term coefficient b2 of the current loop controller to calculate the frequency control amount Icf controlled by the current, Icf = (F2-T2)*a2+(F2-S2)*b2.

4. The low-cost, fast-response voltage drop voltage control and regulation circuit according to claim 1, characterized in that: The clock gating circuit comprises: an adder, one input terminal of which receives a frequency control variable controlled by an input voltage, another input terminal of which receives a frequency control variable controlled by an input current, and outputs a total frequency control variable; a modulator, whose input terminal is connected to the output terminal of the adder and outputs a clock enable signal; and The gated clock unit has an input end connected to the output end of the modulator and outputs a global clock signal.

5. The low-cost, fast-response voltage drop voltage control and regulation circuit according to claim 1, characterized in that: The performance-aware voltage controller comprises: A periodic timer is used to periodically output a full count pulse according to configuration parameters; a clock gating monitor that receives a clock enable signal and a count-up pulse, records the number of times the clock enable signal is invalid within a monitoring cycle, and periodically clears the count of the number of times the clock enable signal is invalid under the action of the count-up pulse; and The voltage judgment logic receives the count value of the number of invalid clock enable signals output by the clock gating monitor, compares the voltage rising threshold with the count value of the number of invalid clock enable signals when the full count pulse is valid, and outputs a voltage rising instruction; when the full count pulse is valid, compares the voltage callback threshold with the count value of the number of invalid clock enable signals and outputs a voltage falling instruction.

6. The voltage control and regulation circuit with low cost and fast response to voltage drop according to claim 1, characterized in that: The current prediction unit, after training and screening the flip weights of the system key signals through a machine learning algorithm, multiplies and accumulates the system key signal flip monitoring results and outputs the prediction results of the current code value in the future clock cycle.

7. The voltage control and regulation circuit with low cost and fast response to voltage drop according to claim 2, characterized in that: A 4th-order low-pass filter implemented by a four-stage pipeline is used to perform low-pass filtering on the voltage code value of the current clock cycle.

8. The voltage control and regulation circuit with low cost and fast response to voltage drop according to claim 3, characterized in that: The current code value of the current clock cycle is obtained according to the current code value of the future clock cycle through the first-level register.

9. The voltage control and regulation circuit with low cost and fast response to voltage drop according to claim 4, characterized in that: The modulator is a delta-sigma modulator.

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