Bias voltage enhancement circuit and radio frequency power amplifier

Abstract

The present invention is applicable to the technical field of wireless communications, and in particular relates to a bias voltage enhancement circuit and a radio frequency power amplifier. The bias voltage enhancement circuit comprises a signal input terminal, a current source generation circuit, an overcharge generation circuit, a linear voltage regulator circuit, and a signal output terminal electrically connected in sequence. The overcharge generation circuit comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, a second resistor, and a first capacitor. Compared with the prior art, the bias voltage enhancement circuit provided by the present invention generates a controllable voltage overcharge at the moment the bias voltage is established, so that the bias voltage of the radio frequency power amplifier is raised during this bias voltage establishment stage, thereby further improving the linearity of the radio frequency power amplifier during the turn-on phase and effectively enhancing the performance of the radio frequency power amplifier.

Description

Bias voltage enhancement circuit and radio frequency power amplifier Technical Field

[0001] The present invention is applicable to the field of wireless communication technology, and in particular relates to a bias voltage enhancement circuit and a radio frequency power amplifier. Background Art

[0002] In wireless RF communication systems, the RF power amplifier (RFPA) primarily amplifies RF signals with minimal distortion. Its linearity is affected by bias voltage. Existing methods use a linear regulator to generate a stable bias voltage. However, for time-division communication systems, linearity is often limited during the RF PA's startup phase, impacting its performance. To address this issue, a voltage boost overcharge is required during the bias voltage establishment phase to effectively improve the RF PA's linearity.

[0003] Therefore, a new bias voltage enhancement circuit and RF power amplifier are urgently needed to solve the above problems. Summary of the Invention

[0004] The present invention provides a bias voltage enhancement circuit and a radio frequency power amplifier, aiming to solve the problem of limited linearity of the bias voltage during the start-up phase of the radio frequency power amplifier.

[0005] In a first aspect, the present invention provides a bias voltage enhancement circuit comprising a signal input terminal, a current source generating circuit, an overcharge generating circuit, a linear voltage regulator circuit, and a signal output terminal electrically connected in sequence;

[0006] The signal input terminal is used to input voltage; the current source generating circuit is used to generate current; the overcharge generating circuit is used to generate overcharge voltage; the linear voltage regulator circuit is used to output a voltage stabilization signal; the signal output terminal is used to output a reference voltage;

[0007] The overcharge generating circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, a second resistor and a first capacitor;

[0008] The first end of the first capacitor is respectively connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor, and the gate of the fourth PMOS transistor. The second end of the first capacitor is respectively connected to the source of the first NMOS transistor and the source of the second NMOS transistor and is grounded. The gate of the first NMOS transistor is connected to an external logic control circuit. The drain of the second NMOS transistor is connected to the source of the third NMOS transistor. The gate of the second NMOS transistor serves as the first output end of the overcharge generating circuit. The gate of the third NMOS transistor serves as the second output end of the overcharge generating circuit. The drain of the third NMOS transistor is respectively connected to the first end of the first resistor and the second NMOS transistor. The gate of the first PMOS tube is connected to the gate of the overcharge generating circuit, the second end of the first resistor is connected to the drain of the fourth PMOS tube and the gate of the third NMOS tube respectively, the source of the fourth PMOS tube is connected to the first end of the second resistor, the second end of the second resistor is connected to the drain of the third PMOS tube, the gate of the third PMOS tube is connected to an external logic control circuit, the source of the third PMOS tube and the source of the second PMOS tube are connected to a power supply voltage, the drain of the second PMOS tube is connected to the source of the first PMOS tube, the gate of the first PMOS tube serves as the first input end of the overcharge generating circuit, and the gate of the second PMOS tube serves as the second input end of the overcharge generating circuit.

[0009] Preferably, the current source generating circuit includes a first filtering and voltage-stabilizing circuit, a first operational amplifier, a first Miller compensation circuit, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor; the first end of the first filtering and voltage-stabilizing circuit is connected to the signal input end as the input end of the current source generating circuit, the second end of the first filtering and voltage-stabilizing circuit is grounded, the third end of the first filtering and voltage-stabilizing circuit is connected to the negative input end of the first operational amplifier, the output end of the first operational amplifier is respectively connected to the first end of the first Miller compensation circuit and the gate of the sixth PMOS transistor, the positive input end of the first operational amplifier is respectively connected to the second end of the first Miller compensation circuit, the drain of the fifth PMOS transistor, and the first end of the third resistor, the second end of the third resistor is connected to the second end of the first capacitor, the source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, the gate of the fifth PMOS transistor is connected to the first input end of the overcharge generating circuit as the first output end of the current source generating circuit, the source of the sixth PMOS transistor is connected to the power supply voltage, and the gate of the sixth PMOS transistor is connected to the second output end of the current source generating circuit as the second input end of the overcharge generating circuit.

[0010] Preferably, the first filtering and voltage-stabilizing circuit includes a second capacitor and a fourth resistor, the first end of the fourth resistor serves as the first end of the first filtering and voltage-stabilizing circuit, the second end of the fourth resistor is connected to the first end of the second capacitor, the second end of the fourth resistor serves as the third end of the filtering and voltage-stabilizing circuit, and the second end of the second capacitor serves as the second end of the filtering and voltage-stabilizing circuit.

[0011] Preferably, the first Miller compensation circuit includes a third capacitor and a fifth resistor, the first end of the fifth resistor serves as the first end of the first Miller compensation circuit, the second end of the fifth resistor is connected to the first end of the third capacitor, and the second end of the third capacitor serves as the second end of the first Miller compensation circuit.

[0012] Preferably, the linear voltage regulator circuit includes a second filtering and voltage stabilizing circuit, a second operational amplifier, a second Miller compensation circuit, a fourth NMOS transistor, a fifth NMOS transistor, a seventh PMOS transistor, a sixth resistor and a seventh resistor, the first end of the second filtering and voltage stabilizing circuit is connected to the signal input end, the second end of the second filtering and voltage stabilizing circuit is grounded, the third end of the second filtering and voltage stabilizing circuit is connected to the negative input end of the second operational amplifier, the output end of the second operational amplifier is respectively connected to the first end of the second Miller compensation circuit and the gate of the seventh PMOS transistor, the first end of the sixth resistor is respectively connected to the second end of the second Miller compensation circuit and the drain of the seventh PMOS transistor, the positive input end of the second operational amplifier is respectively connected to the first end of the second Miller compensation circuit and the drain of the seventh PMOS transistor, The first and second NMOS transistors are connected to the drain of the fifth NMOS transistor, the second end of the sixth resistor, and the first end of the seventh resistor. The source of the seventh PMOS transistor is connected to the power supply. The drain of the seventh PMOS transistor is connected to the signal output terminal as the output terminal of the linear regulator circuit. The source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the second end of the seventh resistor and the source of the second NMOS transistor. The gate of the fourth NMOS transistor is connected to the first output terminal of the overcharge generating circuit as the first input terminal of the linear regulator circuit. The gate of the fifth NMOS transistor is connected to the second output terminal of the overcharge generating circuit as the second input terminal of the linear regulator circuit.

[0013] Preferably, the second filtering and voltage-stabilizing circuit includes an eighth resistor and a fourth capacitor, the first end of the eighth resistor serves as the first end of the second filtering and voltage-stabilizing circuit, the second end of the eighth resistor is connected to the first end of the fourth capacitor, the second end of the fourth capacitor serves as the second end of the second filtering and voltage-stabilizing circuit, and the second end of the eighth resistor serves as the third end of the second filtering and voltage-stabilizing circuit.

[0014] Preferably, the second Miller compensation circuit includes a ninth resistor and a fifth capacitor, the first end of the ninth resistor serves as the first end of the second Miller compensation circuit, the second end of the ninth resistor is connected to the first end of the fifth capacitor, and the second end of the fifth capacitor serves as the second end of the second Miller compensation.

[0015] In a second aspect, the present invention further provides a radio frequency power amplifier, comprising the bias voltage enhancement circuit as described in any one of the above embodiments.

[0016] Compared with the existing technology, the bias voltage enhancement circuit proposed in the present invention generates controllable voltage overcharge at the moment the bias voltage is established. At the moment the bias voltage is established, the bias voltage of the RF power amplifier is increased, and its linearity in the start-up phase is further improved, thereby effectively improving the performance of the RF power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings:

[0018] FIG1 is a schematic structural diagram of a bias voltage enhancement circuit provided in an embodiment of the present invention;

[0019] FIG2 is a schematic diagram of controllable voltage overcharging of a bias voltage enhancement circuit provided by an embodiment of the present invention.

[0020] In the figure, 100, bias voltage enhancement circuit, 1, signal input terminal, 2, current source generating circuit, 3, overcharge generating circuit, 4, linear regulator circuit, 5, signal output terminal. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0022] Example 1

[0023] 1-2 , the present invention provides a bias voltage enhancement circuit 100, which includes a signal input terminal 1, a current source generating circuit 2, an overcharge generating circuit 3, a linear regulator circuit 4, and a signal output terminal 5 electrically connected in sequence; wherein the signal input terminal 1 generates a VBG voltage which is input to the current source generating circuit 2, and the signal output terminal 5 outputs a reference voltage Vreg.

[0024] The signal input terminal 1 is used to input the voltage VBG; the current source 2 generating circuit is used to generate current; the overcharge generating circuit 3 is used to generate an overcharge voltage; the linear voltage regulator circuit 4 is used to output a voltage stabilization signal; the signal output terminal 5 is used to output a reference voltage Vreg;

[0025] The overcharge generating circuit 3 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a first resistor R1, a second resistor R2 and a first capacitor C1;

[0026] The first end of the first capacitor C1 is respectively connected to the drain of the first NMOS transistor MN1, the drain of the first PMOS transistor MP1, and the gate of the fourth PMOS transistor MP4. The second end of the first capacitor C1 is respectively connected to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 and is grounded. The gate of the first NMOS transistor MN1 is connected to the external logic control circuit ENB. The drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 serves as the first output end of the overcharge generating circuit 3. The gate of the third NMOS transistor MN3 serves as the second output end of the overcharge generating circuit 3. The drain of the third NMOS transistor MN3 is respectively connected to the first end of the first resistor R1 and the second NMOS transistor R2. The gate of the overcharge generating circuit 3 is connected to the gate of the overcharge generating circuit 3. The second end of the first resistor R1 is connected to the drain of the fourth PMOS transistor MP4 and the gate of the third NMOS transistor MN3 respectively. The source of the fourth PMOS transistor MP4 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the drain of the third PMOS transistor MP3. The gate of the third PMOS transistor MP3 is connected to the external logic control circuit ENB. The source of the third PMOS transistor MP3 and the source of the second PMOS transistor MP2 are connected to the power supply voltage VDD. The drain of the second PMOS transistor MP2 is connected to the source of the first PMOS transistor MP1. The gate of the first PMOS transistor MP1 serves as the first input terminal of the overcharge generating circuit 3, and the gate of the second PMOS transistor MP2 serves as the second input terminal of the overcharge generating circuit 3.

[0027] In this embodiment, the current source generating circuit 2 includes a first filtering and voltage stabilizing circuit 21, a first operational amplifier OP1, a first Miller compensation circuit 22, a third resistor R3, a fifth PMOS transistor MP5, and a sixth PMOS transistor MP6; the first end of the first filtering and voltage stabilizing circuit 21 is connected to the signal input terminal 1 as the input end of the current source generating circuit 2, the second end of the first filtering and voltage stabilizing circuit 21 is grounded, the third end of the first filtering and voltage stabilizing circuit 21 is connected to the negative input end of the first operational amplifier OP1, the output end of the first operational amplifier OP1 is respectively connected to the first end of the first Miller compensation circuit 22 and the gate of the sixth PMOS transistor MP6, and the first operational amplifier O The positive input terminal of P1 is respectively connected to the second terminal of the first Miller compensation circuit 22, the drain of the fifth PMOS transistor MP5, and the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the second terminal of the first capacitor C1. The source of the fifth PMOS transistor MP5 is connected to the drain of the sixth PMOS transistor MP6. The gate of the fifth PMOS transistor MP5 serves as the first output terminal of the current source generating circuit 2 and is connected to the first input terminal of the overcharge generating circuit 3. The source of the sixth PMOS transistor MP6 is connected to the power supply voltage VDD. The gate of the sixth PMOS transistor MP6 serves as the second output terminal of the current source generating circuit 2 and is connected to the second input terminal of the overcharge generating circuit 3.

[0028] In this embodiment, the first filtering and voltage-stabilizing circuit 21 includes a second capacitor C2 and a fourth resistor R4, the first end of the fourth resistor R4 serves as the first end of the first filtering and voltage-stabilizing circuit 21, the second end of the fourth resistor R4 is connected to the first end of the second capacitor C2, the second end of the fourth resistor R4 serves as the third end of the filtering and voltage-stabilizing circuit 21, and the second end of the second capacitor C2 serves as the second end of the filtering and voltage-stabilizing circuit 21.

[0029] In this embodiment, the first Miller compensation circuit 22 includes a third capacitor C3 and a fifth resistor R5. The first end of the fifth resistor R5 serves as the first end of the first Miller compensation circuit 22. The second end of the fifth resistor R5 is connected to the first end of the third capacitor C3. The second end of the third capacitor C3 serves as the second end of the first Miller compensation circuit 22.

[0030] In this embodiment, the linear voltage regulator circuit 4 includes a second filtering and voltage stabilizing circuit 41, a second operational amplifier OP2, a second Miller compensation circuit 42, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a seventh PMOS transistor MP7, a sixth resistor R6, and a seventh resistor R7. The first end of the second filtering and voltage stabilizing circuit 41 is connected to the signal input end 1, the second end of the second filtering and voltage stabilizing circuit 41 is grounded, the third end of the second filtering and voltage stabilizing circuit 41 is connected to the negative input end of the second operational amplifier OP2, the output end of the second operational amplifier OP2 is respectively connected to the first end of the second Miller compensation circuit 42 and the gate of the seventh PMOS transistor MP7, the first end of the sixth resistor R6 is respectively connected to the second end of the second Miller compensation circuit 42 and the drain of the seventh PMOS transistor MP7, and the output end of the second operational amplifier OP2 is respectively connected to the first end of the second Miller compensation circuit 42 and the drain of the seventh PMOS transistor MP7. The positive input terminal is respectively connected to the drain of the fifth NMOS transistor MN5, the second end of the sixth resistor R6, and the first end of the seventh resistor R7. The source of the seventh PMOS transistor MP7 is connected to the power supply VDD. The drain of the seventh PMOS transistor MP7 is connected to the signal output terminal 1 as the output terminal of the linear regulator circuit 4. The source of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4. The source of the fourth NMOS transistor MN4 is connected to the second end of the seventh resistor R7 and the source of the second NMOS transistor MN2. The gate of the fourth NMOS transistor MN4 is connected to the first output terminal of the overcharge generating circuit 3 as the first input terminal of the linear regulator circuit 4. The gate of the fifth NMOS transistor MN5 is connected to the second output terminal of the overcharge generating circuit 3 as the second input terminal of the linear regulator circuit 4.

[0031] In this embodiment, the second filtering and voltage-stabilizing circuit 41 includes an eighth resistor R8 and a fourth capacitor C4, the first end of the eighth resistor R8 serves as the first end of the second filtering and voltage-stabilizing circuit 41, the second end of the eighth resistor R8 is connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 serves as the second end of the second filtering and voltage-stabilizing circuit 41, and the second end of the eighth resistor R8 serves as the third end of the second filtering and voltage-stabilizing circuit 41.

[0032] In this embodiment, the second Miller compensation circuit 42 includes a ninth resistor R9 and a fifth capacitor C5. The first end of the ninth resistor R9 serves as the first end of the second Miller compensation circuit 42. The second end of the ninth resistor R9 is connected to the first end of the fifth capacitor C5. The second end of the fifth capacitor C5 serves as the second end of the second Miller compensation circuit 42.

[0033] As shown in Figure 2, Figure A shows the waveform of the bias voltage Vreg at the moment the bias voltage Vreg is established and no voltage overcharge occurs; Figure B shows the waveform of the bias voltage Vreg at the moment the bias voltage Vreg is established and a voltage overcharge occurs. The bias voltage boost circuit proposed in this invention generates a voltage overcharge of ΔV with a controllable duration ΔT at the moment the bias voltage Vreg is established. During this stage, the bias voltage of the RF power amplifier is increased, further improving its linearity during the turn-on phase.

[0034] Specifically, the current source generating circuit 2 includes a first operational amplifier OP1 and a PMOS current mirror circuit consisting of a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6. These circuits form negative feedback, generating a fixed current source across resistor R3 via the VBG voltage inputted at signal input terminal 1. A fourth resistor R4 and a second capacitor C2 form a low-pass circuit for filtering and voltage stabilization. A fifth resistor R5 and a third capacitor C3 provide Miller compensation to ensure feedback loop stability. The fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 form a cascode configuration to reduce channel modulation effects and improve current accuracy. In the overcharge generating circuit 3, the first and second PMOS transistors MP1 and MP2 mirror the current and transfer it to the first capacitor C1. The first NMOS transistor MN1 and the third PMOS transistor MP3 act as switches, commencing operation when the external logic control circuit ENB switches from high to low. During the initial enable phase, the voltage at the first terminal of the first capacitor C1 begins to rise from 0V, is charged by the current source, and ultimately reaches the power supply voltage VDD. The capacitor charging time is linearly related to the current source current, which is the time ΔT required to generate the overcharge voltage. During this phase, the fourth PMOS transistor MP4 switches from on to off, and the output current of the fourth PMOS transistor MP4 decreases from high to low, ultimately reaching zero. The second resistor R2 regulates the current. The second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 form an NMOS current mirror circuit, with the first resistor R1 acting as a bias. The fifth NMOS transistor MN5 and the fourth NMOS transistor MN4 inject a controlled current into the feedback node of the linear regulator circuit 4, thereby generating a controllable overcharge voltage. In linear regulator circuit 4, eighth resistor R8 and fourth capacitor C4 provide low-pass filtering. Second operational amplifier OP2, seventh PMOS transistor MP7, sixth resistor R6, and seventh resistor R7 form a linear voltage regulator circuit with a negative feedback loop. Ninth resistor R9 and fifth capacitor C5 provide Miller compensation to ensure loop stability. This ultimately generates a reference voltage Vreg, whose overcharge amplitude and duration are controllable.

[0035] Compared with the existing technology, the bias voltage enhancement circuit proposed in the present invention generates controllable voltage overcharge at the moment the bias voltage is established. At the moment the bias voltage is established, the bias voltage of the RF power amplifier is increased, and its linearity in the start-up phase is further improved, thereby effectively improving the performance of the RF power amplifier.

[0036] Example 2

[0037] An embodiment of the present invention further provides a radio frequency power amplifier, which includes the bias voltage enhancement circuit 100 as described in the above embodiment and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0038] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0039] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A bias voltage boost circuit, characterized in that: The bias voltage enhancement circuit includes a signal input terminal, a current source generating circuit, an overcharge generating circuit, a linear voltage regulator circuit and a signal output terminal which are electrically connected in sequence; The signal input terminal is used to input voltage; the current source generating circuit is used to generate current; the overcharge generating circuit is used to generate overcharge voltage; the linear voltage regulator circuit is used to output a voltage stabilization signal; the signal output terminal is used to output a reference voltage; Wherein, the overcharge generating circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first resistor, a second resistor and a first capacitor; A first end of the first capacitor is connected to the drain of the first NMOS transistor, the drain of the first PMOS transistor, and the gate of the fourth PMOS transistor, respectively; a second end of the first capacitor is connected to the source of the first NMOS transistor and the source of the second NMOS transistor, respectively, and is grounded; and the gate of the first NMOS transistor is connected to an external logic control circuit; The drain of the second NMOS transistor is connected to the source of the third NMOS transistor, and the gate of the second NMOS transistor serves as the first output terminal of the overcharge generating circuit and is connected to the first input terminal of the linear regulator circuit; The gate of the third NMOS transistor serves as the second output terminal of the overcharge generating circuit and is connected to the second input terminal of the linear regulator circuit. The drain of the third NMOS transistor is respectively connected to the first end of the first resistor and the gate of the second NMOS transistor. The second end of the first resistor is respectively connected to the drain of the fourth PMOS transistor and the gate of the third NMOS transistor. The source of the fourth PMOS transistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the drain of the third PMOS transistor, the gate of the third PMOS transistor is connected to an external logic control circuit, and the source of the third PMOS transistor and the source of the second PMOS transistor are respectively connected to a power supply voltage; The drain of the second PMOS transistor is connected to the source of the first PMOS transistor, and the gate of the first PMOS transistor serves as the first input end of the overcharge generating circuit and is connected to the first output end of the current source generating circuit; the gate of the second PMOS transistor serves as the second input end of the overcharge generating circuit and is connected to the second output end of the current source generating circuit.

2. The bias voltage boost circuit according to claim 1, wherein: The current source generating circuit includes a first filtering and voltage-stabilizing circuit, a first operational amplifier, a first Miller compensation circuit, a third resistor, a fifth PMOS transistor, and a sixth PMOS transistor. The first end of the first filtering and voltage-stabilizing circuit is connected to the signal input end as the input end of the current source generating circuit, the second end of the first filtering and voltage-stabilizing circuit is grounded, and the third end of the first filtering and voltage-stabilizing circuit is connected to the negative input end of the first operational amplifier. The output end of the first operational amplifier is respectively connected to the first end of the first Miller compensation circuit and the gate of the sixth PMOS transistor, the positive input end of the first operational amplifier is respectively connected to the second end of the first Miller compensation circuit, the drain of the fifth PMOS transistor, and the first end of the third resistor, and the second end of the third resistor is connected to the second end of the first capacitor. The source of the fifth PMOS transistor is connected to the drain of the sixth PMOS transistor, the gate of the fifth PMOS transistor serves as the first output end of the current source generating circuit, the source of the sixth PMOS transistor is connected to the power supply voltage, and the gate of the sixth PMOS transistor serves as the second output end of the current source generating circuit.

3. The bias voltage boost circuit according to claim 2, wherein: The first filtering and voltage-stabilizing circuit includes a second capacitor and a fourth resistor, the first end of the fourth resistor serves as the first end of the first filtering and voltage-stabilizing circuit, the second end of the fourth resistor is connected to the first end of the second capacitor, the second end of the fourth resistor serves as the third end of the filtering and voltage-stabilizing circuit, and the second end of the second capacitor serves as the second end of the filtering and voltage-stabilizing circuit.

4. The bias voltage boost circuit according to claim 2, wherein: The first Miller compensation circuit includes a third capacitor and a fifth resistor, the first end of the fifth resistor serves as the first end of the first Miller compensation circuit, the second end of the fifth resistor is connected to the first end of the third capacitor, and the second end of the third capacitor serves as the second end of the first Miller compensation circuit.

5. The bias voltage boost circuit according to claim 1, wherein: The linear voltage regulator circuit includes a second filtering and voltage stabilizing circuit, a second operational amplifier, a second Miller compensation circuit, a fourth NMOS transistor, a fifth NMOS transistor, a seventh PMOS transistor, a sixth resistor and a seventh resistor; a first end of the second filtering and voltage stabilizing circuit is connected to the signal input end, a second end of the second filtering and voltage stabilizing circuit is grounded, and a third end of the second filtering and voltage stabilizing circuit is connected to the negative input end of the second operational amplifier; an output end of the second operational amplifier is respectively connected to the first end of the second Miller compensation circuit and the gate of the seventh PMOS transistor, a first end of the sixth resistor is respectively connected to the second end of the second Miller compensation circuit and the drain of the seventh PMOS transistor, The positive input terminal of the second operational amplifier is respectively connected to the drain of the fifth NMOS transistor, the second end of the sixth resistor, and the first end of the seventh resistor; the source of the seventh PMOS transistor is connected to the power supply, and the drain of the seventh PMOS transistor is connected to the signal output terminal as the output terminal of the linear regulator circuit; the source of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the second end of the seventh resistor and the source of the second NMOS transistor, the gate of the fourth NMOS transistor serves as the first input terminal of the linear regulator circuit, and the gate of the fifth NMOS transistor serves as the second input terminal of the linear regulator circuit.

6. The bias voltage boost circuit according to claim 5, wherein: The second filtering and voltage-stabilizing circuit includes an eighth resistor and a fourth capacitor, the first end of the eighth resistor serves as the first end of the second filtering and voltage-stabilizing circuit, the second end of the eighth resistor is connected to the first end of the fourth capacitor, the second end of the fourth capacitor serves as the second end of the second filtering and voltage-stabilizing circuit, and the second end of the eighth resistor serves as the third end of the second filtering and voltage-stabilizing circuit.

7. The bias voltage boost circuit according to claim 5, wherein: The second Miller compensation circuit includes a ninth resistor and a fifth capacitor, wherein the first end of the ninth resistor serves as the first end of the second Miller compensation circuit, the second end of the ninth resistor is connected to the first end of the fifth capacitor, and the second end of the fifth capacitor serves as the second end of the second Miller compensation circuit.

8. A radio frequency power amplifier, characterized in that: The radio frequency power amplifier includes the bias voltage boost circuit according to any one of claims 1 to 7.

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