Method for producing a bonded wafer

Abstract

The invention relates to a method for producing a bonded wafer (100), the method comprising: providing a first MEMS wafer (110), the first MEMS wafer (110) having a first functional layer (112) with first MEMS structures (112'); independently providing a TSV wafer (120) with through-silicon vias (150); and bonding a first side (110a) of the first MEMS wafer (110) to a first side (120a) of the TSV wafer (120) in such a way that a bonded wafer (100) is obtained.

Description

[0001] Description

[0002] title

[0003] Method for producing a coupled wafer

[0004] Technical area

[0005] The present invention relates to the field of wafer processing and relates to a method for producing a coupled wafer, a coupled wafer, a method for producing MEMS chips and a MEMS chip.

[0006] State of the art

[0007] Devices with microelectromechanical systems (MEMS), such as micromirror arrays or micromirror actuators, are used today in a wide variety of devices, for example, in smartphones, projectors, head-up displays, barcode readers, mask exposure units in semiconductor manufacturing, and microscopes. Corresponding micromirror arrays are known, for example, from the documents DE 10 2013 208 446 A1, EP 0 877 272 A1, and WO 2010 / 049076 A2. DE 10 2006 032 195 A1 describes a method for producing microelectromechanical structures (MEMS structures). DE 10 2009 029 202 A1 discloses a micromechanical system and a method for producing a micromechanical system.DE 10 2015 206 996 A1 describes the so-called EPyC process (EPyC: epitaxial polysilicon cycle) for the production of microelectromechanical structures with large vertical dimensions. This process uses epitaxial polysilicon as a functional and sacrificial material and builds a layer structure of epitaxial polysilicon layers (EpiPoly layers) using repeated cycles. Particularly for components constructed from a large number of MEMS components arranged in an array, such as micromirror arrays, the challenge often lies in achieving a high yield of functional MEMS components.

[0008] Disclosure of the invention

[0009] According to the invention, a method for producing a coupled wafer, a coupled wafer, a method for producing MEMS chips and a MEMS chip are proposed.

[0010] According to a first aspect of the invention, a method for producing a coupled wafer is proposed. For this purpose, a first MEMS wafer is provided, wherein the first MEMS wafer has a first functional layer with first MEMS structures, for example for actuators and / or sensors, and a first handle wafer. Such a handle wafer can be an SOI handle wafer / start wafer (SOI: silicon-on-insulator). Independently thereof, a TSV wafer with silicon vias (hereinafter also referred to as Si vias or TSVs for short) is provided, and then a first side of the first MEMS wafer is connected to a first side of the TSV wafer such that a coupled wafer is obtained.

[0011] Preferably, the method further comprises providing a second MEMS wafer, for example in the form of an SOI wafer and / or with structures for mirror plates, wherein the second MEMS wafer has a second functional layer with second MEMS structures and a second handle wafer and preferably a silicon dioxide layer arranged between the handle wafer and the functional layer, and connecting a second side of the first MEMS wafer, which is different from the first side, to a side of the second MEMS wafer, preferably via electrically conductive bond connections.

[0012] The first structures and / or the second MEMS structures can comprise or be structures for one or more MEMS components to be manufactured, such as MEMS sensors and / or MEMS actuators. In particular, the first and / or the second MEMS structures can be arranged such that the MEMS components to be manufactured have an array-shaped and in particular rectangular or square arrangement, for example a 2x2, 3x2, 3x3, 3x4 or 4x4 arrangement. The MEMS components can be, for example, MEMS inertial sensors, MEMS pressure sensors, MEMS microphones, MEMS micromirrors and / or MEMS resonators. For example, the first MEMS structures comprise structures for actuators and / or sensors and the second MEMS structures comprise structures for mirror plates.

[0013] The functional layers and the handle wafers of the first and / or second MEMS wafer consist of or comprise silicon. Metals and / or semiconductor oxides can also be contained in the first and / or second functional layer. For example, the first and / or second functional layer can comprise sacrificial regions made of a semiconductor such as silicon and / or a semiconductor oxide such as silicon dioxide. In addition to purely mechanical structures, the first and / or second MEMS structures can comprise, for example, structures for actuators, sensors, mirror surfaces, one or more electronic circuits, integrated circuits (ICs), electrodes and / or vias such as through-silicon vias (TSVs).

[0014] The TSV wafer can be prepared by first providing a silicon wafer, for example with a thickness of up to 100 pm, up to 200 pm, up to 300 pm, up to 400 pm, up to 500 pm, or more than 500 pm. This thickness of the silicon wafer is selected according to the desired thickness of the TSV wafer. The silicon wafer is then oxidized, for example by thermal oxidation and / or LPCVD (low-pressure chemical vapor deposition), to form a silicon dioxide layer on a surface of the silicon wafer. Oxidation is understood here and below to mean both the induced oxidation of parts of the wafer, for example by thermal oxidation, and the application of an oxide layer from the outside, for example by LPCVD. The surface of the wafer opposite this surface is referred to as the back of the wafer.An etching mask is subsequently created by structuring the silicon oxide layer. Penetrating holes for the silicon vias are then created in the silicon wafer using the etching mask, for example, using the Bosch process. These holes extend to a silicon dioxide layer on the underside, i.e., on the back of the wafer, which acts as an etch stop layer. At least partial removal of the silicon dioxide layer on the back of the wafer, which acts as an etch stop layer, for example, using HF gas-phase etching, plasma etching, and / or wet-chemical etching, exposes the holes. Furthermore, to prepare the TSV wafer, the preferably already exposed holes are oxidized, for example, using thermal oxidation and / or LPCVD.Oxidation creates a passivation layer in the holes, typically in such a way that all open silicon surfaces in and preferably also outside the holes are passivated.

[0015] As an alternative to such a procedure, the TSV wafer can also be prepared by providing a silicon wafer, preferably with a thickness of up to 1000 μm, particularly preferably up to 800 μm, and most particularly preferably up to 725 μm, followed by applying an etching mask, such as a photoresist layer and / or an oxide hard mask, to a surface of the silicon wafer. An oxide hard mask is a variant of an etching mask for structuring trenches and / or holes. It can, for example, consist of a metal or comprise a metal. This step is followed by structuring the etching mask and then etching holes into the silicon wafer using the etching mask structured in this way. These holes are preferably formed as blind holes; consequently, they do not have to penetrate the wafer after this step.Finally, the silicon wafer is thinned back, for example, by back-grinding, such that the holes completely penetrate the silicon wafer. This opens the blind holes. Through this thinning, for example, by grinding, the target thickness of the TSV can be adjusted, for example, to between 50 pm and 700 pm. Finally, the holes are oxidized, for example, by thermal oxidation and / or LPCVD (low-pressure chemical vapor deposition), preferably in such a way that all exposed silicon surfaces are passivated. Cleaning of the TSV wafer can be performed prior to this step.

[0016] In both variants, any required alignment marks can be etched into the raw silicon before the holes are created. In subsequent steps, the alignment marks are protected by the passivation oxide. Alignment marks can be used to bond MEMS wafers and TSV wafers so that structures (e.g., contact areas) are aligned to each other. The alignment marks are used for aligned wafer-to-wafer bonding.

[0017] The method according to the invention preferably comprises, as further steps, an at least partial, preferably complete removal of the first handle wafer and thereby exposing a surface of the first functional layer and an addition of further first MEMS structures by growing one or more further layers with the further first MEMS structures on the exposed surface.

[0018] Furthermore, the first side of the first MEMS wafer is preferably connected to the first side of the TSV wafer before the second side of the first MEMS wafer is connected to the side of the second MEMS wafer.

[0019] Preferably, providing the first MEMS wafer and the TSV wafer comprises producing the first MEMS wafer and the TSV wafer, wherein the production of the first MEMS wafer and the TSV wafer occurs at an overlapping time.

[0020] Furthermore, by connecting the first side of the first MEMS wafer to the first side of the TSV wafer, one or more connection points, in particular bond connections, are formed which are suitable for forwarding electrical signals between a rewiring level of the MEMS wafer and at least some of the silicon vias of the TSV wafer.

[0021] According to a second aspect of the invention, a coupled wafer is proposed, preferably manufactured according to one of the methods described above, comprising a first MEMS wafer, wherein the first MEMS wafer has a first functional layer with first MEMS structures and a first handle wafer, which can be an SOI handle wafer / start wafer. Furthermore, the coupled wafer comprises a TSV wafer with silicon vias, wherein a first side of the first MEMS wafer is connected to a first side of the TSV wafer. According to a third aspect of the invention, a method for manufacturing MEMS chips with one or more MEMS components is proposed.This comprises producing a coupled wafer comprising a coupled wafer according to the invention as just described, as well as singulating the coupled wafer into a plurality of MEMS chips, such as micromirror chips and / or MMA chips, wherein each MEMS chip can comprise multiple MEMS components. Preferably, the coupled wafer is produced by providing a second MEMS wafer as described above, wherein the coupled wafer further comprises the second MEMS wafer.

[0022] After the coupled wafer has been manufactured and before the coupled wafer has been singulated, the first MEMS structures and / or the second MEMS structures can be exposed.

[0023] According to a fourth aspect of the invention, a MEMS chip produced by one of the inventive methods for producing MEMS chips is proposed.

[0024] Advantages of the invention

[0025] The invention describes an approach for providing a TSV wafer in parallel with a MEMS wafer during MEMS chip manufacturing processes, and using this TSV wafer for rewiring as a handle wafer and for further processing. The TSV wafer replaces the traditional layer growth process for creating a base plate. This allows for parallelization of processes, as traditional layer growth is avoided. Consequently, the throughput time is shortened, while simultaneously increasing the stability of the MEMS chips. Overall, this also results in higher yields and high-temperature compatibility, as well as increased flexibility.

[0026] A conventional base plate for MEMS chips typically performs the functions of rewiring, stabilization, and signal routing. The construction of such a base plate from individual layers is very time-consuming. According to the invention, the base plate is implemented as a TSV wafer. With such an inventive use of a TSV wafer, a comparatively thin EPyC layer, for example, can be provided for rewiring. This enables a short overall process time. The thickness of the TSV wafer can be adjusted by back-thinning, for example by grinding, to any thickness between 50 pm and 700 pm or more.

[0027] Short description of the drawings

[0028] Embodiments of the invention are explained in more detail with reference to the drawings and the following description.

[0029] They show:

[0030] Figures 1 A to 1 E are schematic cross-sectional views illustrating a method according to the invention for producing a coupled wafer;

[0031] Figures 2A, 2B are schematic cross-sectional views illustrating a method according to the invention for providing a TSV wafer;

[0032] Figures 3A, 3B are schematic cross-sectional views illustrating details of a method according to the invention for producing MEMS modules;

[0033] Figure 4 shows schematic cross-sectional views to explain details of a method according to the invention for providing a TSV wafer;

[0034] Figure 5 shows a schematic plan view of a coupled wafer according to the invention as well as various TSV cross-sectional areas in a likewise schematic representation; and

[0035] Figure 6 shows in schematic form as a flow chart an exemplary method according to the invention for producing a coupled wafer and MEMS chips therefrom.

[0036] Embodiments of the Invention In the following description of the embodiments of the invention, identical or similar elements are designated by the same reference numerals, whereby a repeated description of these elements is omitted in individual cases. The figures only schematically illustrate the subject matter of the invention.

[0037] Figures 1 A to 1 E show schematic cross-sectional views to explain a method according to the invention for producing a coupled wafer.

[0038] Figure 1A shows a section of a first MEMS wafer 110, wherein the first MEMS wafer 110 has a first functional layer 112 with first MEMS structures 112' and a first handle wafer 114. In this and the following figures, MEMS structures are schematically indicated by horizontal and vertical lines 113, which symbolize, for example, passivation layers.

[0039] This first MEMS wafer 110 is now connected in Figure 1B to a TSV wafer 120 with Si vias 150, which are coated, for example, with doped polysilicon, copper, tungsten, and / or metal silicides, which can be applied, for example, using LPCVD (LPCVD: Low Pressure Chemical Vapor Deposition). More specifically, a first side of the first MEMS wafer (110) is connected to a first side 120a of the TSV wafer 120 in such a way that a coupled wafer 100 is obtained. A material layer, for example, a polysilicon layer 124, was created on the TSV wafer 120 by the LPCVD deposition. In the case of LPCVD polysilicon, this can be doped in-situ with both boron and phosphorus.

[0040] Figure 1C shows the situation after a subsequent complete removal of the first handle wafer 114 and thereby exposing a surface 112a of the first functional layer 112. Further first MEMS structures 116' were added to the coupled wafer 100 by growing one or more further layers 116 with the further first MEMS structures 116' on the exposed surface 112a.

[0041] Now, after providing a second MEMS wafer 130, wherein the second MEMS wafer 130 has a second functional layer 132 with second MEMS structures 132' and a second handle wafer 134, it can be connected to the coupled wafer 100, wherein a second side 110b of the first MEMS wafer 110, different from the first side 110a, is connected to a side 130b of the second MEMS wafer 130 via bond connections 180. The result is shown in Figure 1D.

[0042] Finally, as shown in Figure 1 E, by selectively removing the polysilicon layer 124 and performing metallization, metal contacts 190 can be produced which are in electrical contact with the Si vias 150.

[0043] Figures 2A, 2B now show a schematic cross-sectional representation to explain a method according to the invention for providing a TSV wafer 120 in two variants, wherein the sequence of steps is illustrated by means of arrows 280.

[0044] According to the first variant according to Figure 2A, as shown in sub-figure (i), a silicon wafer 210 is provided with a thickness 211 selected according to the desired target thickness of the TSV wafer 120. For example, this thickness 211 can be up to 100 pm, up to 200 pm, up to 300 pm, up to 400 pm, up to 500 pm, or more than 500 pm. After, for example, thermal oxidation of the silicon wafer 210 to form a silicon dioxide layer 220 on a surface of the silicon wafer 210 (sub-figure (iii)), an etching mask 220' is created by structuring the silicon oxide layer 220 on the upper portion of the silicon dioxide layer 220.

[0045] Using the etching mask 220', holes 250 penetrating the silicon wafer 210 for the silicon vias 150 can be created, as shown in sub-figure (iii). The underlying portion of the silicon dioxide layer 220 serves as an etch stop layer. This portion is then removed in sub-figure (iv) in the region of the holes 250, thereby exposing these holes 250. They now penetrate the silicon wafer 210 across its entire thickness 211. Finally, the holes 250 are thermally oxidized, for example, to create a passivation layer 122 in the holes 250. The result, the finished TSV wafer 120, is shown in sub-figure (v). Figure 2B shows an alternative to the method from Figure 2A. In this case, a silicon wafer 210 (partial figure (i)) is again provided, this time for example with a thickness 211 of up to 1000 pm, preferably up to 800 pm, particularly preferably up to 725 pm.An etching mask 220', such as an oxide hard mask 221, is then applied to the upper surface of the silicon wafer 210 in sub-figure (ii) and then patterned. Next, as shown in sub-figure (iii), holes 250 are etched into the silicon wafer 210 using the patterned etching mask 220'. In contrast to the holes 250 in Figure 2A, these holes 250 are formed as blind holes; they do not penetrate the silicon wafer 210.

[0046] Subsequently, as shown in sub-figure (iv), the silicon wafer 210 can be thinned, for example, by back-grinding. This is done in such a way that the holes 250 completely penetrate the silicon wafer 210. Thus, blind holes are opened. This back-thinning sets the target thickness of the TSV wafer 120 to be produced. Finally, oxidation takes place, for example, thermal oxidation of the thinned silicon wafer 210 or through the use of LPCVD, to passivate all exposed silicon surfaces. The result of this step is shown in sub-figure (v) and represents the finished TSV wafer 120. The oxidation process creates passivation layers 122 on the walls of the holes 250. All remaining open surfaces of the silicon wafer 210 were also passivated by oxidation in this step, as illustrated in sub-figure (v) by further passivation layers 222 drawn in.Before oxidation, the silicon wafer 210 is preferably cleaned.

[0047] Figures 3A and 3B now show schematic cross-sectional views illustrating details of a method according to the invention for manufacturing MEMS assemblies. The chronological sequence of the method steps is indicated by arrows 280, as already shown in Figures 2A and 2B.

[0048] More specifically, Figures 3A and 3B show details of the step of connecting a TSV wafer 120 to a MEMS wafer 110, such as an actuator wafer, showing options for designing a rewiring level 300 and for filling the holes 250. Here, sub-figures (i) to (iv) of Figure 3A and sub-figures (i) to (v) of Figure 3B each show enlarged views of a coupled wafer 100 shown in the top left of Figures 3A, 3B, wherein in this overall view the elements and structures shown are shown in a further simplified manner compared to the sub-figures. For example, the signal lines 330 of the MEMS wafer 110 have been omitted. Roughly speaking, the situation shown in the overall view most closely corresponds to sub-figures (ii).

[0049] Typically, the first MEMS wafer 110 requires only a thin redistribution layer 300. A cover oxide 320 of the redistribution layer 300 of the MEMS wafer 110 on the side of the redistribution layer 300 facing the TSV wafer 120 is polished and structured such that the signal lines 330 are aligned with the holes 250 of the TSV wafer 120. This situation is shown in sub-figure (i), where, in addition to the cover oxide 320, other possible passivation layers 340, 350 of the MEMS wafer 110 are also shown. Subsequently, the wafers 110, 120 are bonded, for example, by hydrophilic SiCh-SiCh bonding. The signal lines 330 of the MEMS wafer 110 are free of oxides and are open and accessible through the holes 250 of the TSV wafer 120 to the backside of the coupled wafer 100. The holes 250 are provided with passivation layers 122. At this point in time (partial figure (ii)), no electrical contact has yet been established between the TSV wafer 120 and the MEMS wafer 110.Any native oxides present on the silicon contact surfaces can be removed by a cleaning step. The electrical contact is then established in the next step (partial figure (iii)) by depositing an electrically conductive material 150, for example, LPCVD-deposited doped polysilicon, although copper, tungsten, and / or metal silicides are also possible. This fill material 150 evenly lines the passivated holes 250 during the process, thus establishing an electrical connection between the signal lines 330 of the first MEMS wafer 110 and the top side of the TSV wafer 120. Sufficient fill material 150 is deposited until the holes 250 are completely closed, in order to achieve a closed plane 124, for example, a polysilicon layer 124, on the top side of the TSV wafer 120 and to ensure further processability.

[0050] To simplify and accelerate the complete closure of holes 250 with polysilicon, an artificial constriction of holes 250 can be provided by a previously deposited PECVD oxide (PECVD: plasma-enhanced chemical vapor deposition). Such a procedure is illustrated in Figure 4. Sub-figure (ii) shows a constriction 410 achieved by anisotropic growth through PECVD, with this procedure being shown in enlarged form in sub-figures (iii) to (v). The chronological sequence of the individual process steps is also indicated in Figure 4 by arrows 280.

[0051] A combination of LPCVD polysilicon 124 (isotropic growth) with a subsequent epitaxial growth step (anisotropic growth), or a combination of both variants, is also possible. This variant is shown in Figure 3B. Here, a hole 250 is first lined with LPCVD polysilicon 124, but not completely filled (partial figure (iii)). Subsequently, the remaining opening is sealed with an anisotropic passivation layer 360 in an epitaxial growth step, leaving a shrinkage cavity 322, i.e., a hollow space (partial figure (iv)).

[0052] The holes 250 are now closed, as shown in sub-figure (iii) of Figure 3A and sub-figure (iv) of Figure 3B, and the TSV wafer 120 can be used as a handle wafer for further processing of the coupled wafer 100. In comparison to Figure 3A, in which the hole 250 is completely filled, the hole 250 is closed in the variant according to Figure 3B by partial filling in combination with a closure.

[0053] At a suitable time, the Si vias 150, which have been short-circuited to this point in the process, are electrically insulated from each other. This can be achieved by metallization to create metal contacts 190 and subsequent passivation to create a passivation layer 350 (Figure 3A, sub-figure (iv)). As an alternative to an isotropic passivation layer 350, the anisotropic polysilicon layer 360 can also be selectively removed to insulate the metal contacts 190, as shown in sub-figure (v) of Figure 3B.

[0054] The process sequence described here is exemplary and can be integrated modularly at any point in the process flow. It is possible to completely finish the TSVs before the first MEMS wafer 110 is fully processed. It is also possible to fully process the first MEMS wafer 110 and only then bond it to the TSV wafer 120. The absolute electrical resistance of the Si vias 150 or the filling material can be adjusted via their cross-sectional area (TSV cross-sectional area). Specifically, the electrical resistance of a Si via 150 depends on both its cross-sectional area and its length. Thus, with a constant length, i.e., TSV depth, the resistance can be varied via the TSV cross-sectional area. The cross-sectional area of ​​a TSV should be selected so that the TSV can be closed.In addition to classic, round, or rectangular shapes, more complex structures such as crosses, spirals, and / or meanders are also conceivable for the shape of a TSV cross-sectional area. The absolute electrical resistance of the Si vias 150 can be specifically adjusted by selecting the TSV cross-sectional area. Corresponding exemplary variants for a TSV cross-sectional area are shown in sub-figure A of Figure 5, with sub-figure B showing the arrangement of the Si vias 150 on a coupled wafer 100 as an example for a plurality of MEMS components 510.

[0055] Figure 6 shows, in schematic form as a flow chart, an exemplary method according to the invention for producing 600 a coupled wafer 100. Furthermore, Figure 6 also shows a method according to the invention for producing MEMS chips 500.

[0056] First, a first MEMS wafer 110 is provided 610, wherein the first MEMS wafer 110 has a first functional layer 112 with first MEMS structures 112' and a first handle wafer 114. Independently of this, a TSV wafer 120 with silicon vias 150 is provided 615. In step 620, a first side 110a of the first MEMS wafer 110 is subsequently connected to a first side 120a of the TSV wafer 120 such that a coupled wafer 100 is obtained.

[0057] Furthermore, a second MEMS wafer 130 is provided (step 630), wherein the second MEMS wafer 130 has a second functional layer 132 with second MEMS structures 132' and a second handle wafer 134. A second side 110b of the first MEMS wafer 110, which is different from the first side 110a, is then connected 640 to a side 130b of the second MEMS wafer 130, for example via bond connections 180. The first handle wafer 114 can now be removed 650, thereby exposing a surface 112a of the first functional layer 112, and further first MEMS structures 116' can be added 660 by growing one or more further layers 116 with the further first MEMS structures 116' on the exposed surface 112.

[0058] After manufacturing 600 the coupled wafer 100, the first MEMS structures 112', 116' and / or the second MEMS structures 132' can be cut out 670. Finally, the coupled wafer 100 is separated 680 into a plurality of MEMS chips 500.

[0059] The invention is not limited to the embodiments described here and the aspects highlighted therein. Rather, numerous modifications are possible within the scope of the claims, which are within the scope of one skilled in the art.

Claims

Claims 1 . A method for producing (600) a coupled wafer (100), comprising the following steps: a. providing (610) a first MEMS wafer (110), the first MEMS wafer (110) having a first functional layer (112) with first MEMS structures (112') and a first handle wafer (114); b. independently providing (615) a TSV wafer (120) with silicon vias (150); and c. connecting (620) a first side (110a) of the first MEMS wafer (110) to a first side (120a) of the TSV wafer (120) such that a coupled wafer (100) is obtained.

2. The method according to claim 1, wherein the method comprises the following further steps: d. Providing (630) a second MEMS wafer (130), wherein the second MEMS wafer (130) has a second functional layer (132) with second MEMS structures (132') and a second handle wafer (134); and e. Connecting (640) a second side (110b) of the first MEMS wafer (110), different from the first side (110a), to a side (130b) of the second MEMS wafer (130).

3. The method according to claim 1 or 2, wherein providing (615) the TSV wafer (120) comprises the following steps: a. providing a silicon wafer (210); b. oxidizing the silicon wafer (210) to form a silicon dioxide layer (220) on a surface of the silicon wafer (210); c. generating an etching mask (220') by patterning the silicon oxide layer (220); d. generating holes (250) penetrating the silicon wafer (210) for the silicon vias (150) using the etching mask (220'); e. at least partially removing the silicon dioxide layer (220) on the back of the wafer to expose the holes (250); and f. oxidizing the holes (250).

4. The method of claim 1 or 2, wherein providing (615) the TSV wafer (120) comprises the following steps: a. providing a silicon wafer (210); b. applying an etching mask (220') to a surface of the Si wafer (210); c. patterning the etching mask (220'); d. etching holes (250) into the silicon wafer (210) using the patterned etching mask (220'); e. back-thinning the silicon wafer (210) such that the holes (250) completely penetrate the silicon wafer (210); and f. oxidizing the holes (250).

5. Method according to one of the preceding claims, wherein the method comprises the following further steps: • at least partially removing (650) the first handle wafer (114) and thereby exposing a surface (112a) of the first functional layer (112); and • Adding (660) further first MEMS structures (116') by growing one or more further layers (116) with the further first MEMS structures (116') on the exposed surface (112a).

6. The method according to any one of the preceding claims, wherein the bonding (620) of the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120) takes place before the bonding (640) of the second side (110b) of the first MEMS wafer (110) to the side (130b) of the second MEMS wafer (130).

7. The method according to any one of the preceding claims, wherein providing (610) the first MEMS wafer (110) and the TSV wafer (120) comprises producing the first MEMS wafer (110) and the TSV wafer (120), and producing the first MEMS wafer (110) and the TSV wafer (120) overlap in time.

8. The method according to any one of the preceding claims, wherein by connecting (620) the first side (110a) of the first MEMS wafer (110) to the first side (120a) of the TSV wafer (120), one or more connection points (180) are formed, which are suitable for forwarding electrical signals between a rewiring level (300) of the MEMS wafer (110) and at least some of the silicon vias (150) of the TSV wafer (120).

9. The method according to any one of claims 1 to 8, wherein the first MEMS structures (112', 116') comprise structures for actuators and / or sensors and the second MEMS structures (132') comprise structures for mirror plates.

10. Coupled wafer (100), preferably produced according to one of the methods 1 to 9, comprising a first MEMS wafer (110), wherein the first MEMS wafer (110) has a first functional layer (112) with first MEMS structures (112') and a first handle wafer (114), and a TSV wafer (120) with silicon vias (150), wherein a first side (110a) of the first MEMS wafer (110) is connected to a first side (120a) of the TSV wafer (120).

11. A method for manufacturing MEMS chips (500) with one or more MEMS components (510), comprising the following steps: a. manufacturing (600) a coupled wafer (100) comprising a coupled wafer (100) according to claim 10; and b. singulating (680) the coupled wafer (100) into a plurality of MEMS chips (500).

12. The method according to claim 11, wherein the manufacturing (600) of the coupled wafer (100) is carried out according to claim 2 and preferably one of claims 3 to 9 and the coupled wafer (100) further comprises the second MEMS wafer (140).

13. The method according to claim 12, wherein after the production (600) of the coupled wafer (100) and before the singulation (680) of the coupled wafer (100), a release (670) of the first MEMS structures (112', 116') and / or the second MEMS structures (132') takes place.

14. MEMS chip (500) manufactured according to one of the methods 11 to 13. 5

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