Semiconductor device

Abstract

This semiconductor device includes: a substrate; a first transistor having a first semiconductor layer and a second semiconductor layer, a first nanosheet, and a first gate electrode formed on a first surface of the substrate; a first power line which is formed on a second surface of the substrate on the opposite side from the first surface and which is electrically connected to the first semiconductor layer; a second power line electrically connected to the second semiconductor layer; a first signal line disposed to overlap the first gate electrode in a plan view; and a first via which is formed in the substrate and which connects the first gate electrode and the first signal line. This allows a power switch circuit to be disposed appropriately in cases where there is a via that connects directly from the back surface of a semiconductor substrate to a gate electrode on the front surface of the semiconductor substrate.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] BS-PDN (Backside Power Delivery Network) technology is known, which supplies power from the back surface of a semiconductor substrate to elements such as transistors formed on the front surface of the semiconductor substrate. Technology is also known in which a via is provided that directly connects the back surface of the semiconductor substrate to the gate electrode of a transistor on the front surface of the semiconductor substrate. Technology is also known in which a power switch circuit is provided that switches the supply of power to a circuit on and off.

[0003] US Patent Application Publication No. 2023 / 0178435 US Patent Application Publication No. 2023 / 0067311 US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0181258 International Publication No. 2020 / 065916 International Publication No. 2020 / 066797 International Publication No. 2020 / 217396 International Publication No. 2020 / 217400 US Patent Application Publication No. 2021 / 0366902 US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2021 / 0210600

[0004] M. Kobrinsky, "A new VLSI R&D frontier: cell-level interconnects to enable back-side power delivery networks and 3D device stacking", 2023 Symposium on VLSI Technology and Circuits Advance Program: Workshop3 (June 11, 2023), Internet <URL: https: / / archive.vlsisymposium.org / 23web / files / program / VLSI2023_Advanceprogram0612.pdf>

[0005] When there is a via that directly connects from the back surface of the semiconductor substrate to the gate electrode on the front surface of the semiconductor substrate, no detailed consideration has been given to how to arrange the power switch circuit that switches the power supply to the circuit on and off.

[0006] The present invention has been made in consideration of the above points, and aims to appropriately arrange a power switch circuit when there is a via that directly connects from the back surface of a semiconductor substrate to a gate electrode on the front surface of the semiconductor substrate.

[0007] In one aspect of the present invention, a semiconductor device includes a substrate, a first semiconductor layer and a second semiconductor layer formed on a first surface of the substrate, a first nanosheet connecting the first semiconductor layer and the second semiconductor layer, a first gate electrode covering the first nanosheet, a first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode, a first power supply line electrically connecting to the first semiconductor layer formed on a second surface of the substrate opposite the first surface, a second power supply line electrically connecting to the second semiconductor layer, a first signal line arranged to overlap the first gate electrode in a planar view, and a first via formed in the substrate, connecting the first gate electrode and the first signal line, and arranged to overlap the first gate electrode and the first signal line in a planar view.

[0008] According to the disclosed technique, it is possible to appropriately arrange the power switch circuit when there is a via that directly connects from the back surface of the semiconductor substrate to the gate electrode on the front surface of the semiconductor substrate.

[0009] 11 is a plan view showing an example of a layout of a semiconductor device in a first embodiment. 12 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of FIG. 1. 13 is a circuit diagram showing an example of a circuit arranged in the standard cell block of FIG. 1. 14 is a diagram showing a legend for circuit elements used in the plan views of the circuits described below. 15 is a plan view showing an example of a circuit layout of a BSM1 layer and a BSM2 layer in a region where the power switch circuit and standard cell of FIG. 3 are formed. 16 is a plan view showing an example of a bottom-side circuit layout formed on the surface of a substrate in a region where the power switch circuit and standard cell of FIG. 5 are formed. 17 is a plan view showing an example of a top-side circuit layout formed on the bottom-side circuit of FIG. 6 in a region where the power switch circuit and standard cell of FIG. 5 are formed. 18 is a cross-sectional view showing an example of a cross-section taken along line X1-X1' in FIGS. 5 to 7. 19 is a cross-sectional view showing an example of a cross-section taken along line X2-X2' in FIGS. 5 to 7. 20 is a cross-sectional view showing an example of a cross-section taken along line Y1-Y1' in FIGS. 5 to 7. 21 is a circuit diagram showing an example of a standard cell block in a first modified example of the first embodiment. 22 is a plan view showing an example of a top-side circuit layout in a region where the power switch circuit and standard cell of FIG. 23 are formed. 18 is a plan view showing an example of a circuit layout on the bottom side of a region where a power switch circuit and a standard cell are formed in a second modified example of the first embodiment. 19 is a plan view showing an example of a circuit layout on the top side formed on the bottom side circuit of FIG. 13 in a second modified example of the first embodiment. 20 is a plan view showing an example of a circuit layout on the bottom side of a region where a power switch circuit and a standard cell are formed in a third modified example of the first embodiment. 21 is a plan view showing an example of a circuit layout on the top side of a region where a power switch circuit and a standard cell are formed in a third modified example of the first embodiment. 22 is a plan view showing an example of a circuit layout on the top side of a region where a power switch circuit and a standard cell are formed in a third modified example of the first embodiment. 23 is a plan view showing an example of a circuit layout of a BSM1 layer and a BSM2 layer in a region where a power switch circuit and a standard cell are formed in a semiconductor device of a second embodiment. 24 is a plan view showing an example of a circuit layout on the bottom side of a region where a power switch circuit and a standard cell of FIG. 17 are formed. 25 is a cross-sectional view showing an example of a cross section taken along line Y2-Y2' in FIGS. 17 and 18.22 is a plan view showing an example of a circuit layout of a BSM1 layer and a BSM2 layer in a region where a power switch circuit and a standard cell are formed in the semiconductor device of the third embodiment. 23 is a plan view showing an example of a circuit layout on the bottom side in a region where the power switch circuit and the standard cell of FIG. 20 are formed. 24 is a plan view showing an example of a circuit layout on the top side in a region where the power switch circuit and the standard cell of FIG. 20 are formed. 25 is a cross-sectional view showing an example of a cross section taken along line X3-X3' in FIGS. 20 to 22. 26 is a cross-sectional view showing an example of a cross section taken along line X4-X4' in FIGS. 20 to 22. 27 is a cross-sectional view showing an example of a cross section taken along line Y3-Y3' in FIGS. 20 to 22.

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply potential is also used to indicate a power supply line or a power supply terminal to which the power supply potential is supplied.

[0011] 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in FIG. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.

[0012] The semiconductor device 100 has a plurality of I / O cells IOC and IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for a signal SGNL such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply potential or a ground potential.

[0013] Each I / O cell IOC, IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB in which standard cells are provided. Note that the internal circuit region INTR may also be equipped with logic circuits other than standard cells, or may also be equipped with a memory. The memory may be equipped within the standard cell block SCB.

[0014] Fig. 2 shows an example of a cross-sectional structure of the semiconductor device 100 of Fig. 1. The semiconductor device 100 has a substrate SUB, a wiring layer WL1 formed on the front surface FS side of the substrate SUB, and a wiring layer WL2 formed on the back surface BS side of the substrate SUB. The front surface FS of the substrate SUB is an example of a first surface, and the back surface BS of the substrate SUB is an example of a second surface.

[0015] A CFET (Complementary Field Effect Transistor) is formed on the surface of the substrate. The CFET has a source S and a drain D formed in semiconductor layers on a bottom side (BTM) that is closer to the substrate SUB and a top side (TOP) that is farther from the substrate SUB. Hereinafter, wiring and semiconductor layers arranged on the bottom BTM side may be denoted by the symbol BTM, and wiring and semiconductor layers arranged on the top TOP side may be denoted by the symbol TOP.

[0016] The wiring arranged on the bottom BTM side may also be referred to as bottom wiring BTMW, and the wiring arranged on the top TOP side may also be referred to as top wiring TOPW. Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer. The semiconductor layer may be referred to as source / drain S / D, even if it does not function as a transistor. Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer, even if it does not function as a transistor.

[0017] The CFET has a nanosheet NS that interconnects the source S and drain D on the bottom BTM side and a nanosheet NS that interconnects the source S and drain D on the top TOP side. The CFET has a gate insulating film (not shown) formed on each nanosheet NS and a gate electrode GT that is common to the top TOP side and the bottom BTM side. The nanosheet NS that interconnects the source S and drain D on the bottom BTM side is an example of a first nanosheet. The nanosheet NS that interconnects the source S and drain D on the top TOP side is an example of a second nanosheet.

[0018] The wiring layer WL1 may have a wiring layer FSM1 (FSM stands for Frontside Metal) on which the wiring W3 is formed above the top region. The wiring layer WL1 may have multiple wiring layers FSM. Hereinafter, the wiring layer FSM is also referred to as an FSM layer.

[0019] The wiring layer WL2 has wiring layers BSM1 and BSM2 (BSM stands for Backside Metal). The wiring layer WL2 may have one wiring layer BSM, or may have three or more wiring layers BSM. For example, wirings W1 and W2 such as power lines, ground lines, or signal lines are formed in the wiring layers BSM1 and BSM2, respectively. The wirings W1 and W2 may be connected to each other via vias VIA.

[0020] A power supply line or a ground line of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA is directly connected to the source S or drain D of the CFET. A signal line of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV, and the other end of the via VIA is directly connected to a gate electrode GT (hereinafter also referred to as gate GT) of the CFET. A via VIA such as a TSV directly connected to the gate GT is sometimes also referred to as a DGC (Direct Gate Contact).

[0021] The wiring W1 of the wiring layer BSM1 may be connected to a buried wiring BPR (Buried Power Rail) buried in the surface of the substrate SUB through a via VIA such as a TSV. The wiring layer WL2 may be a wiring layer formed on the back surface of the substrate SUB, or may be a wiring layer formed in another chip attached to the back surface of the substrate SUB. Hereinafter, the wiring layers BSM1 and BSM2 are also referred to as a BSM1 layer and a BSM2 layer.

[0022] 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW and standard cells SC. The standard cells SC are connected to a virtual power line VVDD and a ground line VSS, and operate by receiving a virtual power potential VVDD from the virtual power line VVDD. The standard cells SC have various logic circuits.

[0023] The power switch circuit PSW is connected to a power line TVDD and a ground line VSS and operates. The power switch circuit PSW includes a control circuit CNTL and a switch transistor SWT. For example, the control circuit CNTL generates a control signal PSWsig that controls the switch transistor SWT in response to an input signal (not shown). The power line TVDD is an example of a first power line, and the virtual power line VVDD is an example of a second power line.

[0024] The switch transistor SWT has a PMOS transistor whose source is connected to the power supply line TVDD and whose drain is connected to the virtual power supply line VVDD, and operates by receiving the potential of a control signal PSWsig from the control circuit CNTL as a gate potential. While the switch transistor SWT is on, the power supply line TVDD and the virtual power supply line VVDD are electrically connected, and the power supply potential TVDD is supplied to the standard cell SC via the virtual power supply line VVDD. While the switch transistor SWT is off, the electrical connection between the power supply line TVDD and the virtual power supply line VVDD is cut off, and the virtual power supply line VVDD is set to a floating state.

[0025] 4 shows a legend for circuit elements used in the plan views of the circuits described below. Note that in the legend, various vias are indicated by solid line shapes, but in the plan views shown in FIG. 5 and subsequent figures, vias hidden by wiring arranged above are indicated by dashed line shapes.

[0026] 5 shows an example of a circuit layout of the BSM1 layer and the BSM2 layer in the region where the power switch circuit PSW and the standard cells SC of FIG. 3 are formed. The wiring in the BSM1 layer extends in the Y direction and is arranged at intervals in the X direction. The wiring in the BSM2 layer extends in the X direction and is arranged at intervals in the Y direction. The Y direction is an example of a first direction, and the X direction is an example of a second direction.

[0027] In the BSM1 layer and the BSM2 layer, wiring of the same type (for example, a virtual power line VVDD) may be connected to each other through vias VIA (BSM1-BSM2). In the region of the power switch circuit PSW, a power line TVDD, a virtual power line VVDD, and a control signal line PSWsig are formed using the BSM1 layer and the BSM2 layer. The control signal line PSWsig is an example of a first signal line. In the region of the standard cell SC, a ground line VSS and a control signal line SCsig are formed using the BSM1 layer and the BSM2 layer, and a virtual power line VVDD is formed using the BSM2 layer. The control signal lines PSWsig and SCsig in the BSM1 layer are each connected to a gate GT of a CFET (not shown) through a via VIA (DGC).

[0028] 6 shows an example of a circuit layout on the bottom BTM side formed on the surface of the substrate SUB in the region where the power switch circuit PSW and standard cell SC of FIG. 5 are formed. A PMOS transistor including a P-type semiconductor layer Pdiff is formed on the bottom BTM side. The symbols S and D shown in the semiconductor layer Pdiff indicate the source and drain, respectively. A semiconductor layer Pdiff without the symbols S and D indicates, for example, that it is set in an open state and does not function as a transistor. The source S of the PMOS transistor is an example of either the first semiconductor layer or the second semiconductor layer, and the drain D of the PMOS transistor is an example of the other of the second semiconductor layer or the first semiconductor layer.

[0029] In the region of the power switch circuit PSW, the switch transistor SWT is formed by a gate GT and a plurality of PMOS transistors, each including a source S and a drain D adjacent to the gate GT in the Y direction. The gate GT of the switch transistor SWT (PMOS transistor) is directly connected to one end of a via VIA (DGC), and the other end of the via VIA (DGC) is directly connected to a control signal line PSWsig of the BSM1 layer. The switch transistor SWT is an example of a first transistor, and the gate GT of the switch transistor SWT is an example of a first gate electrode.

[0030] The source S of the switch transistor SWT (PMOS transistor) is connected to the power supply line TVDD of the BSM1 layer through the bottom wiring BTMW and the via VIA (BSM1-BTM). That is, the source S of the switch transistor SWT is connected to the power supply line TVDD of the BSM1 layer, which is arranged offset in the X direction from the switch transistor SWT in a plan view. The sources S of the switch transistors SWT arranged side by side in the X direction may be connected to each other by the bottom wiring BTMW. The via VIA (DGC) and the via VIA (BSM1-BTM) are examples of first vias.

[0031] The drain D of the switch transistor SWT is connected to the virtual power line VVDD of the BSM1 layer through the bottom wiring BTMW and the via VIA (BSM1-BTM). That is, the drain D of the switch transistor SWT is connected to the virtual power line VVDD of the BSM1 layer, which is arranged offset in the X direction from the switch transistor SWT in a plan view. The drains D of the switch transistors SWT arranged side by side in the X direction may be connected to each other by the bottom wiring BTMW.

[0032] A PMOS transistor including a source S, a drain D, and a gate GT is formed in the region of the standard cell SC. The source S of the PMOS transistor of the standard cell SC is connected to a virtual power line VVDD of the BSM1 layer through a bottom wiring BTMW and a via VIA (BSM1-BTM). The source S of the PMOS transistor of the standard cell SC may be connected to the drain D of the PMOS transistor of the power switch circuit PSW through the bottom wiring BTMW.

[0033] The drain D of the PMOS transistor of the standard cell SC is connected to the TOP wiring TOPW (FIG. 7) through the bottom wiring BTMW and the via VIA (BTM-TOP). One end of the via VIA (DGC) is directly connected to the gate GT of the PMOS transistor of the standard cell SC, and the other end of the via VIA (DGC) is directly connected to the control signal line SCsig of the BSM1 layer.

[0034] 7 shows an example of a circuit layout on the top TOP side formed on the circuit on the bottom BTM side of FIG. 6 in the region where the power switch circuit PSW and standard cell SC of FIG. 5 are formed. An NMOS transistor including an N-type semiconductor layer Ndiff is formed on the top side. The symbols S and D shown in the semiconductor layer Ndiff indicate the source and drain, respectively. A semiconductor layer Ndiff without the symbols S and D indicates, for example, that it is set to an open state and does not function as a transistor. For example, the semiconductor layer Ndiff of an NMOS transistor formed in the region of the power switch circuit PSW is in an open state and does not function as an NMOS transistor. The source S of the NMOS transistor is an example of a third semiconductor layer or a fourth semiconductor layer, and the drain D of the NMOS transistor is an example of a fourth semiconductor layer or a third semiconductor layer.

[0035] An NMOS transistor including a source S, a drain D, and a gate GT is formed in the region of the standard cell SC. The source S of the NMOS transistor of the standard cell SC is connected to the ground line VSS of the BSM1 layer through the top wiring TOPW and a via VIA (BSM1-TOP). The drain D of the NMOS transistor of the standard cell SC is connected to the bottom wiring BTMW (FIG. 6) through the top wiring TOPW and a via VIA (BTM-TOP). The gate GT of the NMOS transistor of the standard cell SC is directly connected to the via VIA (DGC), as shown in FIG. 6. For example, the PMOS transistor and NMOS transistor of the standard cell SC function as a CMOS inverter.

[0036] FIG. 8 shows an example of a cross section taken along line X1-X1' in FIGS. 5 to 7. One end of the via VIA (DGC) is directly connected to the gate GT of the corresponding transistor. The other end of the via VIA (DGC) is directly connected to the control signal line PSWsig in the BSM1 layer. The nanosheet NS is provided so as to penetrate the gate GT. The gate GT is disposed on the substrate SUB via an insulating film. The wiring in the BSM1 layer is disposed below the substrate SUB via an insulating film. The control signal line PSWsig in the BSM1 layer is connected to the control signal line PSWsig in the BSM2 layer via the via VIA (BSM1-BSM2).

[0037] For example, the wiring and vias, etc. of the BSM1 layer and BSM2 layer below the substrate SUB are integrally formed on the underside of the substrate SUB on which the power switch circuit PSW, etc. are formed, using a semiconductor manufacturing process. Note that the wiring and vias, etc. of the BSM1 layer and BSM2 layer below the substrate SUB may be formed on a substrate separate from the substrate SUB on which the power switch circuit PSW and standard cell SC are formed. In this case, the wiring layer including the wiring and vias, etc. of the BSM1 layer and BSM2 layer formed on the separate substrate is joined to the underside of the substrate SUB.

[0038] 9 shows an example of a cross section taken along line X2-X2' in FIGS. 5 to 7. In the switch transistor SWT and the standard cell SC, the P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the source S or drain D (drain D in the cross section of FIG. 9) of the switch transistor SWT. In FIG. 9, the drain D of the switch transistor SWT (PMOS transistor) is connected to the virtual power line VVDD in the BSM1 layer via the bottom wiring BTMW and via VIA. In the switch transistor SWT, the N-type semiconductor layer Ndiff formed on the top TOP side is set to an open state.

[0039] In the standard cell SC, a P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the source S or drain D (source S in the cross section of FIG. 9) of the PMOS transistor. In FIG. 9, the source S of the PMOS transistor of the standard cell SC is connected to the virtual power line VVDD of the BSM1 layer through the bottom wiring BTMW and the via VIA. Here, the source S of the PMOS transistor of the standard cell SC may be connected to the drain D of the switch transistor SWT through the bottom wiring BTMW.

[0040] In the standard cell SC, an N-type semiconductor layer Ndiff formed on the top TOP side functions as a source S or a drain D (source S in the cross section of FIG. 9) of an NMOS transistor. In FIG. 9, the source S of the NMOS transistor of the standard cell SC is connected to a ground line VSS of the BSM1 layer through a top wiring TOPW and a via VIA.

[0041] 9, the ground line VSS of the BSM1 layer is connected to the top wiring TOPW through a via VIA (BSM1-TOP). However, the ground line VSS of the BSM1 layer may be connected to the top wiring TOPW through a via VIA (BSM1-BTM), a bottom wiring BTM, and a via VIA (BTM-TOP), not shown, instead of the via VIA (BSM1-TOP).

[0042] 10 shows an example of a cross section taken along line Y1-Y1' in FIGS. 5 to 7. The P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the source S or drain D of the PMOS transistor, as explained in FIG. 9. The gate GT provided in common to the PMOS transistor and the NMOS transistor is directly connected to one end of the via VIA (DGC), as explained in FIG. 8. Between the P-type semiconductor layers Pdiff adjacent in the Y direction, a nanosheet NS on the bottom BTM side is formed, extending through the gate GT. Between the N-type semiconductor layers Ndiff adjacent in the Y direction, a nanosheet NS on the top TOP side is formed, extending through the gate GT.

[0043] 11 shows an example of a standard cell block SCB in a first modified example of the first embodiment. Detailed description of elements similar to those in FIG. 3 will be omitted. The power switch circuit PSW in FIG. 11 includes an NMOS transistor NM in addition to the control circuit CNTL and switch transistor SWT in FIG. 3. The gate of the NMOS transistor NM is connected to a control signal PSWsig, and the source S and drain D are connected to a ground line VSS. The other configurations of the standard cell block SCB are similar to those in FIG. 3.

[0044] By connecting the source S and drain D of the NMOS transistor to a voltage line such as a ground line VSS with a fixed potential without leaving them open, the potentials of the source S and drain D of the NMOS transistor can be stabilized. This makes it possible to suppress, for example, fluctuations in the characteristics of the NMOS transistor due to noise, etc. Also, it is possible to suppress charge / discharge currents (leak currents) in the source region and drain region. Note that the source S and drain D of the NMOS transistor may be set to an open state while connected to each other by wiring.

[0045] 12 shows an example of a circuit layout on the TOP side in the region where the power switch circuit PSW and standard cell SC of FIG. 11 are formed. Detailed description of the same elements as in FIG. 7 will be omitted. The layout shown in FIG. 12 is the same as FIG. 7 except that the semiconductor layer Ndiff of the NMOS transistor that is not used as the switch transistor SWT among the CFETs is connected to the ground line VSS and fixed to the ground potential VSS.

[0046] For example, in the power switch circuit PSW, the semiconductor layers Ndiff arranged in the X direction are electrically connected to each other by a top wiring TOPW extending in the X direction. One or more rows of the semiconductor layers Ndiff arranged in the Y direction may be connected to the wiring FSMW of the FSM layer through vias VIA (TOP-FSM). This allows the semiconductor layers Ndiff arranged in the Y direction to be electrically connected to each other.

[0047] The configuration in which the open-state semiconductor layer Ndiff is connected to the ground line VSS and the configuration in which the open-state semiconductor layers Ndiff aligned in the Y direction are connected to each other via the wiring FSMW of the FSM layer may be applied to other embodiments (including modified examples).

[0048] 13 and 14 show an example of a circuit layout of an area in which a power switch circuit PSW and standard cells SC are formed in a second modified example of the first embodiment. Fig. 13 shows the circuit layout on the bottom BTM side, and Fig. 14 shows the circuit layout on the top TOP side. Detailed descriptions of elements similar to those in Figs. 6 and 7 will be omitted.

[0049] 13 and 14, the N-type semiconductor layer Ndiff of the NMOS transistor of the CFET is formed on the bottom BTM side, and the P-type semiconductor layer Pdiff of the PMOS transistor of the CFET is formed on the top TOP side. Therefore, the switch transistor SWT is formed on the top TOP side.

[0050] 13, the semiconductor layer Ndiff is set to an open state, but may be connected to the ground line VSS via the bottom wiring BTMW and the via VIA, as in Fig. 12. On the bottom BTM side, the drain D of the NMOS transistor of the standard cell SC is connected to the drain D of the PMOS transistor of the standard cell SC on the top TOP side via the bottom wiring BTMW and the via VIA (BTM-TOP).

[0051] 14, the source S (Pdiff) of the switch transistor SWT (PMOS transistor) is connected to the power supply line TVDD of the BSM1 layer via the top wiring TOPW and the via VIA (BSM1-TOP). The drain D (Pdiff) of the switch transistor SWT is connected to the virtual power supply line VVDD of the BSM1 layer via the top wiring TOPW and the via VIA (BSM1-TOP).

[0052] 14, the source S of the PMOS transistor of the standard cell SC is connected to the virtual power line VVDD of the BSM1 layer through the top wiring TOPW and the via VIA (BSM1-TOP). Note that the configuration in which the NMOS transistor is arranged on the bottom BTM side and the PMOS transistor is arranged on the top TOP side may be applied to other embodiments (including modified examples).

[0053] 15 and 16 show an example of a circuit layout of an area where a power switch circuit PSW and standard cells SC are formed in a third modified example of the first embodiment. FIG. 15 shows the circuit layout on the bottom BTM side, and FIG. 16 shows the circuit layout on the top TOP side. Detailed descriptions of elements similar to those in FIGS. 6 and 14 will be omitted. The circuit layout of the area where the standard cells SC are formed is similar to that in FIGS. 6 and 7.

[0054] 15 and 16, the switch transistors SWT (PMOS transistors) of the power switch circuit PSW are formed on both the bottom BTM side and the top TOP side. Therefore, the bottom wiring BTMW of the power switch circuit PSW in Fig. 15 is connected to the top wiring TOPW of the power switch circuit PSW in Fig. 15 through a via VIA (BTM-TOP).

[0055] As described above, in the first embodiment, by directly connecting the via VIA (DGC) from the back surface of the semiconductor substrate SUB to the gate GT of the switch transistor SWT, it is possible to prevent the wiring layer formed on the front surface FS side of the substrate SUB from being used as the gate wiring. As a result, it is possible to prevent the wiring formed on the front surface FS side of the substrate SUB from becoming dense. Therefore, when there is a via VIA (DGC) that directly connects from the back surface of the semiconductor substrate SUB to the gate GT on the front surface of the semiconductor substrate SUB, it is possible to appropriately arrange the power switch circuit PSW.

[0056] By connecting the source S and drain D of the NMOS transistor of the switch transistor SWT to a voltage line such as the ground line VSS, which has a fixed potential, without leaving them open, the potentials of the source S and drain D of the NMOS transistor can be stabilized. This makes it possible to suppress fluctuations in the characteristics of the NMOS transistor due to noise, for example. It also makes it possible to suppress charge / discharge currents (leak currents) in the source and drain regions.

[0057] By forming the switch transistors SWT on both the bottom BTM side and the top TOP side, the number of switch transistors SWT can be increased. As a result, when the layout area of ​​the power switch circuit PSW is the same, the current supply capability of the switch transistors SWT can be improved. Note that the configuration in which the switch transistors SWT are formed on both the bottom BTM side and the top TOP side may be applied to other embodiments (including modified examples).

[0058] Second Embodiment FIG. 17 shows an example of a circuit layout of the BSM1 layer and the BSM2 layer in an area where the power switch circuit PSW and the standard cells SC of a semiconductor device according to a second embodiment are formed. Detailed description of elements similar to those in FIG. 5 will be omitted. For example, the power switch circuit PSW and the standard cells SC shown in FIG. 17 are mounted in a standard cell block SCB of the semiconductor device 100, similar to FIG. 1. The cross-sectional structure of the semiconductor device 100 in which the power switch circuit PSW and the standard cells SC of FIG. 17 are mounted is similar to FIG. 2. The circuit arranged in the standard cell block SCB is similar to FIG. 3.

[0059] 17 differs from Fig. 5 in the arrangement of the various power supply lines and control signal lines PSWsig formed in the BSM1 layer and the arrangement of the various power supply lines and control signal lines PSWsig formed in the BSM2 layer. Also, in Fig. 17, the wiring in the BSM1 layer arranged below the row of switch transistors SWT extending in the Y direction is separated into a power supply line TVDD and a control signal line PSWsig.

[0060] 18 shows an example of a circuit layout on the bottom BTM side in the region where the power switch circuit PSW and standard cells SC of FIG. 17 are formed. Detailed description of elements similar to those in FIG. 6 will be omitted. Note that in the second embodiment, the circuit layout on the top TOP side is similar to that of the first embodiment (FIG. 7 or FIG. 12), and therefore will not be illustrated or described.

[0061] 18, the power supply line TVDD in the BSM1 layer is arranged below the source S of the switch transistor SWT and is connected to a via VIA (BSM1-BTM) directly connected to the source S of the switch transistor SWT. The control signal line PSWsig in the BSM1 layer is arranged below the gate of the switch transistor SWT and is connected to a via VIA (DGC) directly connected to the gate GT of the switch transistor SWT.

[0062] Therefore, the source S of the switch transistor SWT of the power switch circuit PSW can be connected to the power line TVDD of the BSM1 layer without going through the bottom wiring BTMW, which makes it possible to reduce the power supply resistance to the source S of the switch transistor SWT compared to when going through the bottom wiring BTMW.

[0063] In the power switch circuit PSW, the virtual power line VVDD of the BSM1 layer may be arranged below the drain D of the switch transistor SWT, and a power line TVDD may be arranged instead of the virtual power line VVDD in Fig. 18. In this case, the virtual power line VVDD of the BSM1 layer can be connected to the drain D of the switch transistor SWT by a via VIA (BSM1-BTM) formed below the drain D.

[0064] FIG. 19 shows an example of a cross section taken along line Y2-Y2′ in FIGS. 17 and 18. Detailed description of elements similar to those in FIG. 10 will be omitted. In FIG. 19, as described in FIG. 17, the wiring in the BSM1 layer is separated into a power supply line TVDD and a control signal line PSWsig. This allows the via VIA (BSM1-BTM) connected to the power supply line TVDD in the BSM1 layer to be directly connected to the source S (Pdiff) of the switch transistor SWT. As a result, the resistance of the power supply line TVDD connected to the source S of the switch transistor SWT can be reduced.

[0065] As described above, in the second embodiment, as in the first embodiment, the power switch circuit PSW can be appropriately arranged when there is a via VIA (DGC) that directly connects from the back surface of the semiconductor substrate SUB to the gate GT on the front surface of the semiconductor substrate SUB.

[0066] Furthermore, in the second embodiment, below the switch transistor SWT (PMOS transistor), the wiring of the BSM1 layer extending in the extension direction of the nanosheet NS is separated into a power supply line TVDD and a control signal line PSWsig. The power supply line TVDD of the BSM1 layer is then disposed below the source S (Pdiff) of the switch transistor SWT. This allows the via VIA (BSM1-BTM) connected to the power supply line TVDD of the BSM1 layer to be directly connected to the source S (Pdiff) of the switch transistor SWT. As a result, the power supply resistance to the source S of the switch transistor SWT can be reduced compared to when the bottom wiring BTMW is used, and the resistance of the power supply line TVDD connected to the source S of the switch transistor SWT can be reduced.

[0067] Third Embodiment Figure 20 shows an example of a circuit layout of the BSM1 layer and the BSM2 layer in an area where the power switch circuit PSW and the standard cells SC of a semiconductor device according to a third embodiment are formed. Detailed description of elements similar to those in Figure 5 will be omitted. For example, the power switch circuit PSW and the standard cells SC shown in Figure 20 are mounted in a standard cell block SCB of the semiconductor device 100, similar to Figure 1. The cross-sectional structure of the semiconductor device 100 on which the power switch circuit PSW and the standard cells SC of Figure 20 are mounted is similar to that of Figure 2. The circuit arranged in the standard cell block SCB is similar to that of Figure 3.

[0068] 20, the wiring in the BSM1 layer is spaced apart in the Y direction and extends in the X direction. The wiring in the BSM2 layer is spaced apart in the X direction and extends in the Y direction. That is, in FIG. 20, the arrangement directions of the wiring in the BSM1 layer and the wiring in the BSM2 layer are reversed from those in FIG. 5.

[0069] Fig. 21 shows an example of a circuit layout on the bottom BTM side in the region where the power switch circuit PSW and standard cell SC are formed in Fig. 20. In this embodiment, the arrangement direction (Y direction) of the power line TVDD and virtual power line VVDD in the BSM1 layer is set to be the same as the extension direction (Y direction) of the nanosheet NS of the CFET formed in the power switch circuit PSW and standard cell SC.

[0070] This allows the arrangement direction of the CFET sources S and the arrangement direction of the CFET drains D to be aligned with the arrangement direction of the wiring in the BSM1 layer. Therefore, the CFET sources S and drains D can be directly connected to vias (BSM1-BTM) connected to the power supply line TVDD and the virtual power supply line VVDD, respectively. By aligning the arrangement direction of the wiring in the BSM1 layer with the extension direction of the nanosheet NS in this way, it becomes easy to connect the power supply line TVDD and the virtual power supply line VVDD from the bottom of the substrate SUB to not only the CFET gate GT but also the CFET sources S and drains D.

[0071] The ground line VSS of the BSM1 layer is arranged along the X direction in the region of the standard cells SC, and is connected to the top wiring TOPW (FIG. 22) through a via VIA (BSM1-BTM), a bottom wiring BTMW, and a via (BTM-TOP).

[0072] 22 shows an example of a circuit layout on the TOP side in the region where the power switch circuit PSW and standard cell SC of FIG. 20 are formed. The circuit layout on the TOP side is the same as that of FIG. 7, and the semiconductor layer Ndiff and gate of the power switch circuit PSW are set to an open state. Note that the semiconductor layer Ndiff may be connected to the ground line VSS as in FIG. 12.

[0073] Fig. 23 shows an example of a cross section taken along line X3-X3' in Fig. 20 to Fig. 22. The cross-sectional structure in Fig. 23 is the same as that in Fig. 8, except that the ground line VSS connected to the source S (not shown) of the NMOS transistor NM of the standard cell SC appears as the bottom wiring BTMW.

[0074] Fig. 24 shows an example of a cross section taken along line X4-X4' in Fig. 20 to Fig. 22. In this embodiment, the semiconductor layer Pdiff functioning as the source S and drain D of the switch transistor SWT can be directly connected to a via VIA (BSM1-BTM) connected to the virtual power line VVDD of the BSM1 layer.

[0075] Figure 25 shows an example of a cross section taken along line Y3-Y3' in Figures 20 to 22. In this embodiment, as explained in Figure 21, the arrangement direction of the wiring in the BSM1 layer is aligned with the extension direction of the nanosheet NS, making it easy to connect the virtual power line VVDD from the bottom of the substrate SUB to the drain D of the CFET. Similarly, although not shown in the cross section of Figure 25, it is easy to connect the power line TVDD from the bottom of the substrate SUB to the source S of the CFET.

[0076] As described above, in the third embodiment, as in the first embodiment, the power switch circuit PSW can be appropriately arranged when there is a via VIA (DGC) that directly connects from the back surface of the semiconductor substrate SUB to the gate GT on the front surface of the semiconductor substrate SUB.

[0077] Furthermore, in the third embodiment, by setting the arrangement direction of the power supply line TVDD and the virtual power supply line VVDD in the BSM1 layer to the same as the extension direction of the nanosheet NS, the arrangement direction of the source S and drain D of the CFET can be aligned with the arrangement direction of the wiring in the BSM1 layer. Therefore, the source S and drain D of the CFET can be directly connected to vias (BSM1-BTM) connected to the power supply line TVDD and the virtual power supply line VVDD, respectively. As a result, the power supply line TVDD and the virtual power supply line VVDD can be easily connected from the bottom of the substrate SUB to not only the gate GT of the CFET but also the source S and drain D of the CFET.

[0078] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0079] 100 Semiconductor device BPR Buried wiring BSM1, BSM2 Wiring layer BTMW Bottom wiring CNTL Control circuit D Drain FSM1 Wiring layer FSMW Wiring GT Gate INTR Internal circuit area IOC, IOCP I / O cell Ndiff Semiconductor layer NM NMOS transistor NS Nanosheet Pdiff Semiconductor layer PSW Power switch circuit PSWsig Control signal line S Source SC Standard cell SCB Standard cell block SCsig Control signal line SGNL Signal SUB Substrate SWT Switch transistor TOPW Top wiring TVDD Power supply line VIA Via VSS Ground line VVDD Virtual power line W1, W2, W3 Wiring WL1, WL2 Wiring layer

Claims

1. A semiconductor device comprising: a substrate; a first semiconductor layer and a second semiconductor layer formed on a first surface of the substrate; a first nanosheet connecting the first semiconductor layer and the second semiconductor layer; a first gate electrode covering the first nanosheet; a first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode; a first power supply line electrically connecting to the first semiconductor layer, a second power supply line electrically connecting to the second semiconductor layer, and a first signal line arranged to overlap the first gate electrode in a planar view, which are formed on a second surface of the substrate opposite to the first surface; and a first via formed in the substrate, connecting the first gate electrode and the first signal line, and arranged to overlap the first gate electrode and the first signal line in a planar view.

2. The semiconductor device according to claim 1, wherein one or both of the first power supply line and the second power supply line are arranged offset from the first transistor in a plan view.

3. The semiconductor device according to claim 2, wherein the first semiconductor layer and the second semiconductor layer of the first transistor are arranged side by side in a first direction, the first nanosheet of the first transistor extends in the first direction, the first signal line extends in the first direction and is arranged to overlap the first transistor in a planar view, and the first power supply line and the second power supply line extend in the first direction.

4. The semiconductor device described in claim 1, wherein the first semiconductor layer and the second semiconductor layer of the first transistor are arranged side by side in a first direction, the first nanosheet of the first transistor extends in the first direction, the first signal line is arranged side by side in the first direction sandwiched between a plurality of the first power supply lines arranged at intervals in the first direction, and the first semiconductor layer is directly connected to the first via connected to the first power supply line.

5. The semiconductor device described in claim 1, wherein the first semiconductor layer and the second semiconductor layer of the first transistor are arranged side by side in a first direction, the first nanosheet of the first transistor extends in the first direction, the first signal line is arranged side by side in the first direction sandwiched between a plurality of the second power supply lines arranged at intervals in the first direction, and the second semiconductor layer is directly connected to the first via connected to the second power supply line.

6. The semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer of the first transistor are arranged side by side in a first direction, and the first power supply line, the second power supply line, and the first signal line are arranged side by side in the first direction and extend in a second direction different from the first direction.

7. The semiconductor device according to claim 6, wherein the first semiconductor layer is directly connected to the first via connected to the first power supply line, and the second semiconductor layer is directly connected to the first via connected to the second power supply line.

8. A semiconductor device according to any one of claims 1 to 7, comprising: a third semiconductor layer arranged to overlap the first semiconductor layer in a planar view; a fourth semiconductor layer arranged to overlap the second semiconductor layer in a planar view; and a second nanosheet arranged to overlap the first nanosheet in a planar view.

9. The semiconductor device according to claim 8, wherein the third semiconductor layer and the fourth semiconductor layer are set in a floating state or are electrically connected to a voltage line having a fixed potential.

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